From patchwork Fri May 22 07:53:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1296018 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49SzJq0KfVz9sSW for ; Fri, 22 May 2020 17:53:59 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 78F30813C6; Fri, 22 May 2020 09:53:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9B8A3813C5; Fri, 22 May 2020 09:53:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2C67F813C5 for ; Fri, 22 May 2020 09:53:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ley.foon.tan@intel.com IronPort-SDR: chu/8iwj1F7PaKvUgj6gjgoALBnf7N30zsEouxS6t3RbpydbAYaIAas2SawthEs5dgfhvhj6/w b8df33+Grzug== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2020 00:53:34 -0700 IronPort-SDR: WKblqI9imojrNZPFNQleQhWlw1hN14hqj0MviWQ9Xo9q3OZ6jeF/SNglIvlLkV36Cucm2mO3dt qL8MJpV44EpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,420,1583222400"; d="scan'208";a="254251756" Received: from ppglcf0007.png.intel.com ([10.226.229.23]) by orsmga007.jf.intel.com with ESMTP; 22 May 2020 00:53:32 -0700 From: Ley Foon Tan To: u-boot@lists.denx.de Cc: Jagan Teki , Ley Foon Tan , Vignesh Raghavendra , Chin Liang See , Simon Goldschmidt , Chee Hong Ang , Ley Foon Tan Subject: [PATCH] spi: cadence_spi: Add octal and quad write support Date: Fri, 22 May 2020 15:53:30 +0800 Message-Id: <20200522075330.173132-1-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In Commit d64077202158 ("spi: cadence_qspi: Move to spi-mem framework") it removes setting to quad write bit by accident. This commit restores it back and also adding checking for octal support. Fixes: d64077202158 ("spi: cadence_qspi: Move to spi-mem framework") Signed-off-by: Ley Foon Tan --- drivers/spi/cadence_qspi_apb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index f9675f75a401..aaf5f600c6dc 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -689,6 +689,12 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat, /* Configure the opcode */ reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + + if (op->data.buswidth == 8) + reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + else if (op->data.buswidth == 4) + reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);