From patchwork Thu May 14 09:21:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5fF6ytYz9sVH for ; Thu, 14 May 2020 19:22:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726550AbgENJWG (ORCPT ); Thu, 14 May 2020 05:22:06 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52960 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbgENJVv (ORCPT ); Thu, 14 May 2020 05:21:51 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LQV20025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LQV20025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB01.realtek.com.tw (172.21.6.94) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:25 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXMB01.realtek.com.tw (172.21.6.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:25 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:25 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 1/7] pinctrl: realtek: rtd1295: Add missed pins. Date: Thu, 14 May 2020 17:21:19 +0800 Message-ID: <20200514092125.6875-2-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The current Realtek DHC SoC RTD1295 pinctrl driver missed some pins definition that may make the pin group does not mux completely. Signed-off-by: TY Chang --- drivers/pinctrl/pinctrl-rtd119x.c | 4 +- drivers/pinctrl/pinctrl-rtd1295.h | 192 +++++++++++++++++++++++++----- 2 files changed, 161 insertions(+), 35 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c index d69716243297..60bf8c283a7a 100644 --- a/drivers/pinctrl/pinctrl-rtd119x.c +++ b/drivers/pinctrl/pinctrl-rtd119x.c @@ -304,7 +304,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data) /* Check for function */ for (k = 0; k < data->info->num_functions; k++) { if (strcmp(data->info->functions[k].name, - data->info->muxes[i].functions[j].name) == 0) + data->info->muxes[i].functions[j].name) == 0) break; } if (k == data->info->num_functions) @@ -314,7 +314,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data) /* Check for duplicate mux value - assumption: ascending order */ if (j > 0 && data->info->muxes[i].functions[j].mux_value - <= data->info->muxes[i].functions[j - 1].mux_value) + < data->info->muxes[i].functions[j - 1].mux_value) dev_warn(data->pcdev->dev, "Mux %s function %s has unexpected value\n", data->info->muxes[i].name, data->info->muxes[i].functions[j].name); diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h index 57d8129f12b2..383870adb42f 100644 --- a/drivers/pinctrl/pinctrl-rtd1295.h +++ b/drivers/pinctrl/pinctrl-rtd1295.h @@ -37,6 +37,12 @@ enum rtd1295_iso_pins { RTD1295_NAT_LED_3, RTD1295_ISO_GPIO_33, RTD1295_ISO_GPIO_34, + RTD1295_PWM_23_LOC0, + RTD1295_PWM_01_LOC0, + RTD1295_PWM_23_LOC1, + RTD1295_PWM_01_LOC1, + RTD1295_EJTAG_AVCPU_LOC, + RTD1295_UR2_LOC, }; static const struct pinctrl_pin_desc rtd1295_iso_pins[] = { @@ -75,6 +81,12 @@ static const struct pinctrl_pin_desc rtd1295_iso_pins[] = { PINCTRL_PIN(RTD1295_NAT_LED_3, "nat_led_3"), PINCTRL_PIN(RTD1295_ISO_GPIO_33, "iso_gpio_33"), PINCTRL_PIN(RTD1295_ISO_GPIO_34, "iso_gpio_34"), + PINCTRL_PIN(RTD1295_PWM_23_LOC0, "pwm_23_loc0"), + PINCTRL_PIN(RTD1295_PWM_01_LOC0, "pwm_01_loc0"), + PINCTRL_PIN(RTD1295_PWM_23_LOC1, "pwm_23_loc1"), + PINCTRL_PIN(RTD1295_PWM_01_LOC1, "pwm_01_loc1"), + PINCTRL_PIN(RTD1295_EJTAG_AVCPU_LOC, "ejtag_avcpu_loc"), + PINCTRL_PIN(RTD1295_UR2_LOC, "ur2_loc"), }; static const unsigned int rtd1295_iso_gpio_0_pins[] = { RTD1295_ISO_GPIO_0 }; @@ -112,6 +124,12 @@ static const unsigned int rtd1295_nat_led_2_pins[] = { RTD1295_NAT_LED_2 }; static const unsigned int rtd1295_nat_led_3_pins[] = { RTD1295_NAT_LED_3 }; static const unsigned int rtd1295_iso_gpio_33_pins[] = { RTD1295_ISO_GPIO_33 }; static const unsigned int rtd1295_iso_gpio_34_pins[] = { RTD1295_ISO_GPIO_34 }; +static const unsigned int rtd1295_pwm_23_loc0_pins[] = { RTD1295_PWM_23_LOC0 }; +static const unsigned int rtd1295_pwm_01_loc0_pins[] = { RTD1295_PWM_01_LOC0 }; +static const unsigned int rtd1295_pwm_23_loc1_pins[] = { RTD1295_PWM_23_LOC1 }; +static const unsigned int rtd1295_pwm_01_loc1_pins[] = { RTD1295_PWM_01_LOC1 }; +static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = { RTD1295_EJTAG_AVCPU_LOC }; +static const unsigned int rtd1295_ur2_loc_pins[] = { RTD1295_UR2_LOC }; static const unsigned int rtd1295_i2c0_pins[] = { RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0 }; static const unsigned int rtd1295_i2c1_pins[] = { RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1 }; @@ -164,6 +182,12 @@ static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = { RTD1295_GROUP(nat_led_3), RTD1295_GROUP(iso_gpio_33), RTD1295_GROUP(iso_gpio_34), + RTD1295_GROUP(pwm_23_loc0), + RTD1295_GROUP(pwm_01_loc0), + RTD1295_GROUP(pwm_23_loc1), + RTD1295_GROUP(pwm_01_loc1), + RTD1295_GROUP(ejtag_avcpu_loc), + RTD1295_GROUP(ur2_loc), RTD1295_GROUP(i2c0), RTD1295_GROUP(i2c1), @@ -192,14 +216,25 @@ static const char * const rtd1295_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6" static const char * const rtd1295_iso_ir_rx_groups[] = { "ir_rx" }; static const char * const rtd1295_iso_ir_tx_groups[] = { "ir_tx" }; static const char * const rtd1295_iso_nat_led_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" }; -static const char * const rtd1295_iso_pwm_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" }; +static const char * const rtd1295_iso_pwm_1_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" }; +static const char * const rtd1295_iso_pwm_0_groups[] = { "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24" }; static const char * const rtd1295_iso_rtc_groups[] = { "iso_gpio_25" }; static const char * const rtd1295_iso_sc_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" }; static const char * const rtd1295_iso_standby_dbg_groups[] = { "iso_gpio_2", "iso_gpio_3", "ir_rx" }; static const char * const rtd1295_iso_uart0_groups[] = { "ur0_rx", "ur0_tx", "uart0" }; static const char * const rtd1295_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1" }; -static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5" }; -static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34" }; +static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc" }; +static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc" }; +static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = { "pwm_01_loc0" }; +static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = { "pwm_23_loc0" }; +static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = { "pwm_01_loc0" }; +static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = { "pwm_23_loc0" }; +static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = { "pwm_01_loc1" }; +static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = { "pwm_23_loc1" }; +static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = { "pwm_01_loc1" }; +static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = { "pwm_23_loc1" }; +static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { "ejtag_avcpu_loc" }; + #define RTD1295_FUNC(_name) \ { \ @@ -219,7 +254,8 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = { RTD1295_FUNC(ir_rx), RTD1295_FUNC(ir_tx), RTD1295_FUNC(nat_led), - RTD1295_FUNC(pwm), + RTD1295_FUNC(pwm_0), + RTD1295_FUNC(pwm_1), RTD1295_FUNC(rtc), RTD1295_FUNC(sc), RTD1295_FUNC(standby_dbg), @@ -227,6 +263,15 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = { RTD1295_FUNC(uart1), RTD1295_FUNC(uart2_0), RTD1295_FUNC(uart2_1), + RTD1295_FUNC(pwm_01_loc0_normal), + RTD1295_FUNC(pwm_23_loc0_normal), + RTD1295_FUNC(pwm_01_loc0_open_drain), + RTD1295_FUNC(pwm_23_loc0_open_drain), + RTD1295_FUNC(pwm_01_loc1_normal), + RTD1295_FUNC(pwm_23_loc1_normal), + RTD1295_FUNC(pwm_01_loc1_open_drain), + RTD1295_FUNC(pwm_23_loc1_open_drain), + RTD1295_FUNC(acpu_ejtag_loc_nf), }; #undef RTD1295_FUNC @@ -278,11 +323,11 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_MUX(etn_led_link, 0x10, GENMASK(27, 26), RTK_PIN_FUNC(0x0 << 26, "gpio"), RTK_PIN_FUNC(0x1 << 26, "etn_led"), - RTK_PIN_FUNC(0x2 << 26, "pwm")), + RTK_PIN_FUNC(0x2 << 26, "pwm_1")), RTK_PIN_MUX(etn_led_rxtx, 0x10, GENMASK(29, 28), RTK_PIN_FUNC(0x0 << 28, "gpio"), RTK_PIN_FUNC(0x1 << 28, "etn_led"), - RTK_PIN_FUNC(0x2 << 28, "pwm")), + RTK_PIN_FUNC(0x2 << 28, "pwm_1")), RTK_PIN_MUX(i2c_scl_6, 0x14, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), @@ -311,12 +356,12 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_MUX(nat_led_0, 0x14, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "gpio"), RTK_PIN_FUNC(0x1 << 16, "nat_led"), - RTK_PIN_FUNC(0x2 << 16, "pwm"), + RTK_PIN_FUNC(0x2 << 16, "pwm_1"), RTK_PIN_FUNC(0x3 << 16, "sc")), RTK_PIN_MUX(nat_led_1, 0x14, GENMASK(19, 18), RTK_PIN_FUNC(0x0 << 18, "gpio"), RTK_PIN_FUNC(0x1 << 18, "nat_led"), - RTK_PIN_FUNC(0x2 << 18, "pwm"), + RTK_PIN_FUNC(0x2 << 18, "pwm_1"), RTK_PIN_FUNC(0x3 << 18, "sc")), RTK_PIN_MUX(nat_led_2, 0x14, GENMASK(21, 20), RTK_PIN_FUNC(0x0 << 20, "gpio"), @@ -326,20 +371,38 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_FUNC(0x0 << 22, "gpio"), RTK_PIN_FUNC(0x1 << 22, "nat_led"), RTK_PIN_FUNC(0x3 << 22, "sc")), + RTK_PIN_MUX(pwm_23_loc0, 0x14, GENMASK(24, 24), + RTK_PIN_FUNC(0x0 << 24, "pwm_23_loc0_normal"), + RTK_PIN_FUNC(0x1 << 24, "pwm_23_loc0_open_drain")), + RTK_PIN_MUX(pwm_01_loc0, 0x14, GENMASK(25, 25), + RTK_PIN_FUNC(0x0 << 25, "pwm_01_loc0_normal"), + RTK_PIN_FUNC(0x1 << 25, "pwm_01_loc0_open_drain")), + RTK_PIN_MUX(pwm_23_loc1, 0x14, GENMASK(26, 26), + RTK_PIN_FUNC(0x0 << 26, "pwm_23_loc1_normal"), + RTK_PIN_FUNC(0x1 << 26, "pwm_23_loc1_open_drain")), + RTK_PIN_MUX(pwm_01_loc1, 0x14, GENMASK(27, 27), + RTK_PIN_FUNC(0x0 << 27, "pwm_01_loc1_normal"), + RTK_PIN_FUNC(0x1 << 27, "pwm_01_loc1_open_drain")), + RTK_PIN_MUX(ejtag_avcpu_loc, 0x14, GENMASK(29, 28), + RTK_PIN_FUNC(0x1 << 28, "acpu_ejtag_loc_iso"), + RTK_PIN_FUNC(0x2 << 28, "acpu_ejtag_loc_nf")), + RTK_PIN_MUX(ur2_loc, 0x14, GENMASK(31, 30), + RTK_PIN_FUNC(0x1 << 30, "uart2_0"), + RTK_PIN_FUNC(0x2 << 30, "uart2_1")), RTK_PIN_MUX(iso_gpio_21, 0x1c, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), - RTK_PIN_FUNC(0x1 << 0, "pwm")), + RTK_PIN_FUNC(0x1 << 0, "pwm_0")), RTK_PIN_MUX(iso_gpio_22, 0x1c, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "gpio"), - RTK_PIN_FUNC(0x1 << 2, "pwm")), + RTK_PIN_FUNC(0x1 << 2, "pwm_0")), RTK_PIN_MUX(iso_gpio_23, 0x1c, GENMASK(5, 4), RTK_PIN_FUNC(0x0 << 4, "gpio"), - RTK_PIN_FUNC(0x1 << 4, "pwm"), + RTK_PIN_FUNC(0x1 << 4, "pwm_0"), RTK_PIN_FUNC(0x2 << 4, "uart2_1")), RTK_PIN_MUX(iso_gpio_24, 0x1c, GENMASK(7, 6), RTK_PIN_FUNC(0x0 << 6, "gpio"), - RTK_PIN_FUNC(0x1 << 6, "pwm"), + RTK_PIN_FUNC(0x1 << 6, "pwm_0"), RTK_PIN_FUNC(0x2 << 6, "uart2_1")), RTK_PIN_MUX(iso_gpio_25, 0x1c, GENMASK(9, 8), RTK_PIN_FUNC(0x0 << 8, "gpio"), @@ -420,6 +483,11 @@ enum rtd1295_sb2_pins { RTD1295_RGMII1_RXD_1, RTD1295_RGMII1_RXD_2, RTD1295_RGMII1_RXD_3, + RTD1295_HI_LOC, + RTD1295_EJTAG_SCPU_LOC, + RTD1295_SF_EN, + RTD1295_TP0_LOC, + RTD1295_TP1_LOC, }; static const struct pinctrl_pin_desc rtd1295_sb2_pins[] = { @@ -477,6 +545,11 @@ static const struct pinctrl_pin_desc rtd1295_sb2_pins[] = { PINCTRL_PIN(RTD1295_RGMII1_RXD_1, "rgmii1_rxd_1"), PINCTRL_PIN(RTD1295_RGMII1_RXD_2, "rgmii1_rxd_2"), PINCTRL_PIN(RTD1295_RGMII1_RXD_3, "rgmii1_rxd_3"), + PINCTRL_PIN(RTD1295_HI_LOC, "hif_loc"), + PINCTRL_PIN(RTD1295_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1295_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1295_TP0_LOC, "tp0_loc"), + PINCTRL_PIN(RTD1295_TP1_LOC, "tp1_loc"), }; static const unsigned int rtd1295_gpio_0_pins[] = { RTD1295_GPIO_0 }; @@ -533,6 +606,16 @@ static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = { RTD1295_RGMII1_RXD_0 } static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = { RTD1295_RGMII1_RXD_1 }; static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = { RTD1295_RGMII1_RXD_2 }; static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = { RTD1295_RGMII1_RXD_3 }; +static const unsigned int rtd1295_hif_loc_pins[] = { RTD1295_HI_LOC }; +static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = { RTD1295_EJTAG_SCPU_LOC }; +static const unsigned int rtd1295_sf_en_pins[] = { RTD1295_SF_EN }; +static const unsigned int rtd1295_tp0_loc_pins[] = { RTD1295_TP0_LOC }; +static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC }; + + + + + static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = { RTD1295_GROUP(gpio_0), @@ -589,6 +672,11 @@ static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = { RTD1295_GROUP(rgmii1_rxd_1), RTD1295_GROUP(rgmii1_rxd_2), RTD1295_GROUP(rgmii1_rxd_3), + RTD1295_GROUP(hif_loc), + RTD1295_GROUP(ejtag_scpu_loc), + RTD1295_GROUP(sf_en), + RTD1295_GROUP(tp0_loc), + RTD1295_GROUP(tp1_loc), }; static const char * const rtd1295_sb2_gpio_groups[] = { @@ -619,17 +707,23 @@ static const char * const rtd1295_sb2_rgmii_groups[] = { "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3", "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3", }; -static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8" }; + +static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" }; +static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = { "ejtag_scpu_loc" }; static const char * const rtd1295_sb2_sensor_cko_output_groups[] = { "sensor_cko_0", "sensor_cko_1" }; static const char * const rtd1295_sb2_spi_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" }; static const char * const rtd1295_sb2_test_loop_dis_groups[] = { "usb_id" }; -static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3" }; -static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" }; -static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" }; -static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3" }; -static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk" }; -static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk" }; +static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", "tp0_loc" }; +static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" }; +static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" }; +static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "tp1_loc" }; +static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" }; +static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" }; static const char * const rtd1295_sb2_usb_clock_output_groups[] = { "sensor_cko_1" }; +static const char * const rtd1295_sb2_hif_loc_misc_groups[] = { "hif_loc" }; +static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" }; + + #define RTD1295_FUNC(_name) \ { \ @@ -661,6 +755,9 @@ static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = { RTD1295_FUNC(tp1_loc_tp0), RTD1295_FUNC(tp1_loc_tp1), RTD1295_FUNC(usb_clock_output), + RTD1295_FUNC(hif_loc_misc), + RTD1295_FUNC(hif_loc_nf), + RTD1295_FUNC(scpu_ejtag_loc_cr), }; #undef RTD1295_FUNC @@ -759,6 +856,12 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = { RTK_PIN_MUX(usb_id, 0x0c, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "gpio"), RTK_PIN_FUNC(0x2 << 16, "test_loop_dis")), + RTK_PIN_MUX(hif_loc, 0x0c, GENMASK(19, 18), + RTK_PIN_FUNC(0x1 << 18, "hif_loc_misc"), + RTK_PIN_FUNC(0x2 << 18, "hif_loc_nf")), + RTK_PIN_MUX(ejtag_scpu_loc, 0x0c, GENMASK(21, 20), + RTK_PIN_FUNC(0x1 << 20, "scpu_ejtag_loc_gpio"), + RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_loc_cr")), RTK_PIN_MUX(sensor_stb_1, 0x0c, GENMASK(23, 22), RTK_PIN_FUNC(0x0 << 22, "gpio")), RTK_PIN_MUX(sensor_stb_0, 0x0c, GENMASK(25, 24), @@ -773,6 +876,18 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = { RTK_PIN_FUNC(0x0 << 30, "gpio"), RTK_PIN_FUNC(0x1 << 30, "sensor_cko_output")), + RTK_PIN_MUX(sf_en, 0x14, GENMASK(0, 0), + RTK_PIN_FUNC(0x0 << 0, "gpio"), + RTK_PIN_FUNC(0x1 << 0, "spi")), + RTK_PIN_MUX(tp0_loc, 0x14, GENMASK(7, 7), + RTK_PIN_FUNC(0x0 << 7, "tp0_loc_tp0"), + RTK_PIN_FUNC(0x0 << 7, "tp0_loc_tp1"), + RTK_PIN_FUNC(0x1 << 7, "tp0_loc_rgmii0_tx")), + RTK_PIN_MUX(tp1_loc, 0x14, GENMASK(8, 8), + RTK_PIN_FUNC(0x0 << 8, "tp1_loc_tp1"), + RTK_PIN_FUNC(0x0 << 8, "tp1_loc_tp0"), + RTK_PIN_FUNC(0x1 << 8, "tp1_loc_rgmii0_rx")), + RTK_PIN_MUX(rgmii0_txc, 0x6c, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "rgmii")), @@ -1041,6 +1156,7 @@ enum rtd1295_cr_pins { RTD1295_PROB_1, RTD1295_PROB_2, RTD1295_PROB_3, + RTD1295_SDIO_LOC, }; static const struct pinctrl_pin_desc rtd1295_cr_pins[] = { @@ -1081,6 +1197,7 @@ static const struct pinctrl_pin_desc rtd1295_cr_pins[] = { PINCTRL_PIN(RTD1295_PROB_1, "prob_1"), PINCTRL_PIN(RTD1295_PROB_2, "prob_2"), PINCTRL_PIN(RTD1295_PROB_3, "prob_3"), + PINCTRL_PIN(RTD1295_SDIO_LOC, "sdio_loc"), }; static const unsigned int rtd1295_nf_cle_pins[] = { RTD1295_NF_CLE }; @@ -1120,6 +1237,8 @@ static const unsigned int rtd1295_prob_0_pins[] = { RTD1295_PROB_0 }; static const unsigned int rtd1295_prob_1_pins[] = { RTD1295_PROB_1 }; static const unsigned int rtd1295_prob_2_pins[] = { RTD1295_PROB_2 }; static const unsigned int rtd1295_prob_3_pins[] = { RTD1295_PROB_3 }; +static const unsigned int rtd1295_sdio_loc_pins[] = { RTD1295_SDIO_LOC }; + static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = { RTD1295_GROUP(nf_cle), @@ -1159,6 +1278,7 @@ static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = { RTD1295_GROUP(prob_1), RTD1295_GROUP(prob_2), RTD1295_GROUP(prob_3), + RTD1295_GROUP(sdio_loc), }; static const char * const rtd1295_cr_gpio_groups[] = { @@ -1180,7 +1300,9 @@ static const char * const rtd1295_cr_pcie_groups[] = { "pcie_clkreq_0", "pcie_cl static const char * const rtd1295_cr_pll_test_groups[] = { "prob_0", "prob_1", "prob_2", "prob_3" }; static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3" }; static const char * const rtd1295_cr_sd_card_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" }; -static const char * const rtd1295_cr_sdio_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" }; +static const char * const rtd1295_cr_sdio_0_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3" }; +static const char * const rtd1295_cr_sdio_1_groups[] = { "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" }; + #define RTD1295_FUNC(_name) \ { \ @@ -1200,7 +1322,8 @@ static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = { RTD1295_FUNC(pll_test), RTD1295_FUNC(scpu_ejtag_loc_cr), RTD1295_FUNC(sd_card), - RTD1295_FUNC(sdio), + RTD1295_FUNC(sdio_0), + RTD1295_FUNC(sdio_1), }; #undef RTD1295_FUNC @@ -1277,34 +1400,34 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = { RTK_PIN_MUX(sdio_cmd, 0x04, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), - RTK_PIN_FUNC(0x1 << 0, "sdio")), + RTK_PIN_FUNC(0x1 << 0, "sdio_0")), RTK_PIN_MUX(sdio_clk, 0x04, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "gpio"), - RTK_PIN_FUNC(0x1 << 2, "sdio")), + RTK_PIN_FUNC(0x1 << 2, "sdio_0")), RTK_PIN_MUX(sdio_data_0, 0x04, GENMASK(5, 4), RTK_PIN_FUNC(0x0 << 4, "gpio"), - RTK_PIN_FUNC(0x1 << 4, "sdio")), + RTK_PIN_FUNC(0x1 << 4, "sdio_0")), RTK_PIN_MUX(sdio_data_1, 0x04, GENMASK(7, 6), RTK_PIN_FUNC(0x0 << 6, "gpio"), - RTK_PIN_FUNC(0x1 << 6, "sdio")), + RTK_PIN_FUNC(0x1 << 6, "sdio_0")), RTK_PIN_MUX(sdio_data_2, 0x04, GENMASK(9, 8), RTK_PIN_FUNC(0x0 << 8, "gpio"), - RTK_PIN_FUNC(0x1 << 8, "sdio")), + RTK_PIN_FUNC(0x1 << 8, "sdio_0")), RTK_PIN_MUX(sdio_data_3, 0x04, GENMASK(11, 10), RTK_PIN_FUNC(0x0 << 10, "gpio"), - RTK_PIN_FUNC(0x1 << 10, "sdio")), + RTK_PIN_FUNC(0x1 << 10, "sdio_0")), RTK_PIN_MUX(emmc_dd_sb, 0x04, GENMASK(13, 12), RTK_PIN_FUNC(0x0 << 12, "gpio"), RTK_PIN_FUNC(0x2 << 12, "emmc")), RTK_PIN_MUX(mmc_cmd, 0x04, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "gpio"), RTK_PIN_FUNC(0x1 << 16, "sd_card"), - RTK_PIN_FUNC(0x2 << 16, "sdio"), + RTK_PIN_FUNC(0x2 << 16, "sdio_1"), RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag_loc_cr")), RTK_PIN_MUX(mmc_clk, 0x04, GENMASK(19, 18), RTK_PIN_FUNC(0x0 << 18, "gpio"), RTK_PIN_FUNC(0x1 << 18, "sd_card"), - RTK_PIN_FUNC(0x2 << 18, "sdio"), + RTK_PIN_FUNC(0x2 << 18, "sdio_1"), RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag_loc_cr")), RTK_PIN_MUX(mmc_wp, 0x04, GENMASK(21, 20), RTK_PIN_FUNC(0x0 << 20, "gpio"), @@ -1316,22 +1439,25 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = { RTK_PIN_MUX(mmc_data_0, 0x04, GENMASK(25, 24), RTK_PIN_FUNC(0x0 << 24, "gpio"), RTK_PIN_FUNC(0x1 << 24, "sd_card"), - RTK_PIN_FUNC(0x2 << 24, "sdio"), + RTK_PIN_FUNC(0x2 << 24, "sdio_1"), RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag_loc_cr")), RTK_PIN_MUX(mmc_data_1, 0x04, GENMASK(27, 26), RTK_PIN_FUNC(0x0 << 26, "gpio"), RTK_PIN_FUNC(0x1 << 26, "sd_card"), - RTK_PIN_FUNC(0x2 << 26, "sdio")), + RTK_PIN_FUNC(0x2 << 26, "sdio_1")), RTK_PIN_MUX(mmc_data_2, 0x04, GENMASK(29, 28), RTK_PIN_FUNC(0x0 << 28, "gpio"), RTK_PIN_FUNC(0x1 << 28, "sd_card"), - RTK_PIN_FUNC(0x2 << 28, "sdio")), + RTK_PIN_FUNC(0x2 << 28, "sdio_1")), RTK_PIN_MUX(mmc_data_3, 0x04, GENMASK(31, 30), RTK_PIN_FUNC(0x0 << 30, "gpio"), RTK_PIN_FUNC(0x1 << 30, "sd_card"), - RTK_PIN_FUNC(0x2 << 30, "sdio"), + RTK_PIN_FUNC(0x2 << 30, "sdio_1"), RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag_loc_cr")), + RTK_PIN_MUX(sdio_loc, 0x1c, GENMASK(1, 0), + RTK_PIN_FUNC(0x0 << 0, "sdio_0"), + RTK_PIN_FUNC(0x1 << 0, "sdio_1")), RTK_PIN_MUX(pcie_clkreq_0, 0x1c, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "gpio"), RTK_PIN_FUNC(0x1 << 2, "pcie")), From patchwork Thu May 14 09:21:20 2020 Content-Type: text/plain; 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Thu, 14 May 2020 17:21:25 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 2/7] pinctrl: realtek: rtd1295: Add pin configs. Date: Thu, 14 May 2020 17:21:20 +0800 Message-ID: <20200514092125.6875-3-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pin configs for Realtek DHC SoC RTD1295 pinctrl driver. Signed-off-by: TY Chang --- drivers/pinctrl/pinctrl-rtd119x.c | 160 +++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rtd1295.h | 159 +++++++++++++++++++++++++++++ 2 files changed, 317 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c index 60bf8c283a7a..52b16d610e13 100644 --- a/drivers/pinctrl/pinctrl-rtd119x.c +++ b/drivers/pinctrl/pinctrl-rtd119x.c @@ -36,6 +36,17 @@ struct rtd119x_pin_mux_desc { u32 mux_value; }; +struct rtd119x_pin_config_desc { + const char *name; + unsigned int reg_offset; + unsigned int base_bit; + unsigned int pud_en_offset; + unsigned int pud_sel_offset; + unsigned int curr_offset; + unsigned int smt_offset; + unsigned int curr_type; +}; + struct rtd119x_pin_desc { const char *name; unsigned int mux_offset; @@ -43,6 +54,20 @@ struct rtd119x_pin_desc { const struct rtd119x_pin_mux_desc *functions; }; +#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ + _pud_sel_off, _curr_off, _smt_off, _curr_type) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .base_bit = _base_bit, \ + .pud_en_offset = _pud_en_off, \ + .pud_sel_offset = _pud_sel_off, \ + .curr_offset = _curr_off, \ + .smt_offset = _smt_off, \ + .curr_type = _curr_type, \ + } + + #define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \ { \ .name = # _name, \ @@ -68,8 +93,15 @@ struct rtd119x_pinctrl_desc { unsigned int num_functions; const struct rtd119x_pin_desc *muxes; unsigned int num_muxes; + const struct rtd119x_pin_config_desc *configs; + unsigned int num_configs; }; +#define PCONF_UNSUPP 0xffffffff +#define PADDRI_4_8 1 +#define PADDRI_2_4 0 + + #include "pinctrl-rtd1195.h" #include "pinctrl-rtd1295.h" @@ -165,6 +197,19 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pi return NULL; } +static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(struct rtd119x_pinctrl *data, const char *name) +{ + int i; + + for (i = 0; i < data->info->num_configs; i++) { + if (strcmp(data->info->configs[i].name, name) == 0) + return &data->info->configs[i]; + } + + return NULL; +} + + static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, unsigned int pin, const char *func_name) { @@ -247,10 +292,100 @@ static const struct pinmux_ops rtd119x_pinmux_ops = { .gpio_request_enable = rtd119x_pinctrl_gpio_request_enable, }; + +static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, + const struct rtd119x_pin_config_desc *config_desc, enum pin_config_param param, + enum pin_config_param arg) +{ + u8 set_val = 0; + u16 strength; + u32 val, mask; + int pulsel_off, pulen_off, smt_off, curr_off; + + smt_off = config_desc->base_bit + config_desc->smt_offset; + curr_off = config_desc->base_bit + config_desc->curr_offset; + pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset; + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + set_val = arg; + if (set_val) + set_val = 1; + else + set_val = 0; + + val = readl(data->base + config_desc->reg_offset); + mask = 1 << smt_off; + val = (val & ~mask) | (set_val << smt_off); + writel(val, data->base + config_desc->reg_offset); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + strength = arg; + switch (config_desc->curr_type) { + case PADDRI_4_8: + if (strength == 4) + set_val = 0; + else if (strength == 8) + set_val = 1; + else + return -EINVAL; + break; + case PADDRI_2_4: + if (strength == 2) + set_val = 0; + else if (strength == 4) + set_val = 1; + else + return -EINVAL; + break; + case PCONF_UNSUPP: + pr_err("[%s] not support drive strength\n", config_desc->name); + return -ENOTSUPP; + break; + default: + return -EINVAL; + } + val = readl(data->base + config_desc->reg_offset); + mask = 1 << curr_off; + val = (val & ~mask) | (set_val << curr_off); + writel(val, data->base + config_desc->reg_offset); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + val = readl(data->base + config_desc->reg_offset); + mask = 1 << pulen_off; + val = (val & ~mask) | (1 << pulen_off); + writel(val, data->base + config_desc->reg_offset); + break; + case PIN_CONFIG_BIAS_DISABLE: + val = readl(data->base + config_desc->reg_offset); + mask = 1 << pulen_off; + val = val & ~mask; + writel(val, data->base + config_desc->reg_offset); + break; + case PIN_CONFIG_BIAS_PULL_UP: + val = readl(data->base + config_desc->reg_offset); + mask = (1 << pulen_off) | (1 << pulsel_off); + val = (val & ~mask) | (1 << pulen_off) | (1 << pulsel_off); + writel(val, data->base + config_desc->reg_offset); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + val = readl(data->base + config_desc->reg_offset); + mask = (1 << pulen_off) | (0 << pulsel_off); + val = (val & ~mask) | (1 << pulen_off); + writel(val, data->base + config_desc->reg_offset); + break; + default: + break; + } + + return 0; +} + static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr, unsigned long *config) { - //struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); unsigned int param = pinconf_to_config_param(*config); unsigned int arg = 0; @@ -266,11 +401,32 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr, static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned pinnr, unsigned long *configs, unsigned num_configs) { - //struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd119x_pin_config_desc *config_desc; + const struct pinctrl_pin_desc *pin_desc; + const char *pin_name; + int i; + + pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pinnr); + if (!pin_desc) + return -ENOTSUPP; + + pin_name = pin_desc->name; + config_desc = rtd119x_pinctrl_find_config(data, pin_name); + if (!config_desc) + return -ENOTSUPP; + + for (i = 0; i < num_configs; i++) { + rtd119x_pconf_parse_conf(data, config_desc, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + } return 0; } + + static const struct pinconf_ops rtd119x_pinconf_ops = { .is_generic = true, .pin_config_get = rtd119x_pin_config_get, diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h index 383870adb42f..0232c5d8b353 100644 --- a/drivers/pinctrl/pinctrl-rtd1295.h +++ b/drivers/pinctrl/pinctrl-rtd1295.h @@ -415,6 +415,44 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_FUNC(0x2 << 12, "uart2_1")), }; +static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = { + RTK_PIN_CONFIG(iso_gpio_2, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_3, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_4, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_5, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_7, 0x0, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(i2c_sda_0, 0x0, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_0, 0x0, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(ur1_rx, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_tx, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_rts_n, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_cts_n, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur0_rx, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur0_tx, 0x4, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(etn_led_link, 0x4, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(etn_led_rxtx, 0x4, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_6, 0x8, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_6, 0x8, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(ir_tx, 0x8, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(i2c_sda_1, 0x8, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_1, 0x8, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(hdmi_hpd, 0xc, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(nat_led_0, 0xc, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nat_led_1, 0xc, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nat_led_2, 0xc, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nat_led_3, 0xc, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(iso_gpio_21, 0x18, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_22, 0x18, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_23, 0x18, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_24, 0x18, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_25, 0x18, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(iso_gpio_33, 0x20, 0, 1, 0, 2, 3, 2), + RTK_PIN_CONFIG(iso_gpio_34, 0x20, 4, 1, 0, 2, 3, 2), +}; + + + static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = { .pins = rtd1295_iso_pins, .num_pins = ARRAY_SIZE(rtd1295_iso_pins), @@ -424,6 +462,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1295_iso_pin_functions), .muxes = rtd1295_iso_muxes, .num_muxes = ARRAY_SIZE(rtd1295_iso_muxes), + .configs = rtd1295_iso_configs, + .num_configs = ARRAY_SIZE(rtd1295_iso_configs), }; /* SB2 */ @@ -979,6 +1019,64 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = { RTK_PIN_FUNC(0x1 << 22, "rgmii")), }; +static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = { + RTK_PIN_CONFIG(tp0_clk, 0x28, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp0_sync, 0x28, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp0_valid, 0x28, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp0_data, 0x28, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp1_clk, 0x2C, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp1_sync, 0x2C, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp1_valid, 0x2C, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(tp1_data, 0x2C, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_4, 0x30, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_4, 0x30, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_5, 0x30, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_5, 0x30, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_0, 0x34, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_1, 0x34, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_2, 0x34, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_3, 0x34, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_4, 0x34, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_5, 0x34, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_6, 0x34, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_7, 0x34, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_8, 0x38, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_9, 0x38, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(usb_id, 0x38, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sensor_stb_0, 0x38, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sensor_stb_1, 0x38, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sensor_rst, 0x38, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sensor_cko_0, 0x38, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sensor_cko_1, 0x38, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_txc, 0x64, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_tx_ctl, 0x64, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_txd_0, 0x64, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_txd_1, 0x64, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_txd_2, 0x64, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_txd_3, 0x64, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rxc, 0x64, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rx_ctl, 0x64, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rxd_0, 0x68, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rxd_1, 0x68, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rxd_2, 0x68, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_rxd_3, 0x68, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_mdio, 0x68, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii0_mdc, 0x68, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_txc, 0x74, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_tx_ctl, 0x74, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_txd_0, 0x74, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_txd_1, 0x74, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_txd_2, 0x74, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_txd_3, 0x74, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rxc, 0x74, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rx_ctl, 0x74, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rxd_0, 0x78, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rxd_1, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rxd_2, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(rgmii1_rxd_3, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8), +}; + + static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = { .pins = rtd1295_sb2_pins, .num_pins = ARRAY_SIZE(rtd1295_sb2_pins), @@ -988,6 +1086,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1295_sb2_pin_functions), .muxes = rtd1295_sb2_muxes, .num_muxes = ARRAY_SIZE(rtd1295_sb2_muxes), + .configs = rtd1295_sb2_configs, + .num_configs = ARRAY_SIZE(rtd1295_sb2_configs), }; /* Disp */ @@ -1105,6 +1205,20 @@ static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = { RTK_PIN_FUNC(0x2 << 18, "ai")), }; +static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = { + RTK_PIN_CONFIG(spdif, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(dmic_clk, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(dmic_data, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_lrck, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_bck, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(aock, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_sd_0, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_sd_1, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_sd_2, 0x4, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ao_sd_3, 0x4, 24, 1, 0, 2, 3, PADDRI_2_4), +}; + + static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = { .pins = rtd1295_disp_pins, .num_pins = ARRAY_SIZE(rtd1295_disp_pins), @@ -1114,6 +1228,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1295_disp_pin_functions), .muxes = rtd1295_disp_muxes, .num_muxes = ARRAY_SIZE(rtd1295_disp_muxes), + .configs = rtd1295_disp_configs, + .num_configs = ARRAY_SIZE(rtd1295_disp_configs), }; /* CR */ @@ -1480,6 +1596,47 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = { RTK_PIN_FUNC(0x1 << 12, "pll_test")), }; +static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = { + RTK_PIN_CONFIG(nf_dqs, 0x8, 0, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_ale, 0x8, 4, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_ce_n_0, 0x8, 8, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_ce_n_1, 0x8, 12, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_rdy, 0x8, 16, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_rd_n, 0x8, 20, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_wr_n, 0x8, 24, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_cle, 0x8, 28, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_0, 0xc, 0, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_1, 0xc, 4, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_2, 0xc, 8, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_3, 0xc, 12, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_4, 0xc, 16, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_5, 0xc, 20, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_6, 0xc, 24, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(nf_dd_7, 0xc, 28, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_cmd, 0x10, 0, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_clk, 0x10, 4, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_wp, 0x10, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_cd, 0x10, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_data_0, 0x10, 16, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_data_1, 0x10, 20, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_data_2, 0x10, 24, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(mmc_data_3, 0x10, 28, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_cmd, 0x14, 0, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_clk, 0x14, 4, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_data_0, 0x14, 16, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_data_1, 0x14, 20, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_data_2, 0x14, 24, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(sdio_data_3, 0x14, 28, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(emmc_dd_sb, 0x18, 0, 1, 0, 2, 3, PCONF_UNSUPP), + RTK_PIN_CONFIG(pcie_clkreq_0, 0x18, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(pcie_clkreq_1, 0x18, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(prob_0, 0x18, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(prob_1, 0x18, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(prob_2, 0x18, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(prob_3, 0x18, 24, 1, 0, 2, 3, PADDRI_4_8), +}; + + static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = { .pins = rtd1295_cr_pins, .num_pins = ARRAY_SIZE(rtd1295_cr_pins), @@ -1489,6 +1646,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1295_cr_pin_functions), .muxes = rtd1295_cr_muxes, .num_muxes = ARRAY_SIZE(rtd1295_cr_muxes), + .configs = rtd1295_cr_configs, + .num_configs = ARRAY_SIZE(rtd1295_cr_configs), }; #endif From patchwork Thu May 14 09:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290040 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5f54cX9z9sVG for ; Thu, 14 May 2020 19:22:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725946AbgENJVx (ORCPT ); Thu, 14 May 2020 05:21:53 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52964 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726192AbgENJVx (ORCPT ); Thu, 14 May 2020 05:21:53 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LQV50025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LQV50025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXDAG01.realtek.com.tw (172.21.6.100) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXDAG01.realtek.com.tw (172.21.6.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:25 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:25 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 3/7] pinctrl: realtek: rtd1195: Add missed pins and pin configs. Date: Thu, 14 May 2020 17:21:21 +0800 Message-ID: <20200514092125.6875-4-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add missed pins and pin configs for Realtek DHC SoC RTD1195 pinctrl driver. Signed-off-by: TY Chang --- drivers/pinctrl/pinctrl-rtd1195.h | 332 +++++++++++++++++++++++------- 1 file changed, 258 insertions(+), 74 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/pinctrl-rtd1195.h index 8eaab8a0dbf3..9f3471d02221 100644 --- a/drivers/pinctrl/pinctrl-rtd1195.h +++ b/drivers/pinctrl/pinctrl-rtd1195.h @@ -23,6 +23,11 @@ enum rtd1195_iso_pins { RTD1195_ISO_ETN_LED_RXTX, RTD1195_ISO_I2C_SCL_6, RTD1195_ISO_I2C_SDA_6, + RTD1195_ISO_AI_LOC, + RTD1195_ISO_EJTAG_AVCPU_LOC, + RTD1195_ISO_UR1_LOC, + RTD1195_ISO_PWM_01_OPEN_DRAIN, + RTD1195_ISO_PWM_23_OPEN_DRAIN, }; static const struct pinctrl_pin_desc rtd1195_iso_pins[] = { @@ -47,6 +52,11 @@ static const struct pinctrl_pin_desc rtd1195_iso_pins[] = { PINCTRL_PIN(RTD1195_ISO_ETN_LED_RXTX, "etn_led_rxtx"), PINCTRL_PIN(RTD1195_ISO_I2C_SCL_6, "i2c_scl_6"), PINCTRL_PIN(RTD1195_ISO_I2C_SDA_6, "i2c_sda_6"), + PINCTRL_PIN(RTD1195_ISO_AI_LOC, "ai_loc"), + PINCTRL_PIN(RTD1195_ISO_EJTAG_AVCPU_LOC, "ejtag_avcpu_loc"), + PINCTRL_PIN(RTD1195_ISO_UR1_LOC, "ur1_loc"), + PINCTRL_PIN(RTD1195_ISO_PWM_01_OPEN_DRAIN, "pwm_01_open_drain"), + PINCTRL_PIN(RTD1195_ISO_PWM_23_OPEN_DRAIN, "pwm_23_open_drain"), }; static const unsigned int rtd1195_iso_gpio_0_pins[] = { RTD1195_ISO_GPIO_0 }; @@ -70,6 +80,12 @@ static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LI static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX }; static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 }; static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 }; +static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC }; +static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC }; +static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC }; +static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN }; +static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN }; + #define RTD1195_GROUP(_name) \ { \ @@ -100,6 +116,11 @@ static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = { RTD1195_GROUP(etn_led_rxtx), RTD1195_GROUP(i2c_scl_6), RTD1195_GROUP(i2c_sda_6), + RTD1195_GROUP(ai_loc), + RTD1195_GROUP(ejtag_avcpu_loc), + RTD1195_GROUP(ur1_loc), + RTD1195_GROUP(pwm_01_open_drain), + RTD1195_GROUP(pwm_23_open_drain), }; static const char * const rtd1195_iso_gpio_groups[] = { @@ -112,13 +133,22 @@ static const char * const rtd1195_iso_gpio_groups[] = { "etn_led_link", "etn_led_rxtx", "i2c_scl_6", "i2c_sda_6", }; -static const char * const rtd1195_iso_ai_groups[] = { - "usb0", "usb1", "vfd_cs_n", "vfd_clk", - "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n" +static const char * const rtd1195_iso_ai_ur1_groups[] = { + "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ai_loc" +}; + +static const char * const rtd1195_iso_ai_vfd_groups[] = { + "usb0", "usb1", "vfd_cs_n", "vfd_clk", "ai_loc" +}; + +static const char * const rtd1195_iso_avcpu_ejtag_iso_groups[] = { + "vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1", "ejtag_avcpu_loc" }; -static const char * const rtd1195_iso_avcpu_ejtag_groups[] = { - "vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1" +static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = { + "ejtag_avcpu_loc" }; + + static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" }; static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" }; static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" }; @@ -131,8 +161,16 @@ static const char * const rtd1195_iso_pwm_groups[] = { }; static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" }; static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" }; -static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n" }; +static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" }; +static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" }; static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" }; +static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" }; +static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" }; +static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" }; +static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" }; + + + #define RTD1195_FUNC(_name) \ { \ @@ -143,8 +181,10 @@ static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "v static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = { RTD1195_FUNC(gpio), - RTD1195_FUNC(ai), - RTD1195_FUNC(avcpu_ejtag), + RTD1195_FUNC(ai_ur1), + RTD1195_FUNC(ai_vfd), + RTD1195_FUNC(avcpu_ejtag_iso), + RTD1195_FUNC(avcpu_ejtag_misc_loc), RTD1195_FUNC(etn_led), RTD1195_FUNC(i2c0), RTD1195_FUNC(i2c2), @@ -156,7 +196,12 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = { RTD1195_FUNC(standby_dbg), RTD1195_FUNC(uart0), RTD1195_FUNC(uart1), + RTD1195_FUNC(ur1_misc), RTD1195_FUNC(vfd), + RTD1195_FUNC(pwm_01_normal), + RTD1195_FUNC(pwm_23_normal), + RTD1195_FUNC(pwm_01_open_drain), + RTD1195_FUNC(pwm_23_open_drain), }; #undef RTD1195_FUNC @@ -166,17 +211,17 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = { RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "vfd"), RTK_PIN_FUNC(0x2 << 0, "i2c2"), - RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag_iso")), RTK_PIN_MUX(vfd_clk, 0x10, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "gpio"), RTK_PIN_FUNC(0x1 << 2, "vfd"), - RTK_PIN_FUNC(0x2 << 2, "ai"), - RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")), + RTK_PIN_FUNC(0x2 << 2, "ai_vfd"), + RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_iso")), RTK_PIN_MUX(vfd_cs_n, 0x10, GENMASK(5, 4), RTK_PIN_FUNC(0x0 << 4, "gpio"), RTK_PIN_FUNC(0x1 << 4, "vfd"), - RTK_PIN_FUNC(0x2 << 4, "ai"), - RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")), + RTK_PIN_FUNC(0x2 << 4, "ai_vfd"), + RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_iso")), RTK_PIN_MUX(ir_rx, 0x10, GENMASK(7, 6), RTK_PIN_FUNC(0x0 << 6, "gpio"), RTK_PIN_FUNC(0x1 << 6, "ir_rx"), @@ -184,31 +229,31 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = { RTK_PIN_MUX(usb0, 0x10, GENMASK(9, 8), RTK_PIN_FUNC(0x0 << 8, "gpio"), RTK_PIN_FUNC(0x1 << 8, "standby_dbg"), - RTK_PIN_FUNC(0x2 << 8, "ai"), - RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag")), + RTK_PIN_FUNC(0x2 << 8, "ai_vfd"), + RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag_iso")), RTK_PIN_MUX(usb1, 0x10, GENMASK(11, 10), RTK_PIN_FUNC(0x0 << 10, "gpio"), RTK_PIN_FUNC(0x1 << 10, "standby_dbg"), - RTK_PIN_FUNC(0x2 << 10, "ai"), - RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag")), + RTK_PIN_FUNC(0x2 << 10, "ai_vfd"), + RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag_iso")), RTK_PIN_MUX(ur1_rx, 0x10, GENMASK(13, 12), RTK_PIN_FUNC(0x0 << 12, "gpio"), RTK_PIN_FUNC(0x1 << 12, "uart1"), - RTK_PIN_FUNC(0x2 << 12, "ai"), + RTK_PIN_FUNC(0x2 << 12, "ai_ur1"), RTK_PIN_FUNC(0x3 << 12, "pwm")), RTK_PIN_MUX(ur1_tx, 0x10, GENMASK(15, 14), RTK_PIN_FUNC(0x0 << 14, "gpio"), RTK_PIN_FUNC(0x1 << 14, "uart1"), - RTK_PIN_FUNC(0x2 << 14, "ai"), + RTK_PIN_FUNC(0x2 << 14, "ai_ur1"), RTK_PIN_FUNC(0x3 << 14, "pwm")), RTK_PIN_MUX(ur1_rts_n, 0x10, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "gpio"), RTK_PIN_FUNC(0x1 << 16, "uart1"), - RTK_PIN_FUNC(0x2 << 16, "ai")), + RTK_PIN_FUNC(0x2 << 16, "ai_ur1")), RTK_PIN_MUX(ur1_cts_n, 0x10, GENMASK(19, 18), RTK_PIN_FUNC(0x0 << 18, "gpio"), RTK_PIN_FUNC(0x1 << 18, "uart1"), - RTK_PIN_FUNC(0x2 << 18, "ai")), + RTK_PIN_FUNC(0x2 << 18, "ai_ur1")), RTK_PIN_MUX(ur0_rx, 0x10, GENMASK(21, 20), RTK_PIN_FUNC(0x0 << 20, "gpio"), RTK_PIN_FUNC(0x1 << 20, "uart0"), @@ -242,13 +287,44 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = { RTK_PIN_FUNC(0x0 << 4, "gpio"), RTK_PIN_FUNC(0x1 << 4, "ir_tx"), RTK_PIN_FUNC(0x2 << 4, "i2c3")), - /* pwm_23_open_drain_switch */ - /* pwm_01_open_drain_switch */ - /* ur1_loc */ - /* ejtag_avcpu_loc */ - /* ai_loc */ + RTK_PIN_MUX(pwm_23_open_drain, 0x14, GENMASK(24, 24), + RTK_PIN_FUNC(0x0 << 24, "pwm_23_normal"), + RTK_PIN_FUNC(0x1 << 24, "pwm_23_open_drain")), + RTK_PIN_MUX(pwm_01_open_drain, 0x14, GENMASK(25, 25), + RTK_PIN_FUNC(0x0 << 25, "pwm_01_normal"), + RTK_PIN_FUNC(0x1 << 25, "pwm_01_open_drain")), + RTK_PIN_MUX(ur1_loc, 0x14, GENMASK(27, 26), + RTK_PIN_FUNC(0x1 << 26, "uart1"), + RTK_PIN_FUNC(0x2 << 26, "ur1_misc")), + RTK_PIN_MUX(ejtag_avcpu_loc, 0x14, GENMASK(29, 28), + RTK_PIN_FUNC(0x1 << 28, "avcpu_ejtag_iso"), + RTK_PIN_FUNC(0x2 << 28, "avcpu_ejtag_misc_loc")), + RTK_PIN_MUX(ai_loc, 0x14, GENMASK(31, 30), + RTK_PIN_FUNC(0x1 << 30, "ai_ur1"), + RTK_PIN_FUNC(0x2 << 30, "ai_vfd")), +}; + +static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = { + RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(vfd_d, 0x0, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(i2c_sda_0, 0x0, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_0, 0x0, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(ur1_rx, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_tx, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_rts_n, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur1_cts_n, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur0_rx, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(ur0_tx, 0x4, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(etn_led_link, 0x4, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(etn_led_rxtx, 0x4, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_6, 0x8, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_6, 0x8, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(ir_tx, 0x8, 20, 1, 0, 2, 3, PADDRI_2_4), }; + static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = { .pins = rtd1195_iso_pins, .num_pins = ARRAY_SIZE(rtd1195_iso_pins), @@ -258,6 +334,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1195_iso_pin_functions), .muxes = rtd1195_iso_muxes, .num_muxes = ARRAY_SIZE(rtd1195_iso_muxes), + .configs = rtd1195_iso_configs, + .num_configs = ARRAY_SIZE(rtd1195_iso_configs), }; /* CRT */ @@ -323,6 +401,9 @@ enum rtd1195_crt_pins { RTD1195_SENSOR_RST, RTD1195_SENSOR_STB_0, RTD1195_SENSOR_STB_1, + RTD1195_EJTAG_SCPU_LOC, + RTD1195_HI_LOC, + RTD1195_AO_LOC, }; static const struct pinctrl_pin_desc rtd1195_crt_pins[] = { @@ -386,6 +467,9 @@ static const struct pinctrl_pin_desc rtd1195_crt_pins[] = { PINCTRL_PIN(RTD1195_SENSOR_RST, "sensor_rst"), PINCTRL_PIN(RTD1195_SENSOR_STB_0, "sensor_stb_0"), PINCTRL_PIN(RTD1195_SENSOR_STB_1, "sensor_stb_1"), + PINCTRL_PIN(RTD1195_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1195_HI_LOC, "hif_loc"), + PINCTRL_PIN(RTD1195_AO_LOC, "ao_loc"), }; static const unsigned int rtd1195_gpio_0_pins[] = { RTD1195_GPIO_0 }; @@ -448,6 +532,14 @@ static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 } static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST }; static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 }; static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 }; +static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC }; +static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC }; +static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC }; + + + + + #define RTD1195_GROUP(_name) \ { \ @@ -517,6 +609,9 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = { RTD1195_GROUP(sensor_rst), RTD1195_GROUP(sensor_stb_0), RTD1195_GROUP(sensor_stb_1), + RTD1195_GROUP(ejtag_scpu_loc), + RTD1195_GROUP(hif_loc), + RTD1195_GROUP(ao_loc), }; static const char * const rtd1195_crt_gpio_groups[] = { @@ -540,11 +635,16 @@ static const char * const rtd1195_crt_gpio_groups[] = { "sensor_stb_0", "sensor_stb_1", }; -static const char * const rtd1195_crt_ao_groups[] = { - "gpio_4", "gpio_5", "gpio_6", "gpio_7", - "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", +static const char * const rtd1195_crt_ao_tp0_groups[] = { + "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "ao_loc" +}; + +static const char * const rtd1195_crt_ao_gpio_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7", "ao_loc" }; -static const char * const rtd1195_crt_avcpu_ejtag_groups[] = { + + +static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = { "nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7" }; static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" }; @@ -555,10 +655,15 @@ static const char * const rtd1195_crt_emmc_groups[] = { static const char * const rtd1195_crt_gspi_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3", }; -static const char * const rtd1195_crt_hif_groups[] = { - "gpio_0", "gpio_1", "gpio_2", "gpio_3", - "nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle", +static const char * const rtd1195_crt_hif_nf_groups[] = { + "nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle", "hif_loc" }; + +static const char * const rtd1195_crt_hif_misc_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "hif_loc" +}; + + static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" }; static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" }; static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" }; @@ -572,9 +677,13 @@ static const char * const rtd1195_crt_nand_groups[] = { "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1", }; -static const char * const rtd1195_crt_scpu_ejtag_groups[] = { - "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp" +static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" +}; +static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = { + "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc" }; + static const char * const rtd1195_crt_sdio_groups[] = { "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd", }; @@ -598,12 +707,14 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" }; static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = { RTD1195_FUNC(gpio), - RTD1195_FUNC(ao), - RTD1195_FUNC(avcpu_ejtag), + RTD1195_FUNC(ao_tp0), + RTD1195_FUNC(ao_gpio), + RTD1195_FUNC(avcpu_ejtag_misc), RTD1195_FUNC(cpu_loop), RTD1195_FUNC(emmc), RTD1195_FUNC(gspi), - RTD1195_FUNC(hif), + RTD1195_FUNC(hif_misc), + RTD1195_FUNC(hif_nf), RTD1195_FUNC(i2c1), RTD1195_FUNC(i2c2), RTD1195_FUNC(i2c3), @@ -611,7 +722,8 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = { RTD1195_FUNC(i2c5), RTD1195_FUNC(mmc), RTD1195_FUNC(nand), - RTD1195_FUNC(scpu_ejtag), + RTD1195_FUNC(scpu_ejtag_gpio), + RTD1195_FUNC(scpu_ejtag_cr), RTD1195_FUNC(sdio), RTD1195_FUNC(sensor), RTD1195_FUNC(spdif), @@ -628,27 +740,27 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_FUNC(0x0 << 2, "gpio"), RTK_PIN_FUNC(0x1 << 2, "nand"), RTK_PIN_FUNC(0x2 << 2, "emmc"), - RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_misc")), RTK_PIN_MUX(nf_rd_n, 0x60, GENMASK(5, 4), RTK_PIN_FUNC(0x0 << 4, "gpio"), RTK_PIN_FUNC(0x1 << 4, "nand"), RTK_PIN_FUNC(0x2 << 4, "emmc"), - RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_misc")), RTK_PIN_MUX(nf_wr_n, 0x60, GENMASK(7, 6), RTK_PIN_FUNC(0x0 << 6, "gpio"), RTK_PIN_FUNC(0x1 << 6, "nand"), RTK_PIN_FUNC(0x2 << 6, "emmc"), - RTK_PIN_FUNC(0x3 << 6, "hif")), + RTK_PIN_FUNC(0x3 << 6, "hif_nf")), RTK_PIN_MUX(nf_ale, 0x60, GENMASK(9, 8), RTK_PIN_FUNC(0x0 << 8, "gpio"), RTK_PIN_FUNC(0x1 << 8, "nand"), RTK_PIN_FUNC(0x2 << 8, "emmc"), - RTK_PIN_FUNC(0x3 << 8, "hif")), + RTK_PIN_FUNC(0x3 << 8, "hif_nf")), RTK_PIN_MUX(nf_cle, 0x60, GENMASK(11, 10), RTK_PIN_FUNC(0x0 << 10, "gpio"), RTK_PIN_FUNC(0x1 << 10, "nand"), RTK_PIN_FUNC(0x2 << 10, "emmc"), - RTK_PIN_FUNC(0x3 << 10, "hif")), + RTK_PIN_FUNC(0x3 << 10, "hif_nf")), RTK_PIN_MUX(nf_ce_n_0, 0x60, GENMASK(13, 12), RTK_PIN_FUNC(0x0 << 12, "gpio"), RTK_PIN_FUNC(0x1 << 12, "nand")), @@ -675,22 +787,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_FUNC(0x0 << 24, "gpio"), RTK_PIN_FUNC(0x1 << 24, "nand"), RTK_PIN_FUNC(0x2 << 24, "emmc"), - RTK_PIN_FUNC(0x3 << 24, "hif")), + RTK_PIN_FUNC(0x3 << 24, "hif_nf")), RTK_PIN_MUX(nf_dd_5, 0x60, GENMASK(27, 26), RTK_PIN_FUNC(0x0 << 26, "gpio"), RTK_PIN_FUNC(0x1 << 26, "nand"), RTK_PIN_FUNC(0x2 << 26, "emmc"), - RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag_misc")), RTK_PIN_MUX(nf_dd_6, 0x60, GENMASK(29, 28), RTK_PIN_FUNC(0x0 << 28, "gpio"), RTK_PIN_FUNC(0x1 << 28, "nand"), RTK_PIN_FUNC(0x2 << 28, "emmc"), - RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag_misc")), RTK_PIN_MUX(nf_dd_7, 0x60, GENMASK(31, 30), RTK_PIN_FUNC(0x0 << 30, "gpio"), RTK_PIN_FUNC(0x1 << 30, "nand"), RTK_PIN_FUNC(0x2 << 30, "emmc"), - RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag")), + RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag_misc")), RTK_PIN_MUX(sdio_cmd, 0x64, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), @@ -714,22 +826,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_MUX(mmc_cmd, 0x64, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "gpio"), RTK_PIN_FUNC(0x1 << 16, "mmc"), - RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag")), + RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag_cr")), RTK_PIN_MUX(mmc_clk, 0x64, GENMASK(19, 18), RTK_PIN_FUNC(0x0 << 18, "gpio"), RTK_PIN_FUNC(0x1 << 18, "mmc"), - RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag")), + RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag_cr")), RTK_PIN_MUX(mmc_wp, 0x64, GENMASK(21, 20), RTK_PIN_FUNC(0x0 << 20, "gpio"), RTK_PIN_FUNC(0x1 << 20, "mmc"), - RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag")), + RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag_cr")), RTK_PIN_MUX(mmc_cd, 0x64, GENMASK(23, 22), RTK_PIN_FUNC(0x0 << 22, "gpio"), RTK_PIN_FUNC(0x1 << 22, "mmc")), RTK_PIN_MUX(mmc_data_0, 0x64, GENMASK(25, 24), RTK_PIN_FUNC(0x0 << 24, "gpio"), RTK_PIN_FUNC(0x1 << 24, "mmc"), - RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag")), + RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag_cr")), RTK_PIN_MUX(mmc_data_1, 0x64, GENMASK(27, 26), RTK_PIN_FUNC(0x0 << 26, "gpio"), RTK_PIN_FUNC(0x1 << 26, "mmc")), @@ -739,28 +851,28 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_MUX(mmc_data_3, 0x64, GENMASK(31, 30), RTK_PIN_FUNC(0x0 << 30, "gpio"), RTK_PIN_FUNC(0x1 << 30, "mmc"), - RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag")), + RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag_cr")), RTK_PIN_MUX(tp0_data, 0x68, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "tp0"), RTK_PIN_FUNC(0x1 << 0, "tp1"), RTK_PIN_FUNC(0x2 << 0, "gpio"), - RTK_PIN_FUNC(0x3 << 0, "ao")), + RTK_PIN_FUNC(0x3 << 0, "ao_tp0")), RTK_PIN_MUX(tp0_sync, 0x68, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "tp0"), RTK_PIN_FUNC(0x1 << 2, "tp1"), RTK_PIN_FUNC(0x2 << 2, "gpio"), - RTK_PIN_FUNC(0x3 << 2, "ao")), + RTK_PIN_FUNC(0x3 << 2, "ao_tp0")), RTK_PIN_MUX(tp0_valid, 0x68, GENMASK(5, 4), RTK_PIN_FUNC(0x0 << 4, "tp0"), RTK_PIN_FUNC(0x1 << 4, "tp1"), RTK_PIN_FUNC(0x2 << 4, "gpio"), - RTK_PIN_FUNC(0x3 << 4, "ao")), + RTK_PIN_FUNC(0x3 << 4, "ao_tp0")), RTK_PIN_MUX(tp0_clk, 0x68, GENMASK(7, 6), RTK_PIN_FUNC(0x0 << 6, "tp0"), RTK_PIN_FUNC(0x1 << 6, "tp1"), RTK_PIN_FUNC(0x2 << 6, "gpio"), - RTK_PIN_FUNC(0x3 << 6, "ao")), + RTK_PIN_FUNC(0x3 << 6, "ao_tp0")), RTK_PIN_MUX(tp1_data, 0x68, GENMASK(17, 16), RTK_PIN_FUNC(0x0 << 16, "tp1"), RTK_PIN_FUNC(0x1 << 16, "tp0"), @@ -810,8 +922,12 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_MUX(usb_id, 0x6c, GENMASK(17, 16), RTK_PIN_FUNC(0x1 << 16, "gpio"), RTK_PIN_FUNC(0x2 << 16, "cpu_loop")), - /* hi_loc */ - /* ejtag_scpu_loc */ + RTK_PIN_MUX(hif_loc, 0x6c, GENMASK(19, 18), + RTK_PIN_FUNC(0x1 << 18, "hif_misc"), + RTK_PIN_FUNC(0x2 << 18, "hif_nf")), + RTK_PIN_MUX(ejtag_scpu_loc, 0x6c, GENMASK(21, 20), + RTK_PIN_FUNC(0x1 << 20, "scpu_ejtag_gpio"), + RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_cr")), RTK_PIN_MUX(sensor_stb_1, 0x6c, GENMASK(23, 22), RTK_PIN_FUNC(0x0 << 22, "gpio")), RTK_PIN_MUX(sensor_stb_0, 0x6c, GENMASK(25, 24), @@ -829,47 +945,113 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_MUX(gpio_0, 0x70, GENMASK(2, 0), RTK_PIN_FUNC(0x1 << 0, "gpio"), RTK_PIN_FUNC(0x2 << 0, "uart1"), - RTK_PIN_FUNC(0x3 << 0, "hif"), + RTK_PIN_FUNC(0x3 << 0, "hif_misc"), RTK_PIN_FUNC(0x4 << 0, "gspi")), RTK_PIN_MUX(gpio_1, 0x70, GENMASK(5, 3), RTK_PIN_FUNC(0x1 << 3, "gpio"), RTK_PIN_FUNC(0x2 << 3, "uart1"), - RTK_PIN_FUNC(0x3 << 3, "hif"), + RTK_PIN_FUNC(0x3 << 3, "hif_misc"), RTK_PIN_FUNC(0x4 << 3, "gspi")), RTK_PIN_MUX(gpio_2, 0x70, GENMASK(8, 6), RTK_PIN_FUNC(0x1 << 6, "gpio"), RTK_PIN_FUNC(0x2 << 6, "uart1"), - RTK_PIN_FUNC(0x3 << 6, "hif"), + RTK_PIN_FUNC(0x3 << 6, "hif_misc"), RTK_PIN_FUNC(0x4 << 6, "gspi")), RTK_PIN_MUX(gpio_3, 0x70, GENMASK(11, 9), RTK_PIN_FUNC(0x1 << 9, "gpio"), RTK_PIN_FUNC(0x2 << 9, "uart1"), - RTK_PIN_FUNC(0x3 << 9, "hif"), + RTK_PIN_FUNC(0x3 << 9, "hif_misc"), RTK_PIN_FUNC(0x4 << 9, "gspi")), RTK_PIN_MUX(gpio_4, 0x70, GENMASK(13, 12), RTK_PIN_FUNC(0x1 << 12, "gpio"), - RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag"), - RTK_PIN_FUNC(0x3 << 12, "ao")), + RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag_gpio"), + RTK_PIN_FUNC(0x3 << 12, "ao_gpio")), RTK_PIN_MUX(gpio_5, 0x70, GENMASK(15, 14), RTK_PIN_FUNC(0x1 << 14, "gpio"), - RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag"), - RTK_PIN_FUNC(0x3 << 14, "ao")), + RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag_gpio"), + RTK_PIN_FUNC(0x3 << 14, "ao_gpio")), RTK_PIN_MUX(gpio_6, 0x70, GENMASK(17, 16), RTK_PIN_FUNC(0x1 << 16, "gpio"), - RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag"), - RTK_PIN_FUNC(0x3 << 16, "ao")), + RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag_gpio"), + RTK_PIN_FUNC(0x3 << 16, "ao_gpio")), RTK_PIN_MUX(gpio_7, 0x70, GENMASK(19, 18), RTK_PIN_FUNC(0x1 << 18, "gpio"), - RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag"), - RTK_PIN_FUNC(0x3 << 18, "ao")), + RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag_gpio"), + RTK_PIN_FUNC(0x3 << 18, "ao_gpio")), RTK_PIN_MUX(gpio_8, 0x70, GENMASK(21, 20), RTK_PIN_FUNC(0x1 << 20, "gpio"), - RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag")), + RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_gpio")), + RTK_PIN_MUX(ao_loc, 0x74, GENMASK(3, 2), + RTK_PIN_FUNC(0x1 << 2, "ao_tp0"), + RTK_PIN_FUNC(0x2 << 2, "ao_gpio")), +}; - /* sf_en */ - /* ao_loc */ +static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = { + RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_rdy, 0x78, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_rd_n, 0x78, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_wr_n, 0x78, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_cle, 0x78, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_0, 0x7c, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_1, 0x7c, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_2, 0x7c, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_3, 0x7c, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_4, 0x7c, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_5, 0x7c, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_6, 0x7c, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(nf_dd_7, 0x7c, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_cmd, 0x80, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_clk, 0x80, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_wp, 0x80, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_cd, 0x80, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_data_0, 0x80, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_data_1, 0x80, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_data_2, 0x80, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(mmc_data_3, 0x80, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_cmd, 0x84, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_clk, 0x84, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_wp, 0x84, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_cd, 0x84, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_data_0, 0x84, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_data_1, 0x84, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_data_2, 0x84, 24, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(sdio_data_3, 0x84, 28, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(spdif, 0x88, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp0_clk, 0x8c, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp0_sync, 0x8c, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp0_valid, 0x8c, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp0_data, 0x8c, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp1_clk, 0x90, 0, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp1_sync, 0x90, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp1_valid, 0x90, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(tp1_data, 0x90, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(i2c_sda_1, 0x94, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_1, 0x94, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_4, 0x94, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_4, 0x94, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_sda_5, 0x94, 16, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(i2c_scl_5, 0x94, 20, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_0, 0x98, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_1, 0x98, 4, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_2, 0x98, 8, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_3, 0x98, 12, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(gpio_4, 0x98, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(gpio_5, 0x98, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(gpio_6, 0x98, 24, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(gpio_7, 0x98, 28, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(gpio_8, 0x9c, 0, 1, 0, 2, 3, PADDRI_4_8), + RTK_PIN_CONFIG(hdmi_hpd, 0x9c, 4, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(usb_id, 0x9c, 8, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(sensor_stb_0, 0x9c, 12, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(sensor_stb_1, 0x9c, 16, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(sensor_rst, 0x9c, 20, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(sensor_cko_0, 0x9c, 24, 1, 0, 2, 3, PADDRI_2_4), + RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4), }; + static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = { .pins = rtd1195_crt_pins, .num_pins = ARRAY_SIZE(rtd1195_crt_pins), @@ -879,6 +1061,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = { .num_functions = ARRAY_SIZE(rtd1195_crt_pin_functions), .muxes = rtd1195_crt_muxes, .num_muxes = ARRAY_SIZE(rtd1195_crt_muxes), + .configs = rtd1195_crt_configs, + .num_configs = ARRAY_SIZE(rtd1195_crt_configs), }; #endif From patchwork Thu May 14 09:21:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5dt1q3Xz9sVF for ; Thu, 14 May 2020 19:21:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725970AbgENJVs (ORCPT ); Thu, 14 May 2020 05:21:48 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52954 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725925AbgENJVs (ORCPT ); Thu, 14 May 2020 05:21:48 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LQV60025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LQV60025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXDAG01.realtek.com.tw (172.21.6.100) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXDAG01.realtek.com.tw (172.21.6.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:25 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:25 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 4/7] dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1195 and rtd1295. Date: Thu, 14 May 2020 17:21:22 +0800 Message-ID: <20200514092125.6875-5-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add compatible string for RTD1195 and RTD1295. Signed-off-by: TY Chang --- .../bindings/pinctrl/realtek,rtd-pinctrl.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml new file mode 100644 index 000000000000..5af5fc8fe633 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC pin control + +maintainers: + - Andreas Farber + +properties: + compatible: + enum: + - realtek,rtd1195-iso-pinctrl + - realtek,rtd1195-crt-pinctrl + - realtek,rtd1295-iso-pinctrl + - realtek,rtd1295-sb2-pinctrl + - realtek,rtd1295-disp-pinctrl + - realtek,rtd1295-cr-pinctrl + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + iso_pinctrl: pinctrl@300 { + compatible = "realtek,rtd1195-iso-pinctrl"; + reg = <0x300 0x14>; + } + - | + crt_pinctrl: pinctrl@300 { + compatible = "realtek,rtd1195-crt-pinctrl"; + reg = <0x300 0x78>; + } + - | + iso_pinctrl: pinctrl@300 { + compatible = "realtek,rtd1295-iso-pinctrl"; + reg = <0x300 0x24>; + } + - | + sb2_pinctrl: pinctrl@900 { + compatible = "realtek,rtd1295-sb2-pinctrl"; + reg = <0x900 0x100>; + } + - | + disp_pinctrl: pinctrl@4d000 { + compatible = "realtek,rtd1295-disp-pinctrl"; + reg = <0x4d000 0x100>; + }; + - | + cr_pinctrl: pinctrl@12600 { + compatible = "realtek,rtd1295-cr-pinctrl"; + reg = <0x12600 0x100>; + }; + From patchwork Thu May 14 09:21:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290039 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5f319BNz9sVJ for ; Thu, 14 May 2020 19:22:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726374AbgENJWB (ORCPT ); Thu, 14 May 2020 05:22:01 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52965 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbgENJVz (ORCPT ); Thu, 14 May 2020 05:21:55 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LQV70025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LQV70025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXDAG01.realtek.com.tw (172.21.6.100) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXDAG01.realtek.com.tw (172.21.6.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:26 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 5/7] pinctrl: realtek: DHC: Fix pinctrl driver coding style according to checkpatch.pl. Date: Thu, 14 May 2020 17:21:23 +0800 Message-ID: <20200514092125.6875-6-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix Realtek DHC SoC pinctrl driver coding style. Signed-off-by: TY Chang --- drivers/pinctrl/pinctrl-rtd1195.h | 131 +++++++--- drivers/pinctrl/pinctrl-rtd119x.c | 124 +++++---- drivers/pinctrl/pinctrl-rtd1295.h | 407 ++++++++++++++++++++++-------- 3 files changed, 466 insertions(+), 196 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/pinctrl-rtd1195.h index 9f3471d02221..f0dd91f416e8 100644 --- a/drivers/pinctrl/pinctrl-rtd1195.h +++ b/drivers/pinctrl/pinctrl-rtd1195.h @@ -1,3 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */ + +/* + * Realtek RTD1195 pin controller driver + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + #ifndef PINCTRL_RTD1195_H #define PINCTRL_RTD1195_H @@ -76,15 +84,20 @@ static const unsigned int rtd1195_ur1_cts_n_pins[] = { RTD1195_ISO_UR1_CTS_N }; static const unsigned int rtd1195_ur1_rts_n_pins[] = { RTD1195_ISO_UR1_RTS_N }; static const unsigned int rtd1195_i2c_scl_0_pins[] = { RTD1195_ISO_I2C_SCL_0 }; static const unsigned int rtd1195_i2c_sda_0_pins[] = { RTD1195_ISO_I2C_SDA_0 }; -static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LINK }; -static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX }; +static const unsigned int rtd1195_etn_led_link_pins[] = { + RTD1195_ISO_ETN_LED_LINK }; +static const unsigned int rtd1195_etn_led_rxtx_pins[] = { + RTD1195_ISO_ETN_LED_RXTX }; static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 }; static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 }; static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC }; -static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC }; +static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { + RTD1195_ISO_EJTAG_AVCPU_LOC }; static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC }; -static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN }; -static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN }; +static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { + RTD1195_ISO_PWM_01_OPEN_DRAIN }; +static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { + RTD1195_ISO_PWM_23_OPEN_DRAIN }; #define RTD1195_GROUP(_name) \ @@ -148,26 +161,46 @@ static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = { "ejtag_avcpu_loc" }; - -static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" }; -static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" }; +static const char * const rtd1195_iso_etn_led_groups[] = { + "etn_led_link", "etn_led_rxtx" +}; +static const char * const rtd1195_iso_i2c0_groups[] = { + "i2c_scl_0", "i2c_sda_0" +}; static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" }; static const char * const rtd1195_iso_i2c3_groups[] = { "ir_tx" }; -static const char * const rtd1195_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6" }; +static const char * const rtd1195_iso_i2c6_groups[] = { + "i2c_scl_6", "i2c_sda_6" +}; static const char * const rtd1195_iso_ir_rx_groups[] = { "ir_rx" }; static const char * const rtd1195_iso_ir_tx_groups[] = { "ir_tx" }; static const char * const rtd1195_iso_pwm_groups[] = { "ur0_rx", "ur0_tx", "ur1_rx", "ur1_tx", "etn_led_link", "etn_led_rxtx" }; -static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" }; +static const char * const rtd1195_iso_standby_dbg_groups[] = { + "ir_rx", "usb0", "usb1" +}; static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" }; -static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" }; +static const char * const rtd1195_iso_uart1_groups[] = { + "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" +}; static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" }; -static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" }; -static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" }; -static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" }; -static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" }; -static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" }; +static const char * const rtd1195_iso_vfd_groups[] = { + "vfd_cs_n", "vfd_clk", "vfd_d" +}; +static const char * const rtd1195_iso_pwm_01_normal_groups[] = { + "pwm_01_open_drain" +}; +static const char * const rtd1195_iso_pwm_23_normal_groups[] = { + "pwm_23_open_drain" +}; +static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { + "pwm_01_open_drain" +}; +static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { + "pwm_23_open_drain" + +}; @@ -527,12 +560,17 @@ static const unsigned int rtd1195_i2c_scl_1_pins[] = { RTD1195_I2C_SCL_1 }; static const unsigned int rtd1195_i2c_sda_1_pins[] = { RTD1195_I2C_SDA_1 }; static const unsigned int rtd1195_i2c_scl_4_pins[] = { RTD1195_I2C_SCL_4 }; static const unsigned int rtd1195_i2c_sda_4_pins[] = { RTD1195_I2C_SDA_4 }; -static const unsigned int rtd1195_sensor_cko_0_pins[] = { RTD1195_SENSOR_CKO_0 }; -static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 }; +static const unsigned int rtd1195_sensor_cko_0_pins[] = { + RTD1195_SENSOR_CKO_0 }; +static const unsigned int rtd1195_sensor_cko_1_pins[] = { + RTD1195_SENSOR_CKO_1 }; static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST }; -static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 }; -static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 }; -static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC }; +static const unsigned int rtd1195_sensor_stb_0_pins[] = { + RTD1195_SENSOR_STB_0 }; +static const unsigned int rtd1195_sensor_stb_1_pins[] = { + RTD1195_SENSOR_STB_1 }; +static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { + RTD1195_EJTAG_SCPU_LOC }; static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC }; static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC }; @@ -617,11 +655,14 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = { static const char * const rtd1195_crt_gpio_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", - "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", - "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1", + "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", + "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", + "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", + "nf_cle", "nf_ce_n_0", "nf_ce_n_1", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd", - "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd", + "sdio_clk", "sdio_data_0", "sdio_data_1", + "sdio_data_2", "sdio_data_3", "sdio_cmd", "i2c_scl_5", "i2c_sda_5", "tp1_data", "tp1_clk", "tp1_valid", "tp1_sync", "tp0_data", "tp0_clk", "tp0_valid", "tp0_sync", @@ -649,7 +690,8 @@ static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = { }; static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" }; static const char * const rtd1195_crt_emmc_groups[] = { - "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", + "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", + "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", }; static const char * const rtd1195_crt_gspi_groups[] = { @@ -664,30 +706,45 @@ static const char * const rtd1195_crt_hif_misc_groups[] = { }; -static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" }; -static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" }; -static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" }; -static const char * const rtd1195_crt_i2c4_groups[] = { "i2c_scl_4", "i2c_sda_4" }; -static const char * const rtd1195_crt_i2c5_groups[] = { "i2c_scl_5", "i2c_sda_5" }; +static const char * const rtd1195_crt_i2c1_groups[] = { + "i2c_scl_1", "i2c_sda_1" +}; +static const char * const rtd1195_crt_i2c2_groups[] = { + "tp1_sync", "tp1_clk" +}; +static const char * const rtd1195_crt_i2c3_groups[] = { + "tp1_data", "tp1_valid" }; +static const char * const rtd1195_crt_i2c4_groups[] = { + "i2c_scl_4", "i2c_sda_4" +}; +static const char * const rtd1195_crt_i2c5_groups[] = { + "i2c_scl_5", "i2c_sda_5" +}; static const char * const rtd1195_crt_mmc_groups[] = { "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd", }; static const char * const rtd1195_crt_nand_groups[] = { - "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", - "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1", + "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", + "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", + "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", + "nf_cle", "nf_ce_n_0", "nf_ce_n_1", }; static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" }; static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = { - "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc" + "mmc_data_0", "mmc_data_3", "mmc_clk", + "mmc_cmd", "mmc_wp", "ejtag_scpu_loc" }; static const char * const rtd1195_crt_sdio_groups[] = { - "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd", + "sdio_clk", "sdio_data_0", "sdio_data_1", + "sdio_data_2", "sdio_data_3", "sdio_cmd", +}; +static const char * const rtd1195_crt_sensor_groups[] = { + "sensor_cko_0", "sensor_cko_1" }; -static const char * const rtd1195_crt_sensor_groups[] = { "sensor_cko_0", "sensor_cko_1" }; static const char * const rtd1195_crt_spdif_groups[] = { "spdif" }; static const char * const rtd1195_crt_tp0_groups[] = { "tp0_data", "tp0_clk", "tp0_valid", "tp0_sync", @@ -695,7 +752,9 @@ static const char * const rtd1195_crt_tp0_groups[] = { static const char * const rtd1195_crt_tp1_groups[] = { "tp1_data", "tp1_clk", "tp1_valid", "tp1_sync", }; -static const char * const rtd1195_crt_uart1_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" }; +static const char * const rtd1195_crt_uart1_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3" +}; static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" }; #define RTD1195_FUNC(_name) \ diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c index 52b16d610e13..bda0d1328eb8 100644 --- a/drivers/pinctrl/pinctrl-rtd119x.c +++ b/drivers/pinctrl/pinctrl-rtd119x.c @@ -1,9 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + /* - * Copyright (c) 2017 Andreas Färber + * Realtek DHC pin controller driver * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (c) 2019 Realtek Semiconductor Corp. */ + #include #include #include @@ -120,7 +123,7 @@ static int rtd119x_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) } static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev, - unsigned selector) + unsigned int selector) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); @@ -128,7 +131,8 @@ static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev, } static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, - unsigned selector, const unsigned **pins, unsigned *num_pins) + unsigned int selector, const unsigned int **pins, + unsigned int *num_pins) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); @@ -154,7 +158,7 @@ static int rtd119x_pinctrl_get_functions_count(struct pinctrl_dev *pcdev) } static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev, - unsigned selector) + unsigned int selector) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); @@ -162,8 +166,8 @@ static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev, } static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, - unsigned selector, const char * const **groups, - unsigned * const num_groups) + unsigned int selector, const char * const **groups, + unsigned int * const num_groups) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); @@ -173,7 +177,8 @@ static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, return 0; } -static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(struct rtd119x_pinctrl *data, int number) +static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number( + struct rtd119x_pinctrl *data, int number) { int i; @@ -185,7 +190,8 @@ static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(struct r return NULL; } -static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pinctrl *data, const char *name) +static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux( + struct rtd119x_pinctrl *data, const char *name) { int i; @@ -197,7 +203,8 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pi return NULL; } -static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(struct rtd119x_pinctrl *data, const char *name) +static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config( + struct rtd119x_pinctrl *data, const char *name) { int i; @@ -231,7 +238,8 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, return -ENOTSUPP; if (!mux->functions) { - dev_err(pcdev->dev, "No functions available for pin %s\n", pin_name); + dev_err(pcdev->dev, + "No functions available for pin %s\n", pin_name); return -ENOTSUPP; } @@ -246,12 +254,13 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, return 0; } - dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, pin_name); + dev_err(pcdev->dev, "No function %s available for pin %s\n", + func_name, pin_name); return -EINVAL; } static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, - unsigned function, unsigned group) + unsigned int function, unsigned int group) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); const unsigned int *pins; @@ -265,7 +274,8 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, ret = rtd119x_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); if (ret) { - dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); + dev_err(pcdev->dev, "Getting pins for group %s failed\n", + group_name); return ret; } @@ -279,7 +289,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, } static int rtd119x_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev, - struct pinctrl_gpio_range *range, unsigned offset) + struct pinctrl_gpio_range *range, unsigned int offset) { return rtd119x_pinctrl_set_one_mux(pcdev, offset, "gpio"); } @@ -292,10 +302,9 @@ static const struct pinmux_ops rtd119x_pinmux_ops = { .gpio_request_enable = rtd119x_pinctrl_gpio_request_enable, }; - static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, - const struct rtd119x_pin_config_desc *config_desc, enum pin_config_param param, - enum pin_config_param arg) + const struct rtd119x_pin_config_desc *config_desc, + enum pin_config_param param, enum pin_config_param arg) { u8 set_val = 0; u16 strength; @@ -341,9 +350,9 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, return -EINVAL; break; case PCONF_UNSUPP: - pr_err("[%s] not support drive strength\n", config_desc->name); + dev_err(data->pcdev->dev, "[%s] not support drive strength\n", + config_desc->name); return -ENOTSUPP; - break; default: return -EINVAL; } @@ -383,7 +392,7 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, return 0; } -static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr, +static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, unsigned long *config) { unsigned int param = pinconf_to_config_param(*config); @@ -398,8 +407,8 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr, return 0; } -static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned pinnr, - unsigned long *configs, unsigned num_configs) +static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, + unsigned long *configs, unsigned int num_configs) { struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); const struct rtd119x_pin_config_desc *config_desc; @@ -436,55 +445,66 @@ static const struct pinconf_ops rtd119x_pinconf_ops = { static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data) { int i, j, k; + const struct rtd119x_pinctrl_desc *info = data->info; - for (i = 0; i < data->info->num_muxes; i++) { + for (i = 0; i < info->num_muxes; i++) { /* Check for pin */ - for (j = 0; j < data->info->num_pins; j++) { - if (strcmp(data->info->pins[j].name, data->info->muxes[i].name) == 0) + for (j = 0; j < info->num_pins; j++) { + if (strcmp(info->pins[j].name, + info->muxes[i].name) == 0) break; } - if (j == data->info->num_pins) + if (j == info->num_pins) dev_warn(data->pcdev->dev, "Mux %s lacking matching pin\n", - data->info->muxes[i].name); + info->muxes[i].name); /* Check for group */ - for (j = 0; j < data->info->num_groups; j++) { - if (strcmp(data->info->groups[j].name, data->info->muxes[i].name) == 0) + for (j = 0; j < info->num_groups; j++) { + if (strcmp(info->groups[j].name, + info->muxes[i].name) == 0) break; } - if (j == data->info->num_groups) + if (j == info->num_groups) dev_warn(data->pcdev->dev, "Mux %s lacking matching group\n", - data->info->muxes[i].name); + info->muxes[i].name); - for (j = 0; data->info->muxes[i].functions[j].name; j++) { + for (j = 0; info->muxes[i].functions[j].name; j++) { /* Check for function */ - for (k = 0; k < data->info->num_functions; k++) { - if (strcmp(data->info->functions[k].name, - data->info->muxes[i].functions[j].name) == 0) + for (k = 0; k < info->num_functions; k++) { + if (strcmp(info->functions[k].name, + info->muxes[i].functions[j].name) == 0) break; } - if (k == data->info->num_functions) + if (k == info->num_functions) dev_warn(data->pcdev->dev, "Mux %s lacking function %s\n", - data->info->muxes[i].name, - data->info->muxes[i].functions[j].name); - - /* Check for duplicate mux value - assumption: ascending order */ - if (j > 0 && data->info->muxes[i].functions[j].mux_value - < data->info->muxes[i].functions[j - 1].mux_value) + info->muxes[i].name, + info->muxes[i].functions[j].name); + + /* Check for duplicate mux value + *- assumption: ascending order + */ + if (j > 0 && info->muxes[i].functions[j].mux_value + < info->muxes[i].functions[j - 1].mux_value) dev_warn(data->pcdev->dev, "Mux %s function %s has unexpected value\n", - data->info->muxes[i].name, - data->info->muxes[i].functions[j].name); + info->muxes[i].name, + info->muxes[i].functions[j].name); } } } static const struct of_device_id rtd119x_pinctrl_dt_ids[] = { - { .compatible = "realtek,rtd1195-iso-pinctrl", .data = &rtd1195_iso_pinctrl_desc }, - { .compatible = "realtek,rtd1195-crt-pinctrl", .data = &rtd1195_crt_pinctrl_desc }, - { .compatible = "realtek,rtd1295-iso-pinctrl", .data = &rtd1295_iso_pinctrl_desc }, - { .compatible = "realtek,rtd1295-sb2-pinctrl", .data = &rtd1295_sb2_pinctrl_desc }, - { .compatible = "realtek,rtd1295-disp-pinctrl", .data = &rtd1295_disp_pinctrl_desc }, - { .compatible = "realtek,rtd1295-cr-pinctrl", .data = &rtd1295_cr_pinctrl_desc }, + { .compatible = "realtek,rtd1195-iso-pinctrl", + .data = &rtd1195_iso_pinctrl_desc }, + { .compatible = "realtek,rtd1195-crt-pinctrl", + .data = &rtd1195_crt_pinctrl_desc }, + { .compatible = "realtek,rtd1295-iso-pinctrl", + .data = &rtd1295_iso_pinctrl_desc }, + { .compatible = "realtek,rtd1295-sb2-pinctrl", + .data = &rtd1295_sb2_pinctrl_desc }, + { .compatible = "realtek,rtd1295-disp-pinctrl", + .data = &rtd1295_disp_pinctrl_desc }, + { .compatible = "realtek,rtd1295-cr-pinctrl", + .data = &rtd1295_cr_pinctrl_desc }, { } }; @@ -537,3 +557,5 @@ static struct platform_driver rtd119x_pinctrl_driver = { }, }; builtin_platform_driver(rtd119x_pinctrl_driver); +MODULE_DESCRIPTION("rtk pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h index 0232c5d8b353..f27debc96bb6 100644 --- a/drivers/pinctrl/pinctrl-rtd1295.h +++ b/drivers/pinctrl/pinctrl-rtd1295.h @@ -1,3 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */ + +/* + * Realtek pin controller driver + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + #ifndef PINCTRL_RTD1295_H #define PINCTRL_RTD1295_H @@ -116,8 +124,10 @@ static const unsigned int rtd1295_iso_gpio_23_pins[] = { RTD1295_ISO_GPIO_23 }; static const unsigned int rtd1295_iso_gpio_24_pins[] = { RTD1295_ISO_GPIO_24 }; static const unsigned int rtd1295_iso_gpio_25_pins[] = { RTD1295_ISO_GPIO_25 }; static const unsigned int rtd1295_i2c_sda_6_pins[] = { RTD1295_I2C_SDA_6 }; -static const unsigned int rtd1295_etn_led_link_pins[] = { RTD1295_ETN_LED_LINK }; -static const unsigned int rtd1295_etn_led_rxtx_pins[] = { RTD1295_ETN_LED_RXTX }; +static const unsigned int rtd1295_etn_led_link_pins[] = { + RTD1295_ETN_LED_LINK }; +static const unsigned int rtd1295_etn_led_rxtx_pins[] = { + RTD1295_ETN_LED_RXTX }; static const unsigned int rtd1295_nat_led_0_pins[] = { RTD1295_NAT_LED_0 }; static const unsigned int rtd1295_nat_led_1_pins[] = { RTD1295_NAT_LED_1 }; static const unsigned int rtd1295_nat_led_2_pins[] = { RTD1295_NAT_LED_2 }; @@ -128,16 +138,31 @@ static const unsigned int rtd1295_pwm_23_loc0_pins[] = { RTD1295_PWM_23_LOC0 }; static const unsigned int rtd1295_pwm_01_loc0_pins[] = { RTD1295_PWM_01_LOC0 }; static const unsigned int rtd1295_pwm_23_loc1_pins[] = { RTD1295_PWM_23_LOC1 }; static const unsigned int rtd1295_pwm_01_loc1_pins[] = { RTD1295_PWM_01_LOC1 }; -static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = { RTD1295_EJTAG_AVCPU_LOC }; +static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = { + RTD1295_EJTAG_AVCPU_LOC }; static const unsigned int rtd1295_ur2_loc_pins[] = { RTD1295_UR2_LOC }; -static const unsigned int rtd1295_i2c0_pins[] = { RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0 }; -static const unsigned int rtd1295_i2c1_pins[] = { RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1 }; -static const unsigned int rtd1295_i2c6_pins[] = { RTD1295_I2C_SCL_6, RTD1295_I2C_SDA_6 }; -static const unsigned int rtd1295_uart0_pins[] = { RTD1295_UR0_RX, RTD1295_UR0_TX }; -static const unsigned int rtd1295_uart1_pins[] = { RTD1295_UR1_RX, RTD1295_UR1_TX }; -static const unsigned int rtd1295_uart2_0_pins[] = { RTD1295_ISO_GPIO_2, RTD1295_ISO_GPIO_3, RTD1295_ISO_GPIO_4, RTD1295_ISO_GPIO_5 }; -static const unsigned int rtd1295_uart2_1_pins[] = { RTD1295_ISO_GPIO_23, RTD1295_ISO_GPIO_24, RTD1295_ISO_GPIO_33, RTD1295_ISO_GPIO_34 }; +static const unsigned int rtd1295_i2c0_pins[] = { + RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0 +}; +static const unsigned int rtd1295_i2c1_pins[] = { + RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1 +}; +static const unsigned int rtd1295_i2c6_pins[] = { + RTD1295_I2C_SCL_6, RTD1295_I2C_SDA_6 +}; +static const unsigned int rtd1295_uart0_pins[] = { + RTD1295_UR0_RX, RTD1295_UR0_TX }; +static const unsigned int rtd1295_uart1_pins[] = { + RTD1295_UR1_RX, RTD1295_UR1_TX }; +static const unsigned int rtd1295_uart2_0_pins[] = { + RTD1295_ISO_GPIO_2, RTD1295_ISO_GPIO_3, + RTD1295_ISO_GPIO_4, RTD1295_ISO_GPIO_5 +}; +static const unsigned int rtd1295_uart2_1_pins[] = { + RTD1295_ISO_GPIO_23, RTD1295_ISO_GPIO_24, + RTD1295_ISO_GPIO_33, RTD1295_ISO_GPIO_34 +}; #define RTD1295_GROUP(_name) \ { \ @@ -199,41 +224,90 @@ static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = { }; static const char * const rtd1295_iso_gpio_groups[] = { - "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "hdmi_hpd", "iso_gpio_7", - "ir_rx", "ir_tx", "ur0_rx", "ur0_tx", "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", + "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", + "iso_gpio_5", "hdmi_hpd", "iso_gpio_7", + "ir_rx", "ir_tx", "ur0_rx", "ur0_tx", + "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "i2c_scl_0", "i2c_sda_0", "i2c_scl_1", "i2c_sda_1", "i2c_scl_6", - "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24", "iso_gpio_25", + "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", + "iso_gpio_24", "iso_gpio_25", "i2c_sda_6", "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3", "iso_gpio_33", "iso_gpio_34" }; -static const char * const rtd1295_iso_acpu_ejtag_loc_iso_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "iso_gpio_7" }; +static const char * const rtd1295_iso_acpu_ejtag_loc_iso_groups[] = { + "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "iso_gpio_7" +}; static const char * const rtd1295_iso_edp_hpd_groups[] = { "iso_gpio_7" }; -static const char * const rtd1295_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" }; -static const char * const rtd1295_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0", "i2c0" }; -static const char * const rtd1295_iso_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1", "i2c1" }; -static const char * const rtd1295_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6", "i2c6" }; +static const char * const rtd1295_iso_etn_led_groups[] = { + "etn_led_link", "etn_led_rxtx" +}; +static const char * const rtd1295_iso_i2c0_groups[] = { + "i2c_scl_0", "i2c_sda_0", "i2c0" +}; +static const char * const rtd1295_iso_i2c1_groups[] = { + "i2c_scl_1", "i2c_sda_1", "i2c1" +}; +static const char * const rtd1295_iso_i2c6_groups[] = { + "i2c_scl_6", "i2c_sda_6", "i2c6" +}; static const char * const rtd1295_iso_ir_rx_groups[] = { "ir_rx" }; static const char * const rtd1295_iso_ir_tx_groups[] = { "ir_tx" }; -static const char * const rtd1295_iso_nat_led_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" }; -static const char * const rtd1295_iso_pwm_1_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" }; -static const char * const rtd1295_iso_pwm_0_groups[] = { "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24" }; +static const char * const rtd1295_iso_nat_led_groups[] = { + "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" +}; +static const char * const rtd1295_iso_pwm_1_groups[] = { + "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" +}; +static const char * const rtd1295_iso_pwm_0_groups[] = { + "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24" +}; static const char * const rtd1295_iso_rtc_groups[] = { "iso_gpio_25" }; -static const char * const rtd1295_iso_sc_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" }; -static const char * const rtd1295_iso_standby_dbg_groups[] = { "iso_gpio_2", "iso_gpio_3", "ir_rx" }; -static const char * const rtd1295_iso_uart0_groups[] = { "ur0_rx", "ur0_tx", "uart0" }; -static const char * const rtd1295_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1" }; -static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc" }; -static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc" }; -static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = { "pwm_01_loc0" }; -static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = { "pwm_23_loc0" }; -static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = { "pwm_01_loc0" }; -static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = { "pwm_23_loc0" }; -static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = { "pwm_01_loc1" }; -static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = { "pwm_23_loc1" }; -static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = { "pwm_01_loc1" }; -static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = { "pwm_23_loc1" }; -static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { "ejtag_avcpu_loc" }; +static const char * const rtd1295_iso_sc_groups[] = { + "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" +}; +static const char * const rtd1295_iso_standby_dbg_groups[] = { + "iso_gpio_2", "iso_gpio_3", "ir_rx" +}; +static const char * const rtd1295_iso_uart0_groups[] = { + "ur0_rx", "ur0_tx", "uart0" +}; +static const char * const rtd1295_iso_uart1_groups[] = { + "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1" +}; +static const char * const rtd1295_iso_uart2_0_groups[] = { + "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc" +}; +static const char * const rtd1295_iso_uart2_1_groups[] = { + "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc" +}; +static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = { + "pwm_01_loc0" +}; +static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = { + "pwm_23_loc0" +}; +static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = { + "pwm_01_loc0" +}; +static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = { + "pwm_23_loc0" +}; +static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = { + "pwm_01_loc1" +}; +static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = { + "pwm_23_loc1" +}; +static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = { + "pwm_01_loc1" +}; +static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = { + "pwm_23_loc1" +}; +static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { + "ejtag_avcpu_loc" +}; #define RTD1295_FUNC(_name) \ @@ -608,11 +682,15 @@ static const unsigned int rtd1295_i2c_sda_4_pins[] = { RTD1295_I2C_SDA_4 }; static const unsigned int rtd1295_i2c_scl_5_pins[] = { RTD1295_I2C_SCL_5 }; static const unsigned int rtd1295_i2c_sda_5_pins[] = { RTD1295_I2C_SDA_5 }; static const unsigned int rtd1295_usb_id_pins[] = { RTD1295_USB_ID }; -static const unsigned int rtd1295_sensor_cko_0_pins[] = { RTD1295_SENSOR_CKO_0 }; -static const unsigned int rtd1295_sensor_cko_1_pins[] = { RTD1295_SENSOR_CKO_1 }; +static const unsigned int rtd1295_sensor_cko_0_pins[] = { + RTD1295_SENSOR_CKO_0 }; +static const unsigned int rtd1295_sensor_cko_1_pins[] = { + RTD1295_SENSOR_CKO_1 }; static const unsigned int rtd1295_sensor_rst_pins[] = { RTD1295_SENSOR_RST }; -static const unsigned int rtd1295_sensor_stb_0_pins[] = { RTD1295_SENSOR_STB_0 }; -static const unsigned int rtd1295_sensor_stb_1_pins[] = { RTD1295_SENSOR_STB_1 }; +static const unsigned int rtd1295_sensor_stb_0_pins[] = { + RTD1295_SENSOR_STB_0 }; +static const unsigned int rtd1295_sensor_stb_1_pins[] = { + RTD1295_SENSOR_STB_1 }; static const unsigned int rtd1295_tp0_data_pins[] = { RTD1295_TP0_DATA }; static const unsigned int rtd1295_tp0_clk_pins[] = { RTD1295_TP0_CLK }; static const unsigned int rtd1295_tp0_valid_pins[] = { RTD1295_TP0_VALID }; @@ -621,33 +699,54 @@ static const unsigned int rtd1295_tp1_data_pins[] = { RTD1295_TP1_DATA }; static const unsigned int rtd1295_tp1_clk_pins[] = { RTD1295_TP1_CLK }; static const unsigned int rtd1295_tp1_valid_pins[] = { RTD1295_TP1_VALID }; static const unsigned int rtd1295_rgmii0_txc_pins[] = { RTD1295_RGMII0_TXC }; -static const unsigned int rtd1295_rgmii0_tx_ctl_pins[] = { RTD1295_RGMII0_TX_CTL }; -static const unsigned int rtd1295_rgmii0_txd_0_pins[] = { RTD1295_RGMII0_TXD_0 }; -static const unsigned int rtd1295_rgmii0_txd_1_pins[] = { RTD1295_RGMII0_TXD_1 }; -static const unsigned int rtd1295_rgmii0_txd_2_pins[] = { RTD1295_RGMII0_TXD_2 }; -static const unsigned int rtd1295_rgmii0_txd_3_pins[] = { RTD1295_RGMII0_TXD_3 }; +static const unsigned int rtd1295_rgmii0_tx_ctl_pins[] = { + RTD1295_RGMII0_TX_CTL }; +static const unsigned int rtd1295_rgmii0_txd_0_pins[] = { + RTD1295_RGMII0_TXD_0 }; +static const unsigned int rtd1295_rgmii0_txd_1_pins[] = { + RTD1295_RGMII0_TXD_1 }; +static const unsigned int rtd1295_rgmii0_txd_2_pins[] = { + RTD1295_RGMII0_TXD_2 }; +static const unsigned int rtd1295_rgmii0_txd_3_pins[] = { + RTD1295_RGMII0_TXD_3 }; static const unsigned int rtd1295_rgmii0_rxc_pins[] = { RTD1295_RGMII0_RXC }; -static const unsigned int rtd1295_rgmii0_rx_ctl_pins[] = { RTD1295_RGMII0_RX_CTL }; -static const unsigned int rtd1295_rgmii0_rxd_0_pins[] = { RTD1295_RGMII0_RXD_0 }; -static const unsigned int rtd1295_rgmii0_rxd_1_pins[] = { RTD1295_RGMII0_RXD_1 }; -static const unsigned int rtd1295_rgmii0_rxd_2_pins[] = { RTD1295_RGMII0_RXD_2 }; -static const unsigned int rtd1295_rgmii0_rxd_3_pins[] = { RTD1295_RGMII0_RXD_3 }; +static const unsigned int rtd1295_rgmii0_rx_ctl_pins[] = { + RTD1295_RGMII0_RX_CTL }; +static const unsigned int rtd1295_rgmii0_rxd_0_pins[] = { + RTD1295_RGMII0_RXD_0 }; +static const unsigned int rtd1295_rgmii0_rxd_1_pins[] = { + RTD1295_RGMII0_RXD_1 }; +static const unsigned int rtd1295_rgmii0_rxd_2_pins[] = { + RTD1295_RGMII0_RXD_2 }; +static const unsigned int rtd1295_rgmii0_rxd_3_pins[] = { + RTD1295_RGMII0_RXD_3 }; static const unsigned int rtd1295_rgmii0_mdio_pins[] = { RTD1295_RGMII0_MDIO }; static const unsigned int rtd1295_rgmii0_mdc_pins[] = { RTD1295_RGMII0_MDC }; static const unsigned int rtd1295_rgmii1_txc_pins[] = { RTD1295_RGMII1_TXC }; -static const unsigned int rtd1295_rgmii1_tx_ctl_pins[] = { RTD1295_RGMII1_TX_CTL }; -static const unsigned int rtd1295_rgmii1_txd_0_pins[] = { RTD1295_RGMII1_TXD_0 }; -static const unsigned int rtd1295_rgmii1_txd_1_pins[] = { RTD1295_RGMII1_TXD_1 }; -static const unsigned int rtd1295_rgmii1_txd_2_pins[] = { RTD1295_RGMII1_TXD_2 }; -static const unsigned int rtd1295_rgmii1_txd_3_pins[] = { RTD1295_RGMII1_TXD_3 }; +static const unsigned int rtd1295_rgmii1_tx_ctl_pins[] = { + RTD1295_RGMII1_TX_CTL }; +static const unsigned int rtd1295_rgmii1_txd_0_pins[] = { + RTD1295_RGMII1_TXD_0 }; +static const unsigned int rtd1295_rgmii1_txd_1_pins[] = { + RTD1295_RGMII1_TXD_1 }; +static const unsigned int rtd1295_rgmii1_txd_2_pins[] = { + RTD1295_RGMII1_TXD_2 }; +static const unsigned int rtd1295_rgmii1_txd_3_pins[] = { + RTD1295_RGMII1_TXD_3 }; static const unsigned int rtd1295_rgmii1_rxc_pins[] = { RTD1295_RGMII1_RXC }; -static const unsigned int rtd1295_rgmii1_rx_ctl_pins[] = { RTD1295_RGMII1_RX_CTL }; -static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = { RTD1295_RGMII1_RXD_0 }; -static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = { RTD1295_RGMII1_RXD_1 }; -static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = { RTD1295_RGMII1_RXD_2 }; -static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = { RTD1295_RGMII1_RXD_3 }; +static const unsigned int rtd1295_rgmii1_rx_ctl_pins[] = { + RTD1295_RGMII1_RX_CTL }; +static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = { + RTD1295_RGMII1_RXD_0 }; +static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = { + RTD1295_RGMII1_RXD_1 }; +static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = { + RTD1295_RGMII1_RXD_2 }; +static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = { + RTD1295_RGMII1_RXD_3 }; static const unsigned int rtd1295_hif_loc_pins[] = { RTD1295_HI_LOC }; -static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = { RTD1295_EJTAG_SCPU_LOC }; +static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = { + RTD1295_EJTAG_SCPU_LOC }; static const unsigned int rtd1295_sf_en_pins[] = { RTD1295_SF_EN }; static const unsigned int rtd1295_tp0_loc_pins[] = { RTD1295_TP0_LOC }; static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC }; @@ -720,46 +819,96 @@ static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = { }; static const char * const rtd1295_sb2_gpio_groups[] = { - "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", "i2c_scl_4", "i2c_sda_4", "i2c_scl_5", "i2c_sda_5", "usb_id", - "sensor_cko_0", "sensor_cko_1", "sensor_rst", "sensor_stb_0", "sensor_stb_1", + "sensor_cko_0", "sensor_cko_1", "sensor_rst", + "sensor_stb_0", "sensor_stb_1", "tp0_data", "tp0_clk", "tp0_valid", "tp0_sync", "tp1_data", "tp1_clk", "tp1_valid", "tp1_sync", - "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", - "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", + "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", + "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", + "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", + "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "rgmii0_mdio", "rgmii0_mdc", - "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3", - "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3", + "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", + "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3", + "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", + "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3", +}; +static const char * const rtd1295_sb2_ai_groups[] = { + "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" }; -static const char * const rtd1295_sb2_ai_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" }; static const char * const rtd1295_sb2_dc_fan_sensor_groups[] = { "gpio_9" }; -static const char * const rtd1295_sb2_eth_gpy_groups[] = { "rgmii0_mdio", "rgmii0_mdc" }; -static const char * const rtd1295_sb2_gspi_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7" }; -static const char * const rtd1295_sb2_i2c2_groups[] = { "tp1_sync", "tp1_clk" }; -static const char * const rtd1295_sb2_i2c3_groups[] = { "tp1_data", "tp1_valid" }; -static const char * const rtd1295_sb2_i2c4_groups[] = { "i2c_scl_4", "i2c_sda_4" }; -static const char * const rtd1295_sb2_i2c5_groups[] = { "i2c_scl_5", "i2c_sda_5" }; -static const char * const rtd1295_sb2_nand_groups[] = { "i2c_sda_5", "i2c_scl_5" }; +static const char * const rtd1295_sb2_eth_gpy_groups[] = { + "rgmii0_mdio", "rgmii0_mdc" +}; +static const char * const rtd1295_sb2_gspi_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; +static const char * const rtd1295_sb2_i2c2_groups[] = { + "tp1_sync", "tp1_clk" +}; +static const char * const rtd1295_sb2_i2c3_groups[] = { + "tp1_data", "tp1_valid" +}; +static const char * const rtd1295_sb2_i2c4_groups[] = { + "i2c_scl_4", "i2c_sda_4" +}; +static const char * const rtd1295_sb2_i2c5_groups[] = { + "i2c_scl_5", "i2c_sda_5" +}; +static const char * const rtd1295_sb2_nand_groups[] = { + "i2c_sda_5", "i2c_scl_5" +}; static const char * const rtd1295_sb2_rgmii_groups[] = { - "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", - "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", + "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", + "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", + "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", + "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "rgmii0_mdio", "rgmii0_mdc", - "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3", - "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3", + "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", + "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3", + "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", + "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3", }; -static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" }; -static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = { "ejtag_scpu_loc" }; -static const char * const rtd1295_sb2_sensor_cko_output_groups[] = { "sensor_cko_0", "sensor_cko_1" }; -static const char * const rtd1295_sb2_spi_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" }; +static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" +}; +static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = { + "ejtag_scpu_loc" +}; +static const char * const rtd1295_sb2_sensor_cko_output_groups[] = { + "sensor_cko_0", "sensor_cko_1" +}; +static const char * const rtd1295_sb2_spi_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3" +}; static const char * const rtd1295_sb2_test_loop_dis_groups[] = { "usb_id" }; -static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", "tp0_loc" }; -static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" }; -static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" }; -static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "tp1_loc" }; -static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" }; -static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" }; -static const char * const rtd1295_sb2_usb_clock_output_groups[] = { "sensor_cko_1" }; +static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { + "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", + "rgmii0_txd_3", "tp0_loc" +}; +static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { + "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" +}; +static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { + "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" +}; +static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { + "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", + "rgmii0_rxd_3", "tp1_loc" +}; +static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { + "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" +}; +static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { + "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" +}; +static const char * const rtd1295_sb2_usb_clock_output_groups[] = { + "sensor_cko_1" +}; static const char * const rtd1295_sb2_hif_loc_misc_groups[] = { "hif_loc" }; static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" }; @@ -1146,9 +1295,15 @@ static const char * const rtd1295_disp_gpio_groups[] = { "spdif", "dmic_clk", "dmic_data", "ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3", }; -static const char * const rtd1295_disp_ai_groups[] = { "dmic_clk", "dmic_data", "ao_sd_2", "ao_sd_3" }; -static const char * const rtd1295_disp_ao_groups[] = { "ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3" }; -static const char * const rtd1295_disp_dmic_groups[] = { "dmic_clk", "dmic_data" }; +static const char * const rtd1295_disp_ai_groups[] = { + "dmic_clk", "dmic_data", "ao_sd_2", "ao_sd_3" +}; +static const char * const rtd1295_disp_ao_groups[] = { + "ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3" +}; +static const char * const rtd1295_disp_dmic_groups[] = { + "dmic_clk", "dmic_data" +}; static const char * const rtd1295_disp_spdif_out_groups[] = { "spdif" }; #define RTD1295_FUNC(_name) \ @@ -1347,8 +1502,10 @@ static const unsigned int rtd1295_sdio_data_0_pins[] = { RTD1295_SDIO_DATA_0 }; static const unsigned int rtd1295_sdio_data_1_pins[] = { RTD1295_SDIO_DATA_1 }; static const unsigned int rtd1295_sdio_data_2_pins[] = { RTD1295_SDIO_DATA_2 }; static const unsigned int rtd1295_sdio_data_3_pins[] = { RTD1295_SDIO_DATA_3 }; -static const unsigned int rtd1295_pcie_clkreq_0_pins[] = { RTD1295_PCIE_CLKREQ_0 }; -static const unsigned int rtd1295_pcie_clkreq_1_pins[] = { RTD1295_PCIE_CLKREQ_1 }; +static const unsigned int rtd1295_pcie_clkreq_0_pins[] = { + RTD1295_PCIE_CLKREQ_0 }; +static const unsigned int rtd1295_pcie_clkreq_1_pins[] = { + RTD1295_PCIE_CLKREQ_1 }; static const unsigned int rtd1295_prob_0_pins[] = { RTD1295_PROB_0 }; static const unsigned int rtd1295_prob_1_pins[] = { RTD1295_PROB_1 }; static const unsigned int rtd1295_prob_2_pins[] = { RTD1295_PROB_2 }; @@ -1399,25 +1556,57 @@ static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = { static const char * const rtd1295_cr_gpio_groups[] = { "nf_cle", "nf_ale", "nf_rd_n", "nf_wr_n", "nf_rdy", - "nf_dd_7", "nf_dd_6", "nf_dd_5", "nf_dd_4", "nf_dd_3", "nf_dd_2", "nf_dd_1", "nf_dd_0", + "nf_dd_7", "nf_dd_6", "nf_dd_5", "nf_dd_4", + "nf_dd_3", "nf_dd_2", "nf_dd_1", "nf_dd_0", "nf_dqs", "nf_ce_n_0", "nf_ce_n_1", "emmc_dd_sb", - "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3", - "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", + "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", + "mmc_data_1", "mmc_data_2", "mmc_data_3", + "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", + "sdio_data_2", "sdio_data_3", "pcie_clkreq_0", "pcie_clkreq_1", "prob_0", "prob_1", "prob_2", "prob_3", }; -static const char * const rtd1295_cr_avcpu_ej_groups[] = { "nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7" }; -static const char * const rtd1295_cr_emmc_groups[] = { "nf_rdy", "nf_rd_n", "nf_cle", "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", "emmc_dd_db" }; -static const char * const rtd1295_cr_hif_groups[] = { "nf_wr_n", "nf_ale", "nf_cle", "nf_dd_4" }; -static const char * const rtd1295_cr_nand_groups[] = { "nf_dqs", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1", "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7" }; -static const char * const rtd1295_cr_p2s_groups[] = { "prob_0", "prob_1" }; -static const char * const rtd1295_cr_pcie_groups[] = { "pcie_clkreq_0", "pcie_clkreq_1" }; -static const char * const rtd1295_cr_pll_test_groups[] = { "prob_0", "prob_1", "prob_2", "prob_3" }; -static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3" }; -static const char * const rtd1295_cr_sd_card_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" }; -static const char * const rtd1295_cr_sdio_0_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3" }; -static const char * const rtd1295_cr_sdio_1_groups[] = { "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" }; +static const char * const rtd1295_cr_avcpu_ej_groups[] = { + "nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7" +}; +static const char * const rtd1295_cr_emmc_groups[] = { + "nf_rdy", "nf_rd_n", "nf_cle", "nf_dd_0", "nf_dd_1", + "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", + "nf_dd_7", "emmc_dd_db" +}; +static const char * const rtd1295_cr_hif_groups[] = { + "nf_wr_n", "nf_ale", "nf_cle", "nf_dd_4" +}; +static const char * const rtd1295_cr_nand_groups[] = { + "nf_dqs", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", + "nf_ce_n_0", "nf_ce_n_1", "nf_dd_0", "nf_dd_1", "nf_dd_2", + "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7" +}; +static const char * const rtd1295_cr_p2s_groups[] = { + "prob_0", "prob_1" +}; +static const char * const rtd1295_cr_pcie_groups[] = { + "pcie_clkreq_0", "pcie_clkreq_1" +}; +static const char * const rtd1295_cr_pll_test_groups[] = { + "prob_0", "prob_1", "prob_2", "prob_3" +}; +static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = { + "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3" +}; +static const char * const rtd1295_cr_sd_card_groups[] = { + "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", + "mmc_data_1", "mmc_data_2", "mmc_data_3" +}; +static const char * const rtd1295_cr_sdio_0_groups[] = { + "sdio_cmd", "sdio_clk", "sdio_data_0", + "sdio_data_1", "sdio_data_2", "sdio_data_3" +}; +static const char * const rtd1295_cr_sdio_1_groups[] = { + "mmc_cmd", "mmc_clk", "mmc_data_0", + "mmc_data_1", "mmc_data_2", "mmc_data_3" +}; #define RTD1295_FUNC(_name) \ From patchwork Thu May 14 09:21:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5dv6lYtz9sVF for ; Thu, 14 May 2020 19:21:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726265AbgENJVy (ORCPT ); Thu, 14 May 2020 05:21:54 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52961 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725878AbgENJVw (ORCPT ); Thu, 14 May 2020 05:21:52 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LRV20025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LRV20025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:27 +0800 Received: from RTEXDAG01.realtek.com.tw (172.21.6.100) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXDAG01.realtek.com.tw (172.21.6.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:26 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 6/7] pinctrl: realtek: DHC: Move pinctrl drivers to realtek directory and rename. Date: Thu, 14 May 2020 17:21:24 +0800 Message-ID: <20200514092125.6875-7-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Move Realtek DHC SoC pinctrl drivers to realtek directory and rename pinctrl-rtd119x.c to pinctrl-rtd.c. Signed-off-by: TY Chang --- drivers/pinctrl/Kconfig | 10 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/realtek/Kconfig | 14 ++ drivers/pinctrl/realtek/Makefile | 3 + .../pinctrl-rtd.c} | 166 +++++++++--------- .../pinctrl/{ => realtek}/pinctrl-rtd1195.h | 20 +-- .../pinctrl/{ => realtek}/pinctrl-rtd1295.h | 40 ++--- 7 files changed, 132 insertions(+), 123 deletions(-) create mode 100644 drivers/pinctrl/realtek/Kconfig create mode 100644 drivers/pinctrl/realtek/Makefile rename drivers/pinctrl/{pinctrl-rtd119x.c => realtek/pinctrl-rtd.c} (69%) rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1195.h (98%) rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1295.h (98%) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 311fe1eafe76..a3e1d45a604c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -198,15 +198,6 @@ config PINCTRL_OXNAS select GPIOLIB_IRQCHIP select MFD_SYSCON -config PINCTRL_REALTEK - bool "Realtek RTD129x pinctrl driver" - depends on OF - depends on ARCH_REALTEK || COMPILE_TEST - select GENERIC_PINCONF - select PINMUX - help - This selects pinctrl driver for Realtek RTD1295 platforms. - config PINCTRL_ROCKCHIP bool select PINMUX @@ -430,6 +421,7 @@ source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/zte/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/realtek/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d4bec880c9bc..2bda2e19da8b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o -obj-$(CONFIG_PINCTRL_REALTEK) += pinctrl-rtd119x.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o @@ -73,3 +72,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_ZX) += zte/ obj-y += cirrus/ +obj-y += realtek/ \ No newline at end of file diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig new file mode 100644 index 000000000000..12c05799d223 --- /dev/null +++ b/drivers/pinctrl/realtek/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_REALTEK_DHC + bool "Realtek DHC pinctrl driver" + depends on OF + depends on ARCH_REALTEK || COMPILE_TEST + select GENERIC_PINCONF + select PINMUX + help + This is the pinctrl, pinmux, pinconf driver for + Realtek DHC SoC platforms. + + + diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile new file mode 100644 index 000000000000..0d18245ead77 --- /dev/null +++ b/drivers/pinctrl/realtek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +# Realtek pin control drivers +obj-$(CONFIG_PINCTRL_REALTEK_DHC) += pinctrl-rtd.o diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/realtek/pinctrl-rtd.c similarity index 69% rename from drivers/pinctrl/pinctrl-rtd119x.c rename to drivers/pinctrl/realtek/pinctrl-rtd.c index bda0d1328eb8..4d9740f875ff 100644 --- a/drivers/pinctrl/pinctrl-rtd119x.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -19,27 +19,27 @@ #include #include #include -#include "core.h" -#include "pinctrl-utils.h" +#include "../core.h" +#include "../pinctrl-utils.h" -struct rtd119x_pin_group_desc { +struct rtd_pin_group_desc { const char *name; const unsigned int *pins; unsigned int num_pins; }; -struct rtd119x_pin_func_desc { +struct rtd_pin_func_desc { const char *name; const char * const *groups; unsigned int num_groups; }; -struct rtd119x_pin_mux_desc { +struct rtd_pin_mux_desc { const char *name; u32 mux_value; }; -struct rtd119x_pin_config_desc { +struct rtd_pin_config_desc { const char *name; unsigned int reg_offset; unsigned int base_bit; @@ -50,11 +50,11 @@ struct rtd119x_pin_config_desc { unsigned int curr_type; }; -struct rtd119x_pin_desc { +struct rtd_pin_desc { const char *name; unsigned int mux_offset; u32 mux_mask; - const struct rtd119x_pin_mux_desc *functions; + const struct rtd_pin_mux_desc *functions; }; #define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ @@ -76,7 +76,7 @@ struct rtd119x_pin_desc { .name = # _name, \ .mux_offset = _mux_off, \ .mux_mask = _mux_mask, \ - .functions = (const struct rtd119x_pin_mux_desc []) { \ + .functions = (const struct rtd_pin_mux_desc []) { \ __VA_ARGS__, { } \ }, \ } @@ -87,16 +87,16 @@ struct rtd119x_pin_desc { .mux_value = _mux_val, \ } -struct rtd119x_pinctrl_desc { +struct rtd_pinctrl_desc { const struct pinctrl_pin_desc *pins; unsigned int num_pins; - const struct rtd119x_pin_group_desc *groups; + const struct rtd_pin_group_desc *groups; unsigned int num_groups; - const struct rtd119x_pin_func_desc *functions; + const struct rtd_pin_func_desc *functions; unsigned int num_functions; - const struct rtd119x_pin_desc *muxes; + const struct rtd_pin_desc *muxes; unsigned int num_muxes; - const struct rtd119x_pin_config_desc *configs; + const struct rtd_pin_config_desc *configs; unsigned int num_configs; }; @@ -108,33 +108,33 @@ struct rtd119x_pinctrl_desc { #include "pinctrl-rtd1195.h" #include "pinctrl-rtd1295.h" -struct rtd119x_pinctrl { +struct rtd_pinctrl { struct pinctrl_dev *pcdev; void __iomem *base; struct pinctrl_desc desc; - const struct rtd119x_pinctrl_desc *info; + const struct rtd_pinctrl_desc *info; }; -static int rtd119x_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) +static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); return data->info->num_groups; } -static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev, +static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev, unsigned int selector) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); return data->info->groups[selector].name; } -static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, +static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, unsigned int selector, const unsigned int **pins, unsigned int *num_pins) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); *pins = data->info->groups[selector].pins; *num_pins = data->info->groups[selector].num_pins; @@ -142,34 +142,34 @@ static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, return 0; } -static const struct pinctrl_ops rtd119x_pinctrl_ops = { +static const struct pinctrl_ops rtd_pinctrl_ops = { .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinctrl_utils_free_map, - .get_groups_count = rtd119x_pinctrl_get_groups_count, - .get_group_name = rtd119x_pinctrl_get_group_name, - .get_group_pins = rtd119x_pinctrl_get_group_pins, + .get_groups_count = rtd_pinctrl_get_groups_count, + .get_group_name = rtd_pinctrl_get_group_name, + .get_group_pins = rtd_pinctrl_get_group_pins, }; -static int rtd119x_pinctrl_get_functions_count(struct pinctrl_dev *pcdev) +static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); return data->info->num_functions; } -static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev, +static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev, unsigned int selector) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); return data->info->functions[selector].name; } -static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, +static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, unsigned int selector, const char * const **groups, unsigned int * const num_groups) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); *groups = data->info->functions[selector].groups; *num_groups = data->info->functions[selector].num_groups; @@ -177,8 +177,8 @@ static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, return 0; } -static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number( - struct rtd119x_pinctrl *data, int number) +static const struct pinctrl_pin_desc *rtd_pinctrl_get_pin_by_number( + struct rtd_pinctrl *data, int number) { int i; @@ -190,8 +190,8 @@ static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number( return NULL; } -static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux( - struct rtd119x_pinctrl *data, const char *name) +static const struct rtd_pin_desc *rtd_pinctrl_find_mux( + struct rtd_pinctrl *data, const char *name) { int i; @@ -203,8 +203,8 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux( return NULL; } -static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config( - struct rtd119x_pinctrl *data, const char *name) +static const struct rtd_pin_config_desc *rtd_pinctrl_find_config( + struct rtd_pinctrl *data, const char *name) { int i; @@ -217,23 +217,23 @@ static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config( } -static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, +static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, unsigned int pin, const char *func_name) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); const struct pinctrl_pin_desc *pin_desc; - const struct rtd119x_pin_desc *mux; + const struct rtd_pin_desc *mux; const char *pin_name; u32 val; int i; - pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pin); + pin_desc = rtd_pinctrl_get_pin_by_number(data, pin); if (!pin_desc) return -ENOTSUPP; pin_name = pin_desc->name; - mux = rtd119x_pinctrl_find_mux(data, pin_name); + mux = rtd_pinctrl_find_mux(data, pin_name); if (!mux) return -ENOTSUPP; @@ -259,10 +259,10 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, return -EINVAL; } -static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, +static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev, unsigned int function, unsigned int group) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); const unsigned int *pins; unsigned int num_pins; const char *func_name; @@ -272,7 +272,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, func_name = data->info->functions[function].name; group_name = data->info->groups[group].name; - ret = rtd119x_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); + ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); if (ret) { dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); @@ -280,7 +280,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, } for (i = 0; i < num_pins; i++) { - ret = rtd119x_pinctrl_set_one_mux(pcdev, pins[i], func_name); + ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name); if (ret) return ret; } @@ -288,22 +288,22 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev, return 0; } -static int rtd119x_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev, +static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev, struct pinctrl_gpio_range *range, unsigned int offset) { - return rtd119x_pinctrl_set_one_mux(pcdev, offset, "gpio"); + return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio"); } -static const struct pinmux_ops rtd119x_pinmux_ops = { - .get_functions_count = rtd119x_pinctrl_get_functions_count, - .get_function_name = rtd119x_pinctrl_get_function_name, - .get_function_groups = rtd119x_pinctrl_get_function_groups, - .set_mux = rtd119x_pinctrl_set_mux, - .gpio_request_enable = rtd119x_pinctrl_gpio_request_enable, +static const struct pinmux_ops rtd_pinmux_ops = { + .get_functions_count = rtd_pinctrl_get_functions_count, + .get_function_name = rtd_pinctrl_get_function_name, + .get_function_groups = rtd_pinctrl_get_function_groups, + .set_mux = rtd_pinctrl_set_mux, + .gpio_request_enable = rtd_pinctrl_gpio_request_enable, }; -static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, - const struct rtd119x_pin_config_desc *config_desc, +static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, + const struct rtd_pin_config_desc *config_desc, enum pin_config_param param, enum pin_config_param arg) { u8 set_val = 0; @@ -392,7 +392,7 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data, return 0; } -static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, +static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, unsigned long *config) { unsigned int param = pinconf_to_config_param(*config); @@ -407,26 +407,26 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, return 0; } -static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, +static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, unsigned long *configs, unsigned int num_configs) { - struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); - const struct rtd119x_pin_config_desc *config_desc; + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd_pin_config_desc *config_desc; const struct pinctrl_pin_desc *pin_desc; const char *pin_name; int i; - pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pinnr); + pin_desc = rtd_pinctrl_get_pin_by_number(data, pinnr); if (!pin_desc) return -ENOTSUPP; pin_name = pin_desc->name; - config_desc = rtd119x_pinctrl_find_config(data, pin_name); + config_desc = rtd_pinctrl_find_config(data, pin_name); if (!config_desc) return -ENOTSUPP; for (i = 0; i < num_configs; i++) { - rtd119x_pconf_parse_conf(data, config_desc, + rtd_pconf_parse_conf(data, config_desc, pinconf_to_config_param(configs[i]), pinconf_to_config_argument(configs[i])); } @@ -436,16 +436,16 @@ static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, -static const struct pinconf_ops rtd119x_pinconf_ops = { +static const struct pinconf_ops rtd_pinconf_ops = { .is_generic = true, - .pin_config_get = rtd119x_pin_config_get, - .pin_config_set = rtd119x_pin_config_set, + .pin_config_get = rtd_pin_config_get, + .pin_config_set = rtd_pin_config_set, }; -static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data) +static void rtd_pinctrl_selftest(struct rtd_pinctrl *data) { int i, j, k; - const struct rtd119x_pinctrl_desc *info = data->info; + const struct rtd_pinctrl_desc *info = data->info; for (i = 0; i < info->num_muxes; i++) { /* Check for pin */ @@ -492,7 +492,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data) } } -static const struct of_device_id rtd119x_pinctrl_dt_ids[] = { +static const struct of_device_id rtd_pinctrl_dt_ids[] = { { .compatible = "realtek,rtd1195-iso-pinctrl", .data = &rtd1195_iso_pinctrl_desc }, { .compatible = "realtek,rtd1195-crt-pinctrl", @@ -508,12 +508,12 @@ static const struct of_device_id rtd119x_pinctrl_dt_ids[] = { { } }; -static int rtd119x_pinctrl_probe(struct platform_device *pdev) +static int rtd_pinctrl_probe(struct platform_device *pdev) { - struct rtd119x_pinctrl *data; + struct rtd_pinctrl *data; const struct of_device_id *match; - match = of_match_node(rtd119x_pinctrl_dt_ids, pdev->dev.of_node); + match = of_match_node(rtd_pinctrl_dt_ids, pdev->dev.of_node); if (!match) return -EINVAL; @@ -529,9 +529,9 @@ static int rtd119x_pinctrl_probe(struct platform_device *pdev) data->desc.name = "foo"; data->desc.pins = data->info->pins; data->desc.npins = data->info->num_pins; - data->desc.pctlops = &rtd119x_pinctrl_ops; - data->desc.pmxops = &rtd119x_pinmux_ops; - data->desc.confops = &rtd119x_pinconf_ops; + data->desc.pctlops = &rtd_pinctrl_ops; + data->desc.pmxops = &rtd_pinmux_ops; + data->desc.confops = &rtd_pinconf_ops; data->desc.custom_params = NULL; data->desc.num_custom_params = 0; data->desc.owner = THIS_MODULE; @@ -542,20 +542,20 @@ static int rtd119x_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, data); - rtd119x_pinctrl_selftest(data); + rtd_pinctrl_selftest(data); dev_info(&pdev->dev, "probed\n"); return 0; } -static struct platform_driver rtd119x_pinctrl_driver = { - .probe = rtd119x_pinctrl_probe, +static struct platform_driver rtd_pinctrl_driver = { + .probe = rtd_pinctrl_probe, .driver = { - .name = "rtd1295-pinctrl", - .of_match_table = rtd119x_pinctrl_dt_ids, + .name = "rtd-pinctrl", + .of_match_table = rtd_pinctrl_dt_ids, }, }; -builtin_platform_driver(rtd119x_pinctrl_driver); -MODULE_DESCRIPTION("rtk pinctrl driver"); +builtin_platform_driver(rtd_pinctrl_driver); +MODULE_DESCRIPTION("rtd pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/realtek/pinctrl-rtd1195.h similarity index 98% rename from drivers/pinctrl/pinctrl-rtd1195.h rename to drivers/pinctrl/realtek/pinctrl-rtd1195.h index f0dd91f416e8..74139345083c 100644 --- a/drivers/pinctrl/pinctrl-rtd1195.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd1195.h @@ -107,7 +107,7 @@ static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { .num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \ } -static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1195_iso_pin_groups[] = { RTD1195_GROUP(iso_gpio_0), RTD1195_GROUP(iso_gpio_1), RTD1195_GROUP(usb0), @@ -212,7 +212,7 @@ static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { .num_groups = ARRAY_SIZE(rtd1195_iso_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1195_iso_pin_functions[] = { RTD1195_FUNC(gpio), RTD1195_FUNC(ai_ur1), RTD1195_FUNC(ai_vfd), @@ -239,7 +239,7 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = { #undef RTD1195_FUNC -static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = { +static const struct rtd_pin_desc rtd1195_iso_muxes[] = { RTK_PIN_MUX(vfd_d, 0x10, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "vfd"), @@ -337,7 +337,7 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = { RTK_PIN_FUNC(0x2 << 30, "ai_vfd")), }; -static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = { +static const struct rtd_pin_config_desc rtd1195_iso_configs[] = { RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4), @@ -358,7 +358,7 @@ static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = { }; -static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = { .pins = rtd1195_iso_pins, .num_pins = ARRAY_SIZE(rtd1195_iso_pins), .groups = rtd1195_iso_pin_groups, @@ -586,7 +586,7 @@ static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC }; .num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \ } -static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1195_crt_pin_groups[] = { RTD1195_GROUP(gpio_0), RTD1195_GROUP(gpio_1), RTD1195_GROUP(gpio_2), @@ -764,7 +764,7 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" }; .num_groups = ARRAY_SIZE(rtd1195_crt_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1195_crt_pin_functions[] = { RTD1195_FUNC(gpio), RTD1195_FUNC(ao_tp0), RTD1195_FUNC(ao_gpio), @@ -794,7 +794,7 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = { #undef RTD1195_FUNC -static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { +static const struct rtd_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_MUX(nf_rdy, 0x60, GENMASK(3, 2), RTK_PIN_FUNC(0x0 << 2, "gpio"), RTK_PIN_FUNC(0x1 << 2, "nand"), @@ -1045,7 +1045,7 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = { RTK_PIN_FUNC(0x2 << 2, "ao_gpio")), }; -static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = { +static const struct rtd_pin_config_desc rtd1195_crt_configs[] = { RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8), RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8), RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8), @@ -1111,7 +1111,7 @@ static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = { }; -static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = { .pins = rtd1195_crt_pins, .num_pins = ARRAY_SIZE(rtd1195_crt_pins), .groups = rtd1195_crt_pin_groups, diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/realtek/pinctrl-rtd1295.h similarity index 98% rename from drivers/pinctrl/pinctrl-rtd1295.h rename to drivers/pinctrl/realtek/pinctrl-rtd1295.h index f27debc96bb6..14d46baa97d8 100644 --- a/drivers/pinctrl/pinctrl-rtd1295.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd1295.h @@ -171,7 +171,7 @@ static const unsigned int rtd1295_uart2_1_pins[] = { .num_pins = ARRAY_SIZE(rtd1295_ ## _name ## _pins), \ } -static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1295_iso_pin_groups[] = { RTD1295_GROUP(iso_gpio_0), RTD1295_GROUP(iso_gpio_1), RTD1295_GROUP(iso_gpio_2), @@ -317,7 +317,7 @@ static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { .num_groups = ARRAY_SIZE(rtd1295_iso_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1295_iso_pin_functions[] = { RTD1295_FUNC(gpio), RTD1295_FUNC(acpu_ejtag_loc_iso), RTD1295_FUNC(edp_hpd), @@ -350,7 +350,7 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = { #undef RTD1295_FUNC -static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { +static const struct rtd_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_MUX(iso_gpio_4, 0x10, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "uart2_0"), @@ -489,7 +489,7 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = { RTK_PIN_FUNC(0x2 << 12, "uart2_1")), }; -static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = { +static const struct rtd_pin_config_desc rtd1295_iso_configs[] = { RTK_PIN_CONFIG(iso_gpio_2, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(iso_gpio_3, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), @@ -527,7 +527,7 @@ static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = { -static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = { .pins = rtd1295_iso_pins, .num_pins = ARRAY_SIZE(rtd1295_iso_pins), .groups = rtd1295_iso_pin_groups, @@ -756,7 +756,7 @@ static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC }; -static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1295_sb2_pin_groups[] = { RTD1295_GROUP(gpio_0), RTD1295_GROUP(gpio_1), RTD1295_GROUP(gpio_2), @@ -921,7 +921,7 @@ static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" }; .num_groups = ARRAY_SIZE(rtd1295_sb2_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1295_sb2_pin_functions[] = { RTD1295_FUNC(gpio), RTD1295_FUNC(ai), RTD1295_FUNC(dc_fan_sensor), @@ -951,7 +951,7 @@ static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = { #undef RTD1295_FUNC -static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = { +static const struct rtd_pin_desc rtd1295_sb2_muxes[] = { RTK_PIN_MUX(tp0_data, 0x08, GENMASK(2, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "tp0_loc_tp0"), @@ -1168,7 +1168,7 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = { RTK_PIN_FUNC(0x1 << 22, "rgmii")), }; -static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = { +static const struct rtd_pin_config_desc rtd1295_sb2_configs[] = { RTK_PIN_CONFIG(tp0_clk, 0x28, 0, 1, 0, 2, 3, PADDRI_4_8), RTK_PIN_CONFIG(tp0_sync, 0x28, 4, 1, 0, 2, 3, PADDRI_4_8), RTK_PIN_CONFIG(tp0_valid, 0x28, 8, 1, 0, 2, 3, PADDRI_4_8), @@ -1226,7 +1226,7 @@ static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = { }; -static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = { .pins = rtd1295_sb2_pins, .num_pins = ARRAY_SIZE(rtd1295_sb2_pins), .groups = rtd1295_sb2_pin_groups, @@ -1278,7 +1278,7 @@ static const unsigned int rtd1295_ao_sd_1_pins[] = { RTD1295_AO_SD_1 }; static const unsigned int rtd1295_ao_sd_2_pins[] = { RTD1295_AO_SD_2 }; static const unsigned int rtd1295_ao_sd_3_pins[] = { RTD1295_AO_SD_3 }; -static const struct rtd119x_pin_group_desc rtd1295_disp_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1295_disp_pin_groups[] = { RTD1295_GROUP(spdif), RTD1295_GROUP(dmic_clk), RTD1295_GROUP(dmic_data), @@ -1313,7 +1313,7 @@ static const char * const rtd1295_disp_spdif_out_groups[] = { "spdif" }; .num_groups = ARRAY_SIZE(rtd1295_disp_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1295_disp_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1295_disp_pin_functions[] = { RTD1295_FUNC(gpio), RTD1295_FUNC(ai), RTD1295_FUNC(ao), @@ -1323,7 +1323,7 @@ static const struct rtd119x_pin_func_desc rtd1295_disp_pin_functions[] = { #undef RTD1295_FUNC -static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = { +static const struct rtd_pin_desc rtd1295_disp_muxes[] = { RTK_PIN_MUX(spdif, 0x08, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "spdif_out")), @@ -1360,7 +1360,7 @@ static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = { RTK_PIN_FUNC(0x2 << 18, "ai")), }; -static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = { +static const struct rtd_pin_config_desc rtd1295_disp_configs[] = { RTK_PIN_CONFIG(spdif, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(dmic_clk, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4), RTK_PIN_CONFIG(dmic_data, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4), @@ -1374,7 +1374,7 @@ static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = { }; -static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = { .pins = rtd1295_disp_pins, .num_pins = ARRAY_SIZE(rtd1295_disp_pins), .groups = rtd1295_disp_pin_groups, @@ -1513,7 +1513,7 @@ static const unsigned int rtd1295_prob_3_pins[] = { RTD1295_PROB_3 }; static const unsigned int rtd1295_sdio_loc_pins[] = { RTD1295_SDIO_LOC }; -static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = { +static const struct rtd_pin_group_desc rtd1295_cr_pin_groups[] = { RTD1295_GROUP(nf_cle), RTD1295_GROUP(nf_ale), RTD1295_GROUP(nf_rd_n), @@ -1616,7 +1616,7 @@ static const char * const rtd1295_cr_sdio_1_groups[] = { .num_groups = ARRAY_SIZE(rtd1295_cr_ ## _name ## _groups), \ } -static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = { +static const struct rtd_pin_func_desc rtd1295_cr_pin_functions[] = { RTD1295_FUNC(gpio), RTD1295_FUNC(avcpu_ej), RTD1295_FUNC(emmc), @@ -1633,7 +1633,7 @@ static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = { #undef RTD1295_FUNC -static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = { +static const struct rtd_pin_desc rtd1295_cr_muxes[] = { RTK_PIN_MUX(nf_dqs, 0x00, GENMASK(1, 0), RTK_PIN_FUNC(0x0 << 0, "gpio"), RTK_PIN_FUNC(0x1 << 0, "nand")), @@ -1785,7 +1785,7 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = { RTK_PIN_FUNC(0x1 << 12, "pll_test")), }; -static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = { +static const struct rtd_pin_config_desc rtd1295_cr_configs[] = { RTK_PIN_CONFIG(nf_dqs, 0x8, 0, 1, 0, 2, 3, PCONF_UNSUPP), RTK_PIN_CONFIG(nf_ale, 0x8, 4, 1, 0, 2, 3, PCONF_UNSUPP), RTK_PIN_CONFIG(nf_ce_n_0, 0x8, 8, 1, 0, 2, 3, PCONF_UNSUPP), @@ -1826,7 +1826,7 @@ static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = { }; -static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = { +static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = { .pins = rtd1295_cr_pins, .num_pins = ARRAY_SIZE(rtd1295_cr_pins), .groups = rtd1295_cr_pin_groups, From patchwork Thu May 14 09:21:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?VFlfQ2hhbmdb5by15a2Q6YC4XQ==?= X-Patchwork-Id: 1290043 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49N5fQ6vy2z9sVF for ; Thu, 14 May 2020 19:22:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726197AbgENJVv (ORCPT ); Thu, 14 May 2020 05:21:51 -0400 Received: from rtits2.realtek.com ([211.75.126.72]:52956 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725946AbgENJVu (ORCPT ); Thu, 14 May 2020 05:21:50 -0400 Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.69 with qID 04E9LRV30025255, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexmb06.realtek.com.tw[172.21.6.99]) by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id 04E9LRV30025255 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 14 May 2020 17:21:27 +0800 Received: from RTEXDAG01.realtek.com.tw (172.21.6.100) by RTEXMB06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from RTEXMB06.realtek.com.tw (172.21.6.99) by RTEXDAG01.realtek.com.tw (172.21.6.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 14 May 2020 17:21:26 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXMB01.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 14 May 2020 17:21:26 +0800 From: TY Chang To: , CC: , , , , Subject: [PATCH 7/7] pinctrl: realtek: DHC: Add suspend/resume callback function. Date: Thu, 14 May 2020 17:21:25 +0800 Message-ID: <20200514092125.6875-8-tychang@realtek.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200514092125.6875-1-tychang@realtek.com> References: <20200514092125.6875-1-tychang@realtek.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add suspend and resume callback function for Realtek DHC SoC pinctrl driver. Signed-off-by: TY Chang --- drivers/pinctrl/realtek/pinctrl-rtd.c | 39 +++++++++++++ drivers/pinctrl/realtek/pinctrl-rtd1195.h | 33 +++++++++++ drivers/pinctrl/realtek/pinctrl-rtd1295.h | 67 ++++++++++++++++++++++- 3 files changed, 138 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 4d9740f875ff..f327453b01df 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -57,6 +57,12 @@ struct rtd_pin_desc { const struct rtd_pin_mux_desc *functions; }; +struct rtd_pin_reg_list { + unsigned int reg_offset; + unsigned int val; +}; + + #define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ _pud_sel_off, _curr_off, _smt_off, _curr_type) \ { \ @@ -98,6 +104,8 @@ struct rtd_pinctrl_desc { unsigned int num_muxes; const struct rtd_pin_config_desc *configs; unsigned int num_configs; + struct rtd_pin_reg_list *lists; + unsigned int num_regs; }; #define PCONF_UNSUPP 0xffffffff @@ -549,8 +557,39 @@ static int rtd_pinctrl_probe(struct platform_device *pdev) return 0; } +static int rtd_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct rtd_pinctrl *data = platform_get_drvdata(pdev); + struct rtd_pin_reg_list *list; + int i; + + for (i = 0; i < data->info->num_regs; i++) { + list = &data->info->lists[i]; + list->val = readl(data->base + list->reg_offset); + } + + return 0; +} + +static int rtd_pinctrl_resume(struct platform_device *pdev) +{ + struct rtd_pinctrl *data = platform_get_drvdata(pdev); + const struct rtd_pin_reg_list *list; + int i; + + for (i = 0; i < data->info->num_regs; i++) { + list = &data->info->lists[i]; + writel(list->val, data->base + list->reg_offset); + } + + return 0; +} + + static struct platform_driver rtd_pinctrl_driver = { .probe = rtd_pinctrl_probe, + .suspend = rtd_pinctrl_suspend, + .resume = rtd_pinctrl_resume, .driver = { .name = "rtd-pinctrl", .of_match_table = rtd_pinctrl_dt_ids, diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1195.h b/drivers/pinctrl/realtek/pinctrl-rtd1195.h index 74139345083c..c9d6e7894d66 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd1195.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd1195.h @@ -358,6 +358,16 @@ static const struct rtd_pin_config_desc rtd1195_iso_configs[] = { }; +static struct rtd_pin_reg_list rtd1195_iso_reg_lists[] = { + {.reg_offset = 0x0}, + {.reg_offset = 0x4}, + {.reg_offset = 0x8}, + {.reg_offset = 0xc}, + {.reg_offset = 0x10}, + {.reg_offset = 0x14}, +}; + + static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = { .pins = rtd1195_iso_pins, .num_pins = ARRAY_SIZE(rtd1195_iso_pins), @@ -369,6 +379,8 @@ static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1195_iso_muxes), .configs = rtd1195_iso_configs, .num_configs = ARRAY_SIZE(rtd1195_iso_configs), + .lists = rtd1195_iso_reg_lists, + .num_regs = ARRAY_SIZE(rtd1195_iso_reg_lists), }; /* CRT */ @@ -1110,6 +1122,25 @@ static const struct rtd_pin_config_desc rtd1195_crt_configs[] = { RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4), }; +static struct rtd_pin_reg_list rtd1195_crt_reg_lists[] = { + {.reg_offset = 0x60}, + {.reg_offset = 0x64}, + {.reg_offset = 0x68}, + {.reg_offset = 0x6c}, + {.reg_offset = 0x70}, + {.reg_offset = 0x74}, + {.reg_offset = 0x78}, + {.reg_offset = 0x7c}, + {.reg_offset = 0x80}, + {.reg_offset = 0x84}, + {.reg_offset = 0x88}, + {.reg_offset = 0x8c}, + {.reg_offset = 0x90}, + {.reg_offset = 0x94}, + {.reg_offset = 0x98}, + {.reg_offset = 0x9c}, +}; + static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = { .pins = rtd1195_crt_pins, @@ -1122,6 +1153,8 @@ static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1195_crt_muxes), .configs = rtd1195_crt_configs, .num_configs = ARRAY_SIZE(rtd1195_crt_configs), + .lists = rtd1195_crt_reg_lists, + .num_regs = ARRAY_SIZE(rtd1195_crt_reg_lists), }; #endif diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1295.h b/drivers/pinctrl/realtek/pinctrl-rtd1295.h index 14d46baa97d8..7cd12f66e02f 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd1295.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd1295.h @@ -525,7 +525,17 @@ static const struct rtd_pin_config_desc rtd1295_iso_configs[] = { RTK_PIN_CONFIG(iso_gpio_34, 0x20, 4, 1, 0, 2, 3, 2), }; - +static struct rtd_pin_reg_list rtd1295_iso_reg_lists[] = { + {.reg_offset = 0x0}, + {.reg_offset = 0x4}, + {.reg_offset = 0x8}, + {.reg_offset = 0xc}, + {.reg_offset = 0x10}, + {.reg_offset = 0x14}, + {.reg_offset = 0x18}, + {.reg_offset = 0x1c}, + {.reg_offset = 0x20}, +}; static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = { .pins = rtd1295_iso_pins, @@ -538,6 +548,8 @@ static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1295_iso_muxes), .configs = rtd1295_iso_configs, .num_configs = ARRAY_SIZE(rtd1295_iso_configs), + .lists = rtd1295_iso_reg_lists, + .num_regs = ARRAY_SIZE(rtd1295_iso_reg_lists), }; /* SB2 */ @@ -1225,6 +1237,28 @@ static const struct rtd_pin_config_desc rtd1295_sb2_configs[] = { RTK_PIN_CONFIG(rgmii1_rxd_3, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8), }; +static struct rtd_pin_reg_list rtd1295_sb2_reg_lists[] = { + {.reg_offset = 0x8}, + {.reg_offset = 0xc}, + {.reg_offset = 0x10}, + {.reg_offset = 0x14}, + {.reg_offset = 0x28}, + {.reg_offset = 0x14}, + {.reg_offset = 0x2c}, + {.reg_offset = 0x30}, + {.reg_offset = 0x34}, + {.reg_offset = 0x38}, + {.reg_offset = 0x3c}, + {.reg_offset = 0x60}, + {.reg_offset = 0x64}, + {.reg_offset = 0x68}, + {.reg_offset = 0x6c}, + {.reg_offset = 0x70}, + {.reg_offset = 0x74}, + {.reg_offset = 0x78}, + {.reg_offset = 0x7c}, +}; + static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = { .pins = rtd1295_sb2_pins, @@ -1237,6 +1271,8 @@ static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1295_sb2_muxes), .configs = rtd1295_sb2_configs, .num_configs = ARRAY_SIZE(rtd1295_sb2_configs), + .lists = rtd1295_sb2_reg_lists, + .num_regs = ARRAY_SIZE(rtd1295_sb2_reg_lists), }; /* Disp */ @@ -1373,6 +1409,12 @@ static const struct rtd_pin_config_desc rtd1295_disp_configs[] = { RTK_PIN_CONFIG(ao_sd_3, 0x4, 24, 1, 0, 2, 3, PADDRI_2_4), }; +static struct rtd_pin_reg_list rtd1295_disp_reg_lists[] = { + {.reg_offset = 0x0}, + {.reg_offset = 0x4}, + {.reg_offset = 0x8}, +}; + static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = { .pins = rtd1295_disp_pins, @@ -1385,6 +1427,8 @@ static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1295_disp_muxes), .configs = rtd1295_disp_configs, .num_configs = ARRAY_SIZE(rtd1295_disp_configs), + .lists = rtd1295_disp_reg_lists, + .num_regs = ARRAY_SIZE(rtd1295_disp_reg_lists), }; /* CR */ @@ -1825,6 +1869,25 @@ static const struct rtd_pin_config_desc rtd1295_cr_configs[] = { RTK_PIN_CONFIG(prob_3, 0x18, 24, 1, 0, 2, 3, PADDRI_4_8), }; +static struct rtd_pin_reg_list rtd1295_cr_reg_lists[] = { + {.reg_offset = 0x0}, + {.reg_offset = 0x4}, + {.reg_offset = 0x8}, + {.reg_offset = 0xc}, + {.reg_offset = 0x10}, + {.reg_offset = 0x14}, + {.reg_offset = 0x18}, + {.reg_offset = 0x1c}, + {.reg_offset = 0x20}, + {.reg_offset = 0x24}, + {.reg_offset = 0x28}, + {.reg_offset = 0x2c}, + {.reg_offset = 0x30}, + {.reg_offset = 0x34}, + {.reg_offset = 0x38}, + {.reg_offset = 0x3c}, + {.reg_offset = 0x40}, +}; static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = { .pins = rtd1295_cr_pins, @@ -1837,6 +1900,8 @@ static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = { .num_muxes = ARRAY_SIZE(rtd1295_cr_muxes), .configs = rtd1295_cr_configs, .num_configs = ARRAY_SIZE(rtd1295_cr_configs), + .lists = rtd1295_cr_reg_lists, + .num_regs = ARRAY_SIZE(rtd1295_cr_reg_lists), }; #endif