From patchwork Wed May 13 12:55:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=fXj5Izqa; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZRY23mXz9sSk for ; Wed, 13 May 2020 22:56:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728591AbgEMM4I (ORCPT ); Wed, 13 May 2020 08:56:08 -0400 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:41461 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728413AbgEMM4H (ORCPT ); Wed, 13 May 2020 08:56:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374567; x=1620910567; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tWUrw/osLjvb/c0rlAloWSn6upuy4DQgjffgP9JdqBU=; b=fXj5IzqatnlmyMgZfRkj1ugYDueFfws12kYd6ZfyLtohOPHskYcdypub naxOw3T6+MR+ZChif35dzcNcjWvDZdGSdkBu7kIXBbyhpfU3nG3Yt8fKL uS9iT7tCfp4h1ldO79JZVd7/r5b5RmijqKbMKTIoyFCSR9OFHk88MHURu FiCniTpbPYymJ5SH3YeoPDH/MqfqXEx7Wm9G6cujVG5rvwzyQ5tQ5/V5+ h1Evoa03BWXzXota0fgePY+jZCM+mI6EZ2CkbGr7rUEiCoyAYGzOzKRMd 9H0ajpSyHMxHCcqzcy9n2g0GpMdWTbD6fFkyprbgLV6e5YE6fnv6Wd5O5 A==; IronPort-SDR: 5GHqSiFtKgWIC8va82L+s6NuvHwV62gTUokLdXnoPAjLf5/HA5uwPqmcP00xXoVlF0HErxDLTG 9aLm3xM6vdtFRug26VdhIpctNXmcVVZ/IfHQL43hxYe3FijQxx6p+g6diKrDY4WJgjxUgydAmQ m1Rkuu5XoerHhbojxsEY/QGTsPcpUhhDi77/5WeWsgE46h+bjosOvGqQ5RhOXeMnwdPTysupA4 c0QvLKjHNmh1h0HP1r6VIPqUZxvZK64FulwW5Z3tR5rtef98cJW0byFBlYHWJehBKrOStYPJ0E scM= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="79436238" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:08 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:02 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 01/14] pinctrl: ocelot: Should register GPIO's even if not irq controller Date: Wed, 13 May 2020 14:55:19 +0200 Message-ID: <20200513125532.24585-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This fixes the situation where the GPIO controller is not used as an interrupt controller as well. Previously, the driver would silently fail to register even the GPIO's. With this change, the driver will only register as an interrupt controller if a parent interrupt is provided. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/pinctrl/pinctrl-ocelot.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index ed8eac6c14944..d4ac65b1efc0b 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -751,21 +751,21 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (irq <= 0) - return irq; - - girq = &gc->irq; - girq->chip = &ocelot_irqchip; - girq->parent_handler = ocelot_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_edge_irq; + irq = irq_of_parse_and_map(gc->of_node, 0); + if (irq) { + girq = &gc->irq; + girq->chip = &ocelot_irqchip; + girq->parent_handler = ocelot_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + } ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) From patchwork Wed May 13 12:55:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289252 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=ojoNBcdF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZRt2hTGz9sRf for ; Wed, 13 May 2020 22:56:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733013AbgEMM4R (ORCPT ); Wed, 13 May 2020 08:56:17 -0400 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:41487 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728379AbgEMM4P (ORCPT ); Wed, 13 May 2020 08:56:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374575; x=1620910575; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z3RtA3Is19gMLuQPixC7qZLhsQ/ltAtQlKTqxZJF4kc=; b=ojoNBcdFjwObnjL0HOqbNOrH51SzViNsZ+9gpZV7Y42CvkaJ9A9mcPB3 pn0Nz+BB+ideeUHu8n6YH3UW9SJV05RHNlgE2Yn7i20N+iab2jwTXHf4P 1yGzTUNCUjszYDDyYfli0/eujJNuv8wYkyUpV9Y4DTLaq48X+A094jMbD wyiptExhTZB1fKrplwnXabUFAODEyQ5AzL1r6d6X6RA8OKvj6IppFkS5U p2phRFqWed952seyhzsADn+xFJP5Hv7KKMDrer7ZRfzB+YPNJZKZGveSM LtiQKaBN28k/VHf8rlCuiaFNPr9eOZ8lCA/aTGD9vQmp9Hec9maNzM+t4 A==; IronPort-SDR: lO6DOcnAhr84ZBSxSAxSdxBBd5w2TOugv8+G0o0Vq5kEETCRHS/5YLSTywa4ycsGzA1J4ByVAq 0aS6FSaHetV7NqZ3WCeiHYIfI//XOXuyourN3Jp1z2/a1cSJLwCmZvqi2VGZ07o6j/1bUGyyOx SlYno5D6xVWWhZkAU6os1SH41UkBGaSEVxdsgvmUFQ9CA42JixTkKyJ3FJbtTLB1PEcJFqWcit 3xoupXRGh9bPwFty1g3eLsZpsguJOLBYe/iTZXIn37JhtZSaRjGeiSLroSxuzed6U5uCtgLv6G fwI= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="79436261" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:14 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:11 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 02/14] pinctrl: ocelot: Remove instance number from pin functions Date: Wed, 13 May 2020 14:55:20 +0200 Message-ID: <20200513125532.24585-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch removes the instance number from the "miim", "reco_clk" and "sfp" pin function. The change needed is to prepare the driver for adding new platforms with more of these instances. The instance number is also redundant, as this is implicit for each pin. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/pinctrl/pinctrl-ocelot.c | 94 ++++++++++---------------------- 1 file changed, 30 insertions(+), 64 deletions(-) -- 2.26.2 diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index d4ac65b1efc0b..375f3ea3b80c4 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -46,32 +46,15 @@ enum { FUNC_IRQ0_OUT, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, - FUNC_MIIM1, - FUNC_MIIM2, + FUNC_MIIM, FUNC_PCI_WAKE, FUNC_PTP0, FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, FUNC_PWM, - FUNC_RECO_CLK0, - FUNC_RECO_CLK1, - FUNC_SFP0, - FUNC_SFP1, - FUNC_SFP2, - FUNC_SFP3, - FUNC_SFP4, - FUNC_SFP5, - FUNC_SFP6, - FUNC_SFP7, - FUNC_SFP8, - FUNC_SFP9, - FUNC_SFP10, - FUNC_SFP11, - FUNC_SFP12, - FUNC_SFP13, - FUNC_SFP14, - FUNC_SFP15, + FUNC_RECO_CLK, + FUNC_SFP, FUNC_SG0, FUNC_SG1, FUNC_SG2, @@ -92,32 +75,15 @@ static const char *const ocelot_function_names[] = { [FUNC_IRQ0_OUT] = "irq0_out", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", - [FUNC_MIIM1] = "miim1", - [FUNC_MIIM2] = "miim2", + [FUNC_MIIM] = "miim", [FUNC_PCI_WAKE] = "pci_wake", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", [FUNC_PWM] = "pwm", - [FUNC_RECO_CLK0] = "reco_clk0", - [FUNC_RECO_CLK1] = "reco_clk1", - [FUNC_SFP0] = "sfp0", - [FUNC_SFP1] = "sfp1", - [FUNC_SFP2] = "sfp2", - [FUNC_SFP3] = "sfp3", - [FUNC_SFP4] = "sfp4", - [FUNC_SFP5] = "sfp5", - [FUNC_SFP6] = "sfp6", - [FUNC_SFP7] = "sfp7", - [FUNC_SFP8] = "sfp8", - [FUNC_SFP9] = "sfp9", - [FUNC_SFP10] = "sfp10", - [FUNC_SFP11] = "sfp11", - [FUNC_SFP12] = "sfp12", - [FUNC_SFP13] = "sfp13", - [FUNC_SFP14] = "sfp14", - [FUNC_SFP15] = "sfp15", + [FUNC_RECO_CLK] = "reco_clk", + [FUNC_SFP] = "sfp", [FUNC_SG0] = "sg0", [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", @@ -168,18 +134,18 @@ OCELOT_P(6, UART, TWI_SCL_M, NONE); OCELOT_P(7, UART, TWI_SCL_M, NONE); OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); -OCELOT_P(10, PTP2, TWI_SCL_M, SFP0); -OCELOT_P(11, PTP3, TWI_SCL_M, SFP1); -OCELOT_P(12, UART2, TWI_SCL_M, SFP2); -OCELOT_P(13, UART2, TWI_SCL_M, SFP3); -OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4); -OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5); +OCELOT_P(10, PTP2, TWI_SCL_M, SFP); +OCELOT_P(11, PTP3, TWI_SCL_M, SFP); +OCELOT_P(12, UART2, TWI_SCL_M, SFP); +OCELOT_P(13, UART2, TWI_SCL_M, SFP); +OCELOT_P(14, MIIM, TWI_SCL_M, SFP); +OCELOT_P(15, MIIM, TWI_SCL_M, SFP); OCELOT_P(16, TWI, NONE, SI); OCELOT_P(17, TWI, TWI_SCL_M, SI); OCELOT_P(18, PTP0, TWI_SCL_M, NONE); OCELOT_P(19, PTP1, TWI_SCL_M, NONE); -OCELOT_P(20, RECO_CLK0, TACHO, NONE); -OCELOT_P(21, RECO_CLK1, PWM, NONE); +OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); +OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); #define OCELOT_PIN(n) { \ .number = n, \ @@ -264,22 +230,22 @@ JAGUAR2_P(40, NONE, TWI_SCL_M); JAGUAR2_P(41, NONE, TWI_SCL_M); JAGUAR2_P(42, NONE, TWI_SCL_M); JAGUAR2_P(43, NONE, TWI_SCL_M); -JAGUAR2_P(44, NONE, SFP8); -JAGUAR2_P(45, NONE, SFP9); -JAGUAR2_P(46, NONE, SFP10); -JAGUAR2_P(47, NONE, SFP11); -JAGUAR2_P(48, SFP0, NONE); -JAGUAR2_P(49, SFP1, SI); -JAGUAR2_P(50, SFP2, SI); -JAGUAR2_P(51, SFP3, SI); -JAGUAR2_P(52, SFP4, NONE); -JAGUAR2_P(53, SFP5, NONE); -JAGUAR2_P(54, SFP6, NONE); -JAGUAR2_P(55, SFP7, NONE); -JAGUAR2_P(56, MIIM1, SFP12); -JAGUAR2_P(57, MIIM1, SFP13); -JAGUAR2_P(58, MIIM2, SFP14); -JAGUAR2_P(59, MIIM2, SFP15); +JAGUAR2_P(44, NONE, SFP); +JAGUAR2_P(45, NONE, SFP); +JAGUAR2_P(46, NONE, SFP); +JAGUAR2_P(47, NONE, SFP); +JAGUAR2_P(48, SFP, NONE); +JAGUAR2_P(49, SFP, SI); +JAGUAR2_P(50, SFP, SI); +JAGUAR2_P(51, SFP, SI); +JAGUAR2_P(52, SFP, NONE); +JAGUAR2_P(53, SFP, NONE); +JAGUAR2_P(54, SFP, NONE); +JAGUAR2_P(55, SFP, NONE); +JAGUAR2_P(56, MIIM, SFP); +JAGUAR2_P(57, MIIM, SFP); +JAGUAR2_P(58, MIIM, SFP); +JAGUAR2_P(59, MIIM, SFP); JAGUAR2_P(60, NONE, NONE); JAGUAR2_P(61, NONE, NONE); JAGUAR2_P(62, NONE, NONE); From patchwork Wed May 13 12:55:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=1u1xnpu1; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZS00GgTz9sSw for ; Wed, 13 May 2020 22:56:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733088AbgEMM42 (ORCPT ); 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d="scan'208";a="75132769" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:28 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:23 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 Date: Wed, 13 May 2020 14:55:21 +0200 Message-ID: <20200513125532.24585-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This fixes a problem with using the GPIO as an interrupt on Jaguar2 (and similar), as the register layout of the platforms with 64 GPIO's are pairwise, such that the original offset must be multiplied with the platform stride. Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/pinctrl/pinctrl-ocelot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 375f3ea3b80c4..95c225bc7572f 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -680,11 +680,12 @@ static void ocelot_irq_handler(struct irq_desc *desc) struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; unsigned int reg = 0, irq, i; unsigned long irqs; for (i = 0; i < info->stride; i++) { - regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); + regmap_read(info->map, id_reg + 4 * i, ®); if (!reg) continue; From patchwork Wed May 13 12:55:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=muJMCVLB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZS90vCwz9sSg for ; Wed, 13 May 2020 22:56:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733141AbgEMM4g (ORCPT ); Wed, 13 May 2020 08:56:36 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:6871 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732989AbgEMM4e (ORCPT ); Wed, 13 May 2020 08:56:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374593; x=1620910593; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XzyAjS+VdICD+VDbBl+tF57k++B6rYPYjva3OeaJ/X8=; b=muJMCVLBG01L3Gkgt5yYVoHUxYX8DuTMCbc3r+l/Q1Wmn5BEwRpks4ON PVlYaH8QRNblx8VNSTvoknEEN/do5+Kn3bthzmVX9AwxCGpP5e1fDKVI+ 9coRCf1gcKSkOmhP+6oN4qUtffyXCiKv5+Rvxtpn36AO+gmS/KqvglWUy PnJXgJ1qmUr91Y+p4RSzq97Gt9bzzjkkFIhrZqGSCuP8m5BcfZJAz7rSh w2u0Zgct0liLFN2Wm3S5o376WxBnl1Pk7VhXiPRvvdO0c6NIYgxpkEELH Uc/thI3LG0HIwuOys0Qprohn4X841g8BISPXEoGOPu0P52o1Y7LK+jSp+ Q==; IronPort-SDR: JwLwlM1erNzBBGrUO3T1+ZqDwN8fhRVhDgIwzSxlGBJtM46S/CKnrYo4HkoV/lOh6UzB2CqgAu a4xgKEkrsGAhVgDYrbv6HCfdIGBxKv/tUn0OKhb8cHQj0bUWBWnDwRI0DyO/bs3Lu8HCffr4Re I2ZgrNSvM5UF2ub5WOoWyPliNeAYMKom1MVzcuFN3zeJBWDssIa3fvY6Vc4AICcjOfNxlWtaNY KsKGX3TX+AxoU54N/faoOMEmT6yWR08YKHYD521JoOMg+VJ+m6vCeVKeNMTNXVDb3j7PkR/9ZS 3tc= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132778" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:33 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:30 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 04/14] arm64: sparx5: Add support for Microchip 2xA53 SoC Date: Wed, 13 May 2020 14:55:22 +0200 Message-ID: <20200513125532.24585-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) -- 2.26.2 diff --git a/MAINTAINERS b/MAINTAINERS index 091ec22c1a23f..1b5a18d3dbb9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2079,6 +2079,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +N: sparx5 +S: Supported + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 55d70cfe0f9e1..e1734a13a967b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM From patchwork Wed May 13 12:55:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=19ZI/nOy; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZSN4MJsz9sSf for ; Wed, 13 May 2020 22:56:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732989AbgEMM4s (ORCPT ); Wed, 13 May 2020 08:56:48 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:29570 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731644AbgEMM4r (ORCPT ); Wed, 13 May 2020 08:56:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374606; x=1620910606; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=poBPrhT3w6QbThTNX7WMhvl6ITRtWZafa6qFqSWWJSM=; b=19ZI/nOyOQ1yISZ95HqFgMsJfoNCP1o6QilIEtkIeFZzP6oG9MO4HE5w rOBhuWvbYAux5N5aRp4TWCfH/Yi42QtY/cluJgoyEHkfDpogrc9cIQAQo UVQ1qA9Pl4+ZCgF76ZbBKjJKzyKmhGm/uEd85/w8U8zOTfGAQbueVRMY8 dWRgqWMjgNdYgX2Pna0+jRD8X5bw5scDxL9YEIqbR61saMANjdUh1RvNH BQ0XcLWKEq0ZntWc75NVPB3XqacRdUeFaH6I//O7VAFBjwXpytvbi+QV5 x5dWvmDIho3dMWtMQEsueqnKi5A8OzS+1XtEsgbRAaOloKxmP1T7g0dJF g==; IronPort-SDR: xxJdrEOxoKFUoLTD14Tc43OvYgZ/knJ6/cbfPW9+CoTHjCaaQ1u/jmYup6A6CbZQhwERynlnod rFRLF3M/WkpD1TVTYVAN1fmXQV9PmBKBpdq21AnRDX3Htw4lER5Hn6WV0fZ3Q+Z5l/HVaEko8p DE3WRmiUUiLPbP3U1bNAyP2RpFCyQlU7/Vwwl2No0MeKdcrk8QFbonZJpZzCpkVPeGL0+z01xE s/CVAdnli96L3/nH5bHtKt61tiSbkEh+u8NbFYaWRLA9pYgSkO3cTnj7eVdZV4Lvewn6indXai sFM= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76494614" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:48 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:42 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Rob Herring CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC Date: Wed, 13 May 2020 14:55:23 +0200 Message-ID: <20200513125532.24585-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds the main Sparx5 SoC DT documentation file, with information abut the supported board types. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml new file mode 100644 index 0000000000000..83b36d1217988 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Boards Device Tree Bindings + +maintainers: + - Lars Povlsen + +description: |+ + The Microchip Sparx5 SoC is a ARMv8-based used in a family of + gigabit TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of switching + features such as advanced TCAM-based VLAN and QoS processing + enabling delivery of differentiated services, and security through + TCAM-based frame processing using versatile content aware processor + (VCAP) + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The Sparx5 pcb125 board is a modular board, + which has both spi-nor and eMMC storage. The modular design + allows for connection of different network ports. + items: + - const: microchip,sparx5-pcb125 + - const: microchip,sparx5 + + - description: The Sparx5 pcb134 is a pizzabox form factor + gigabit switch with 20 SFP ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb134 + - const: microchip,sparx5 + + - description: The Sparx5 pcb135 is a pizzabox form factor + gigabit switch with 48+4 Cu ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb135 + - const: microchip,sparx5 + + axi@600000000: + type: object + description: the root node in the Sparx5 platforms must contain + an axi bus child node. They are always at physical address + 0x600000000 in all the Sparx5 variants. + properties: + compatible: + items: + - const: simple-bus + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + description: All Sparx5 boards must provide a system controller, + typically under the axi bus node. It contain reset registers and + other system control. + type: object + properties: + compatible: + items: + - const: microchip,sparx5-cpu-syscon + - const: syscon + reg: + maxItems: 1 + + required: + - compatible + - reg + +required: + - compatible + - axi@600000000 + - syscon@600000000 + +... From patchwork Wed May 13 12:55:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=aOdspnol; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZTC2jYKz9sTD for ; Wed, 13 May 2020 22:57:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733183AbgEMM4w (ORCPT ); Wed, 13 May 2020 08:56:52 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:6948 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729345AbgEMM4v (ORCPT ); Wed, 13 May 2020 08:56:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374610; x=1620910610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rD85cOeaPlQ4sx7WF3mvHfNPUAPNhYYnUKJHjynNaA0=; b=aOdspnolZIyBhYCZr24ftY/vauxSVe5f7XYQ0J9roDv8xPaiqnxyEsPR gn9fpxxcSirWXLUg4WvkuwkfaiFOrDeh5GTj+gUeb/PaUlFLI86dJsI9r XmY16q0QRO03lCGLaU+kvGdt6uU3dMKlXcj1hu4lxkEVHCHZFXOCN3lAO IhKZz8/R8f+fak6c9AxAUPaYWk6hLBGIpuk40TY/RnVY+8nCmpehXGmgp MT0ulU1r2cPRbFkOR9fe7TEbjaWwLMhIXqdvF+Y9gDdw6/a9VH2cPDWGR FY6os38aWXjkMnyC/OEO2Rv2qlQnkptei47bMRreZyXVH9lL/E3qoxN2L A==; IronPort-SDR: T8QRGAV2QR9+jQHrc5zBPqCszPh+6v9mgKmxyzvl7rcpe7eYFEivMrh3Kms/iVTUsyqzwrPMKD WItq0WOnjftDoMA0IZ/ATi0ak/qe3mAhjjEqhF5IWfAWihKofvHly5rzSWICC21m3i0s7hYXmh FSrENPNJtxmzn0B2t/zFt0ZcDUYoo9qQQ7fW+3U9qkbL0UzE/1UA7wRNmp2MDUX18iU0rCKp+g pyeqoB5NEnAH/nunqz+RHB3CyGHASzyNfcmb5y6eVvIcgOMNHSLnQflKjSYzMiCgTqrgkvBErx 2bI= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132812" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:52 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:46 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support Date: Wed, 13 May 2020 14:55:24 +0200 Message-ID: <20200513125532.24585-7-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option), Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/microchip/Makefile | 4 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 135 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++ .../dts/microchip/sparx5_pcb134_board.dtsi | 15 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++ .../dts/microchip/sparx5_pcb135_board.dtsi | 15 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++ 12 files changed, 271 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/Makefile create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi -- 2.26.2 diff --git a/MAINTAINERS b/MAINTAINERS index 1b5a18d3dbb9f..5aa28d6e39d4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2084,6 +2084,7 @@ M: Lars Povlsen M: Steen Hegelund M: Microchip Linux Driver Support L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +F: arch/arm64/boot/dts/microchip/ N: sparx5 S: Supported diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d8..9680a7f20c307 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y += intel subdir-y += lg subdir-y += marvell subdir-y += mediatek +subdir-y += microchip subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile new file mode 100644 index 0000000000000..c6e0313eea0f9 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi new file mode 100644 index 0000000000000..3136b4369f507 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include + +/ { + compatible = "microchip,sparx5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = + , + , + , + ; + }; + + clocks: clocks { + #address-cells = <2>; + #size-cells = <1>; + ranges; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; + }; + }; + + axi: axi@600000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@600300000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x6 0x00300000 0x20000>, /* GICD */ + <0x6 0x00340000 0x1000000>; /* GICR */ + interrupts = ; + }; + + uart0: serial@600100000 { + compatible = "ns16550a"; + reg = <0x6 0x00100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + uart1: serial@600102000 { + compatible = "ns16550a"; + reg = <0x6 0x00102000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + timer1: timer@600105000 { + compatible = "snps,dw-apb-timer"; + reg = <0x6 0x00105000 0x1000>; + clocks = <&ahb_clk>; + clock-names = "timer"; + interrupts = ; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts new file mode 100644 index 0000000000000..d7f985f7ee020 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts new file mode 100644 index 0000000000000..feee4e99ff57c --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi new file mode 100644 index 0000000000000..9b2aec400101b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts new file mode 100644 index 0000000000000..10081a66961bb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts new file mode 100644 index 0000000000000..20e409a9be196 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi new file mode 100644 index 0000000000000..9b2aec400101b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 0000000000000..741f0e12260e5 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi new file mode 100644 index 0000000000000..1f99d0db1284f --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5.dtsi" + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; From patchwork Wed May 13 12:55:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=iJ0lAY6T; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZSR69v9z9sSw for ; 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IronPort-SDR: QXtlxX7NyirgBub3OISAMGW9qKQT642hpZ1yT3JRhXxIVl8H14pGuLTHjq6CjlWacEjvDqLaMt OJmicgPs4QfAyPqiacyrmxjxxxX2LuQAna0XK/69Mw8To41S/EbVBoHnnkh7qfBlujkwjtT81r tq3INKPS6L+hywv59717IMTQcVt9Yr7rGBoIS70/dQ46KkIkAvzLPIa75DL0SFM6dkAZrXPx9n LWdxB9TO2l94M0ejWWrVx9voNth2G5NDx+EG6VNmLQL00z9Fqsbyxfz0vpJEMHUWhiyLLl6/H7 7jY= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132817" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:55 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:49 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Rob Herring CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 07/14] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support Date: Wed, 13 May 2020 14:55:25 +0200 Message-ID: <20200513125532.24585-8-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation for the "compatible" value designated for Sparx5 Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 32a8a8fa7805d..00912449237bd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,8 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" or - "mscc,jaguar2-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl", + "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From patchwork Wed May 13 12:55:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=jWMv1SiE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZT91tCtz9sSr for ; Wed, 13 May 2020 22:57:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733243AbgEMM47 (ORCPT ); Wed, 13 May 2020 08:56:59 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:29599 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733200AbgEMM45 (ORCPT ); Wed, 13 May 2020 08:56:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374616; x=1620910616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tnLWmU9TG0hHNpiEsQJmeBvXg8PJsOm3nln/lwMbNII=; b=jWMv1SiElsKoLpJiDb0vND4QaEsOf5JjkWYiqsVDmZKGLDy2JO1FK26+ WGvGBEjtWZFCa+xYTmaYP+VM40rFBwKqReHNIdfXVsZnxj2wHYGdajaVR zw4O+KXZBEfqf56D5objzPvlg6Zk7Nqa7lnoPFTDO7movSsp9Y413eLpm Aa9SHTnzzcK+u7Nbk0xM0KdqeMmvdXTEJfj0ilkkfjZAaeNDX3Ia1G+jr BhoS/LZZuliSeUKsmZRaAy1kmZG4RDEHmErJd8qFzuejKWDdBP6Eruz2K S87VNLQ77kPjMj1hoAY68rdS2QMo0YkF3dtY/eOFZO3plDMZGmrT/z51V w==; IronPort-SDR: iPcmnwfvFRdYKmx9fcBuWP/43p5J+o/Hc4a9KPJnQ45OI62gYQOywxkAutC2Lxc7aN6VKmbdQL C2romUuZo8OLj5ePxprebSXup3EIm2IxT467FjHmpBibuXw4O5t/lLOAMF2oijchUKNYVdYxgx de2mmO/IDSBNmxot12YgHkFtgxLmatdkOmeSHLg6u6cP1ktNiIZ0gYtSGEur/x6MBjKuhNBNxX 7hbb9JM2e1M5PqbaYX2TiRVSkMANTEgGHXfmQxgxJR3QK6R+T018jvB0OUR4mJy7YnxQfJEU+B wgU= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76494636" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:58 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:52 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 08/14] arm64: dts: sparx5: Add pinctrl support Date: Wed, 13 May 2020 14:55:26 +0200 Message-ID: <20200513125532.24585-9-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This add pinctrl support to the Microchip Sparx5 SoC. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 3136b4369f507..45a60993789c8 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -102,6 +102,8 @@ gic: interrupt-controller@600300000 { }; uart0: serial@600100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; @@ -113,6 +115,8 @@ uart0: serial@600100000 { }; uart1: serial@600102000 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; @@ -131,5 +135,27 @@ timer1: timer@600105000 { interrupts = ; }; + gpio: pinctrl@6110101e0 { + compatible = "microchip,sparx5-pinctrl"; + reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart2"; + }; + + }; + }; }; From patchwork Wed May 13 12:55:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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IronPort-SDR: 8pxY2N4AhB5MDJIuUrKYkIFV93fsdFGNQlld5+o4rlzgWrKz/MZqXRyfzpzjus0mV7HZQBOz7k XEsbjszk1kXRTzv2hnfEMu8xNz9dzLupDN3tYE65D/YkA5ivupI1xf+uOGZLUYp58wwLmQvVEG 9yGXIk8T3xSBo9YeFEoXgVw4c/oO9OyGRIJoTKlavgCn0WEevHkXEM2WLAlaTPV7h8H1PUJAOM EzcFzaDPT+ZwDQSrVDPdqktK4LxHFVcT/yURBd+tF+jQxNPo11db2birKxo+5zA/zMj67TVzEI sic= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="79436349" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:58 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:55 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support Date: Wed, 13 May 2020 14:55:27 +0200 Message-ID: <20200513125532.24585-10-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This add support for Sparx5 pinctrl, using the ocelot drives as basis. It adds pinconfig support as well, as supported by the platform. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Reported-by: kbuild test robot --- drivers/pinctrl/pinctrl-ocelot.c | 431 ++++++++++++++++++++++++++++++- 1 file changed, 430 insertions(+), 1 deletion(-) -- 2.26.2 diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 95c225bc7572f..35a482dc6b1a0 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -25,6 +25,23 @@ #include "pinconf.h" #include "pinmux.h" +#define clrsetbits(addr, clear, set) \ + writel((readl(addr) & ~(clear)) | (set), (addr)) + +/* PINCONFIG bits (sparx5 only) */ +enum { + PINCONF_BIAS, + PINCONF_SCHMITT, + PINCONF_DRIVE_STRENGTH, +}; + +#define BIAS_PD_BIT BIT(4) +#define BIAS_PU_BIT BIT(3) +#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) +#define SCHMITT_BIT BIT(2) +#define DRIVE_BITS GENMASK(1, 0) + +/* GPIO standard registers */ #define OCELOT_GPIO_OUT_SET 0x0 #define OCELOT_GPIO_OUT_CLR 0x4 #define OCELOT_GPIO_OUT 0x8 @@ -42,12 +59,17 @@ enum { FUNC_NONE, FUNC_GPIO, + FUNC_IRQ0, FUNC_IRQ0_IN, FUNC_IRQ0_OUT, + FUNC_IRQ1, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, + FUNC_EXT_IRQ, FUNC_MIIM, + FUNC_PHY_LED, FUNC_PCI_WAKE, + FUNC_MD, FUNC_PTP0, FUNC_PTP1, FUNC_PTP2, @@ -59,24 +81,36 @@ enum { FUNC_SG1, FUNC_SG2, FUNC_SI, + FUNC_SI2, FUNC_TACHO, FUNC_TWI, FUNC_TWI2, + FUNC_TWI3, FUNC_TWI_SCL_M, FUNC_UART, FUNC_UART2, + FUNC_UART3, + FUNC_PLL_STAT, + FUNC_EMMC, + FUNC_REF_CLK, + FUNC_RCVRD_CLK, FUNC_MAX }; static const char *const ocelot_function_names[] = { [FUNC_NONE] = "none", [FUNC_GPIO] = "gpio", + [FUNC_IRQ0] = "irq0", [FUNC_IRQ0_IN] = "irq0_in", [FUNC_IRQ0_OUT] = "irq0_out", + [FUNC_IRQ1] = "irq1", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", + [FUNC_EXT_IRQ] = "ext_irq", [FUNC_MIIM] = "miim", + [FUNC_PHY_LED] = "phy_led", [FUNC_PCI_WAKE] = "pci_wake", + [FUNC_MD] = "md", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", @@ -88,12 +122,19 @@ static const char *const ocelot_function_names[] = { [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", [FUNC_SI] = "si", + [FUNC_SI2] = "si2", [FUNC_TACHO] = "tacho", [FUNC_TWI] = "twi", [FUNC_TWI2] = "twi2", + [FUNC_TWI3] = "twi3", [FUNC_TWI_SCL_M] = "twi_scl_m", [FUNC_UART] = "uart", [FUNC_UART2] = "uart2", + [FUNC_UART3] = "uart3", + [FUNC_PLL_STAT] = "pll_stat", + [FUNC_EMMC] = "emmc", + [FUNC_REF_CLK] = "ref_clk", + [FUNC_RCVRD_CLK] = "rcvrd_clk", }; struct ocelot_pmx_func { @@ -111,6 +152,7 @@ struct ocelot_pinctrl { struct pinctrl_dev *pctl; struct gpio_chip gpio_chip; struct regmap *map; + void __iomem *pincfg; struct pinctrl_desc *desc; struct ocelot_pmx_func func[FUNC_MAX]; u8 stride; @@ -324,6 +366,152 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { JAGUAR2_PIN(63), }; +#define SPARX5_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps sparx5_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ + }, \ +} + +SPARX5_P(0, SG0, PLL_STAT, NONE); +SPARX5_P(1, SG0, NONE, NONE); +SPARX5_P(2, SG0, NONE, NONE); +SPARX5_P(3, SG0, NONE, NONE); +SPARX5_P(4, SG1, NONE, NONE); +SPARX5_P(5, SG1, NONE, NONE); +SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); +SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); +SPARX5_P(8, PTP0, NONE, SFP); +SPARX5_P(9, PTP1, SFP, TWI_SCL_M); +SPARX5_P(10, UART, NONE, NONE); +SPARX5_P(11, UART, NONE, NONE); +SPARX5_P(12, SG1, NONE, NONE); +SPARX5_P(13, SG1, NONE, NONE); +SPARX5_P(14, TWI, TWI_SCL_M, NONE); +SPARX5_P(15, TWI, NONE, NONE); +SPARX5_P(16, SI, TWI_SCL_M, SFP); +SPARX5_P(17, SI, TWI_SCL_M, SFP); +SPARX5_P(18, SI, TWI_SCL_M, SFP); +SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); +SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); +SPARX5_P(21, IRQ1_OUT, TACHO, SFP); +SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); +SPARX5_P(23, PWM, UART3, TWI_SCL_M); +SPARX5_P(24, PTP2, UART3, TWI_SCL_M); +SPARX5_P(25, PTP3, SI, TWI_SCL_M); +SPARX5_P(26, UART2, SI, TWI_SCL_M); +SPARX5_P(27, UART2, SI, TWI_SCL_M); +SPARX5_P(28, TWI2, SI, SFP); +SPARX5_P(29, TWI2, SI, SFP); +SPARX5_P(30, SG2, SI, PWM); +SPARX5_P(31, SG2, SI, TWI_SCL_M); +SPARX5_P(32, SG2, SI, TWI_SCL_M); +SPARX5_P(33, SG2, SI, SFP); +SPARX5_P(34, NONE, TWI_SCL_M, EMMC); +SPARX5_P(35, SFP, TWI_SCL_M, EMMC); +SPARX5_P(36, SFP, TWI_SCL_M, EMMC); +SPARX5_P(37, SFP, NONE, EMMC); +SPARX5_P(38, NONE, TWI_SCL_M, EMMC); +SPARX5_P(39, SI2, TWI_SCL_M, EMMC); +SPARX5_P(40, SI2, TWI_SCL_M, EMMC); +SPARX5_P(41, SI2, TWI_SCL_M, EMMC); +SPARX5_P(42, SI2, TWI_SCL_M, EMMC); +SPARX5_P(43, SI2, TWI_SCL_M, EMMC); +SPARX5_P(44, SI, SFP, EMMC); +SPARX5_P(45, SI, SFP, EMMC); +SPARX5_P(46, NONE, SFP, EMMC); +SPARX5_P(47, NONE, SFP, EMMC); +SPARX5_P(48, TWI3, SI, SFP); +SPARX5_P(49, TWI3, NONE, SFP); +SPARX5_P(50, SFP, NONE, TWI_SCL_M); +SPARX5_P(51, SFP, SI, TWI_SCL_M); +SPARX5_P(52, SFP, MIIM, TWI_SCL_M); +SPARX5_P(53, SFP, MIIM, TWI_SCL_M); +SPARX5_P(54, SFP, PTP2, TWI_SCL_M); +SPARX5_P(55, SFP, PTP3, PCI_WAKE); +SPARX5_P(56, MIIM, SFP, TWI_SCL_M); +SPARX5_P(57, MIIM, SFP, TWI_SCL_M); +SPARX5_P(58, MIIM, SFP, TWI_SCL_M); +SPARX5_P(59, MIIM, SFP, NONE); +SPARX5_P(60, RECO_CLK, NONE, NONE); +SPARX5_P(61, RECO_CLK, NONE, NONE); +SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); +SPARX5_P(63, RECO_CLK, NONE, NONE); + +#define SPARX5_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &sparx5_pin_##n \ +} + +static const struct pinctrl_pin_desc sparx5_pins[] = { + SPARX5_PIN(0), + SPARX5_PIN(1), + SPARX5_PIN(2), + SPARX5_PIN(3), + SPARX5_PIN(4), + SPARX5_PIN(5), + SPARX5_PIN(6), + SPARX5_PIN(7), + SPARX5_PIN(8), + SPARX5_PIN(9), + SPARX5_PIN(10), + SPARX5_PIN(11), + SPARX5_PIN(12), + SPARX5_PIN(13), + SPARX5_PIN(14), + SPARX5_PIN(15), + SPARX5_PIN(16), + SPARX5_PIN(17), + SPARX5_PIN(18), + SPARX5_PIN(19), + SPARX5_PIN(20), + SPARX5_PIN(21), + SPARX5_PIN(22), + SPARX5_PIN(23), + SPARX5_PIN(24), + SPARX5_PIN(25), + SPARX5_PIN(26), + SPARX5_PIN(27), + SPARX5_PIN(28), + SPARX5_PIN(29), + SPARX5_PIN(30), + SPARX5_PIN(31), + SPARX5_PIN(32), + SPARX5_PIN(33), + SPARX5_PIN(34), + SPARX5_PIN(35), + SPARX5_PIN(36), + SPARX5_PIN(37), + SPARX5_PIN(38), + SPARX5_PIN(39), + SPARX5_PIN(40), + SPARX5_PIN(41), + SPARX5_PIN(42), + SPARX5_PIN(43), + SPARX5_PIN(44), + SPARX5_PIN(45), + SPARX5_PIN(46), + SPARX5_PIN(47), + SPARX5_PIN(48), + SPARX5_PIN(49), + SPARX5_PIN(50), + SPARX5_PIN(51), + SPARX5_PIN(52), + SPARX5_PIN(53), + SPARX5_PIN(54), + SPARX5_PIN(55), + SPARX5_PIN(56), + SPARX5_PIN(57), + SPARX5_PIN(58), + SPARX5_PIN(59), + SPARX5_PIN(60), + SPARX5_PIN(61), + SPARX5_PIN(62), + SPARX5_PIN(63), +}; + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(ocelot_function_names); @@ -382,6 +570,7 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, * ALT[1] * This is racy because both registers can't be updated at the same time * but it doesn't matter much for now. + * Note: ALT0/ALT1 are organized specially for 64 gpio targets */ regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), BIT(p), f << p); @@ -458,6 +647,220 @@ static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, return 0; } +static int ocelot_hw_get_value(struct ocelot_pinctrl *info, + unsigned int pin, + unsigned int reg, + int *val) +{ + int ret = -ENOTSUPP; + + if (info->pincfg) { + u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); + u32 value; + + ret = 0; + switch (reg) { + case PINCONF_BIAS: + value = regcfg & BIAS_BITS; + break; + + case PINCONF_SCHMITT: + value = regcfg & SCHMITT_BIT; + break; + + case PINCONF_DRIVE_STRENGTH: + value = regcfg & DRIVE_BITS; + break; + + default: + ret = -ENOTSUPP; + break; + } + } + return ret; +} + +static int ocelot_hw_set_value(struct ocelot_pinctrl *info, + unsigned int pin, + unsigned int reg, + int val) +{ + int ret = -ENOTSUPP; + + if (info->pincfg) { + void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); + + ret = 0; + switch (reg) { + case PINCONF_BIAS: + clrsetbits(regaddr, BIAS_BITS, val); + break; + + case PINCONF_SCHMITT: + clrsetbits(regaddr, SCHMITT_BIT, val); + break; + + case PINCONF_DRIVE_STRENGTH: + if (val <= 3) + clrsetbits(regaddr, DRIVE_BITS, val); + else + ret = -EINVAL; + break; + + default: + ret = -ENOTSUPP; + break; + } + } + return ret; +} + +static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + u32 param = pinconf_to_config_param(*config); + int val, err; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); + if (err) + return err; + if (param == PIN_CONFIG_BIAS_DISABLE) + val = (val == 0 ? true : false); + else if (param == PIN_CONFIG_BIAS_PULL_DOWN) + val = (val & BIAS_PD_BIT ? true : false); + else /* PIN_CONFIG_BIAS_PULL_UP */ + val = (val & BIAS_PU_BIT ? true : false); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); + if (err) + return err; + + val = (val & SCHMITT_BIT ? true : false); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, + &val); + if (err) + return err; + break; + + case PIN_CONFIG_OUTPUT: + err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), + &val); + if (err) + return err; + val = !!(val & BIT(pin % 32)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: + err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), + &val); + if (err) + return err; + val = val & BIT(pin % 32); + if (param == PIN_CONFIG_OUTPUT_ENABLE) + val = !!val; + else + val = !val; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +noinline int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + u32 param, arg, p; + int cfg, err = 0; + + for (cfg = 0; cfg < num_configs; cfg++) { + param = pinconf_to_config_param(configs[cfg]); + arg = pinconf_to_config_argument(configs[cfg]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : + (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : + BIAS_PD_BIT; + + err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); + if (err) + goto err; + + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = arg ? SCHMITT_BIT : 0; + err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, + arg); + if (err) + goto err; + + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + err = ocelot_hw_set_value(info, pin, + PINCONF_DRIVE_STRENGTH, + arg); + if (err) + goto err; + + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + p = pin % 32; + if (arg) + regmap_write(info->map, + REG(OCELOT_GPIO_OUT_SET, info, + pin), + BIT(p)); + else + regmap_write(info->map, + REG(OCELOT_GPIO_OUT_CLR, info, + pin), + BIT(p)); + regmap_update_bits(info->map, + REG(OCELOT_GPIO_OE, info, pin), + BIT(p), + param == PIN_CONFIG_INPUT_ENABLE ? + 0 : BIT(p)); + break; + + default: + err = -ENOTSUPP; + } + } +err: + return err; +} + +static const struct pinconf_ops ocelot_confops = { + .is_generic = true, + .pin_config_get = ocelot_pinconf_get, + .pin_config_set = ocelot_pinconf_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + static const struct pinctrl_ops ocelot_pctl_ops = { .get_groups_count = ocelot_pctl_get_groups_count, .get_group_name = ocelot_pctl_get_group_name, @@ -484,6 +887,16 @@ static struct pinctrl_desc jaguar2_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc sparx5_desc = { + .name = "sparx5-pinctrl", + .pins = sparx5_pins, + .npins = ARRAY_SIZE(sparx5_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .confops = &ocelot_confops, + .owner = THIS_MODULE, +}; + static int ocelot_create_group_func_map(struct device *dev, struct ocelot_pinctrl *info) { @@ -511,7 +924,8 @@ static int ocelot_create_group_func_map(struct device *dev, } for (i = 0; i < npins; i++) - info->func[f].groups[i] = info->desc->pins[pins[i]].name; + info->func[f].groups[i] = + info->desc->pins[pins[i]].name; } kfree(pins); @@ -744,6 +1158,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, + { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, {}, }; @@ -752,6 +1167,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; void __iomem *base; + struct resource *res; int ret; struct regmap_config regmap_config = { .reg_bits = 32, @@ -773,6 +1189,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) } info->stride = 1 + (info->desc->npins - 1) / 32; + regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; info->map = devm_regmap_init_mmio(dev, base, ®map_config); @@ -783,6 +1200,16 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) dev_set_drvdata(dev, info->map); info->dev = dev; + /* Pinconf registers */ + if (info->desc->confops) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); + else + info->pincfg = base; + } + ret = ocelot_pinctrl_register(pdev, info); if (ret) return ret; @@ -791,6 +1218,8 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) if (ret) return ret; + dev_info(dev, "driver registered\n"); + return 0; } From patchwork Wed May 13 12:55:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=PZLEjl0b; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZSk0Cxfz9sRK for ; Wed, 13 May 2020 22:57:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728737AbgEMM5F (ORCPT ); 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d="scan'208";a="75132842" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:57:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:57:02 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:59 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Rob Herring CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Date: Wed, 13 May 2020 14:55:28 +0200 Message-ID: <20200513125532.24585-11-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This add the DT bindings documentation for the Sparx5 SoC DPLL clock Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml new file mode 100644 index 0000000000000..594007d8fc59a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 DPLL Clock + +maintainers: + - Lars Povlsen + +description: | + The Sparx5 DPLL clock controller generates and supplies clock to + various peripherals within the SoC. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + const: microchip,sparx5-dpll + + reg: + items: + - description: dpll registers + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock provider for eMMC: + - | + clks: clks@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + reg = <0x1110000c 0x24>; + }; + +... From patchwork Wed May 13 12:55:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=VwNouJhC; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZSk5sfyz9sSr for ; Wed, 13 May 2020 22:57:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728673AbgEMM5J (ORCPT ); Wed, 13 May 2020 08:57:09 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:7011 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728100AbgEMM5G (ORCPT ); Wed, 13 May 2020 08:57:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374626; x=1620910626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xXJynxC1V+h72C8jGLqY9iD3zxa+PCkiEZWrzWLo4sc=; b=VwNouJhCByK3bn7CwPfNUVwngLRxKUEAfhbkYa84veCGBnmdEawZL3wN RSXIr2A8LW4LFfoMVoKt+2D0ChcFIaCpHfAweo00qE5tQsG+SRcUBMhoK e/AbmZroqAc2jooB8v2f0D/B4fqEdmtCJf38N582YpEoukBaoVef8Qzf5 Ovwx9KjWDgv1M33BUcu72MU2Iee+LiXgNwoylrJCJz5Ef6bVXjioqZ4no vBN+h0iJ6zAuOqQDVhG0V1tRtpOCUUqvxZ2bYMrUAC8Py00Eio+wXeTb6 whALgA/OG3WeQx4iWlhSmmxL0317p+d0CLNQRa3/id19AQP3UGhnYuq95 A==; IronPort-SDR: NvIML1Er/K90nIzYLbI8PG5XGtzccaa59ul/HN7TPT0pSCir3gKv9DnyhjUOSU5kx8utt4y68X SDygjKCvEZ2UI/fnAJnrZNIbjveyyH4J9b2akdOdsbEnf0Zh2yZ7UsLMyIEVUeOtrWZEGOMlo4 hkIEwcwYhN6wHrnzfJ1vdC1ezZLigalGeC1GiSthWba5ahB7qrf89nmjSM5ERpAJWruiaFmA5w pUwkawnxrP6DD4mObHusuFYyISg1BhnWValJ9+XFC+8+hGvDqWdd/vSfJm8fq3VrFQAPDumNEU cFw= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132848" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:57:05 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:57:05 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:57:02 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Rob Herring CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 11/14] dt-bindings: clock: sparx5: Add bindings include file Date: Wed, 13 May 2020 14:55:29 +0200 Message-ID: <20200513125532.24585-12-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- include/dt-bindings/clock/microchip,sparx5.h | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,sparx5.h -- 2.26.2 diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h new file mode 100644 index 0000000000000..4b04dabacec2c --- /dev/null +++ b/include/dt-bindings/clock/microchip,sparx5.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 Microchip Inc. + * + * Author: Lars Povlsen + */ + +#ifndef _DT_BINDINGS_CLK_SPARX5_H +#define _DT_BINDINGS_CLK_SPARX5_H + +#define CLK_ID_CORE 0 +#define CLK_ID_DDR 1 +#define CLK_ID_CPU2 2 +#define CLK_ID_ARM2 3 +#define CLK_ID_AUX1 4 +#define CLK_ID_AUX2 5 +#define CLK_ID_AUX3 6 +#define CLK_ID_AUX4 7 +#define CLK_ID_SYNCE 8 + +#define N_CLOCKS 9 + +#endif From patchwork Wed May 13 12:55:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289265 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=mfGR7wnx; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZT54W2Lz9sSr for ; Wed, 13 May 2020 22:57:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728100AbgEMM5N (ORCPT ); Wed, 13 May 2020 08:57:13 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:7011 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732929AbgEMM5M (ORCPT ); Wed, 13 May 2020 08:57:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374629; x=1620910629; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tWX49PxHY1FHfz7Y567qk5pJ2z/xgyylC7uI4FTvRcY=; b=mfGR7wnxBPr4uFY/HPvc3l2nk8xgXyGl+eisV6B1i8rv6xl+z4g40Inf CImPNw7yWqyiU3wzndqaiWxDXZ5Y7AQSFIAxPDxn1CiAYNlWZk/5idzD/ Nyn0YG02thcsSUm2lexwOa6EQepyym2uLRpagqY7isexeTo7J+8hIcKQX lKGzQ/F6EEwDRH+jCD0nATRqMH3gGJOjqYDb3/5pOVikoZ7bP+oOXzTNo Gob6X+KDPXB2TCk0GebSiOjXZXmoTbtZ1M5ZwMLDglY+EM2Q81KPJJ1SJ m7/ExA1sUG7bHHZ343Nr+Cs5BU/OVEDllQYq6ionKOKjBC60PLT4rYZX8 g==; IronPort-SDR: 0T/1mF9VhtLi2S+VHmfucuR37o7EA5agqvmbSVyqN3NEUpfwFkXVg/IA2X+idUdpRvKfup6HpU aSjB8pW1bpRy8H6UNhmZfvQJ3dD4tsmpQxPAoSWQdFDf18lx2T0kRu4Ngzl+QY/TFqyeLpea0y qkYFZKpiPYGfOZHW6Lwq2/nWmT60ptvkzVrigvvkxL3utXwCLnalNLf195D0W0xzY/6WYmO8sf O1EHOJBOoMBSHoehQfXjqXO0WJ/2ZF02wf+wZm+pvMcIEiI98RvfK5AFYw+rBpNB2tQsN8GQwX rVw= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132853" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:57:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:57:08 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:57:05 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 12/14] clk: sparx5: Add Sparx5 SoC DPLL clock driver Date: Wed, 13 May 2020 14:55:30 +0200 Message-ID: <20200513125532.24585-13-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds a device driver for the Sparx5 SoC DPLL clock Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/clk/Makefile | 1 + drivers/clk/clk-sparx5.c | 269 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 270 insertions(+) create mode 100644 drivers/clk/clk-sparx5.c -- 2.26.2 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f4169cc2fd318..9332e32667527 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o diff --git a/drivers/clk/clk-sparx5.c b/drivers/clk/clk-sparx5.c new file mode 100644 index 0000000000000..685b3028a7071 --- /dev/null +++ b/drivers/clk/clk-sparx5.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Microchip Sparx5 SoC Clock driver. + * + * Copyright (c) 2019 Microchip Inc. + * + * Author: Lars Povlsen + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PLL_DIV_MASK GENMASK(7, 0) +#define PLL_PRE_DIV_MASK GENMASK(10, 8) +#define PLL_PRE_DIV_SHIFT 8 +#define PLL_ROT_DIR BIT(11) +#define PLL_ROT_SEL_MASK GENMASK(13, 12) +#define PLL_ROT_SEL_SHIFT 12 +#define PLL_ROT_ENA BIT(14) +#define PLL_CLK_ENA BIT(15) + +#define MAX_SEL 4 +#define MAX_PRE BIT(3) + +#define KHZ 1000 +#define MHZ (KHZ*KHZ) + +#define BASE_CLOCK (2500UL*MHZ) + +static u8 sel_rates[MAX_SEL] = { 0, 2*8, 2*4, 2*2 }; + +static const char *clk_names[N_CLOCKS] = { + "core", "ddr", "cpu2", "arm2", + "aux1", "aux2", "aux3", "aux4", + "synce", +}; + +struct s5_hw_clk { + struct clk_hw hw; + void __iomem *reg; + int index; +}; + +struct s5_clk_data { + void __iomem *base; + struct s5_hw_clk s5_hw[N_CLOCKS]; +}; + +struct pll_conf { + int freq; + u8 div; + bool rot_ena; + u8 rot_sel; + u8 rot_dir; + u8 pre_div; +}; + +#define to_clk_pll(hw) container_of(hw, struct s5_hw_clk, hw) + +unsigned long calc_freq(const struct pll_conf *pdata) +{ + unsigned long rate = BASE_CLOCK / pdata->div; + + if (pdata->rot_ena) { + unsigned long base = BASE_CLOCK / pdata->div; + int sign = pdata->rot_dir ? -1 : 1; + int divt = sel_rates[pdata->rot_sel] * (1 + pdata->pre_div); + int divb = divt + sign; + + rate = mult_frac(base, divt, divb); + rate = roundup(rate, 1000); + } + + return rate; +} + +static unsigned long clk_calc_params(unsigned long rate, + struct pll_conf *conf) +{ + memset(conf, 0, sizeof(*conf)); + + conf->div = DIV_ROUND_CLOSEST_ULL(BASE_CLOCK, rate); + + if (BASE_CLOCK % rate) { + struct pll_conf best; + ulong cur_offset, best_offset = rate; + int i, j; + + /* Enable fractional rotation */ + conf->rot_ena = true; + + if ((BASE_CLOCK / rate) != conf->div) { + /* Overshoot, adjust other direction */ + conf->rot_dir = 1; + } + + /* Brute force search over MAX_PRE * (MAX_SEL - 1) = 24 */ + for (i = 0; i < MAX_PRE; i++) { + conf->pre_div = i; + for (j = 1; j < MAX_SEL; j++) { + conf->rot_sel = j; + conf->freq = calc_freq(conf); + cur_offset = abs(rate - conf->freq); + if (cur_offset == 0) + /* Perfect fit */ + goto done; + if (cur_offset < best_offset) { + /* Better fit found */ + best_offset = cur_offset; + best = *conf; + } + } + } + /* Best match */ + *conf = best; + } + +done: + return conf->freq; +} + +static int clk_pll_enable(struct clk_hw *hw) +{ + struct s5_hw_clk *pll = to_clk_pll(hw); + u32 val = readl(pll->reg); + + val |= PLL_CLK_ENA; + writel(val, pll->reg); + pr_debug("%s: Enable val %04x\n", clk_names[pll->index], val); + return 0; +} + +static void clk_pll_disable(struct clk_hw *hw) +{ + struct s5_hw_clk *pll = to_clk_pll(hw); + u32 val = readl(pll->reg); + + val &= ~PLL_CLK_ENA; + writel(val, pll->reg); + pr_debug("%s: Disable val %04x\n", clk_names[pll->index], val); +} + +static int clk_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct s5_hw_clk *pll = to_clk_pll(hw); + struct pll_conf conf; + unsigned long eff_rate; + int ret = 0; + + eff_rate = clk_calc_params(rate, &conf); + if (eff_rate == rate) { + u32 val; + + val = readl(pll->reg) & PLL_CLK_ENA; + val |= PLL_DIV_MASK & conf.div; + if (conf.rot_ena) { + val |= (PLL_ROT_ENA | + (PLL_ROT_SEL_MASK & + (conf.rot_sel << PLL_ROT_SEL_SHIFT)) | + (PLL_PRE_DIV_MASK & + (conf.pre_div << PLL_PRE_DIV_SHIFT))); + if (conf.rot_dir) + val |= PLL_ROT_DIR; + } + pr_debug("%s: Rate %ld >= 0x%04x\n", + clk_names[pll->index], rate, val); + writel(val, pll->reg); + } else { + pr_err("%s: freq unsupported: %ld paren %ld\n", + clk_names[pll->index], rate, parent_rate); + ret = -ENOTSUPP; + } + + return ret; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Don't care */ + return 0; +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct pll_conf conf; + unsigned long eff_rate; + + eff_rate = clk_calc_params(rate, &conf); + pr_debug("%s: Rate %ld rounded to %ld\n", __func__, rate, eff_rate); + + return eff_rate; +} + +static const struct clk_ops s5_pll_ops = { + .enable = clk_pll_enable, + .disable = clk_pll_disable, + .set_rate = clk_pll_set_rate, + .round_rate = clk_pll_round_rate, + .recalc_rate = clk_pll_recalc_rate, +}; + +static struct s5_clk_data *s5_clk_alloc(struct device_node *np) +{ + struct s5_clk_data *clk_data; + + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + if (WARN_ON(!clk_data)) + return NULL; + + clk_data->base = of_iomap(np, 0); + if (WARN_ON(!clk_data->base)) + return NULL; + + return clk_data; +} + +static struct clk_hw *s5_clk_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct s5_clk_data *pll_clk = data; + unsigned int idx = clkspec->args[0]; + + if (idx >= N_CLOCKS) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return &pll_clk->s5_hw[idx].hw; +} + +static void __init s5_pll_init(struct device_node *np) +{ + int i, ret; + struct s5_clk_data *pll_clk; + struct clk_init_data init = { 0 }; + + pll_clk = s5_clk_alloc(np); + if (!pll_clk) + return; + + init.ops = &s5_pll_ops; + init.parent_names = NULL; + init.num_parents = 0; + + for (i = 0; i < N_CLOCKS; i++) { + struct s5_hw_clk *s5_hw = &pll_clk->s5_hw[i]; + + init.name = clk_names[i]; + s5_hw->index = i; + s5_hw->reg = pll_clk->base + (i * sizeof(u32)); + s5_hw->hw.init = &init; + ret = of_clk_hw_register(np, &s5_hw->hw); + if (ret) { + pr_err("failed to register %s clock\n", init.name); + return; + } + } + + of_clk_add_hw_provider(np, s5_clk_hw_get, pll_clk); +} +CLK_OF_DECLARE_DRIVER(microchip_s5, "microchip,sparx5-dpll", s5_pll_init); From patchwork Wed May 13 12:55:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=dLSr9niX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZSt2XFKz9sSw for ; Wed, 13 May 2020 22:57:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733282AbgEMM5Q (ORCPT ); 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d="scan'208";a="79436370" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:57:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:57:14 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:57:09 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 13/14] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Date: Wed, 13 May 2020 14:55:31 +0200 Message-ID: <20200513125532.24585-14-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 45a60993789c8..ca4055f04ac26 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -82,6 +82,11 @@ sys_clk: sys-clk { #clock-cells = <0>; clock-frequency = <625000000>; }; + clks: clks@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + reg = <0x6 0x1110000c 0x24>; + }; }; axi: axi@600000000 { From patchwork Wed May 13 12:55:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1289264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=EFFUIYKk; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49MZT45L1Gz9sTD for ; Wed, 13 May 2020 22:57:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728313AbgEMM5Y (ORCPT ); Wed, 13 May 2020 08:57:24 -0400 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:29647 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733272AbgEMM5R (ORCPT ); Wed, 13 May 2020 08:57:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374636; x=1620910636; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=teOkRdmWsO8hsGpIQIKDLfq0daEHQBt9t9McFUxCb/A=; b=EFFUIYKkMAH+BPfl3n1zte6ug1HtOsUOOV76Y9aicseWibCCGvX4qaO1 LBRTWQ1TJhxBZ0Wro09zUhITDOXcRx8eRauMyvsGHUA9gLs6a6jAnyMoR pKlMWVwaouvwyuiTnkP7EXoZSKJ4Giv9OeicgbnTPXCtKCR02oDAmh46u 87URBo4LR+Nq3qLAaT7ErkwSU7qCa6157DfXo04LKlSn85FxT0P40wqcZ rI8FaaAujCNfb89wHrJ3fDANVi6Nb87MHENaOUwhRchU1l2fi4daJt7SB 65DJFpU8aXEZGs1XtVkrEsB+DIjlC0UWA+wdbsG167XYYAGYtt6GkOKwa Q==; IronPort-SDR: rqBnLP1FqUJkvx+dcF74gvjjXlA0wyOAkQ2Caz6kGznkNvwj335M3jJQB112iDy2R0RXyCppFq Hd/GLj63YMDEEt3PWnJaSP2H8qdqQSaUz3rkyYvPn2/vwedkTcYgyP5o0KZEeNwinqIme2ufjM 4OLJtO6fnDsZCVA3xkyFvRBi0C1y44zKGrg21JE9f1ExXNVNhxOT3MvteEflLQziWTjYvBf3z9 XtAepliyaf0rHrLaTIZeV6ieFWOd776MQU1Uw/l9Eyj5Sx4KajI9CT4nzPss8qulXPV2GPtaAy jok= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76494682" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:57:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:57:18 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:57:12 -0700 From: Lars Povlsen To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 14/14] arm64: dts: sparx5: Add i2c devices, i2c muxes Date: Wed, 13 May 2020 14:55:32 +0200 Message-ID: <20200513125532.24585-15-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds i2c devices and muxes to the Sparx5 reference boards. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 36 +++ .../boot/dts/microchip/sparx5_pcb125.dts | 4 + .../dts/microchip/sparx5_pcb134_board.dtsi | 237 ++++++++++++++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 77 ++++++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 4 + 5 files changed, 358 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index ca4055f04ac26..b5cb3d8dc876b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -160,7 +160,43 @@ uart2_pins: uart2-pins { function = "uart2"; }; + i2c_pins: i2c-pins { + pins = "GPIO_14", "GPIO_15"; + function = "twi"; + }; + + i2c2_pins: i2c2-pins { + pins = "GPIO_28", "GPIO_29"; + function = "twi2"; + }; + }; + + i2c0: i2c@600101000 { + compatible = "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + reg = <0x6 0x00101000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; }; + i2c1: i2c@600103000 { + compatible = "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x00103000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; + }; }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index d7f985f7ee020..91ee5b6cfc37a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -15,3 +15,7 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 9b2aec400101b..18a535a043686 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,9 +7,246 @@ #include "sparx5_pcb_common.dtsi" /{ + aliases { + i2c0 = &i2c0; + i2c100 = &i2c100; + i2c101 = &i2c101; + i2c102 = &i2c102; + i2c103 = &i2c103; + i2c104 = &i2c104; + i2c105 = &i2c105; + i2c106 = &i2c106; + i2c107 = &i2c107; + i2c108 = &i2c108; + i2c109 = &i2c109; + i2c110 = &i2c110; + i2c111 = &i2c111; + i2c112 = &i2c112; + i2c113 = &i2c113; + i2c114 = &i2c114; + i2c115 = &i2c115; + i2c116 = &i2c116; + i2c117 = &i2c117; + i2c118 = &i2c118; + i2c119 = &i2c119; + }; + gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; }; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", + "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", + "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_16"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_17"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_2: i2cmux-2 { + pins = "GPIO_18"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_3: i2cmux-3 { + pins = "GPIO_19"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_4: i2cmux-4 { + pins = "GPIO_20"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_5: i2cmux-5 { + pins = "GPIO_22"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_6: i2cmux-6 { + pins = "GPIO_36"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_7: i2cmux-7 { + pins = "GPIO_35"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_8: i2cmux-8 { + pins = "GPIO_50"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_9: i2cmux-9 { + pins = "GPIO_51"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_10: i2cmux-10 { + pins = "GPIO_56"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_11: i2cmux-11 { + pins = "GPIO_57"; + function = "twi_scl_m"; + output-high; + }; +}; + +&axi { + i2c0_imux: i2c0-imux@0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + i2c0_emux: i2c0-emux@0 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; +}; + +&i2c0_imux { + pinctrl-names = + "i2c100", "i2c101", "i2c102", "i2c103", + "i2c104", "i2c105", "i2c106", "i2c107", + "i2c108", "i2c109", "i2c110", "i2c111", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_2>; + pinctrl-3 = <&i2cmux_3>; + pinctrl-4 = <&i2cmux_4>; + pinctrl-5 = <&i2cmux_5>; + pinctrl-6 = <&i2cmux_6>; + pinctrl-7 = <&i2cmux_7>; + pinctrl-8 = <&i2cmux_8>; + pinctrl-9 = <&i2cmux_9>; + pinctrl-10 = <&i2cmux_10>; + pinctrl-11 = <&i2cmux_11>; + pinctrl-12 = <&i2cmux_pins_i>; + i2c100: i2c_sfp1 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c101: i2c_sfp2 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c102: i2c_sfp3 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c103: i2c_sfp4 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c104: i2c_sfp5 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c105: i2c_sfp6 { + reg = <0x5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c106: i2c_sfp7 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c107: i2c_sfp8 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c108: i2c_sfp9 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c109: i2c_sfp10 { + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c110: i2c_sfp11 { + reg = <0xa>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c111: i2c_sfp12 { + reg = <0xb>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c0_emux { + mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH + &gpio 60 GPIO_ACTIVE_HIGH + &gpio 61 GPIO_ACTIVE_HIGH + &gpio 54 GPIO_ACTIVE_HIGH>; + idle-state = <0x8>; + i2c112: i2c_sfp13 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c113: i2c_sfp14 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c114: i2c_sfp15 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c115: i2c_sfp16 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c116: i2c_sfp17 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c117: i2c_sfp18 { + reg = <0x5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c118: i2c_sfp19 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c119: i2c_sfp20 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 9b2aec400101b..d71f11a10b3d2 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,9 +7,86 @@ #include "sparx5_pcb_common.dtsi" /{ + aliases { + i2c0 = &i2c0; + i2c152 = &i2c152; + i2c153 = &i2c153; + i2c154 = &i2c154; + i2c155 = &i2c155; + }; + gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; }; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_35", "GPIO_36", + "GPIO_50", "GPIO_51"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_s29: i2cmux-0 { + pins = "GPIO_35"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s30: i2cmux-1 { + pins = "GPIO_36"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s31: i2cmux-2 { + pins = "GPIO_50"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s32: i2cmux-3 { + pins = "GPIO_51"; + function = "twi_scl_m"; + output-high; + }; +}; + +&axi { + i2c0_imux: i2c0-imux@0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; +}; + +&i2c0_imux { + pinctrl-names = + "i2c152", "i2c153", "i2c154", "i2c155", + "idle"; + pinctrl-0 = <&i2cmux_s29>; + pinctrl-1 = <&i2cmux_s30>; + pinctrl-2 = <&i2cmux_s31>; + pinctrl-3 = <&i2cmux_s32>; + pinctrl-4 = <&i2cmux_pins_i>; + i2c152: i2c_sfp1 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c153: i2c_sfp2 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c154: i2c_sfp3 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c155: i2c_sfp4 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 1f99d0db1284f..9d1a082de3e29 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -13,3 +13,7 @@ &uart0 { &uart1 { status = "okay"; }; + +&i2c0 { + status = "okay"; +};