From patchwork Tue Apr 28 23:07:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 1278775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=b4oEVM9C; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49BckR6B2Gz9sSX for ; Wed, 29 Apr 2020 09:07:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726256AbgD1XH5 (ORCPT ); Tue, 28 Apr 2020 19:07:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726044AbgD1XH4 (ORCPT ); Tue, 28 Apr 2020 19:07:56 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C77CC03C1AC; Tue, 28 Apr 2020 16:07:56 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id 18so116867pfv.8; Tue, 28 Apr 2020 16:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=zQ1AN2qLuGSeriYOxLxpDZYr+EholNiT0zZxYuiIwcw=; b=b4oEVM9CyNeYtoxafbq+JAL+h5ey/mUcxOqqHN+XAc5LZf1lgHDA+Rj7zRz1Oj9JLp 15C3fHQt6Mi0TvmQxsqnq3+qcaGXM0id9myxH52BYD0o9DOVD0/zuGNvXkW8z6yFbOz+ zOuqxDamL1N5d1MZDZJuG2cTr0OnewmuPcVH4UIdUomSk7xRaxCG7LBTeO52b4vKqdeY IFbGD6/H09Au+EPchC9Di8ZygjvkpmPxr49/I0spBEtfikaTZNBiw7seew2L1Z9jgvfu oISjH0q5N3yrm1++FLs/HXLHaXLWjlscHBk57XbPQS0ohSFjJjuW3b+VJzNmCCddSN8A iSEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=zQ1AN2qLuGSeriYOxLxpDZYr+EholNiT0zZxYuiIwcw=; b=TDGB2lWgstzLeR03EfZr83oGgiyMdEhjETLGmr+yyP5A9Ly2/cEt0QXVT30z90l2Dw rJmikZGrDoXSiOLYn6ntPNNy5O4VAEcaq7Obs0CWwW9akZXi5PM/0vf5+k/egi6aMl7k w1U49f0fXWDvCYdR3g+gkTjKHY4IMe8hu1sP9EBlceFt8cF7svokzFDLcbId3iEF2Xsk OL6vt7cbJAQjZJq98AksR+S6SnO56ekinTdF4YOYOrNnfigsbalWK0t0jPCvHLacqG+T jqacWd79fXvX6wm+O7WcjiHO9oAOxI2+ZW83CPjtOTv2nZfXngAjU84HqUZRuHY9Ih4D 3FHg== X-Gm-Message-State: AGi0PuZvryPg7XDZJAVrk8NLfeTfhoxjycgQRtCdcyADmuMMobhNIqrL FJ5k+dYB2p7bJY9oDAVFe1E= X-Google-Smtp-Source: APiQypLjJoieB0Lu8Y7K+KgvHsR98OFs5tWWuZhvEaVCWrhgeb6GzvIdO0fy+bkn5Nao58qOe6HuPw== X-Received: by 2002:a63:ef12:: with SMTP id u18mr25903105pgh.347.1588115276125; Tue, 28 Apr 2020 16:07:56 -0700 (PDT) Received: from syed ([106.202.21.137]) by smtp.gmail.com with ESMTPSA id g6sm5459558pja.2.2020.04.28.16.07.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Apr 2020 16:07:55 -0700 (PDT) Date: Wed, 29 Apr 2020 04:37:41 +0530 From: Syed Nayyar Waris To: akpm@linux-foundation.org Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, rrichter@marvell.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] gpio: thunderx: Utilize for_each_set_clump macro Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch reimplements the thunderx_gpio_set_multiple function in drivers/gpio/gpio-thunderx.c to use the new for_each_set_clump macro. Instead of looping for each bank in thunderx_gpio_set_multiple function, now we can skip bank which is not set and save cycles. Cc: Robert Richter Cc: Linus Walleij Cc: Bartosz Golaszewski Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v3: - Change datatype of some variables from u64 to unsigned long in function thunderx_gpio_set_multiple to resolve build errors. CHanges in v2: - No change. drivers/gpio/gpio-thunderx.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 9f66deab46ea..e577ab7e9e3c 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -275,12 +275,16 @@ static void thunderx_gpio_set_multiple(struct gpio_chip *chip, unsigned long *bits) { int bank; - u64 set_bits, clear_bits; + unsigned long set_bits, clear_bits, gpio_mask; + const unsigned long bank_size = 64; + unsigned long offset; + struct thunderx_gpio *txgpio = gpiochip_get_data(chip); - for (bank = 0; bank <= chip->ngpio / 64; bank++) { - set_bits = bits[bank] & mask[bank]; - clear_bits = ~bits[bank] & mask[bank]; + for_each_set_clump(offset, gpio_mask, mask, chip->ngpio, bank_size) { + bank = offset / bank_size; + set_bits = bits[bank] & gpio_mask; + clear_bits = ~bits[bank] & gpio_mask; writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); } From patchwork Tue Apr 28 23:09:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 1278776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=XjQhU/J/; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49Bcmz52r6z9sSY for ; Wed, 29 Apr 2020 09:10:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726490AbgD1XKG (ORCPT ); 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Tue, 28 Apr 2020 16:10:03 -0700 (PDT) Date: Wed, 29 Apr 2020 04:39:47 +0530 From: Syed Nayyar Waris To: akpm@linux-foundation.org Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] gpio: xilinx: Utilize for_each_set_clump macro Message-ID: <80745504d15c87aa1da0d4be3c16d1279f48615b.1588112716.git.syednwaris@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch reimplements the xgpio_set_multiple function in drivers/gpio/gpio-xilinx.c to use the new for_each_set_clump macro. Instead of looping for each bit in xgpio_set_multiple function, now we can check each channel at a time and save cycles. Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Michal Simek Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v3: - No change. Changes in v2: - No change. drivers/gpio/gpio-xilinx.c | 64 ++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 67f9f82e0db0..428207f9ab91 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -136,39 +136,43 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - unsigned long flags; + unsigned long flags[2]; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; - - spin_lock_irqsave(&chip->gpio_lock[index], flags); - - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock[index], flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } + u32 *const state = chip->gpio_state; + unsigned int *const width = chip->gpio_width; + const unsigned long state_size = BITS_PER_TYPE(*state); + unsigned long offset, clump; + size_t index; + +#define TOTAL_BITS BITS_PER_TYPE(chip->gpio_state) + DECLARE_BITMAP(old, TOTAL_BITS); + DECLARE_BITMAP(new, TOTAL_BITS); + DECLARE_BITMAP(changed, TOTAL_BITS); + + spin_lock_irqsave(&chip->gpio_lock[0], flags[0]); + spin_lock_irqsave(&chip->gpio_lock[1], flags[1]); + + bitmap_set_value(old, state[0], 0, width[0]); + bitmap_set_value(old, state[1], width[0], width[1]); + bitmap_replace(new, old, bits, mask, gc->ngpio); + + bitmap_set_value(old, state[0], 0, state_size); + bitmap_set_value(old, state[1], state_size, state_size); + state[0] = bitmap_get_value(new, 0, width[0]); + state[1] = bitmap_get_value(new, width[0], width[1]); + bitmap_set_value(new, state[0], 0, state_size); + bitmap_set_value(new, state[1], state_size, state_size); + bitmap_xor(changed, old, new, TOTAL_BITS); + + for_each_set_clump(offset, clump, changed, TOTAL_BITS, state_size) { + index = offset / state_size; + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + + index * XGPIO_CHANNEL_OFFSET, + state[index]); } - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock[1], flags[1]); + spin_unlock_irqrestore(&chip->gpio_lock[0], flags[0]); } /**