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This appears to solve it but I didn't look too far into why it mostly works (or can be made to work with make clean) without this. Signed-off-by: Nicholas Piggin --- libstb/container.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libstb/container.h b/libstb/container.h index f0b54fc01..dd58b4697 100644 --- a/libstb/container.h +++ b/libstb/container.h @@ -5,7 +5,9 @@ #define __STB_CONTAINER_H #include +#include #include +#include #include #define SECURE_BOOT_HEADERS_SIZE 4096 From patchwork Mon Apr 27 11:07:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hww6TNSz9sP7 for ; Mon, 27 Apr 2020 21:13:52 +1000 (AEST) Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:12:41 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:07:59 +1000 Message-Id: <20200427110813.1276533-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 02/16] asm/head.S: QUIESCE_REJECT fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This was returning to the wrong point and loading some garbage that had not been set up yet. Signed-off-by: Nicholas Piggin --- asm/head.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/asm/head.S b/asm/head.S index aea49d279..735e624bc 100644 --- a/asm/head.S +++ b/asm/head.S @@ -881,7 +881,7 @@ opal_entry: cmpwi %cr0,%r11,QUIESCE_REJECT bne 2f li %r3,OPAL_BUSY - b .Lreturn /* reject */ + b .Lreject 2: /* hold */ lwz %r11,CPUTHREAD_IN_OPAL_CALL(%r12) subi %r11,%r11,1 @@ -984,6 +984,7 @@ opal_entry: mr %r12,%r13 ld %r13,STACK_GPR13(%r1) ld %r1,STACK_GPR1(%r1) +.Lreject: sync /* release barrier vs quiescing */ lwz %r11,CPUTHREAD_IN_OPAL_CALL(%r12) subi %r11,%r11,1 From patchwork Mon Apr 27 11:08:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277545 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hxP6MMsz9sP7 for ; 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Mon, 27 Apr 2020 04:12:43 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:00 +1000 Message-Id: <20200427110813.1276533-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 03/16] move the __this_cpu register to r16, reserve r13-r15 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There have been several bugs between Linux and OPAL caused by both using r13 for their primary per-CPU data address. This patch moves OPAL to use r16 for this, and prevents the compiler from touching r13-r15 (r14,r15 allow Linux to use additional fixed registers in future). This helps code to be a little more robust, and may make crashes in OPAL (or debugging with pdbg or in simulators) easier to debug by having easy access to the PACA. Later, if we allow interrupts (other than non-maskable) to be taken when running in skiboot, Linux's interrupt return handler does not restore r13 if the interrupt was taken in PR=0 state, which would corrupt the skiboot r13 register, so this allows for the possibility, although it will have to become a formal OPAL ABI requirement if we rely on it. Signed-off-by: Nicholas Piggin --- Makefile.main | 11 +++++++++-- asm/head.S | 36 ++++++++++++++++++------------------ asm/misc.S | 8 ++++---- include/cpu.h | 2 +- 4 files changed, 32 insertions(+), 25 deletions(-) diff --git a/Makefile.main b/Makefile.main index deea59db8..86642ad67 100644 --- a/Makefile.main +++ b/Makefile.main @@ -96,7 +96,14 @@ endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables CFLAGS += -mcpu=power8 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb -CFLAGS += $(call try-cflag,$(CC),-ffixed-r13) +# r13,r14,r15 are preserved for OS to use as fixed registers. +# These could be saved and restored in and out of skiboot, but it's more +# robust to avoid touching them. +CFLAGS += -ffixed-r13 +CFLAGS += -ffixed-r14 +CFLAGS += -ffixed-r15 +# r16 is skiboot's per-CPU data pointer. +CFLAGS += -ffixed-r16 CFLAGS += $(call try-cflag,$(CC),-std=gnu11) ifeq ($(LITTLE_ENDIAN),1) @@ -127,7 +134,7 @@ endif # Check if the new parametrized stack protector option is supported # by gcc, otherwise disable stack protector -STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r13 +STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r16 STACK_PROT_CFLAGS += -mstack-protector-guard-offset=0 HAS_STACK_PROT := $(call test_cflag,$(CC),$(STACK_PROT_CFLAGS)) diff --git a/asm/head.S b/asm/head.S index 735e624bc..6a167e564 100644 --- a/asm/head.S +++ b/asm/head.S @@ -25,7 +25,7 @@ addi stack_reg,stack_reg,EMERGENCY_CPU_STACKS_OFFSET@l; #define GET_CPU() \ - clrrdi %r13,%r1,STACK_SHIFT + clrrdi %r16,%r1,STACK_SHIFT #define SAVE_GPR(reg,sp) std %r##reg,STACK_GPR##reg(sp) #define REST_GPR(reg,sp) ld %r##reg,STACK_GPR##reg(sp) @@ -403,7 +403,7 @@ boot_entry: * before relocation so we need to keep track of its location to wake * them up. */ - mr %r15,%r30 + mr %r18,%r30 /* Check if we need to copy ourselves up and update %r30 to * be our new offset @@ -449,7 +449,7 @@ boot_entry: /* Tell secondaries to move to second stage (relocated) spin loop */ LOAD_IMM32(%r3, boot_flag - __head) - add %r3,%r3,%r15 + add %r3,%r3,%r18 li %r0,1 stw %r0,0(%r3) @@ -464,18 +464,18 @@ boot_entry: addi %r3,%r3,8 bdnz 1b - /* Get our per-cpu pointer into r13 */ + /* Get our per-cpu pointer into r16 */ GET_CPU() #ifdef STACK_CHECK_ENABLED /* Initialize stack bottom mark to 0, it will be updated in C code */ li %r0,0 - std %r0,CPUTHREAD_STACK_BOT_MARK(%r13) + std %r0,CPUTHREAD_STACK_BOT_MARK(%r16) #endif /* Initialize the stack guard */ LOAD_IMM64(%r3,STACK_CHECK_GUARD_BASE); xor %r3,%r3,%r31 - std %r3,0(%r13) + std %r3,0(%r16) /* Jump to C */ mr %r3,%r27 @@ -536,7 +536,7 @@ secondary_not_found: b . call_relocate: - mflr %r14 + mflr %r17 LOAD_IMM32(%r4,__dynamic_start - __head) LOAD_IMM32(%r5,__rela_dyn_start - __head) add %r4,%r4,%r30 @@ -545,7 +545,7 @@ call_relocate: bl relocate cmpwi %r3,0 bne 1f - mtlr %r14 + mtlr %r17 blr 1: /* Fatal relocate failure */ attn @@ -592,12 +592,12 @@ reset_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() /* Restore original stack pointer */ - ld %r1,CPUTHREAD_SAVE_R1(%r13) + ld %r1,CPUTHREAD_SAVE_R1(%r16) /* Restore more stuff */ lwz %r4,STACK_CR(%r1) @@ -655,7 +655,7 @@ reset_fast_reboot_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() @@ -923,17 +923,17 @@ opal_entry: std %r9,STACK_GPR9(%r1) std %r10,STACK_GPR10(%r1) - /* Save Token (r0), LR and r13 */ + /* Save Token (r0), LR and r16 */ mflr %r12 std %r0,STACK_GPR0(%r1) - std %r13,STACK_GPR13(%r1) + std %r16,STACK_GPR16(%r1) std %r12,STACK_LR(%r1) /* Get the CPU thread */ GET_CPU() /* Store token in CPU thread */ - std %r0,CPUTHREAD_CUR_TOKEN(%r13) + std %r0,CPUTHREAD_CUR_TOKEN(%r16) /* Mark the stack frame */ li %r12,STACK_ENTRY_OPAL_API @@ -975,14 +975,14 @@ opal_entry: bl opal_exit_check /* r3 is preserved */ /* - * Restore r1 and r13 before decrementing in_opal_call. - * Move per-cpu pointer to volatile r12, restore lr, r1, r13. + * Restore r1 and r16 before decrementing in_opal_call. + * Move per-cpu pointer to volatile r12, restore lr, r1, r16. */ .Lreturn: ld %r12,STACK_LR(%r1) mtlr %r12 - mr %r12,%r13 - ld %r13,STACK_GPR13(%r1) + mr %r12,%r16 + ld %r16,STACK_GPR16(%r1) ld %r1,STACK_GPR1(%r1) .Lreject: sync /* release barrier vs quiescing */ diff --git a/asm/misc.S b/asm/misc.S index e797efcf1..10c1d1463 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -213,7 +213,7 @@ enter_p8_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) /* Winkle or nap ? */ cmpli %cr0,0,%r3,0 @@ -221,7 +221,7 @@ enter_p8_pm_state: /* nap sequence */ ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_NAP @@ -229,7 +229,7 @@ enter_p8_pm_state: /* rvwinkle sequence */ 1: ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_RVWINKLE @@ -250,7 +250,7 @@ enter_p9_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) mtspr SPR_PSSCR,%r3 PPC_INST_STOP diff --git a/include/cpu.h b/include/cpu.h index 686310d71..9b7f41dfb 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -212,7 +212,7 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id); core = next_available_core_in_chip(core, chip_id)) /* Return the caller CPU (only after init_cpu_threads) */ -register struct cpu_thread *__this_cpu asm("r13"); +register struct cpu_thread *__this_cpu asm("r16"); static inline __nomcount struct cpu_thread *this_cpu(void) { return __this_cpu; From patchwork Mon Apr 27 11:08:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hxr5h1Zz9sSc for ; Mon, 27 Apr 2020 21:14:40 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:12:46 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:12:46 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:01 +1000 Message-Id: <20200427110813.1276533-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 04/16] fast-reboot: add missing clear memory fallback X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/mem_region.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/core/mem_region.c b/core/mem_region.c index 00548326c..36de2d094 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -1379,8 +1379,14 @@ void start_mem_region_clear_unused(void) free(path); jobs[i] = cpu_queue_job_on_node(chip_id, job_args[i].job_name, - mem_region_clear_job, - &job_args[i]); + mem_region_clear_job, + &job_args[i]); + if (!jobs[i]) + jobs[i] = cpu_queue_job(NULL, + job_args[i].job_name, + mem_region_clear_job, + &job_args[i]); + assert(jobs[i]); i++; } unlock(&mem_region_lock); From patchwork Mon Apr 27 11:08:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hyK0S9Cz9sP7 for ; Mon, 27 Apr 2020 21:15:05 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:12:49 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:12:49 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:02 +1000 Message-Id: <20200427110813.1276533-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 05/16] fast-reboot: don't back up old vectors upon fast reboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Initial boot already saved original exception vectors to old_vectors, copying again upon fast reboot will overwrite old_vectors with some arbitrary vectors set up by the current OS. Signed-off-by: Nicholas Piggin --- core/init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/core/init.c b/core/init.c index 595d087fa..2bb48845d 100644 --- a/core/init.c +++ b/core/init.c @@ -859,11 +859,6 @@ void copy_sreset_vector_fast_reboot(void) void copy_exception_vectors(void) { - /* Backup previous vectors as this could contain a kernel - * image. - */ - memcpy_null(old_vectors, NULL, EXCEPTION_VECTORS_END); - /* Copy from 0x100 to EXCEPTION_VECTORS_END, avoid below 0x100 as * this is the boot flag used by CPUs still potentially entering * skiboot. @@ -1021,6 +1016,11 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) */ clear_console(); + /* Backup previous vectors as this could contain a kernel + * image. + */ + memcpy_null(old_vectors, NULL, EXCEPTION_VECTORS_END); + /* * Some boot firmwares enter OPAL with MSR[ME]=1, as they presumably * handle machine checks until we take over. As we overwrite the From patchwork Mon Apr 27 11:08:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hyf1TgFz9sSc for ; Mon, 27 Apr 2020 21:15:22 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=d3jUt/pu; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 499hyd3l8qzDqZ9 for ; Mon, 27 Apr 2020 21:15:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::532; helo=mail-pg1-x532.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=d3jUt/pu; dkim-atps=neutral Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 499hvr3N38zDqWJ for ; Mon, 27 Apr 2020 21:12:56 +1000 (AEST) Received: by mail-pg1-x532.google.com with SMTP id n11so437293pgl.9 for ; Mon, 27 Apr 2020 04:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XMVKUwcTNhJXWMAktsz/RMJU6gP5kdL4plnBmD7k6BU=; b=d3jUt/pumILMSjXeGzREuWqOOVMHqwG+rwB6xfIW7ldbQspbRCWvJCOzNXTI3T9MwA 32HKYcwbwugWomizV9FsywMR5eA5cewdGp23wsv0CXnyz1LEe2gE7EkW3YSkJ8ptz7Ko Xa+XBAQGxdgoH5rxsfyv1pidUru1KeSwjY187waLjijb6zoOcT8xtBe0QO/Dx7RbOdlK B0Gm0pSDH94E+W3Q3GIwbltpc7MYZlTrLyQxVfKn6PCFRXfosbS/Lk/NBI1FUZP1pTgN zwMjuZxCSuk0XkucX8FsF0mfBlr6ifM3h1QGnHU6iwhnD6Vii5KUS4q8TsV+GH1W409f tYkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XMVKUwcTNhJXWMAktsz/RMJU6gP5kdL4plnBmD7k6BU=; b=nZNuiUqUqjnPZoRO18xWdMPfBZIWS/Zhr8C70b4pVyxFDGpDt9qwH/YYhkiTZehQl+ zciOjjyzreJXrQOeS5obq12JBTTQf+CIFCBLumNWM9luTWCkuw9BvBI+olXeUsZScnra PLjIc5MDnwU8zLOgH/e8UCw32T+uFx2dGVnUP3Vm51M29LKnOp+UgXwtzsPV5JFccjMw 7898GAcWRHTMi0r53gWbDGe9FOTyDje74j3dIrs67rG4SYeV45C9oimLVAWtTsJpEAEj OBCUpdLS5iqLvUk7pcDIiZJ3r2Tj/LNOJ/yRO3r4UezRhovbi+HlrqttEyNAGqihT4jT /ynQ== X-Gm-Message-State: AGi0PubKp391I7VU3/9ZULmzS7tR782XTOTHHaDnJR/cF6q4apI4tmNM TuirYfw0YedOlReM7xVloVyXok92 X-Google-Smtp-Source: APiQypKq0ZeJASDCBuR6J73QDADrcjhTRhUbXLzbN7uWVk5GZiJVldRt90NCIk/IPiwsOSHay1c1EQ== X-Received: by 2002:a63:6302:: with SMTP id x2mr22042962pgb.375.1587985972262; Mon, 27 Apr 2020 04:12:52 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:12:51 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:03 +1000 Message-Id: <20200427110813.1276533-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 06/16] fast-reboot: improve fast reboot sequence X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The current fast reboot sequence is not as robust as it could be. It is this: - Fast reboot CPU stops all other threads with direct control xscoms; - it disables ME (machine checks become checkstops); - resets its SPRs (to get HID[HILE] for machine check interrupts) and overwrites exception vectors with our vectors, with a special fast reboot sreset vector that fixes endian (because OS owns HILE); - then the fast reboot CPU enables ME. At this point the fast reboot CPU can handle machine checks with the skiboot handler, but no other cores can if the OS had switched HILE (they'll execute garbled byte swapped instructions and crash badly). - Then all CPUs run various cleanups, XIVE, resync TOD, etc. - The boot CPU, which is not necessarily the same as the fast reboot initiator CPU, runs xive_reset. This is a lot of code to run, including locking and xscoms, with machine check inoperable. - Finally secondaries are released and everyone sets SPRs and enables ME. Secondaries on other cores don't wait for their thread 0 to set shared SPRs before calling into the normal OPAL secondary code. This is mostly okay because the boot CPU pauses here until all secondaries reach their idle code, but it's not nice to release them out of the fast reboot code in a state with various per-core SPRs in flux. Fix this by having the fast reboot CPU not disable ME or reset its SPRs, because machine checks can still be handled by the OS. Then wait until all CPUs are called into fast reboot and spinning with ME disabled, only then reset any SPRs, copy remaining exception vectors, and now skiboot has taken over the machine check handling, then the CPUs enable ME before cleaning up other things. This way, the region with ME disabled and SPRs and exception vectors in flux is kept absolutely minimal, with no xscoms, no MMIOs, and few significant memory modifications, and all threads kept closely in step. There are no windows where a machine check interrupt may execute garbage due to mismatched HILE on any CPU. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 239 +++++++++++++++++++++++---------------------- include/cpu.h | 1 + 2 files changed, 121 insertions(+), 119 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 02f0ca05b..03777543a 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -26,6 +26,20 @@ /* Flag tested by the OPAL entry code */ static volatile bool fast_boot_release; +static volatile bool spr_set_release; +static volatile bool nmi_mce_release; + +static void wait_on(volatile bool *cond) +{ + sync(); + if (!*cond) { + smt_lowest(); + while (!*cond) + barrier(); + smt_medium(); + } + sync(); +} static bool cpu_state_wait_all_others(enum cpu_thread_state state, unsigned long timeout_tb) @@ -131,6 +145,8 @@ void fast_reboot(void) prlog(PR_NOTICE, "RESET: Initiating fast reboot %d...\n", ++fast_reboot_count); fast_boot_release = false; + spr_set_release = false; + nmi_mce_release = false; sync(); /* Put everybody in stop except myself */ @@ -150,50 +166,16 @@ void fast_reboot(void) cpu_set_ipi_enable(false); /* - * There is no point clearing special wakeup or un-quiesce due to - * failure after this point, because we will be going to full IPL. - * Less cleanup work means less opportunity to fail. - */ - - /* - * Move SPRs and exception vectors back to OPAL-mode while all - * others are quiesced. MSR[ME] is disabled while these are switched, - * but system reset can not be blocked -- in theory an sreset coming - * from the BMC or SPE could crash here. - */ - disable_machine_check(); - - /* - * Primarily we want to fix up the HID bits here to allow the OPAL - * exception handlers to work. Machine check would be the important - * one. - * - * This is one case where a thread other than thread0 of the core - * may update the shared SPRs. All other threads are stopped, so - * there should be no races. - */ - init_shared_sprs(); - init_replicated_sprs(); - - /* Restore skiboot vectors */ - copy_exception_vectors(); - patch_traps(true); - - /* - * Secondaries may still have an issue with machine checks if they have - * HILE set because the machine check exception does not FIXUP_ENDIAN. - * Adding that would trash CFAR however. So we have a window where - * if a secondary takes an interrupt before the HILE is fixed, it will - * crash. + * The fast reboot sreset vector has FIXUP_ENDIAN, so secondaries can + * cope with a wrong HILE setting. */ - enable_machine_check(); - mtmsrd(MSR_RI, 1); + copy_sreset_vector_fast_reboot(); /* - * sreset vector has a FIXUP_ENDIAN sequence at the start, so - * secondaries can cope. + * There is no point clearing special wakeup or un-quiesce due to + * failure after this point, because we will be going to full IPL. + * Less cleanup work means less opportunity to fail. */ - copy_sreset_vector_fast_reboot(); /* Send everyone else to 0x100 */ if (sreset_all_others() != OPAL_SUCCESS) { @@ -203,7 +185,7 @@ void fast_reboot(void) } /* Ensure all the sresets get through */ - if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(1000))) { + if (!cpu_state_wait_all_others(cpu_state_fast_reboot_entry, msecs_to_tb(1000))) { prlog(PR_NOTICE, "RESET: Fast reboot timed out waiting for " "secondaries to call in\n"); return; @@ -217,48 +199,12 @@ void fast_reboot(void) console_complete_flush(); + mtmsrd(0, 1); /* Clear MSR[RI] for 0x100 reset */ asm volatile("ba 0x100\n\t" : : : "memory"); for (;;) ; } -static void cleanup_cpu_state(void) -{ - struct cpu_thread *cpu = this_cpu(); - - /* Per core cleanup */ - if (cpu_is_thread0(cpu)) { - /* Shared SPRs whacked back to normal */ - - /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ - init_shared_sprs(); - - if (proc_gen == proc_gen_p8) { - /* If somebody was in fast_sleep, we may have a - * workaround to undo - */ - if (cpu->in_fast_sleep) { - prlog(PR_DEBUG, "RESET: CPU 0x%04x in fast sleep" - " undoing workarounds...\n", cpu->pir); - fast_sleep_exit(); - } - - /* The TLB surely contains garbage. - * P9 clears TLBs in cpu_fast_reboot_complete - */ - cleanup_local_tlb(); - } - - /* And we might have lost TB sync */ - chiptod_wakeup_resync(); - } - - /* Per-thread additional cleanup */ - init_replicated_sprs(); - - // XXX Cleanup SLW, check HIDs ... -} - void __noreturn enter_nap(void); static void check_split_core(void) @@ -310,17 +256,46 @@ static void check_split_core(void) } } +static void cleanup_cpu_state(void) +{ + struct cpu_thread *cpu = this_cpu(); + + if (proc_gen == proc_gen_p9) + xive_cpu_reset(); + + /* Per core cleanup */ + if (cpu_is_thread0(cpu)) { + /* XXX should reset the SLW SPR restore values*/ + + if (proc_gen == proc_gen_p8) { + /* If somebody was in fast_sleep, we may have a + * workaround to undo + */ + if (cpu->in_fast_sleep) { + prlog(PR_DEBUG, "RESET: CPU 0x%04x in fast sleep" + " undoing workarounds...\n", cpu->pir); + fast_sleep_exit(); + } + + /* The TLB surely contains garbage. + * P9 clears TLBs in cpu_fast_reboot_complete + */ + cleanup_local_tlb(); + } + + /* And we might have lost TB sync */ + chiptod_wakeup_resync(); + } +} /* Entry from asm after a fast reset */ void __noreturn fast_reboot_entry(void); void __noreturn fast_reboot_entry(void) { - prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", this_cpu()->pir); + struct cpu_thread *cpu = this_cpu(); - if (proc_gen == proc_gen_p9) { - xive_cpu_reset(); - } else if (proc_gen == proc_gen_p8) { + if (proc_gen == proc_gen_p8) { /* We reset our ICP first ! Otherwise we might get stray * interrupts when unsplitting */ @@ -332,51 +307,87 @@ void __noreturn fast_reboot_entry(void) check_split_core(); } + /* Until SPRs (notably HID[HILE]) are set and new exception vectors + * installed, nobody should take machine checks. Try to do minimal + * work between these points. + */ + disable_machine_check(); + mtmsrd(0, 1); /* Clear RI */ + sync(); - this_cpu()->state = cpu_state_present; + cpu->state = cpu_state_fast_reboot_entry; sync(); + if (cpu == boot_cpu) { + cpu_state_wait_all_others(cpu_state_fast_reboot_entry, 0); + spr_set_release = true; + } else { + wait_on(&spr_set_release); + } - /* Are we the original boot CPU ? If not, we spin waiting - * for a relase signal from CPU 1, then we clean ourselves - * up and go processing jobs. - */ - if (this_cpu() != boot_cpu) { - if (!fast_boot_release) { - smt_lowest(); - while (!fast_boot_release) - barrier(); - smt_medium(); - } - sync(); - cleanup_cpu_state(); - enable_machine_check(); - mtmsrd(MSR_RI, 1); - __secondary_cpu_entry(); + /* Reset SPRs */ + if (cpu_is_thread0(cpu)) + init_shared_sprs(); + init_replicated_sprs(); + + if (cpu == boot_cpu) { + /* Restore skiboot vectors */ + copy_exception_vectors(); + copy_sreset_vector(); + patch_traps(true); } - prlog(PR_INFO, "RESET: Boot CPU waiting for everybody...\n"); + /* Must wait for others to because shared SPRs like HID0 are only set + * by thread0, so can't enable machine checks until those have been + * set. + */ + sync(); + cpu->state = cpu_state_present; + sync(); + if (cpu == boot_cpu) { + cpu_state_wait_all_others(cpu_state_present, 0); + nmi_mce_release = true; + } else { + wait_on(&nmi_mce_release); + } + + /* At this point skiboot exception vectors are in place and all + * cores/threads have SPRs set for running skiboot. + */ + enable_machine_check(); + mtmsrd(MSR_RI, 1); + + cleanup_cpu_state(); + + prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", cpu->pir); - /* We are the original boot CPU, wait for secondaries to - * be captured. + /* The original boot CPU (not the fast reboot initiator) takes + * command. Secondaries wait for the signal then go to their secondary + * entry point. */ - cpu_state_wait_all_others(cpu_state_present, 0); + if (cpu != boot_cpu) { + wait_on(&fast_boot_release); + + __secondary_cpu_entry(); + } if (proc_gen == proc_gen_p9) xive_reset(); + /* Let the CPU layer do some last minute global cleanups */ + cpu_fast_reboot_complete(); + + /* We can now do NAP mode */ + cpu_set_sreset_enable(true); + cpu_set_ipi_enable(true); + prlog(PR_INFO, "RESET: Releasing secondaries...\n"); /* Release everybody */ sync(); fast_boot_release = true; - - /* Cleanup ourselves */ - cleanup_cpu_state(); - - /* Set our state to active */ sync(); - this_cpu()->state = cpu_state_active; + cpu->state = cpu_state_active; sync(); /* Wait for them to respond */ @@ -389,16 +400,6 @@ void __noreturn fast_reboot_entry(void) /* Clear release flag for next time */ fast_boot_release = false; - /* Let the CPU layer do some last minute global cleanups */ - cpu_fast_reboot_complete(); - - /* Restore OPAL's sreset vector now that all CPUs have HILE clear */ - copy_sreset_vector(); - - /* We can now do NAP mode */ - cpu_set_sreset_enable(true); - cpu_set_ipi_enable(true); - if (!chip_quirk(QUIRK_MAMBO_CALLOUTS)) { /* * mem_region_clear_unused avoids these preload regions diff --git a/include/cpu.h b/include/cpu.h index 9b7f41dfb..8ef20e35b 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -21,6 +21,7 @@ enum cpu_thread_state { cpu_state_no_cpu = 0, /* Nothing there */ cpu_state_unknown, /* In PACA, not called in yet */ cpu_state_unavailable, /* Not available */ + cpu_state_fast_reboot_entry, /* Called back into OPAL, real mode */ cpu_state_present, /* Assumed to spin in asm entry */ cpu_state_active, /* Secondary called in */ cpu_state_os, /* Under OS control */ From patchwork Mon Apr 27 11:08:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hzC0vNRz9sP7 for ; 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Mon, 27 Apr 2020 04:12:54 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:04 +1000 Message-Id: <20200427110813.1276533-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 07/16] move opal_branch_table, opal_num_args to .rodata section X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" .head is for code and data which must reside at a fixed low address, mainly entry points. These are moved into .rodata. Despite being modified at runtime, this facilitates these tables being write-protected in a later patch. Signed-off-by: Nicholas Piggin --- asm/head.S | 7 ------- asm/misc.S | 10 ++++++++++ core/opal.c | 12 ++++++------ 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/asm/head.S b/asm/head.S index 6a167e564..450fb71f1 100644 --- a/asm/head.S +++ b/asm/head.S @@ -299,13 +299,6 @@ exception_entry_foo: b . .= EXCEPTION_VECTORS_END - /* This is the OPAL branch table. It's populated at boot time - * with function pointers to the various OPAL functions from - * the content of the .opal_table section, indexed by Token. - */ -.global opal_branch_table -opal_branch_table: - .space 8 * (OPAL_LAST + 1) /* Stores the offset we were started from. Used later on if we want to * read any unrelocated code/data such as the built-in kernel image diff --git a/asm/misc.S b/asm/misc.S index 10c1d1463..b016e6405 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -9,9 +9,19 @@ #include #include #include +#include #define OLD_BINUTILS 1 + .section ".rodata" + /* This is the OPAL branch table. It's populated at boot time + * with function pointers to the various OPAL functions from + * the content of the .opal_table section, indexed by Token. + */ +.global opal_branch_table +opal_branch_table: + .space 8 * (OPAL_LAST + 1) + .section ".text","ax" .balign 0x10 diff --git a/core/opal.c b/core/opal.c index 64fdfe62a..46518c445 100644 --- a/core/opal.c +++ b/core/opal.c @@ -28,10 +28,10 @@ uint64_t opal_pending_events; /* OPAL dispatch table defined in head.S */ -extern uint64_t opal_branch_table[]; +extern const uint64_t opal_branch_table[]; /* Number of args expected for each call. */ -static u8 opal_num_args[OPAL_LAST+1]; +static const u8 opal_num_args[OPAL_LAST+1]; /* OPAL anchor node */ struct dt_node *opal_node; @@ -53,8 +53,8 @@ void opal_table_init(void) prlog(PR_DEBUG, "OPAL table: %p .. %p, branch table: %p\n", s, e, opal_branch_table); while(s < e) { - opal_branch_table[s->token] = function_entry_address(s->func); - opal_num_args[s->token] = s->nargs; + ((uint64_t *)opal_branch_table)[s->token] = function_entry_address(s->func); + ((u8 *)opal_num_args)[s->token] = s->nargs; s++; } } @@ -321,8 +321,8 @@ void __opal_register(uint64_t token, void *func, unsigned int nargs) { assert(token <= OPAL_LAST); - opal_branch_table[token] = function_entry_address(func); - opal_num_args[token] = nargs; + ((uint64_t *)opal_branch_table)[token] = function_entry_address(func); + ((u8 *)opal_num_args)[token] = nargs; } /* From patchwork Mon Apr 27 11:08:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hzY1GRvz9sSc for ; Mon, 27 Apr 2020 21:16:09 +1000 (AEST) Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:12:57 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:05 +1000 Message-Id: <20200427110813.1276533-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 08/16] skiboot.lds.S: remove dynsym/dynstr and plt X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" skiboot is static so these are always empty. Signed-off-by: Nicholas Piggin --- skiboot.lds.S | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/skiboot.lds.S b/skiboot.lds.S index 3431f1f88..eed26eab0 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -163,10 +163,6 @@ SECTIONS __platforms_end = .; } - /* Do I need to keep these ? */ - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - /* Relocations */ . = ALIGN(0x10); .dynamic : { @@ -181,12 +177,8 @@ SECTIONS *(.rela*) __rela_dyn_end = .; } - .plt : { *(.plt) *(.iplt) } - .hash : { *(.hash) } .gnu.hash : { *(.gnu.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } .gnu.version : { *(.gnu.version) } .gnu.version_d : { *(.gnu.version_d) } .gnu.version_r : { *(.gnu.version_r) } @@ -252,5 +244,9 @@ SECTIONS *(.eh_frame) *(.interp) *(.fini_array.*) + *(.dynsym) + *(.dynstr) + *(.plt) + *(.iplt) } } From patchwork Mon Apr 27 11:08:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499hzw2rvFz9sP7 for ; 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Mon, 27 Apr 2020 04:12:59 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:06 +1000 Message-Id: <20200427110813.1276533-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 09/16] skiboot.lds.S: introduce PAGE_SIZE, use it to lay out sections X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Separate code, data, read-only data, and other significant sections with PAGE_SIZE alignment. This enables memory protection for these sections with a later patch. Signed-off-by: Nicholas Piggin --- include/config.h | 3 +++ skiboot.lds.S | 22 ++++++++++++++-------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/config.h b/include/config.h index cb88edbc7..fd9521fa2 100644 --- a/include/config.h +++ b/include/config.h @@ -4,6 +4,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* Alignment to which skiboot lays out memory. */ +#define PAGE_SIZE 0x10000 + #define HAVE_TYPEOF 1 #define HAVE_BUILTIN_TYPES_COMPATIBLE_P 1 diff --git a/skiboot.lds.S b/skiboot.lds.S index eed26eab0..b136e4004 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -75,6 +75,7 @@ SECTIONS } _head_end = .; + . = ALIGN(PAGE_SIZE); /* * The following sections are read-write at runtime. We need @@ -107,14 +108,14 @@ SECTIONS } /* ...and back to RO */ - - . = ALIGN(0x10); + . = ALIGN(PAGE_SIZE); _stext = .; .text : { *(.text*) *(.sfpr .glink) } _etext = .; + . = ALIGN(PAGE_SIZE); .rodata : { __rodata_start = .; @@ -177,6 +178,7 @@ SECTIONS *(.rela*) __rela_dyn_end = .; } + .hash : { *(.hash) } .gnu.hash : { *(.gnu.hash) } .gnu.version : { *(.gnu.version) } @@ -196,22 +198,26 @@ SECTIONS */ _romem_end = .; + . = ALIGN(PAGE_SIZE); + + _sdata = .; .data : { /* * A couple of things that need to be 4K aligned and * to reside in their own pages for the sake of TCE - * mappings + * mappings, so use PAGE_SIZE alignment. */ - . = ALIGN(0x1000); + . = ALIGN(PAGE_SIZE); *(.data.memcons); - . = ALIGN(0x10000); + . = ALIGN(PAGE_SIZE); *(.data.boot_trace); - . = ALIGN(0x10000); + . = ALIGN(PAGE_SIZE); *(.data*) *(.force.data) *(.toc1) *(.branch_lt) } + _edata = .; /* We locate the BSS at 4M to leave room for the symbol map */ . = 0x400000; @@ -221,7 +227,7 @@ SECTIONS *(.dynbss) *(.bss*) } - . = ALIGN(0x10000); + . = ALIGN(PAGE_SIZE); _ebss = .; _end = .; @@ -230,7 +236,7 @@ SECTIONS DEBUG_SECTIONS /* Optional kernel image */ - . = ALIGN(0x10000); + . = ALIGN(PAGE_SIZE); .builtin_kernel : { __builtin_kernel_start = .; KEEP(*(.builtin_kernel)) From patchwork Mon Apr 27 11:08:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499j08648lz9sP7 for ; Mon, 27 Apr 2020 21:16:40 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Mon, 27 Apr 2020 04:13:02 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:13:02 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:07 +1000 Message-Id: <20200427110813.1276533-11-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 10/16] core: interrupt markers for stack traces X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Use magic marker in the exception stack frame that is used by the unwinder to decode the interrupt type and NIA. The below example trace comes from a modified skiboot that uses virtual memory, but any interrupt type will appear similarly. CPU 0000 Backtrace: S: 0000000031c13580 R: 0000000030028210 .vm_dsi+0x360 S: 0000000031c13630 R: 000000003003b0dc .exception_entry+0x4fc S: 0000000031c13830 R: 0000000030001f4c exception_entry_foo+0x4 --- Interrupt 0x300 at 000000003002431c --- S: 0000000031c13b40 R: 000000003002430c .make_free.isra.0+0x110 S: 0000000031c13bd0 R: 0000000030025198 .mem_alloc+0x4a0 S: 0000000031c13c80 R: 0000000030028bac .__memalign+0x48 S: 0000000031c13d10 R: 0000000030028da4 .__zalloc+0x18 S: 0000000031c13d90 R: 000000003002fb34 .opal_init_msg+0x34 S: 0000000031c13e20 R: 00000000300234b4 .main_cpu_entry+0x61c S: 0000000031c13f00 R: 00000000300031b8 boot_entry+0x1b0 --- OPAL boot --- Signed-off-by: Nicholas Piggin --- asm/asm-offsets.c | 1 + asm/head.S | 5 +++++ core/exceptions.c | 2 ++ core/stack.c | 11 +++++++++++ include/mem-map.h | 2 +- include/stack.h | 6 ++++++ 6 files changed, 26 insertions(+), 1 deletion(-) diff --git a/asm/asm-offsets.c b/asm/asm-offsets.c index 2328d4d0f..7be0a1157 100644 --- a/asm/asm-offsets.c +++ b/asm/asm-offsets.c @@ -38,6 +38,7 @@ int main(void) OFFSET(CPUTHREAD_STACK_BOT_TOK, cpu_thread, stack_bot_tok); #endif OFFSET(STACK_TYPE, stack_frame, type); + OFFSET(STACK_MAGIC, stack_frame, magic); OFFSET(STACK_LOCALS, stack_frame, locals); OFFSET(STACK_GPR0, stack_frame, gpr[0]); OFFSET(STACK_GPR1, stack_frame, gpr[1]); diff --git a/asm/head.S b/asm/head.S index 450fb71f1..88b2bc12a 100644 --- a/asm/head.S +++ b/asm/head.S @@ -176,6 +176,7 @@ _exception: mfspr %r3,SPR_SRR0 mfspr %r4,SPR_SRR1 std %r3,STACK_SRR0(%r1) + std %r3,16(%r1) std %r4,STACK_SRR1(%r1) mfspr %r3,SPR_DSISR mfspr %r4,SPR_DAR @@ -231,6 +232,8 @@ _exception: stw %r4,STACK_XER(%r1) std %r5,STACK_CTR(%r1) std %r6,STACK_LR(%r1) + LOAD_IMM64(%r3,STACK_INT_MAGIC) + std %r3,STACK_MAGIC(%r1) LOAD_IMM64(%r4, SKIBOOT_BASE) LOAD_IMM32(%r5,__toc_start - __head) LOAD_IMM32(%r6, exception_entry_foo - __head) @@ -928,6 +931,8 @@ opal_entry: /* Store token in CPU thread */ std %r0,CPUTHREAD_CUR_TOKEN(%r16) + LOAD_IMM64(%r12,STACK_INT_MAGIC) + std %r12,STACK_MAGIC(%r1) /* Mark the stack frame */ li %r12,STACK_ENTRY_OPAL_API std %r12,STACK_TYPE(%r1) diff --git a/core/exceptions.c b/core/exceptions.c index dacc02a28..fd069aa60 100644 --- a/core/exceptions.c +++ b/core/exceptions.c @@ -65,6 +65,8 @@ void exception_entry(struct stack_frame *stack) nip = stack->srr0; msr = stack->srr1; } + stack->msr = msr; + stack->pc = nip; if (!(msr & MSR_RI)) fatal = true; diff --git a/core/stack.c b/core/stack.c index 688ef7044..2df960b3e 100644 --- a/core/stack.c +++ b/core/stack.c @@ -35,6 +35,12 @@ static void __nomcount __backtrace_create(struct bt_entry *entries, if (!fp || (unsigned long)fp > top_adj) break; eframe = (struct stack_frame *)fp; + if (eframe->magic == STACK_INT_MAGIC) { + entries->exception_type = eframe->type; + entries->exception_pc = eframe->pc; + } else { + entries->exception_type = 0; + } entries->sp = (unsigned long)fp; entries->pc = fp[2]; entries++; @@ -99,6 +105,11 @@ void backtrace_print(struct bt_entry *entries, struct bt_metadata *metadata, if (symbols) l += snprintf_symbol(buf + l, max - l, entries->pc); l += snprintf(buf + l, max - l, "\n"); + if (entries->exception_type) { + l += snprintf(buf + l, max - l, + " --- Interrupt 0x%lx at %016lx ---\n", + entries->exception_type, entries->exception_pc); + } entries++; } if (metadata->token <= OPAL_LAST) diff --git a/include/mem-map.h b/include/mem-map.h index b65401257..15ec09ea0 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -19,7 +19,7 @@ /* End of the exception region we copy from 0x0. 0x0-0x100 will have * IPL data and is not actually for exception vectors. */ -#define EXCEPTION_VECTORS_END 0x2000 +#define EXCEPTION_VECTORS_END 0x3000 #define NACA_OFF 0x4000 diff --git a/include/stack.h b/include/stack.h index bd4fa2f64..3e987ea81 100644 --- a/include/stack.h +++ b/include/stack.h @@ -45,6 +45,7 @@ #define STACK_WARNING_GAP 2048 #define STACK_CHECK_GUARD_BASE 0xdeadf00dbaad300 +#define STACK_INT_MAGIC 0xb1ab1af00ba1234ULL #ifndef __ASSEMBLY__ @@ -72,6 +73,9 @@ struct stack_frame { * one doubleword. */ uint64_t locals[1]; + /* Interrupt entry magic value */ + uint64_t magic; + /* Entry type */ uint64_t type; @@ -104,6 +108,8 @@ struct stack_frame { struct bt_entry { unsigned long sp; unsigned long pc; + unsigned long exception_type; + unsigned long exception_pc; }; /* Backtrace metadata */ From patchwork Mon Apr 27 11:08:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499j0W6mMmz9sP7 for ; Mon, 27 Apr 2020 21:16:59 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:13:05 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:13:04 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:08 +1000 Message-Id: <20200427110813.1276533-12-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 11/16] core/mce: add support for decoding and handling machine checks X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This provides an initial facility to decode machine checks into human readable strings, plus a minimum amount of metadata that a handler has to understand in order to deal with the machine check. For now this is only used by skiboot to make MCE reporting nicer, and an ERAT flush recovery attempt which is more about code coverage than really being helpful. *********************************************** Fatal MCE at 00000000300c9c0c .memcmp+0x3c MSR 9000000000141002 Cause: instruction fetch TLB multi-hit error Effective address: 0x00000000300c9c0c ... The intention is to subsequently provide an OPAL API with this information that will enable an OS to implement a machine independent OPAL machine check driver. The code and data tables are derived from Linux code that I wrote, so relicensing is okay. Signed-off-by: Nicholas Piggin --- core/Makefile.inc | 2 +- core/exceptions.c | 57 ++++++++++++-- core/mce.c | 187 ++++++++++++++++++++++++++++++++++++++++++++ include/processor.h | 6 ++ include/ras.h | 47 +++++++++++ 5 files changed, 293 insertions(+), 6 deletions(-) create mode 100644 core/mce.c create mode 100644 include/ras.h diff --git a/core/Makefile.inc b/core/Makefile.inc index cc7d7895c..829800e5b 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -7,7 +7,7 @@ CORE_OBJS = relocate.o console.o stack.o init.o chip.o mem_region.o CORE_OBJS += malloc.o lock.o cpu.o utils.o fdt.o opal.o interrupts.o timebase.o CORE_OBJS += opal-msg.o pci.o pci-virt.o pci-slot.o pcie-slot.o CORE_OBJS += pci-opal.o fast-reboot.o device.o exceptions.o trace.o affinity.o -CORE_OBJS += vpd.o platform.o nvram.o nvram-format.o hmi.o +CORE_OBJS += vpd.o platform.o nvram.o nvram-format.o hmi.o mce.o CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o diff --git a/core/exceptions.c b/core/exceptions.c index fd069aa60..389548d16 100644 --- a/core/exceptions.c +++ b/core/exceptions.c @@ -10,6 +10,7 @@ #include #include #include +#include #define REG "%016llx" #define REG32 "%08x" @@ -32,6 +33,54 @@ static void dump_regs(struct stack_frame *stack) #define EXCEPTION_MAX_STR 320 +static void handle_mce(struct stack_frame *stack, uint64_t nip, uint64_t msr, bool *fatal) +{ + uint64_t mce_flags, mce_addr; + const char *mce_err; + const char *mce_fix = NULL; + char buf[EXCEPTION_MAX_STR]; + size_t l; + + decode_mce(stack->srr0, stack->srr1, stack->dsisr, stack->dar, + &mce_flags, &mce_err, &mce_addr); + + /* Try to recover. */ + if (mce_flags & MCE_ERAT_ERROR) { + /* Real-mode still uses ERAT, flush transient bitflips */ + flush_erat(); + mce_fix = "ERAT flush"; + + } else { + *fatal = true; + } + + prerror("***********************************************\n"); + l = 0; + l += snprintf(buf + l, EXCEPTION_MAX_STR - l, + "%s MCE at "REG" ", *fatal ? "Fatal" : "Non-fatal", nip); + l += snprintf_symbol(buf + l, EXCEPTION_MAX_STR - l, nip); + l += snprintf(buf + l, EXCEPTION_MAX_STR - l, " MSR "REG, msr); + prerror("%s\n", buf); + + l = 0; + l += snprintf(buf + l, EXCEPTION_MAX_STR - l, + "Cause: %s", mce_err); + prerror("%s\n", buf); + if (mce_flags & MCE_INVOLVED_EA) { + l = 0; + l += snprintf(buf + l, EXCEPTION_MAX_STR - l, + "Effective address: 0x%016llx", mce_addr); + prerror("%s\n", buf); + } + + if (!*fatal) { + l = 0; + l += snprintf(buf + l, EXCEPTION_MAX_STR - l, + "Attempting recovery: %s", mce_fix); + prerror("%s\n", buf); + } +} + void exception_entry(struct stack_frame *stack) { bool fatal = false; @@ -85,11 +134,8 @@ void exception_entry(struct stack_frame *stack) break; case 0x200: - fatal = true; - prerror("***********************************************\n"); - l += snprintf(buf + l, EXCEPTION_MAX_STR - l, - "Fatal MCE at "REG" ", nip); - break; + handle_mce(stack, nip, msr, &fatal); + goto no_symbol; case 0x700: { struct trap_table_entry *tte; @@ -130,6 +176,7 @@ void exception_entry(struct stack_frame *stack) l += snprintf_symbol(buf + l, EXCEPTION_MAX_STR - l, nip); l += snprintf(buf + l, EXCEPTION_MAX_STR - l, " MSR "REG, msr); prerror("%s\n", buf); +no_symbol: dump_regs(stack); backtrace_r1((uint64_t)stack); if (fatal) { diff --git a/core/mce.c b/core/mce.c new file mode 100644 index 000000000..a07eeb6a8 --- /dev/null +++ b/core/mce.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: Apache-2.0 +/* + * Machine Check Exceptions + * + * Copyright 2020 IBM Corp. + */ + +#define pr_fmt(fmt) "MCE: " fmt + +#include +#include +#include + +#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) + +struct mce_ierror_table { + unsigned long srr1_mask; + unsigned long srr1_value; + uint64_t type; + const char *error_str; +}; + +static const struct mce_ierror_table mce_p9_ierror_table[] = { +{ 0x00000000081c0000, 0x0000000000040000, + MCE_INSNFETCH | MCE_MEMORY_ERROR | MCE_INVOLVED_EA, + "instruction fetch memory uncorrectable error", }, +{ 0x00000000081c0000, 0x0000000000080000, + MCE_INSNFETCH | MCE_SLB_ERROR | MCE_INVOLVED_EA, + "instruction fetch SLB parity error", }, +{ 0x00000000081c0000, 0x00000000000c0000, + MCE_INSNFETCH | MCE_SLB_ERROR | MCE_INVOLVED_EA, + "instruction fetch SLB multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000100000, + MCE_INSNFETCH | MCE_INVOLVED_EA | MCE_ERAT_ERROR, + "instruction fetch ERAT multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000140000, + MCE_INSNFETCH | MCE_INVOLVED_EA | MCE_TLB_ERROR, + "instruction fetch TLB multi-hit error", }, +{ 0x00000000081c0000, 0x0000000000180000, + MCE_INSNFETCH | MCE_MEMORY_ERROR | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access memory uncorrectable error", }, +{ 0x00000000081c0000, 0x00000000001c0000, + MCE_INSNFETCH | MCE_INVOLVED_EA, + "instruction fetch to foreign address", }, +{ 0x00000000081c0000, 0x0000000008000000, + MCE_INSNFETCH | MCE_INVOLVED_EA, + "instruction fetch foreign link time-out", }, +{ 0x00000000081c0000, 0x0000000008040000, + MCE_INSNFETCH | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access foreign link time-out", }, +{ 0x00000000081c0000, 0x00000000080c0000, + MCE_INSNFETCH | MCE_INVOLVED_EA, + "instruction fetch real address error", }, +{ 0x00000000081c0000, 0x0000000008100000, + MCE_INSNFETCH | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access real address error", }, +{ 0x00000000081c0000, 0x0000000008140000, + MCE_LOADSTORE | MCE_IMPRECISE, + "store real address asynchronous error", }, +{ 0x00000000081c0000, 0x0000000008180000, + MCE_LOADSTORE | MCE_IMPRECISE, + "store foreign link time-out asynchronous error", }, +{ 0x00000000081c0000, 0x00000000081c0000, + MCE_INSNFETCH | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "instruction fetch page table access to foreign address", }, +{ 0 } }; + +struct mce_derror_table { + unsigned long dsisr_value; + uint64_t type; + const char *error_str; +}; + +static const struct mce_derror_table mce_p9_derror_table[] = { +{ 0x00008000, + MCE_LOADSTORE | MCE_MEMORY_ERROR, + "load/store memory uncorrectable error", }, +{ 0x00004000, + MCE_LOADSTORE | MCE_MEMORY_ERROR | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "load/store page table access memory uncorrectable error", }, +{ 0x00002000, + MCE_LOADSTORE | MCE_INVOLVED_EA, + "load/store foreign link time-out", }, +{ 0x00001000, + MCE_LOADSTORE | MCE_TABLE_WALK | MCE_INVOLVED_EA, + "load/store page table access foreign link time-out", }, +{ 0x00000800, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_ERAT_ERROR, + "load/store ERAT multi-hit error", }, +{ 0x00000400, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_TLB_ERROR, + "load/store TLB multi-hit error", }, +{ 0x00000200, + MCE_LOADSTORE | MCE_TLBIE_ERROR, + "TLBIE or TLBIEL instruction programming error", }, +{ 0x00000100, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_SLB_ERROR, + "load/store SLB parity error", }, +{ 0x00000080, + MCE_LOADSTORE | MCE_INVOLVED_EA | MCE_SLB_ERROR, + "load/store SLB multi-hit error", }, +{ 0x00000040, + MCE_LOADSTORE | MCE_INVOLVED_EA, + "load real address error", }, +{ 0x00000020, + MCE_LOADSTORE | MCE_TABLE_WALK, + "load/store page table access real address error", }, +{ 0x00000010, + MCE_LOADSTORE | MCE_TABLE_WALK, + "load/store page table access to foreign address", }, +{ 0x00000008, + MCE_LOADSTORE, + "load/store to foreign address", }, +{ 0 } }; + +static void decode_ierror(const struct mce_ierror_table table[], + uint64_t srr1, + uint64_t *type, + const char **error_str) +{ + int i; + + for (i = 0; table[i].srr1_mask; i++) { + if ((srr1 & table[i].srr1_mask) != table[i].srr1_value) + continue; + + *type = table[i].type; + *error_str = table[i].error_str; + } +} + +static void decode_derror(const struct mce_derror_table table[], + uint32_t dsisr, + uint64_t *type, + const char **error_str) +{ + int i; + + for (i = 0; table[i].dsisr_value; i++) { + if (!(dsisr & table[i].dsisr_value)) + continue; + + *type = table[i].type; + *error_str = table[i].error_str; + } +} + +void decode_mce(uint64_t srr0, uint64_t srr1, + uint32_t dsisr, uint64_t dar, + uint64_t *type, const char **error_str, + uint64_t *address) +{ + *type = MCE_UNKNOWN; + *error_str = "unknown error"; + *address = 0; + + if (proc_gen != proc_gen_p9) { + *error_str = "unknown error (processor not supported)"; + return; + } + + /* + * On POWER9 DD2.1 and below, it's possible to get a machine check + * caused by a paste instruction where only DSISR bit 25 is set. This + * will result in the MCE handler seeing an unknown event and the + * kernel crashing. An MCE that occurs like this is spurious, so we + * don't need to do anything in terms of servicing it. If there is + * something that needs to be serviced, the CPU will raise the MCE + * again with the correct DSISR so that it can be serviced properly. + * So detect this case and mark it as handled. + */ + if (SRR1_MC_LOADSTORE(srr1) && dsisr == 0x02000000) { + *type = MCE_NO_ERROR; + *error_str = "no error (superfluous machine check)"; + return; + } + + if (SRR1_MC_LOADSTORE(srr1)) { + decode_derror(mce_p9_derror_table, dsisr, type, error_str); + if (*type & MCE_INVOLVED_EA) + *address = dar; + } else { + decode_ierror(mce_p9_ierror_table, srr1, type, error_str); + if (*type & MCE_INVOLVED_EA) + *address = srr0; + } +} diff --git a/include/processor.h b/include/processor.h index 57c2ee13a..7ba251bb4 100644 --- a/include/processor.h +++ b/include/processor.h @@ -230,6 +230,12 @@ static inline bool is_power9n(uint32_t version) #ifndef __TEST__ +/* POWER9 and above only */ +static inline void flush_erat(void) +{ + asm volatile("slbia 7"); +} + /* * SMT priority */ diff --git a/include/ras.h b/include/ras.h new file mode 100644 index 000000000..d0faaeefb --- /dev/null +++ b/include/ras.h @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2020 IBM Corp. */ + +#ifndef __RAS_H +#define __RAS_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MCE_NO_ERROR 0x0001 +#define MCE_UNKNOWN 0x0002 +#define MCE_INSNFETCH 0x0004 +#define MCE_LOADSTORE 0x0008 +#define MCE_TABLE_WALK 0x0010 +#define MCE_IMPRECISE 0x0020 +#define MCE_MEMORY_ERROR 0x0040 +#define MCE_SLB_ERROR 0x0080 +#define MCE_ERAT_ERROR 0x0100 +#define MCE_TLB_ERROR 0x0200 +#define MCE_TLBIE_ERROR 0x0400 +#define MCE_INVOLVED_EA 0x0800 +#define MCE_INVOLVED_PA 0x1000 + +void decode_mce(uint64_t srr0, uint64_t srr1, + uint32_t dsisr, uint64_t dar, + uint64_t *type, const char **error_str, + uint64_t *address); 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Mon, 27 Apr 2020 04:13:07 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:13:07 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:09 +1000 Message-Id: <20200427110813.1276533-13-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 12/16] build: -fverbose-asm for .s targets X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- Makefile.rules | 4 ++++ asm/asm-offsets.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile.rules b/Makefile.rules index 8c41c26e4..dcebde6d2 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -64,6 +64,10 @@ endif $(call Q,CC, $(CC) $(call cook_cflags,$@) -x c -c $< -o $@, $@) %.s : %.c + $(call Q,CC, $(CC) $(call cook_cflags,$@) -fverbose-asm -S -c $< -o $@, $@) + +# no -fverbose-asm for asm-offsets.s +asm/asm-offsets.s: asm/asm-offsets.c $(call Q,CC, $(CC) $(call cook_cflags,$@) -S -c $< -o $@, $@) %.i : %.c diff --git a/asm/asm-offsets.c b/asm/asm-offsets.c index 7be0a1157..532437c1b 100644 --- a/asm/asm-offsets.c +++ b/asm/asm-offsets.c @@ -11,7 +11,7 @@ #include #define DEFINE(sym, val) \ - asm volatile("\n#define " #sym " %0 /* " #val " */" : : "i" (val)) + asm volatile("\n#define " #sym " %0 /* " #val " */\n" : : "i" (val)) #define OFFSET(sym, str, mem) \ DEFINE(sym, offsetof(struct str, mem)) From patchwork Mon Apr 27 11:08:10 2020 Content-Type: text/plain; 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Mon, 27 Apr 2020 04:13:10 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:13:09 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:10 +1000 Message-Id: <20200427110813.1276533-14-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 13/16] hdata: MS AREA endian fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hdata/memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index 7ce927502..a9db9d744 100755 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -512,11 +512,11 @@ static void add_memory_buffer_mmio(const struct HDIF_common_hdr *msarea) const struct HDIF_array_hdr *array; unsigned int i, count, ranges = 0; struct dt_node *membuf; - uint64_t *reg, *flags; + beint64_t *reg, *flags; - if (be32_to_cpu(msarea->version) < 0x50) { + if (be16_to_cpu(msarea->version) < 0x50) { prlog(PR_WARNING, "MS AREA: Inconsistent MSAREA version %x for P9P system", - be32_to_cpu(msarea->version)); + be16_to_cpu(msarea->version)); return; } From patchwork Mon Apr 27 11:08:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499j1K59wcz9sP7 for ; Mon, 27 Apr 2020 21:17:41 +1000 (AEST) Authentication-Results: ozlabs.org; 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Mon, 27 Apr 2020 04:13:12 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:11 +1000 Message-Id: <20200427110813.1276533-15-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 14/16] platform/blackbird: endian fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- platforms/astbmc/blackbird.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/astbmc/blackbird.c b/platforms/astbmc/blackbird.c index 41de010f7..d7a1f81d6 100644 --- a/platforms/astbmc/blackbird.c +++ b/platforms/astbmc/blackbird.c @@ -61,7 +61,7 @@ static int64_t blackbird_write_oppanel_async(uint64_t async_token __unused, return OPAL_PARAMETER; line = (void *) be64_to_cpu(lines[0].line); - len = lines[0].line_len; + len = be64_to_cpu(lines[0].line_len); if (len > 0) lpc_probe_write(OPAL_LPC_IO, 0x80, line[0], 1); From patchwork Mon Apr 27 11:08:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499j1Y6Tdpz9sP7 for ; Mon, 27 Apr 2020 21:17:53 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=utiu8gVK; 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Mon, 27 Apr 2020 04:13:15 -0700 (PDT) Received: from bobo.ibm.com ([203.220.177.17]) by smtp.gmail.com with ESMTPSA id b1sm10567431pfi.140.2020.04.27.04.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2020 04:13:14 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:12 +1000 Message-Id: <20200427110813.1276533-16-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 15/16] io: endian annotations and fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Annotate io accessor pointer types with endian. sparse caught a bug in memcpy_from_ci, which is fixed. From: Nicholas Piggin --- hw/npu2-opencapi.c | 12 ++++----- include/io.h | 48 ++++++++++++++++++------------------ libc/string/memcpy_from_ci.c | 7 +++++- 3 files changed, 36 insertions(+), 31 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index b03aad345..035c6cdc3 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1427,7 +1427,7 @@ static int64_t npu2_opencapi_pcicfg_read(struct phb *phb, uint32_t bdfn, cfg_addr = SETFIELD(NPU2_CQ_CTL_CONFIG_ADDR_REGISTER_NUMBER, cfg_addr, offset & ~3u); - out_be64((uint64_t *)genid_base, cfg_addr); + out_be64((beint64_t *)genid_base, cfg_addr); sync(); switch (size) { @@ -1437,10 +1437,10 @@ static int64_t npu2_opencapi_pcicfg_read(struct phb *phb, uint32_t bdfn, break; case 2: *((uint16_t *)data) = - in_le16((volatile uint16_t *)(genid_base + 128 + (offset & 2))); + in_le16((volatile leint16_t *)(genid_base + 128 + (offset & 2))); break; case 4: - *((uint32_t *)data) = in_le32((volatile uint32_t *)(genid_base + 128)); + *((uint32_t *)data) = in_le32((volatile leint32_t *)(genid_base + 128)); break; default: return OPAL_PARAMETER; @@ -1485,7 +1485,7 @@ static int64_t npu2_opencapi_pcicfg_write(struct phb *phb, uint32_t bdfn, cfg_addr = SETFIELD(NPU2_CQ_CTL_CONFIG_ADDR_REGISTER_NUMBER, cfg_addr, offset & ~3u); - out_be64((uint64_t *)genid_base, cfg_addr); + out_be64((beint64_t *)genid_base, cfg_addr); sync(); switch (size) { @@ -1494,11 +1494,11 @@ static int64_t npu2_opencapi_pcicfg_write(struct phb *phb, uint32_t bdfn, data); break; case 2: - out_le16((volatile uint16_t *)(genid_base + 128 + (offset & 2)), + out_le16((volatile leint16_t *)(genid_base + 128 + (offset & 2)), data); break; case 4: - out_le32((volatile uint32_t *)(genid_base + 128), data); + out_le32((volatile leint32_t *)(genid_base + 128), data); break; default: return OPAL_PARAMETER; diff --git a/include/io.h b/include/io.h index ecdd3d0bf..f00021dcd 100644 --- a/include/io.h +++ b/include/io.h @@ -34,7 +34,7 @@ static inline uint8_t in_8(const volatile uint8_t *addr) return __in_8(addr); } -static inline uint16_t __in_be16(const volatile uint16_t *addr) +static inline uint16_t __in_be16(const volatile beint16_t *addr) { __be16 val; asm volatile("lhzcix %0,0,%1" : @@ -42,13 +42,13 @@ static inline uint16_t __in_be16(const volatile uint16_t *addr) return be16_to_cpu(val); } -static inline uint16_t in_be16(const volatile uint16_t *addr) +static inline uint16_t in_be16(const volatile beint16_t *addr) { sync(); return __in_be16(addr); } -static inline uint16_t __in_le16(const volatile uint16_t *addr) +static inline uint16_t __in_le16(const volatile leint16_t *addr) { __le16 val; asm volatile("lhzcix %0,0,%1" : @@ -56,13 +56,13 @@ static inline uint16_t __in_le16(const volatile uint16_t *addr) return le16_to_cpu(val); } -static inline uint16_t in_le16(const volatile uint16_t *addr) +static inline uint16_t in_le16(const volatile leint16_t *addr) { sync(); return __in_le16(addr); } -static inline uint32_t __in_be32(const volatile uint32_t *addr) +static inline uint32_t __in_be32(const volatile beint32_t *addr) { __be32 val; asm volatile("lwzcix %0,0,%1" : @@ -70,13 +70,13 @@ static inline uint32_t __in_be32(const volatile uint32_t *addr) return be32_to_cpu(val); } -static inline uint32_t in_be32(const volatile uint32_t *addr) +static inline uint32_t in_be32(const volatile beint32_t *addr) { sync(); return __in_be32(addr); } -static inline uint32_t __in_le32(const volatile uint32_t *addr) +static inline uint32_t __in_le32(const volatile leint32_t *addr) { __le32 val; asm volatile("lwzcix %0,0,%1" : @@ -84,13 +84,13 @@ static inline uint32_t __in_le32(const volatile uint32_t *addr) return le32_to_cpu(val); } -static inline uint32_t in_le32(const volatile uint32_t *addr) +static inline uint32_t in_le32(const volatile leint32_t *addr) { sync(); return __in_le32(addr); } -static inline uint64_t __in_be64(const volatile uint64_t *addr) +static inline uint64_t __in_be64(const volatile beint64_t *addr) { __be64 val; asm volatile("ldcix %0,0,%1" : @@ -98,13 +98,13 @@ static inline uint64_t __in_be64(const volatile uint64_t *addr) return be64_to_cpu(val); } -static inline uint64_t in_be64(const volatile uint64_t *addr) +static inline uint64_t in_be64(const volatile beint64_t *addr) { sync(); return __in_be64(addr); } -static inline uint64_t __in_le64(const volatile uint64_t *addr) +static inline uint64_t __in_le64(const volatile leint64_t *addr) { __le64 val; asm volatile("ldcix %0,0,%1" : @@ -112,7 +112,7 @@ static inline uint64_t __in_le64(const volatile uint64_t *addr) return le64_to_cpu(val); } -static inline uint64_t in_le64(const volatile uint64_t *addr) +static inline uint64_t in_le64(const volatile leint64_t *addr) { sync(); return __in_le64(addr); @@ -130,73 +130,73 @@ static inline void out_8(volatile uint8_t *addr, uint8_t val) return __out_8(addr, val); } -static inline void __out_be16(volatile uint16_t *addr, uint16_t val) +static inline void __out_be16(volatile beint16_t *addr, uint16_t val) { asm volatile("sthcix %0,0,%1" : : "r"(cpu_to_be16(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_be16(volatile uint16_t *addr, uint16_t val) +static inline void out_be16(volatile beint16_t *addr, uint16_t val) { sync(); return __out_be16(addr, val); } -static inline void __out_le16(volatile uint16_t *addr, uint16_t val) +static inline void __out_le16(volatile leint16_t *addr, uint16_t val) { asm volatile("sthcix %0,0,%1" : : "r"(cpu_to_le16(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_le16(volatile uint16_t *addr, uint16_t val) +static inline void out_le16(volatile leint16_t *addr, uint16_t val) { sync(); return __out_le16(addr, val); } -static inline void __out_be32(volatile uint32_t *addr, uint32_t val) +static inline void __out_be32(volatile beint32_t *addr, uint32_t val) { asm volatile("stwcix %0,0,%1" : : "r"(cpu_to_be32(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_be32(volatile uint32_t *addr, uint32_t val) +static inline void out_be32(volatile beint32_t *addr, uint32_t val) { sync(); return __out_be32(addr, val); } -static inline void __out_le32(volatile uint32_t *addr, uint32_t val) +static inline void __out_le32(volatile leint32_t *addr, uint32_t val) { asm volatile("stwcix %0,0,%1" : : "r"(cpu_to_le32(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_le32(volatile uint32_t *addr, uint32_t val) +static inline void out_le32(volatile leint32_t *addr, uint32_t val) { sync(); return __out_le32(addr, val); } -static inline void __out_be64(volatile uint64_t *addr, uint64_t val) +static inline void __out_be64(volatile beint64_t *addr, uint64_t val) { asm volatile("stdcix %0,0,%1" : : "r"(cpu_to_be64(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_be64(volatile uint64_t *addr, uint64_t val) +static inline void out_be64(volatile beint64_t *addr, uint64_t val) { sync(); return __out_be64(addr, val); } -static inline void __out_le64(volatile uint64_t *addr, uint64_t val) +static inline void __out_le64(volatile leint64_t *addr, uint64_t val) { asm volatile("stdcix %0,0,%1" : : "r"(cpu_to_le64(val)), "r"(addr), "m"(*addr) : "memory"); } -static inline void out_le64(volatile uint64_t *addr, uint64_t val) +static inline void out_le64(volatile leint64_t *addr, uint64_t val) { sync(); return __out_le64(addr, val); diff --git a/libc/string/memcpy_from_ci.c b/libc/string/memcpy_from_ci.c index 103853b45..dd4d94e02 100644 --- a/libc/string/memcpy_from_ci.c +++ b/libc/string/memcpy_from_ci.c @@ -16,7 +16,12 @@ void *memcpy_from_ci(void *destpp, const void *srcpp, size_t len) /* Copy as many blocks as possible if srcp is block aligned */ if ((srcp % block) == 0) { while ((len - block) > -1) { - *((uint64_t*) destp) = in_be64((uint64_t*)srcp); + uint64_t v; + if (HAVE_BIG_ENDIAN) + v = in_be64((beint64_t*)srcp); + else + v = in_le64((leint64_t*)srcp); + *((uint64_t *) destp) = v; srcp += block; destp += block; len -= block; From patchwork Mon Apr 27 11:08:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1277559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 499j1q1JBBz9sP7 for ; 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Mon, 27 Apr 2020 04:13:17 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2020 21:08:13 +1000 Message-Id: <20200427110813.1276533-17-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200427110813.1276533-1-npiggin@gmail.com> References: <20200427110813.1276533-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 16/16] include/ocmb.h: Add a newline to end of file X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Sparse complains about no newline at end of file. Signed-off-by: Nicholas Piggin --- include/ocmb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/ocmb.h b/include/ocmb.h index e7531885d..92212f33c 100644 --- a/include/ocmb.h +++ b/include/ocmb.h @@ -10,4 +10,4 @@ extern void ocmb_init(void); -#endif /* __OCMB_H */ \ No newline at end of file +#endif /* __OCMB_H */