From patchwork Fri Apr 24 18:20:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1276562 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.a=rsa-sha256 header.s=STMicroelectronics header.b=oSi2CoAQ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4982Yv30zPz9sSG for ; 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Fri, 24 Apr 2020 20:20:58 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F03F710002A; Fri, 24 Apr 2020 20:20:57 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E58A82CF9BE; Fri, 24 Apr 2020 20:20:57 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 20:20:57 +0200 From: Patrick Delaunay To: CC: Marek Vasut , Simon Glass , Patrick Delaunay , Alexey Brodkin , Lokesh Vutla , Tom Rini , Trevor Woerner , U-Boot STM32 Subject: [PATCH v2 1/3] arm: caches: protect dram_bank_mmu_setup access to bi_dram Date: Fri, 24 Apr 2020 20:20:15 +0200 Message-ID: <20200424201957.v2.1.I64599059b66bacb531db38c67273754a145dbad8@changeid> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424182017.11852-1-patrick.delaunay@st.com> References: <20200424182017.11852-1-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-24_09:2020-04-24, 2020-04-24 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram before relocation. This patch allow to use the generic weak function dram_bank_mmu_setup to activate the MMU and the data cache in SPL or in U-Boot before relocation, when bd->bi_dram is not yet initialized. In this cases, the MMU must be initialized explicitly with mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- Changes in v2: None arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d20960da..54509f11c3 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -91,6 +91,10 @@ __weak void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + From patchwork Fri Apr 24 18:20:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1276564 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 24 Apr 2020 20:20:58 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9B94D2CF9BE; Fri, 24 Apr 2020 20:20:58 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 20:20:58 +0200 From: Patrick Delaunay To: CC: Marek Vasut , Simon Glass , Patrick Delaunay , Alexey Brodkin , Lokesh Vutla , Rajesh Ravi , Tom Rini , Trevor Woerner , Vladimir Olovyannikov , U-Boot STM32 Subject: [PATCH v2 2/3] arm: caches: add DCACHE_DEFAULT_OPTION Date: Fri, 24 Apr 2020 20:20:16 +0200 Message-ID: <20200424201957.v2.2.Ib6abcb05422a74bc6bc03daa71b15c98c99dbc5d@changeid> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424182017.11852-1-patrick.delaunay@st.com> References: <20200424182017.11852-1-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG3NODE1.st.com (10.75.127.7) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-24_09:2020-04-24, 2020-04-24 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay --- CONFIG_SYS_ARM_CACHE_WRITEBACK dependency with [v2] configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig http://patchwork.ozlabs.org/patch/1269103/ Changes in v2: None arch/arm/include/asm/system.h | 8 ++++++++ arch/arm/lib/cache-cp15.c | 11 ++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead112..a3147fde14 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -485,6 +485,14 @@ enum dcache_option { }; #endif +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 54509f11c3..d15144188b 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -99,15 +99,8 @@ __weak void dram_bank_mmu_setup(int bank) for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) - set_section_dcache(i, DCACHE_WRITEALLOC); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); } /* to activate the MMU we need to set up virtual memory: use 1M areas */ From patchwork Fri Apr 24 18:20:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1276563 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Fri, 24 Apr 2020 20:20:59 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5B4C62CF9BD; Fri, 24 Apr 2020 20:20:59 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 20:20:58 +0200 From: Patrick Delaunay To: CC: Marek Vasut , Simon Glass , Patrick Delaunay , Alexey Brodkin , Lokesh Vutla , Tom Rini , Trevor Woerner , U-Boot STM32 Subject: [PATCH v2 3/3] arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour Date: Fri, 24 Apr 2020 20:20:17 +0200 Message-ID: <20200424201957.v2.3.Ic2c7c6923035711a4c653d52ae7c0f57ca6f9210@changeid> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424182017.11852-1-patrick.delaunay@st.com> References: <20200424182017.11852-1-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-24_09:2020-04-24, 2020-04-24 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Solved the overflow on phys_addr_t type for start + size in mmu_set_region_dcache_behaviour() function. This overflow is avoided by dividing start and end by 2 before addition, and we only expecting that start and size are even. This patch doesn't change the current function behavior if the parameters (start or size) are not aligned on MMU_SECTION_SIZE. For example, this overflow occurs on ARM32 with: start = 0xC0000000 and size = 0x40000000 then start + size = 0x100000000 and end = 0x0. For information the function behavior change with risk of regression, if we just shift start and size before the addition. Example with 2MB section size: MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21 with start = 0x1000000, size = 0x1000000, - with the proposed patch, start = 0 and end = 0x1 as previously - with the more simple patch: end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT) the value of end change: start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!! Signed-off-by: Patrick Delaunay --- Changes in v2: - update patch after Marek's proposal. but I just divided by 2 instead of 4kB (minimal MMU page size) arch/arm/lib/cache-cp15.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index d15144188b..f803d6fb8c 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -61,8 +61,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, unsigned long startpt, stoppt; unsigned long upto, end; - end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; + /* div by 2 before start + size to avoid phys_addr_t overflow */ + end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2) + >> (MMU_SECTION_SHIFT - 1); start = start >> MMU_SECTION_SHIFT; + #ifdef CONFIG_ARMV7_LPAE debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, option);