From patchwork Thu Apr 23 16:01:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 1275841 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.a=rsa-sha256 header.s=STMicroelectronics header.b=GT/73xOz; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 497MXG1PYTz9sSX for ; Fri, 24 Apr 2020 02:02:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 314FC804F5; Thu, 23 Apr 2020 18:02:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="GT/73xOz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 274E780390; Thu, 23 Apr 2020 18:02:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DEBEE80390 for ; Thu, 23 Apr 2020 18:02:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=patrice.chotard@st.com Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03NFqIVV005150; Thu, 23 Apr 2020 18:02:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=EIFbQ5vOjghQj8OBGAUUa5LUp2mtz9ui3WYEuHbTn34=; b=GT/73xOzHy0r838Nx18PWLxgZmQFFWNQbA6RZBTKlfEKUklgHUDAXfHXlWVKxz5zbife dVlQbmUC6q4MVEXvn1+um4b6bTXtSdD0Z+WdoJ1Ny1BHGhsP5aGOxk2eoCSv/kKaNXz6 J5pLlrYm9jI72KRNnQoF4KW179c0aZvk7J9748g1GLz9Ms3PPNJAKnoQ5weOf1MzME2Z X651IVvwTZeZsr211qnqAaEAoqs+wWevomTBGdnDtBpI+Yfaw9huefUod+AzTy1LWPc5 CFiB2obHSr7KrBXzq9RCe6/OefzvSMFJJFwduEcyYh4OKlXtfVyJX8AtCFGYKd6quPjc 5w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 30fq11ww5r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2020 18:02:23 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A2CB9100034; Thu, 23 Apr 2020 18:02:20 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7D5342A8A8E; Thu, 23 Apr 2020 18:02:20 +0200 (CEST) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Apr 2020 18:02:19 +0200 From: Patrice Chotard To: CC: Patrice CHOTARD , Patrick DELAUNAY , U-Boot STM32 , Marek Vasut , Joe Hershberger , Ramon Fried , Stephen Warren , Alexey Brodkin , Eric Perie , Rajesh Ravi , Simon Glass , Trevor Woerner , Vladimir Olovyannikov Subject: [PATCH] cmd: cache: Fix non-cached memory cachability Date: Thu, 23 Apr 2020 18:01:55 +0200 Message-ID: <20200423160155.9258-1-patrice.chotard@st.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG4NODE1.st.com (10.75.127.10) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-23_12:2020-04-23, 2020-04-23 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean If dcache is switched OFF to ON state and if non-cached memory is used, this non-cached memory must be re-declared as uncached to mmu each time dcache is set ON. Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver, when going from dcache OFF to dcache ON state, ethernet driver issued TX timeout errors when performing dhcp or ping. It can be reproduced with the following sequence: dhcp while true ; do ping 192.168.1.300 ; dcache off ; ping 192.168.1.300 ; dcache on ; done Signed-off-by: Patrice Chotard Cc: Marek Vasut Cc: Joe Hershberger Cc: Ramon Fried Cc: Stephen Warren --- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache.c | 13 ++++++++++--- cmd/cache.c | 3 +++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead112..06fb458301 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -584,6 +584,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, #ifdef CONFIG_SYS_NONCACHED_MEMORY void noncached_init(void); +void noncached_set_region(void); phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_SYS_NONCACHED_MEMORY */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 007d4ebc49..7f3cfb407c 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -73,6 +73,15 @@ static unsigned long noncached_start; static unsigned long noncached_end; static unsigned long noncached_next; +void noncached_set_region(void) +{ +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) + mmu_set_region_dcache_behaviour(noncached_start, + noncached_end - noncached_start, + DCACHE_OFF); +#endif +} + void noncached_init(void) { phys_addr_t start, end; @@ -89,9 +98,7 @@ void noncached_init(void) noncached_end = end; noncached_next = start; -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) - mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); -#endif + noncached_set_region(); } phys_addr_t noncached_alloc(size_t size, size_t align) diff --git a/cmd/cache.c b/cmd/cache.c index 27dcec0931..86fbaf8dd6 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -64,6 +64,9 @@ static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; case 1: dcache_enable(); +#ifdef CONFIG_SYS_NONCACHED_MEMORY + noncached_set_region(); +#endif break; case 2: flush_dcache_all();