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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id q71sm14830635pfc.92.2020.04.07.12.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2020 12:07:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-5.0? v2] target/xtensa: Statically allocate xtensa_insnbufs in DisasContext Date: Tue, 7 Apr 2020 12:07:38 -0700 Message-Id: <20200407190738.15162-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Max Filippov Rather than dynamically allocate, and risk failing to free when we longjmp out of the translator, allocate the maximum buffer size from any of the supported cpus. Signed-off-by: Max Filippov [rth: Merged the fixup in Max's reply to his original] Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 3 +++ target/xtensa/helper.c | 1 + target/xtensa/translate.c | 18 ++---------------- 3 files changed, 6 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c0d69fad96..7a46dccbe1 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -213,6 +213,9 @@ enum { #define MEMCTL_IL0EN 0x1 #define MAX_INSN_LENGTH 64 +#define MAX_INSNBUF_LENGTH \ + ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ + sizeof(xtensa_insnbuf_word)) #define MAX_INSN_SLOTS 32 #define MAX_OPCODE_ARGS 16 #define MAX_NAREG 64 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 376a61f339..7073381f03 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -96,6 +96,7 @@ static void init_libisa(XtensaConfig *config) config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); + assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH); opcodes = xtensa_isa_num_opcodes(config->isa); formats = xtensa_isa_num_formats(config->isa); regfiles = xtensa_isa_num_regfiles(config->isa); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 37f65b1f03..b898ee2261 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -72,8 +72,8 @@ struct DisasContext { unsigned cpenable; uint32_t op_flags; - xtensa_insnbuf insnbuf; - xtensa_insnbuf slotbuf; + xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH]; + xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH]; }; static TCGv_i32 cpu_pc; @@ -1173,16 +1173,6 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> XTENSA_TBFLAG_CALLINC_SHIFT); - - /* - * FIXME: This will leak when a failed instruction load or similar - * event causes us to longjump out of the translation loop and - * hence not clean-up in xtensa_tr_tb_stop - */ - if (dc->config->isa) { - dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); - dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); - } init_sar_tracker(dc); } @@ -1272,10 +1262,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); reset_sar_tracker(dc); - if (dc->config->isa) { - xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); - xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); - } if (dc->icount) { tcg_temp_free(dc->next_icount); }