From patchwork Fri Apr 3 20:22:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266207 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=WkkX/ox3; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBDw6PXQz9sSM for ; Sat, 4 Apr 2020 07:22:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728133AbgDCUWU (ORCPT ); Fri, 3 Apr 2020 16:22:20 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:38133 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727627AbgDCUWT (ORCPT ); Fri, 3 Apr 2020 16:22:19 -0400 Received: by mail-wr1-f65.google.com with SMTP id c7so10001293wrx.5; Fri, 03 Apr 2020 13:22:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ds23RDty3T9KSp1T//1bKmXLBRBBOLQ6ILYzvtVdGuk=; b=WkkX/ox3pxwosR0x0gjkJmKmzUbhartWZp9pSZVVDqgH437Km9+myxlO7waBXheKip 0dKE9MWfkgaX/bfUFgvbHwfU8Q7sMbwq9roXr/Vg/ltyDIe4HvfDTdARfVxf4gpEBBsl uwU6KSayyZSr577rYckhT9MMLNcocOEA6V8R7rOP/rCbNNiyRk0UV28uTQ4DKQV5Uyni 7NDwUyirqKg7ut6yR9n0YG0mT6kiQo58ohap779Oh6f31/Un5KlwL0Ry2gL4Bvsz9c2z ZDYqPr+Va648b+UuXNTSyg5Ibds758YzBdXY2O3Ml8MXC6IhIyLiDVwyKGlvlhThZvbs FqrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ds23RDty3T9KSp1T//1bKmXLBRBBOLQ6ILYzvtVdGuk=; b=Do8I1DizsCYj6eIMOBNYyaLZp3vCeOQXzZwxZH3phbOyfb1jco0t2n2jHbvwrOaeAm D+1QmirkJA/Q3ZDZgqIgS53hrHVNUBEvi/yFp7bqhqyMovHjeWCemEhU+xkm2TLMxIm4 2/xwP0H+qEcVX7r1+nyFGgvAffwcsWoKHXQeZ95zH13a3bYKob0PkhMBQydhk8dxUZpW Sfm48ELQ8zyQxq7iqMXlNHCa4zzNTHUOG9DGpnv2p83B0dG+nMKlTKsMQvDbQTOAkPCH F6xc6vs3l9DePcIWgGO5Xcqyem+Rnfeee1xYcnwzco8OGyBRJWig4lJ7mEjPQGnFdpRn GopA== X-Gm-Message-State: AGi0PuZyj3xD9zuhL7yoo5jlQYVNLw1ajvWanSt06eXg5yXPaxy7y2nG zP2xLoXLv81SVd6p+UCDApIWbB4C X-Google-Smtp-Source: APiQypIlXc3c4rHatTLupXgeOHasAqZiJ/mK3qaB+KZQH4fd7SrGbTqkI3398BCNgxbrqwTlELQAjA== X-Received: by 2002:adf:e403:: with SMTP id g3mr10252917wrm.333.1585945338024; Fri, 03 Apr 2020 13:22:18 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id z129sm12870112wmb.7.2020.04.03.13.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:17 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers Date: Fri, 3 Apr 2020 22:22:03 +0200 Message-Id: <20200403202209.299823-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The NVIDIA Tegra186 SoC contains an IP block that provides a register interface for ten timers with a 29-bit counter that can generate one- shot, periodic or watchdog interrupts. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v2: - add required properties section - add additionalProperties: false - do not show status in example .../bindings/timer/nvidia,tegra186-timer.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..d722cd267bf9 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 timers + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: | + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC + (timestamp counter). The timers run at either a fixed 1 MHz clock rate + derived from the oscillator clock. Each timer can be programmed to raise + one-shot, periodic, or watchdog interrupts. + +properties: + compatible: + oneOf: + - description: NVIDIA Tegra186 + items: + - const: nvidia,tegra186-timer + + - description: NVIDIA Tegra194 + items: + - const: nvidia,tegra194-timer + - const: nvidia,tegra186-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 10 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + }; From patchwork Fri Apr 3 20:22:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=iDj9dZiO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBFP4Ftgz9sSM for ; Sat, 4 Apr 2020 07:22:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728327AbgDCUW0 (ORCPT ); Fri, 3 Apr 2020 16:22:26 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:41997 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728160AbgDCUWX (ORCPT ); Fri, 3 Apr 2020 16:22:23 -0400 Received: by mail-wr1-f65.google.com with SMTP id h15so10004239wrx.9; Fri, 03 Apr 2020 13:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/byLbPHXzqGipkHiLkMGAF22eE4Djb4LKjST/QT+s8=; b=iDj9dZiOMzlXhqYhZlQFeQF/3gqWfaA0K5JW8BEEvnc/96y7pDTraUo6oxRLWdQ8fF eLdpo/O1156ORg9GSWIxQDEBQvwP1F+MzvSyz15ZNOU8cW7BSP7V3IcUQXIEPG/8yuac /TbSO2KtkfOqZThXXNOOimYCFdLBLDnHPkoPg2n1Up9ABQXhmOAbsPnAKK4kLO1Jm80y xasMTJl3fWReQVi8Gk/kfKwrK/0+3EPUOI8eut4kL6BSpr6FlMRMc0CW/EPQ0/IHdQLF iQteVH12XwU2MsYJDnTj8llC23arNhxvuoex6llGv6DeNa/QFVOcgm3B5Cp9vCkHj8K8 MEpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/byLbPHXzqGipkHiLkMGAF22eE4Djb4LKjST/QT+s8=; b=UZ+sH5taGUpJWBdeaWYeiB8EPQyCxq6olw0tysOIVw2hxEJEHGdunGTyTRhqihv6Cv ImM/H1h7rfafczhxfZoWelAV13aFHpTHQwEfPs2L6q7w9j9o/BqM0R7OMdoa9pN3WTRR hntixVon57pb5gQxDpdnANHOmu53vl2SJPSOq4SHgQEE+7ekjCNSGRFyDf5txRd/9ONG 5ulT0Bdp6fHGTA2Z5fDEvwEcmGzz2D6QcED7vhfmF/m/vYtJoeD5DDejZV1uAO/07zWM ETMAeUlBkFLJCxdAOBNJWytej6l9Z7H9ma2H7nn8a83nahgAYJKKUd2rO4INZ3eKF7VX 6cxw== X-Gm-Message-State: AGi0PuaNCrgyIAkqW4fXc2AGc0U9dr9aaCflUXjTQ7VbywbxeHtgNWPw yP49jhD7e+7vHjXK9doNjGc= X-Google-Smtp-Source: APiQypKajEF8cK5QClBk4bdpnUf6bKa1FDujNyfEbQKLZPbxoMGF3ByzOjRGvlgVaQSpkTgahjdNyA== X-Received: by 2002:a05:6000:10c8:: with SMTP id b8mr10207717wrx.138.1585945339852; Fri, 03 Apr 2020 13:22:19 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id t17sm8409161wrv.53.2020.04.03.13.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:18 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/7] clocksource: Add Tegra186 timers support Date: Fri, 3 Apr 2020 22:22:04 +0200 Message-Id: <20200403202209.299823-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Currently this only supports a single watchdog, which uses a timer in the background for countdown. Eventually the timers could be used for various time-keeping tasks, but by default the architected timer will already provide that functionality. Signed-off-by: Thierry Reding --- Changes in v3: - request IRQ at the end of ->probe() to avoid race condition - only enable/disable watchdog when it's active - use _relaxed variants of register accessors - drop tegra186_timer.irq field Changes in v2: - add dependency on WATCHDOG && WATCHDOG_CORE - expose TSC, OSC and USEC clocksources - implement suspend/resume support - make driver tristate drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-tegra186.c | 508 +++++++++++++++++++++++++++ 3 files changed, 517 insertions(+) create mode 100644 drivers/clocksource/timer-tegra186.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f2142e6bbea3..385573c215d8 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -149,6 +149,14 @@ config TEGRA_TIMER help Enables support for the Tegra driver. +config TEGRA186_TIMER + tristate "NVIDIA Tegra186 timer driver" + depends on ARCH_TEGRA || COMPILE_TEST + depends on WATCHDOG && WATCHDOG_CORE + help + Enables support for the timers and watchdogs found on NVIDIA + Tegra186 and later SoCs. + config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 641ba5383ab5..ffa7950f4b7c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o +obj-$(CONFIG_TEGRA186_TIMER) += timer-tegra186.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c new file mode 100644 index 000000000000..4515517c87a5 --- /dev/null +++ b/drivers/clocksource/timer-tegra186.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* shared registers */ +#define TKETSC0 0x000 +#define TKETSC1 0x004 +#define TKEUSEC 0x008 +#define TKEOSC 0x00c + +#define TKEIE(x) (0x100 + ((x) * 4)) +#define TKEIE_WDT_MASK(x, y) ((y) << (16 + 4 * (x))) + +/* timer registers */ +#define TMRCR 0x000 +#define TMRCR_ENABLE BIT(31) +#define TMRCR_PERIODIC BIT(30) +#define TMRCR_PTV(x) ((x) & 0x0fffffff) + +#define TMRSR 0x004 +#define TMRSR_INTR_CLR BIT(30) + +#define TMRCSSR 0x008 +#define TMRCSSR_SRC_USEC (0 << 0) + +/* watchdog registers */ +#define WDTCR 0x000 +#define WDTCR_SYSTEM_POR_RESET_ENABLE BIT(16) +#define WDTCR_SYSTEM_DEBUG_RESET_ENABLE BIT(15) +#define WDTCR_REMOTE_INT_ENABLE BIT(14) +#define WDTCR_LOCAL_FIQ_ENABLE BIT(13) +#define WDTCR_LOCAL_INT_ENABLE BIT(12) +#define WDTCR_PERIOD_MASK (0xff << 4) +#define WDTCR_PERIOD(x) (((x) & 0xff) << 4) +#define WDTCR_TIMER_SOURCE_MASK 0xf +#define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) + +#define WDTCMDR 0x008 +#define WDTCMDR_DISABLE_COUNTER BIT(1) +#define WDTCMDR_START_COUNTER BIT(0) + +#define WDTUR 0x00c +#define WDTUR_UNLOCK_PATTERN 0x0000c45a + +struct tegra186_timer_soc { + unsigned int num_timers; + unsigned int num_wdts; +}; + +struct tegra186_tmr { + struct tegra186_timer *parent; + void __iomem *regs; + unsigned int index; + unsigned int hwirq; +}; + +struct tegra186_wdt { + struct watchdog_device base; + + void __iomem *regs; + unsigned int index; + bool locked; + + struct tegra186_tmr *tmr; +}; + +static inline struct tegra186_wdt *to_tegra186_wdt(struct watchdog_device *wdd) +{ + return container_of(wdd, struct tegra186_wdt, base); +} + +struct tegra186_timer { + const struct tegra186_timer_soc *soc; + struct device *dev; + void __iomem *regs; + + struct tegra186_wdt *wdt; + struct clocksource usec; + struct clocksource tsc; + struct clocksource osc; +}; + +static void tmr_writel(struct tegra186_tmr *tmr, u32 value, unsigned int offset) +{ + writel_relaxed(value, tmr->regs + offset); +} + +static void wdt_writel(struct tegra186_wdt *wdt, u32 value, unsigned int offset) +{ + writel_relaxed(value, wdt->regs + offset); +} + +static u32 wdt_readl(struct tegra186_wdt *wdt, unsigned int offset) +{ + return readl_relaxed(wdt->regs + offset); +} + +static struct tegra186_tmr *tegra186_tmr_create(struct tegra186_timer *tegra, + unsigned int index) +{ + unsigned int offset = 0x10000 + index * 0x10000; + struct tegra186_tmr *tmr; + + tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); + if (!tmr) + return ERR_PTR(-ENOMEM); + + tmr->parent = tegra; + tmr->regs = tegra->regs + offset; + tmr->index = index; + tmr->hwirq = 0; + + return tmr; +} + +static const struct watchdog_info tegra186_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, + .identity = "NVIDIA Tegra186 WDT", +}; + +static void tegra186_wdt_disable(struct tegra186_wdt *wdt) +{ + /* unlock and disable the watchdog */ + wdt_writel(wdt, WDTUR_UNLOCK_PATTERN, WDTUR); + wdt_writel(wdt, WDTCMDR_DISABLE_COUNTER, WDTCMDR); + + /* disable timer */ + tmr_writel(wdt->tmr, 0, TMRCR); +} + +static void tegra186_wdt_enable(struct tegra186_wdt *wdt) +{ + struct tegra186_timer *tegra = wdt->tmr->parent; + u32 value; + + /* unmask hardware IRQ, this may have been lost across powergate */ + value = TKEIE_WDT_MASK(wdt->index, 1); + writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); + + /* clear interrupt */ + tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR); + + /* select microsecond source */ + tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); + + /* configure timer (system reset happens on the fifth expiration) */ + value = TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) | + TMRCR_PERIODIC | TMRCR_ENABLE; + tmr_writel(wdt->tmr, value, TMRCR); + + if (!wdt->locked) { + value = wdt_readl(wdt, WDTCR); + + /* select the proper timer source */ + value &= ~WDTCR_TIMER_SOURCE_MASK; + value |= WDTCR_TIMER_SOURCE(wdt->tmr->index); + + /* single timer period since that's already configured */ + value &= ~WDTCR_PERIOD_MASK; + value |= WDTCR_PERIOD(1); + + /* enable local interrupt for WDT petting */ + value |= WDTCR_LOCAL_INT_ENABLE; + + /* enable local FIQ and remote interrupt for debug dump */ + if (0) + value |= WDTCR_REMOTE_INT_ENABLE | + WDTCR_LOCAL_FIQ_ENABLE; + + /* enable system debug reset (doesn't properly reboot) */ + if (0) + value |= WDTCR_SYSTEM_DEBUG_RESET_ENABLE; + + /* enable system POR reset */ + value |= WDTCR_SYSTEM_POR_RESET_ENABLE; + + wdt_writel(wdt, value, WDTCR); + } + + wdt_writel(wdt, WDTCMDR_START_COUNTER, WDTCMDR); +} + +static int tegra186_wdt_start(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_stop(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + + return 0; +} + +static int tegra186_wdt_ping(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + if (watchdog_active(&wdt->base)) + tegra186_wdt_disable(wdt); + + wdt->base.timeout = timeout; + + if (watchdog_active(&wdt->base)) + tegra186_wdt_enable(wdt); + + return 0; +} + +static const struct watchdog_ops tegra186_wdt_ops = { + .owner = THIS_MODULE, + .start = tegra186_wdt_start, + .stop = tegra186_wdt_stop, + .ping = tegra186_wdt_ping, + .set_timeout = tegra186_wdt_set_timeout, +}; + +static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, + unsigned int index) +{ + unsigned int offset = 0x10000, source; + struct tegra186_wdt *wdt; + u32 value; + int err; + + offset += tegra->soc->num_timers * 0x10000 + index * 0x10000; + + wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return ERR_PTR(-ENOMEM); + + wdt->regs = tegra->regs + offset; + wdt->index = index; + + /* read the watchdog configuration since it might be locked down */ + value = wdt_readl(wdt, WDTCR); + + if (value & WDTCR_LOCAL_INT_ENABLE) + wdt->locked = true; + + source = value & WDTCR_TIMER_SOURCE_MASK; + + wdt->tmr = tegra186_tmr_create(tegra, source); + if (IS_ERR(wdt->tmr)) + return ERR_CAST(wdt->tmr); + + wdt->base.info = &tegra186_wdt_info; + wdt->base.ops = &tegra186_wdt_ops; + wdt->base.min_timeout = 1; + wdt->base.max_timeout = 255; + wdt->base.parent = tegra->dev; + + err = watchdog_init_timeout(&wdt->base, 5, tegra->dev); + if (err < 0) { + dev_err(tegra->dev, "failed to initialize timeout: %d\n", err); + return ERR_PTR(err); + } + + err = devm_watchdog_register_device(tegra->dev, &wdt->base); + if (err < 0) { + dev_err(tegra->dev, "failed to register WDT: %d\n", err); + return ERR_PTR(err); + } + + return wdt; +} + +static u64 tegra186_timer_tsc_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer, + tsc); + u32 hi, lo, ss; + + hi = readl_relaxed(tegra->regs + TKETSC1); + + /* + * The 56-bit value of the TSC is spread across two registers that are + * not synchronized. In order to read them atomically, ensure that the + * high 24 bits match before and after reading the low 32 bits. + */ + do { + /* snapshot the high 24 bits */ + ss = hi; + + lo = readl_relaxed(tegra->regs + TKETSC0); + hi = readl_relaxed(tegra->regs + TKETSC1); + } while (hi != ss); + + return (u64)hi << 32 | lo; +} + +static int tegra186_timer_tsc_init(struct tegra186_timer *tegra) +{ + tegra->tsc.name = "tsc"; + tegra->tsc.rating = 300; + tegra->tsc.read = tegra186_timer_tsc_read; + tegra->tsc.mask = CLOCKSOURCE_MASK(56); + tegra->tsc.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->tsc, 31250000); +} + +static u64 tegra186_timer_osc_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer, + osc); + + return readl_relaxed(tegra->regs + TKEOSC); +} + +static int tegra186_timer_osc_init(struct tegra186_timer *tegra) +{ + tegra->osc.name = "osc"; + tegra->osc.rating = 300; + tegra->osc.read = tegra186_timer_osc_read; + tegra->osc.mask = CLOCKSOURCE_MASK(32); + tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->osc, 38400000); +} + +static u64 tegra186_timer_usec_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra = container_of(cs, struct tegra186_timer, + usec); + + return readl_relaxed(tegra->regs + TKEUSEC); +} + +static int tegra186_timer_usec_init(struct tegra186_timer *tegra) +{ + tegra->usec.name = "usec"; + tegra->usec.rating = 300; + tegra->usec.read = tegra186_timer_usec_read; + tegra->usec.mask = CLOCKSOURCE_MASK(32); + tegra->usec.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); +} + +static irqreturn_t tegra186_timer_irq(int irq, void *data) +{ + struct tegra186_timer *tegra = data; + + if (watchdog_active(&tegra->wdt->base)) { + tegra186_wdt_disable(tegra->wdt); + tegra186_wdt_enable(tegra->wdt); + } + + return IRQ_HANDLED; +} + +static int tegra186_timer_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tegra186_timer *tegra; + unsigned int irq; + int err; + + tegra = devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); + if (!tegra) + return -ENOMEM; + + tegra->soc = of_device_get_match_data(dev); + dev_set_drvdata(dev, tegra); + tegra->dev = dev; + + tegra->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tegra->regs)) + return PTR_ERR(tegra->regs); + + err = platform_get_irq(pdev, 0); + if (err < 0) + return err; + + irq = err; + + /* create a watchdog using a preconfigured timer */ + tegra->wdt = tegra186_wdt_create(tegra, 0); + if (IS_ERR(tegra->wdt)) { + err = PTR_ERR(tegra->wdt); + dev_err(dev, "failed to create WDT: %d\n", err); + return err; + } + + err = tegra186_timer_tsc_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register TSC counter: %d\n", err); + return err; + } + + err = tegra186_timer_osc_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register OSC counter: %d\n", err); + goto unregister_tsc; + } + + err = tegra186_timer_usec_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register USEC counter: %d\n", err); + goto unregister_osc; + } + + err = devm_request_irq(dev, irq, tegra186_timer_irq, 0, + "tegra186-timer", tegra); + if (err < 0) { + dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); + goto unregister_usec; + } + + return 0; + +unregister_usec: + clocksource_unregister(&tegra->usec); +unregister_osc: + clocksource_unregister(&tegra->osc); +unregister_tsc: + clocksource_unregister(&tegra->tsc); + return err; +} + +static int tegra186_timer_remove(struct platform_device *pdev) +{ + struct tegra186_timer *tegra = platform_get_drvdata(pdev); + + clocksource_unregister(&tegra->usec); + clocksource_unregister(&tegra->osc); + clocksource_unregister(&tegra->tsc); + + return 0; +} + +static int __maybe_unused tegra186_timer_suspend(struct device *dev) +{ + struct tegra186_timer *tegra = dev_get_drvdata(dev); + + if (watchdog_active(&tegra->wdt->base)) + tegra186_wdt_disable(tegra->wdt); + + return 0; +} + +static int __maybe_unused tegra186_timer_resume(struct device *dev) +{ + struct tegra186_timer *tegra = dev_get_drvdata(dev); + + if (watchdog_active(&tegra->wdt->base)) + tegra186_wdt_enable(tegra->wdt); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra186_timer_pm_ops, tegra186_timer_suspend, + tegra186_timer_resume); + +static const struct tegra186_timer_soc tegra186_timer = { + .num_timers = 10, + .num_wdts = 3, +}; + +static const struct of_device_id tegra186_timer_of_match[] = { + { .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra186_timer_of_match); + +static struct platform_driver tegra186_wdt_driver = { + .driver = { + .name = "tegra186-timer", + .pm = &tegra186_timer_pm_ops, + .of_match_table = tegra186_timer_of_match, + }, + .probe = tegra186_timer_probe, + .remove = tegra186_timer_remove, +}; +module_platform_driver(tegra186_wdt_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra186 timers driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Apr 3 20:22:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266215 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.28.220]) by smtp.gmail.com with ESMTPSA id h132sm13714318wmf.18.2020.04.03.13.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:20 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/7] arm64: tegra: Order nodes by unit-address on Tegra194 Date: Fri, 3 Apr 2020 22:22:05 +0200 Message-Id: <20200403202209.299823-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The pin controller device tree node was accidentally added in the wrong place. Move it to the correct location to keep nodes ordered by unit- address. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 64 ++++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f4ede86e32b4..019f66f03a97 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -45,6 +45,38 @@ gpio: gpio@2200000 { gpio-controller; }; + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x2430000 0x17000 + 0xc300000 0x4000>; + + status = "okay"; + + pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + + clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { + clkreq { + nvidia,pins = "pex_l5_clkreq_n_pgg0"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; + ethernet@2490000 { compatible = "nvidia,tegra194-eqos", "nvidia,tegra186-eqos", @@ -139,38 +171,6 @@ agic: interrupt-controller@2a40000 { }; }; - pinmux: pinmux@2430000 { - compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000 - 0xc300000 0x4000>; - - status = "okay"; - - pex_rst_c5_out_state: pex_rst_c5_out { - pex_rst { - nvidia,pins = "pex_l5_rst_n_pgg1"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-high-voltage = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { - clkreq { - nvidia,pins = "pex_l5_clkreq_n_pgg0"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-high-voltage = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - }; - mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; reg = <0x02c00000 0x100000>, From patchwork Fri Apr 3 20:22:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VhMUnKIW; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBF05cgwz9sSj for ; Sat, 4 Apr 2020 07:22:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728415AbgDCUW1 (ORCPT ); Fri, 3 Apr 2020 16:22:27 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35616 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728147AbgDCUW0 (ORCPT ); Fri, 3 Apr 2020 16:22:26 -0400 Received: by mail-wr1-f68.google.com with SMTP id g3so7724640wrx.2; Fri, 03 Apr 2020 13:22:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UNPe3Sj9nisgX8TMQG4uvyThsRCvZnaiE/iNxuk8GJ8=; b=VhMUnKIWuGyXO9Wk/YcdTBcgSMYnN4H26x6y7/9SgmCzWy4Vf6g8fQ6XchCp0Kko61 x59FMlJkWblglZmlr9PibNCvCdg+/cbB2bzk/c7tV3wMMYpkGD+wOE3ZS2f/u+3pefKS V9aNke9IErE3yghtXR012FEnNkXmnyVSjgswey95eT1GBwLyxhOouZvW4LhflDdNdHhL bOMct7S3a5fnTeAhYYcUJBHE8H7Q3/K1OhvaEl6o30MORyFRYmfjowZ3+mQMilawVZdR xx3vkYhI3qMQNRmwtvfHJSVV21lwWy6Of/BrM97wDImyirH+nuaa+W0cDpGNMj7340Xn OmCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UNPe3Sj9nisgX8TMQG4uvyThsRCvZnaiE/iNxuk8GJ8=; b=MusC5UO9GmCuR8Dwy59rTrCOL3D2ankYho3vonag5LxoBAL5czzpB+3eR4wRLwQQcY PSa3R0J/LfNeEZ6Hqo9tw+kfFlQ6GWivxlAesBAIj9oHFbRfGHvs5kMQqZlSdUJF+005 hDQ1hgB7RV7iR04tMCyQGXv5nEqvdOxT42Y0fjdy5z7c5tXzdLEy9UUf/w2v7GlGDAWk bFCZaauMVZ8DrAcUC30Q4R+26XAcUa/rDtqnuXoZDoEOUmJYD269gmj94Nr83dS/h7HK 9w7q+9wJL11NVPXuCMSF5PrKJjhMhwMgJaewLv7jgkpOdKHEUJMdku/mbZRAzhUYO/jg hOxQ== X-Gm-Message-State: AGi0PuaLxMD5dpCtXDepEG2daVqLQaouOFp8FQBIRU2R12OBtYnHwtfZ OiTjVlXf9byaIvVvw7qhd+E= X-Google-Smtp-Source: APiQypLT9r357ptijr1DMYEYfVwzqiVe4R9FAoRQ/z4pi7HhWS8SjPiZBFyKIpQ4+XmTShtzshM9+w== X-Received: by 2002:a5d:6605:: with SMTP id n5mr10565784wru.303.1585945344205; Fri, 03 Apr 2020 13:22:24 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id d13sm13804946wrq.11.2020.04.03.13.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:23 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/7] arm64: tegra: Add native timer support on Tegra186 Date: Fri, 3 Apr 2020 22:22:06 +0200 Message-Id: <20200403202209.299823-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb9cd8b..4dfa70e93693 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -167,6 +167,22 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From patchwork Fri Apr 3 20:22:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=E9pFk0M6; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBFG4xQ3z9sPF for ; Sat, 4 Apr 2020 07:22:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728664AbgDCUWh (ORCPT ); Fri, 3 Apr 2020 16:22:37 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:35178 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728416AbgDCUW3 (ORCPT ); Fri, 3 Apr 2020 16:22:29 -0400 Received: by mail-wm1-f65.google.com with SMTP id i19so9133741wmb.0; Fri, 03 Apr 2020 13:22:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ie6jFqOSrTu+xf/V4MNbj7GzVLme0az5kv4/5mQNB0k=; b=E9pFk0M60FMxmXq0jC2JbvyM3NnJkoT4O/tYp8hJMLeeVtcX9ZZ+URGVGxtv93oZjs CQUBPv40PISGgkI7Jz7m3Wg3kbpVoTJxz0ZQ0FOF2EGx9oHhtSysK2zjSbkrt7ICXxUf z9TmIjkXgk/y3zBddDyydf03QLfoP6opcxl0wuiG9PD71h0uMDK40t32nwvHsAeKZtwQ 940eefC9IocgZwAp1Hge6bSpWY/K8xcFszS4mTZuSqcZr0sz7bwQzpBvCeKGqWHbkXcI P5ryXtYcJPJBFLDCMu4my9NXikOfCLWj6dSn/kLF/cwnZQQET6lzxPgFwDYovK8pkUzi ZMVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ie6jFqOSrTu+xf/V4MNbj7GzVLme0az5kv4/5mQNB0k=; b=YwkayA8cYhQaPYKm14f/NW281rSOvDSzARTWakDluAk0qAXMLvC1xj0d91FZGoNlIh hkFzelFHrUdn7IUhD0Yf7nUthb78VmBdbC7m2nlU7LBrb0m6cH4GpijHHf5MxRzLOWn/ 8pZZHnPODyhEvCUYjcSVTny5rRmpOFKRP0ICuhX3c9Teg63arj+BEFRmdQt/sC3dc3wT /zVJBG1uijDYfrX2W1TZfR43Yo7/pa/Pp+f/xjD4O7oUqlCR+uoa5HuOnniDy+3nUmEz NzMWbpEnYWG8PotCIgfycN1+VloK0NVoSkcOO8g81sjfvX6PkN5pE9wcplgg4Iu1ldCl tBmw== X-Gm-Message-State: AGi0PuZ40MGmLcLDIKSMJDm3pTru6URsHn0LLV9RmepqNpsO72jX5/Le VWyD8Y3da8bwk8nlfomsR34= X-Google-Smtp-Source: APiQypJK3zLGT47/3do2eHeIDloqjzmPGIsDYIKPT4ovLYkP7JxPwlI/CajThmFE5FBlH4geNSo3UQ== X-Received: by 2002:a05:600c:2297:: with SMTP id 23mr9796857wmf.166.1585945345935; Fri, 03 Apr 2020 13:22:25 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id j11sm12724139wmi.33.2020.04.03.13.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:25 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/7] arm64: tegra: Enable native timers on Jetson TX2 Date: Fri, 3 Apr 2020 22:22:07 +0200 Message-Id: <20200403202209.299823-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Enable the native timers on Jetson TX2 to allow using the watchdog functionality to recover from system hangs, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index da96de04d003..9aa17744c4a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -58,6 +58,10 @@ memory-controller@2c00000 { status = "okay"; }; + timer@3010000 { + status = "okay"; + }; + serial@3100000 { status = "okay"; }; From patchwork Fri Apr 3 20:22:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=APq8zqvn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBFN0yc4z9sSM for ; Sat, 4 Apr 2020 07:22:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728264AbgDCUWn (ORCPT ); Fri, 3 Apr 2020 16:22:43 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:51072 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728417AbgDCUW3 (ORCPT ); Fri, 3 Apr 2020 16:22:29 -0400 Received: by mail-wm1-f68.google.com with SMTP id t128so8471547wma.0; Fri, 03 Apr 2020 13:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WS2drkVzUywPkUAraDwxibChKAzL4Ioj5dgxbparViM=; b=APq8zqvnzru0QNSUVmz1Bamnt9WwBG0Ba+0o9zlwP5hmr9KKGSVgL1qxQwwWq+YrqV JxrqA4jdfSxyIygLsRySycAtz3JbJk1RM76CM7zDmzYh4vHK9Y1FYY9M5JP+8o+9sEHQ puINkczY1Sp5tXnYikpww0JpzJOOK9/MG1n3papRoGb83am1XzDV1N+u5VC8ChZYQfhO Mdy0V15OW14tmkNe7LY7XnpuqRRlhPshIWzkWRm0C28JyNuSmovLDzkuQgESWJcCkciE z1XSEpha/t2YzEhZW52xQc7G+if7YZOUbyJR/SPriub5kHQIuJC7JtdU1vBHxeGGJoH2 7msQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WS2drkVzUywPkUAraDwxibChKAzL4Ioj5dgxbparViM=; b=F6hpXLbDLQfpadaEFLnyavFPXSNy/4qU+XMgN3gMwBpfvrtayWsADYzXRyxxvoG8c2 BuhuAtFk4z0U/59ilyejcBDv9HCPmYca91+rHZzRwTO/y7XxwpIyPB0wEA0i4wSxIJF6 zZLz2y6EFt7sL+VWOT7GlqF4VbjBXWWqtGr4/uqm/RRKWHtCboUUX/bRtKXcOeuQdA+B mQNc7FFLilW51zQks67+3/X9PArvqhavcL4XMtM7TkFkzN8680SdlpZRPYtTVNpbm9DT fg0XjokZSbPEXObEcrL+ftJiUrRk9trHQsrKW2bPWU0eSCUwY/TN7+KDLTUQgUMWZDLW 4waw== X-Gm-Message-State: AGi0PuYhC9ypq1A06iaqxrihDOP7Jdsk/taraDEsLZLokPZoZEoYA+L8 2HftOF2BCU9urVULbwbueeY9gCu+ X-Google-Smtp-Source: APiQypK7NTafTkpGY2knIzDtkbi/m/65q+yopgUPWyBDnGa4LDCAPZpjpPNjHOgsFE+8seD7lY5AhQ== X-Received: by 2002:a1c:3281:: with SMTP id y123mr10095222wmy.140.1585945347470; Fri, 03 Apr 2020 13:22:27 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id v186sm12715529wme.24.2020.04.03.13.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:26 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/7] arm64: tegra: Add native timer support on Tegra194 Date: Fri, 3 Apr 2020 22:22:08 +0200 Message-Id: <20200403202209.299823-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra194. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 019f66f03a97..a0a5b44ff9bb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -213,6 +213,23 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra194-timer", + "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; From patchwork Fri Apr 3 20:22:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1266211 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=HUU2B0i/; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48vBFB1bpBz9sPF for ; Sat, 4 Apr 2020 07:22:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728147AbgDCUWd (ORCPT ); Fri, 3 Apr 2020 16:22:33 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:33388 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728589AbgDCUWb (ORCPT ); Fri, 3 Apr 2020 16:22:31 -0400 Received: by mail-wr1-f66.google.com with SMTP id a25so10080866wrd.0; Fri, 03 Apr 2020 13:22:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fhOtbK0ZVL1ABebYKJYf0UxxzluO0JY5MJfCTLBiR34=; b=HUU2B0i/AmHt/U6+7pI3Nauxs8P31FCocmOO2SiELa6ftuHKRB5A/klDwvPpBAd+Ft dZCIqTaqcZnPCMujHH6Pwp4gyP0HayYsOuCtQ42+7r09dezJ3DHyKjohpu/k+vbRHYIc LS5/aP50jeO18Fwhia9Xyea/+z4kaIE1fBubPoh3Yk0eM2D0BpL8N5xznFVgl/HG+ktr /V9VsrNDeVgw/+AF/57iazt4FWaIDFrBlFU2rWXvZb9qwdKU5LyBFbS8byg9ep3gaZSj d3X/DY+5vlyqezN/Z21RV1OH7KEk6iOoykOKxGbgxlyyNFkgsCzVl0lIX4iMlQnMopz7 hokA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fhOtbK0ZVL1ABebYKJYf0UxxzluO0JY5MJfCTLBiR34=; b=FZTakWi7o3BUjUbEMVq6Nukn+2G4y2Td3B7Z0K9JvUiD/LHr2945kOXFy/lx00bkPV z/Kn+2kJ9dFyEtEDmCIimW79i1wPXTrOfUDXR18IcelKkUjGZSI7vGdtTFcdwCl5uHaW fVNf+CFQHUW7FkAsof9vsTxzKBztBRnnsuoG6/XzEKDd2qi2z1HVz+JY1AC4t/sisJn4 h1d2vtY9F/odLf6ZtYDcncC9xZtDGGtUYO9+c4LMK1UmGcZrvuSgA8/Ibk044SS7Q5b1 nmpmEnIq/eCwUtq51kvnceVSBFa/fLEfSEBoko6QBCKHC7RyTLOwBRF7mIRvrsTEVLvy Tl6w== X-Gm-Message-State: AGi0PuaxeKauYtaZspgiixoO6KDbYIJyzRsIyTKwLfIqTUErWdqjvH4P GFzGiX27/3lGLAt6QLnVxMw= X-Google-Smtp-Source: APiQypJwyjlC81w8tMkFTyU/xyPrx4riYwln0dT/JL05SWu258U0MNk5jFQCBvuNXkA7PF2MiX9s9A== X-Received: by 2002:a5d:4602:: with SMTP id t2mr11734250wrq.347.1585945349386; Fri, 03 Apr 2020 13:22:29 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id y189sm13005619wmb.26.2020.04.03.13.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 13:22:28 -0700 (PDT) From: Thierry Reding To: Daniel Lezcano , Thomas Gleixner , Thierry Reding Cc: Rob Herring , Dmitry Osipenko , Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/7] arm64: tegra: Enable native timers on Jetson AGX Xavier Date: Fri, 3 Apr 2020 22:22:09 +0200 Message-Id: <20200403202209.299823-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200403202209.299823-1-thierry.reding@gmail.com> References: <20200403202209.299823-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Enable the native timers on Jetson AGX Xavier to allow using the watchdog functionality to recover from system hangs, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 623f7d7d216b..d68588f2709e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -52,6 +52,10 @@ memory-controller@2c00000 { status = "okay"; }; + timer@3010000 { + status = "okay"; + }; + serial@3110000 { status = "okay"; };