From patchwork Thu Apr 2 10:38:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rayagonda Kokatanur X-Patchwork-Id: 1265517 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=aHDC7uWg; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48tKKv2SQXz9sSJ for ; Thu, 2 Apr 2020 21:38:43 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C78B480363; Thu, 2 Apr 2020 12:38:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.b="aHDC7uWg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 71511800A9; Thu, 2 Apr 2020 12:38:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E2FA5800A9 for ; Thu, 2 Apr 2020 12:38:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rayagonda.kokatanur@broadcom.com Received: by mail-wm1-x343.google.com with SMTP id f6so3067572wmj.3 for ; Thu, 02 Apr 2020 03:38:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id; bh=7mr9j4tdxtzRsl6UkP5OdfqUyCmPS2yfHII6rNgNRaU=; b=aHDC7uWgEvlq0tFM3w+ia3gbktvPgZFsuiLsnfGsmETWWEFe+tsBRdcO2P7gFCChas ZpTqoOhMciTxlU91CX+kC207caZEHovClPhKUvkOjKFAGOlFW60QSGqEZbchXdIDxUBa fQU9FCgkXfp1E9PBLzQbHOcZM2GXGIUDx2//g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7mr9j4tdxtzRsl6UkP5OdfqUyCmPS2yfHII6rNgNRaU=; b=rq5Uf7g3tMXtVWA0xl1SOU6zpV3HpMscsOaB4DMxRaOT8IBF/E5M1D3uNak2hqSZmj oVIf++U2+ZkS+pdbCwPGf/96ediTRbK77mINrgzaReukMjvesejnQQwnuiEmvWQkOm7G MqR0derY/92TBOWe956cqV+B0d98RU0sjaGur0uwrUaLWyTZExYLhPjhoI/OwhIMTDXL 6F7wfOXZE8GDMvl4Z5uqpiYxCOlVkPmP8qnABVkCPllCz2zVEF3RsoW1pgB2RLjvWTD8 OsGAjlwPihjpNoym4ghgLB/S4J2OvBBnMgNaCFpVypCrX9huXVcKfouydLL2kZLuwThH XUBA== X-Gm-Message-State: AGi0PubpRZkNWOAs6l9NS41N04iqwC5MjwGNz5W01msRw+vJmKqN4PPi /uhR5XPyzWCfvdYAb/7xeaDVyZ8XoKSBs5mHabO2+dRMPz+JcSzIA2VPZJ7GGb2vDaOKZPy9mN6 HhRfxCn4A9vYlpOQWDV6DwQkS6QP9mW7bWbls3kIOIE4POPh5pmDLHzeBQlkFe9mkSpXoiNlHCX FMUIkNkw== X-Google-Smtp-Source: APiQypKhWi1Y+KGZnY5Kq+EvdmcKd6DvW1NvVN3NZTmYFyTcpsDghtNDskY2GkDKXIEq3UXot5ItRA== X-Received: by 2002:a1c:bb89:: with SMTP id l131mr2746336wmf.37.1585823906690; Thu, 02 Apr 2020 03:38:26 -0700 (PDT) Received: from rayagonda.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id 138sm6665287wmb.21.2020.04.02.03.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 03:38:25 -0700 (PDT) From: Rayagonda Kokatanur To: u-boot@lists.denx.de, Neil Armstrong , Adam Ford , Srinath Mannam , Stefan Roese , Weijie Gao , Sekhar Nori , Ryder Lee , Daniel Schwierzeck , Frank Wunderlich Cc: bharat.gooty@broadcom.com, vladimir.olovyannikov@broadcom.com, Rayagonda Kokatanur Subject: [PATCH v3 1/1] phy: add support for stingray PAXB PHY controller Date: Thu, 2 Apr 2020 16:08:12 +0530 Message-Id: <20200402103812.7775-1-rayagonda.kokatanur@broadcom.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Srinath Mannam Add support for stingray PAXB PHY controller driver. This driver supports maximum 8 PAXB phys using pipemux data. Signed-off-by: Srinath Mannam Signed-off-by: Rayagonda Kokatanur Reviewed-by: Stefan Roese --- Changes from v2: -Address review comments from Stefan Roese, Rearrange the include files. Remove dm/device.h as its included part of dm.h. Changes from v1: -Address review comments from Stefan Roese, Use GENMASK() instead of hard code value. Remove unwanted struct declaration. Get pr_err() into single line. drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-bcm-sr-pcie.c | 177 ++++++++++++++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/phy/phy-bcm-sr-pcie.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a72f34f0d4..f7003807fc 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -84,6 +84,13 @@ config BCM6368_USBH_PHY help Support for the Broadcom MIPS BCM6368 USBH PHY. +config BCM_SR_PCIE_PHY + bool "Broadcom Stingray PCIe PHY driver" + depends on PHY + help + Enable this to support the Broadcom Stingray PCIe PHY + If unsure, say N. + config PHY_DA8XX_USB tristate "TI DA8xx USB PHY Driver" depends on PHY && ARCH_DAVINCI diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 43ce62e08c..3958f7899c 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o +obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c new file mode 100644 index 0000000000..36c77c4b63 --- /dev/null +++ b/drivers/phy/phy-bcm-sr-pcie.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Broadcom + */ + +#include +#include +#include +#include +#include + +/* we have up to 8 PAXB based RC. The 9th one is always PAXC */ +#define SR_NR_PCIE_PHYS 8 + +#define PCIE_PIPEMUX_CFG_OFFSET 0x10c +#define PCIE_PIPEMUX_SELECT_STRAP GENMASK(3, 0) + +#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c +#define PCIE_PIPEMUX_SHIFT 19 +#define PCIE_PIPEMUX_MASK GENMASK(3, 0) + +/** + * struct sr_pcie_phy_core - Stingray PCIe PHY core control + * + * @dev: pointer to device + * @base: base register of PCIe SS + * @cdru: CDRU base address + * @pipemux: pipemuex strap + */ +struct sr_pcie_phy_core { + struct udevice *dev; + void __iomem *base; + void __iomem *cdru; + u32 pipemux; +}; + +/* + * PCIe PIPEMUX lookup table + * + * Each array index represents a PIPEMUX strap setting + * The array element represents a bitmap where a set bit means the PCIe + * core and associated serdes has been enabled as RC and is available for use + */ +static const u8 pipemux_table[] = { + /* PIPEMUX = 0, EP 1x16 */ + 0x00, + /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */ + 0x80, + /* PIPEMUX = 2, EP 4x4 */ + 0x00, + /* PIPEMUX = 3, RC 2x8, cores 0, 7 */ + 0x81, + /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */ + 0xc3, + /* PIPEMUX = 5, RC 8x2, all 8 cores */ + 0xff, + /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */ + 0xcd, + /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */ + 0xfd, + /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */ + 0xf0, + /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */ + 0xc0, + /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */ + 0x42, + /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */ + 0x3c, + /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */ + 0xfc, + /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */ + 0x4c, +}; + +/* + * Return true if the strap setting is valid + */ +static bool pipemux_strap_is_valid(u32 pipemux) +{ + return !!(pipemux < ARRAY_SIZE(pipemux_table)); +} + +/* + * Read the PCIe PIPEMUX from strap + */ +static u32 pipemux_strap_read(struct sr_pcie_phy_core *core) +{ + u32 pipemux; + + /* + * Read PIPEMUX configuration register to determine the pipemux setting + * + * In the case when the value indicates using HW strap, fall back to + * use HW strap + */ + pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET); + pipemux &= PCIE_PIPEMUX_MASK; + if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) { + pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET); + pipemux >>= PCIE_PIPEMUX_SHIFT; + pipemux &= PCIE_PIPEMUX_MASK; + } + + return pipemux; +} + +static int sr_pcie_phy_init(struct phy *phy) +{ + struct sr_pcie_phy_core *core = dev_get_priv(phy->dev); + unsigned int core_idx = phy->id; + + debug("%s %lx\n", __func__, phy->id); + /* + * Check whether this PHY is for root complex or not. If yes, return + * zero so the host driver can proceed to enumeration. If not, return + * an error and that will force the host driver to bail out + */ + if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1)) + return 0; + + return -ENODEV; +} + +static int sr_pcie_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +{ + debug("%s %d\n", __func__, args->args[0]); + if (args->args_count && args->args[0] < SR_NR_PCIE_PHYS) + phy->id = args->args[0]; + else + return -ENODEV; + + return 0; +} + +static const struct phy_ops sr_pcie_phy_ops = { + .of_xlate = sr_pcie_phy_xlate, + .init = sr_pcie_phy_init, +}; + +static int sr_pcie_phy_probe(struct udevice *dev) +{ + struct sr_pcie_phy_core *core = dev_get_priv(dev); + + core->dev = dev; + + core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base"); + core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base"); + debug("ip base %p\n", core->base); + debug("cdru base %p\n", core->cdru); + + /* read the PCIe PIPEMUX strap setting */ + core->pipemux = pipemux_strap_read(core); + if (!pipemux_strap_is_valid(core->pipemux)) { + pr_err("invalid PCIe PIPEMUX strap %u\n", core->pipemux); + return -EIO; + } + debug("%s %#x\n", __func__, core->pipemux); + + pr_info("Stingray PCIe PHY driver initialized\n"); + + return 0; +} + +static const struct udevice_id sr_pcie_phy_match_table[] = { + { .compatible = "brcm,sr-pcie-phy" }, + { } +}; + +U_BOOT_DRIVER(sr_pcie_phy) = { + .name = "sr-pcie-phy", + .id = UCLASS_PHY, + .probe = sr_pcie_phy_probe, + .of_match = sr_pcie_phy_match_table, + .ops = &sr_pcie_phy_ops, + .platdata_auto_alloc_size = sizeof(struct sr_pcie_phy_core), + .priv_auto_alloc_size = sizeof(struct sr_pcie_phy_core), +};