From patchwork Mon Mar 30 01:08:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KP9TxrfH; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDtS419fz9sSK for ; Mon, 30 Mar 2020 12:11:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728114AbgC3BJi (ORCPT ); Sun, 29 Mar 2020 21:09:38 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:44882 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbgC3BJi (ORCPT ); Sun, 29 Mar 2020 21:09:38 -0400 Received: by mail-lj1-f196.google.com with SMTP id p14so16282742lji.11; Sun, 29 Mar 2020 18:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SyPm2KUzhH4yj1dDse11pz3n8NBqlBEAYiobqyRVKu0=; b=KP9TxrfH1Yf2u0M+Qtac+pS0JF1w7wo582/b4iHBGbtBNizsLtp/XIKOhtjx1hlfvL R6t/LkbP+19Yq1EXACCNsU+pkMNzVT4AiHeHn/0lr4pEKcJuPzvoFZ/wxAPjKYR757Ho a5PvbKFSiO3kOk24Yvx2hSWeACsEowJuj/Ub6d7ov70sS9Xbv9XPLdDICyRYEbiAUBj6 S4NuHgx2bM/09Q8WZ8qLgPNP0j9TzqOJajKK7y0Gm0gcGh4ZHlNMhv7R4N872aiyRql6 k5NMBWn9V+dwJ5HXs/lF6jcJ7NZaXjejWFecR//GK+8G8bhe2w94UnhZdEuzhkiLYSCx P4LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SyPm2KUzhH4yj1dDse11pz3n8NBqlBEAYiobqyRVKu0=; b=DXGYEOOeLGdyw2vJ43owk79mJ5pwzlsfJhHie/45RCYRNYNG0Snuvuu/fpAWTqyItu 6Z3EL6uTkpfrM+cGYZCGvb5vgRBgaPEo/sMd8p+qNZvDBQny88mWmdhu9FUc4I+BKWlo q5pj7jHpY6Njmst++PnEBtieqSz6ljYrKGUQMlT9BiecA+zKs9k2Ig7dRWKD0mpbvARz /T3meIDsipDfC4qQnEzPxw4/MFbfx/pM2UZFzqS6G4qu0Ls25YfD6x+wpLdOgkjziLke cHN2w+e4F+NIegqx1gkZcRMigiq9UBKw+JaANVNyk8Zo3CicNsyuKYvo5UiAzz8V7ngp NpVQ== X-Gm-Message-State: AGi0Pub6TotPWsZaT+CN+Ran+pGkO6s1JFM9WMhAnPXyXXDOR7quyot/ cJjT23/eNPxgQGejn7z/Dew= X-Google-Smtp-Source: APiQypLbylsFxaY2bHTyqNbB0g8en9J+rivsuZCDeT0HmvlMHYmh+tF0t5nYIOiPUvnJQ/+pK6AF9A== X-Received: by 2002:a05:651c:310:: with SMTP id a16mr5341055ljp.275.1585530575210; Sun, 29 Mar 2020 18:09:35 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:34 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:43 +0300 Message-Id: <20200330010904.27643-2-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Memory controller is interconnected with memory clients and with the external memory controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file . Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 { From patchwork Mon Mar 30 01:08:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Pg3NEZBI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDtN5Nngz9sSb for ; Mon, 30 Mar 2020 12:11:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728189AbgC3BJm (ORCPT ); Sun, 29 Mar 2020 21:09:42 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44882 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727941AbgC3BJj (ORCPT ); Sun, 29 Mar 2020 21:09:39 -0400 Received: by mail-lj1-f193.google.com with SMTP id p14so16282792lji.11; Sun, 29 Mar 2020 18:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=THnwhwTdTmg4c86hFlh2qknbtHQvbfTX5IFqa2InF7g=; b=Pg3NEZBItMfCSgDZPKnxTIcXNI+xr/d79Of+mkt+dYMW5wLwo4Ok4roS8EnABFr8to xwy1Sr5/1/6SLKsSJM0j0LjHENfTxhyPHZyEORqb2qJlsTpnub+E1FEtrgj1IRH81M6t dNlP8O6iO/HB5amOL4OsRy3/ZOzQ7DIz7nIygl7Mi5CFGOFhObTMot7NqF94YE0HnILN 6u3UmhkiAOd9W++3BaZ6hFxXzZtoKFDtBLhW0Iw1k/suQz/MPpg7FJucm/Sl5yiKtdWS soby3PljbjCvP0aiph0jIIhGe13/Y2UxSrt1aRvhemGgtUV3to0eaAg5RFUHE6fBl9A2 i9Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=THnwhwTdTmg4c86hFlh2qknbtHQvbfTX5IFqa2InF7g=; b=n1UPFzo9HMSHUCyNNzRMPTy6KtT1oGYci9+6UlgdEdtp5UonSbawd5/ZiedeT5ejdB mMcRR2UGJljjKDWXwLcqQrolkI0IN+ZsqTJIyce7DPOUVHUQ4fPs8zyu3W1o3uJwPaSK UULNabYHpp/+yI0t0qbotZHVH8wvs07a6aDw8dZpvNlPUggDZdkl1dqNcXUTznoxoA8V adiXPq268yjlnUOGJgTb3sUxEQbl+CreR1OfjIy1bJC4juFsp8iOFAxTK9yq7NyiUNHN Zca+OqH0L4Ea8gL5o+ArKlMp6of9uNi3r/aTG9pSUT068nASkUs3r+vq/McxXkXrzhQv Cigw== X-Gm-Message-State: AGi0PuZYdGWHIYNkX1BXGktdANjjHUzATtfx6pSSQEYWMbN+DDJsfSpc MulMBvonJNWdQlvgd3CGOnE= X-Google-Smtp-Source: APiQypKDy2Ro7EQKBqSUe7PyjSLNAnaV0wdFF27xRufe2z5meT1FtGCGpLLX8lEkaMU6PMzGngPfnA== X-Received: by 2002:a05:651c:552:: with SMTP id q18mr5910854ljp.1.1585530576340; Sun, 29 Mar 2020 18:09:36 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:35 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 02/22] dt-bindings: memory: tegra20: emc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:44 +0300 Message-Id: <20200330010904.27643-3-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns external memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..f51da7662de4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. +- #interconnect-cells : Should be 0. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; + #interconnect-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; From patchwork Mon Mar 30 01:08:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=XxBzBB8C; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDtR0xQmz9sSK for ; Mon, 30 Mar 2020 12:11:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728177AbgC3BJl (ORCPT ); Sun, 29 Mar 2020 21:09:41 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:33675 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728096AbgC3BJk (ORCPT ); Sun, 29 Mar 2020 21:09:40 -0400 Received: by mail-lf1-f66.google.com with SMTP id x200so5558818lff.0; Sun, 29 Mar 2020 18:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pGhshIQ08W/fF40FAntS+cxcTBW0fRcj4eZ28EWAmTE=; b=XxBzBB8C/ouLvpvhWv1tCGRnvopFMnR02tvWDdHXE34VMJoFRNre/opbCtXicTKrzV qZyMxdHtx9nh3QfyBBDUF5WO0UAdCOtboU2OXh8FvVLeOHYffG/yVfjb33pkfyFATTP2 GScNvvzwf9E9GE8Mw5OT7LAkm/VwTyoLDmyKs3QR0jsH4X6PbVSK0cEP60Lzy3HC/ADd 948zayzTPaM/FaB4TU8EkObczi75mj8ZAMirY/qlyv5PwPXL3w0JVCf0Zqqb7IF8tcxz zixt0HJclbyM7lNFFQx3qn8AsoyuOE5n3mg8k1IeFQCBuMZ6AlihowbLymymM5a4YsGt kUWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pGhshIQ08W/fF40FAntS+cxcTBW0fRcj4eZ28EWAmTE=; b=cloU/Nzc4nXGMZr+2LVPRNEnIrUSCt1ccrsZ2zHMEC/nq3WnfDk1sjiw8lKiOF6mIE XE+b+sI3lovSZwN1k0J/3eq33pKfV2j6RsdD3sLjjG0cJ3RRM9qjHe0pMuOa0GNpCyBg r7+OoXw8hBuSn4TJu/U8OOqrjJ0YCUF3jK1hQFEXkJtnjm1eE0OSqTJ7wocoovuPQJ5m uPzQt5PPXkl8QA5WXjK3trEogtdJ1uShfrqTxAW9c4fU7LysdZ1JVT1/e6ednFOzC6Lm CEsSrp9j3buH+lJGWWanJyxhSltqyHhuatrd7voJHUxIAnnEkc20RNy2WqrJawReqHsr YeNA== X-Gm-Message-State: AGi0PuZXwdSt5pPmDhBTUw+HxFzurmh603KLyi9ltBbdZVKAotSl9/4w v8KO8cKOZCEn5ad1jcHgaZ4= X-Google-Smtp-Source: APiQypLyzsbk89h1xbagVghUO7mdmiHIeONm1fV88bNjfaxU8lIGGhlh4l/LkO7c6iKxzJDhMtB4yA== X-Received: by 2002:a19:4a50:: with SMTP id x77mr6474950lfa.159.1585530577323; Sun, 29 Mar 2020 18:09:37 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:36 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 03/22] dt-bindings: memory: tegra30: mc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:45 +0300 Message-Id: <20200330010904.27643-4-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Memory controller is interconnected with memory clients and with the external memory controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 4b9196c83291..083676676d0d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -121,6 +124,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -136,6 +140,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; From patchwork Mon Mar 30 01:08:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=aAfRh2hP; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDtS0klcz9sQt for ; Mon, 30 Mar 2020 12:11:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728256AbgC3BLG (ORCPT ); Sun, 29 Mar 2020 21:11:06 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:38702 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728129AbgC3BJk (ORCPT ); Sun, 29 Mar 2020 21:09:40 -0400 Received: by mail-lj1-f193.google.com with SMTP id w1so16277661ljh.5; Sun, 29 Mar 2020 18:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EC82F0fSy3SGAzZ5vo6pkiYKuzU18mbiBELCUdjdApo=; b=aAfRh2hPeJ5U8aqPYvJk9kV4DbkEc3hB2h3TgpqjZNydVjAJl7Tvnh7VWeRlsUZNJi RqmVtFDLMuERdmbPCWaM5BIBv/Lo1hIu6d3UpKM/dWrbvbanJU0WUzwNqOxIldVRGwtV CRCs/cOWwqqxiYHAigdROhOK01KYBKVOLNWyZaMeictkfj3voWItSh6IOAzzZUHZS3y8 cAY04+Pwpn8yyTpXMvNFGSKr9QtWsLszeDFNmvZpqeJiUpXLecaUAzkUx1SpHsVAnNAs 63Q4ugparHN/KsR8ZQ9fAnrDXAWF2TB+YrtREY/PfNXjz/fPCV3ejgYYL2zrXKFTQvdR V3lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EC82F0fSy3SGAzZ5vo6pkiYKuzU18mbiBELCUdjdApo=; b=ekkxO4554kXpnzn5deurLCouLIJXgrLlxWHHlkC3lovEzkQXKuIZrly5d4DQnU0L4u 8nhybfe8tjoYhVfllTfIhhazi4N6Z+aS7lU+0yEnO/y966xaZ0H1GUo5eKxmhVs4kH3r cYfnGcGFACgFxHeOS/gbLGfu73oxEhDr09G2slTX9mTMFPyU/o68kQNEBRlWA6u6ZxrM mw9Knep7QHPldl1AlLACSn8vnRr/ETTMkr7N5v+1boObVwROeL8XituyHzvHctck4oo4 LBnsGh65q45fFPktjV25A3H+chyD08v1HOdg19Zhh9JKMkzVqunR+qNz6fSMCz9aQTC3 lG4w== X-Gm-Message-State: AGi0PuaWGUvi9DH33VxVOaNHagjeCmFFJNHjpWDYIw14RiO85S+q9PpR iQIKe3J0Kwfw752UkJRBb9o= X-Google-Smtp-Source: APiQypK+LJHCIcBln1YFym+wyJQvikaZ6KKCNt2Pt1rTIIshYKQAwMhdCBctd/5zaYU6dVLvDlO7AQ== X-Received: by 2002:a2e:9d83:: with SMTP id c3mr5746993ljj.3.1585530578298; Sun, 29 Mar 2020 18:09:38 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:37 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 04/22] dt-bindings: memory: tegra30: emc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:46 +0300 Message-Id: <20200330010904.27643-5-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns external memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index e4135bac6957..2d7aed245552 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -217,6 +220,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -230,6 +234,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>; From patchwork Mon Mar 30 01:08:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=br2TMenO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDt944WFz9sSZ for ; Mon, 30 Mar 2020 12:10:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728445AbgC3BKz (ORCPT ); Sun, 29 Mar 2020 21:10:55 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33156 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbgC3BJm (ORCPT ); Sun, 29 Mar 2020 21:09:42 -0400 Received: by mail-lj1-f193.google.com with SMTP id f20so16335771ljm.0; Sun, 29 Mar 2020 18:09:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0J6DRAOAyaTpCiYOkunPcKmZ48BaOfYFgW2usyzuKP8=; b=br2TMenOYQKMU0MQqe5hNERWMDXSym6KywsvVY9MbiXbFgwB15/mNeYK9ffd+tuYgX I9cwr0aUwbzVYEVHJUQmRq2gih6WeT7J+zk6ei65m0q80UFYOk9zbygJPZfjcfHinQi3 S5VSjv+rQxVaycNdEOzS7xZy0rNH2hLvwgfesGzqh+tnroOisljSZpIT+XFlLOW0rDoZ KkUjKUTT8cnlJpS+FNjwCS4vAX6SvcPnjMB1ikRwA4nUVr+M2DPPXLqUdYguUihw5GEO RBj1yvBEiG2ozqqPn1wn2OHrBSxfy4Ilq4AAPpxcMWxbRfaSqw90MTm/8a+umdjTEBQ5 lBMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0J6DRAOAyaTpCiYOkunPcKmZ48BaOfYFgW2usyzuKP8=; b=j2t1rQ1ln/b3D9Ql/Q7iEZ3xxsrT3BkuZ3wQ4nekjlS6whmbzyom7vnWn3rFsm7qJD 0xpxL/aoUNNPzJGZa2aeV1ail3P/4sIoAqb25K2wPRKhhzp2mnPiwaNifFIkudtmwIxs wQQOOL3g6My7y0LeHfCsG7l0LpxQ6iJGIs5HroZLJCHAI+ONNt2kOv0u3/vu/ob9DwQU DXRYaRMMG3tn8hj9ZKRnSBsPXJ8j1yk7ug3IsJ0GJXWUD2wJuLq3HJ3SsKY7MMt+yaKP w3WmPzBNdoCb6phrZ7trqRItHbgjzCLPsbwugNbvzD/gPmQW3r3E8NOGFNfIjQz4zWlp 1TjA== X-Gm-Message-State: AGi0PuajbYX58Ej94WTa+7CX1/94d0gD/hZ29v1ITP3or240X7bKSyUp FwtbnGwmxtS9vX4T6Eib5IM= X-Google-Smtp-Source: APiQypJxz4N3lr7iOdRVaNWJ1a7Kt/SBCUYZhP3n8W449ZXJ7fMfJK3kvtdPi2dOpFJR6QpwemcihA== X-Received: by 2002:a2e:904b:: with SMTP id n11mr5525552ljg.171.1585530579284; Sun, 29 Mar 2020 18:09:39 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:38 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/22] dt-bindings: host1x: Document new interconnect properties Date: Mon, 30 Mar 2020 04:08:47 +0300 Message-Id: <20200330010904.27643-6-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Signed-off-by: Dmitry Osipenko --- .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255ac5b6..d92d4e814d77 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,10 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +40,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the MPE memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - vi: video input Required properties: @@ -49,6 +59,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vi + Optional properties: + - interconnects: Must contain entry for the VI memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - epp: encoder pre-processor Required properties: @@ -62,6 +78,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the EPP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - isp: image signal processor Required properties: @@ -75,6 +97,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the ISP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - gr2d: 2D graphics engine Required properties: @@ -88,6 +116,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the GR2D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - gr3d: 3D graphics engine Required properties: @@ -106,6 +140,12 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the GR3D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + - dc: display controller Required properties: @@ -133,6 +173,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the DC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. - hdmi: High Definition Multimedia Interface @@ -281,6 +325,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the VIC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients. + Example: / { @@ -363,6 +413,15 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -378,6 +437,15 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; From patchwork Mon Mar 30 01:08:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=O6r9IkP9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDtJ31nrz9sRf for ; Mon, 30 Mar 2020 12:11:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728902AbgC3BKy (ORCPT ); Sun, 29 Mar 2020 21:10:54 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:46474 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728162AbgC3BJm (ORCPT ); Sun, 29 Mar 2020 21:09:42 -0400 Received: by mail-lj1-f194.google.com with SMTP id r7so8639692ljg.13; Sun, 29 Mar 2020 18:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M8DwevTofPw/pIdfp/6Cb1DGwp3gDQ5YLGJ2daY85MQ=; b=O6r9IkP9gT5mV1V+BtMChNkuEDA23g0XoMFPgKrfLC+yuksJd+kdDolL2UC22dmopL 8dRNBCHi6LH8QW6N5NcbEtW4SDXNG/MExceo4TisUduBw64+BAVDGYmAAQdz3Be0LHCX mjfTEe6cl0PW4dxXnpcjbBZCxPoJKShkYTanh08JV583adSP2d0dDdfpep8wEeORsAM8 3t2+4S53B48ZvhAP+LympPmE4r/XEcCcZWovbKkeLJ1edLnk05mFThwKS/geusT9gLtm joORZjx+6oCNPKX8VF+NcQNPo3CHNAbP4CcaX37k6Ib9ig2gzPMOUEQK+hmSWJfNDYnu A6Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M8DwevTofPw/pIdfp/6Cb1DGwp3gDQ5YLGJ2daY85MQ=; b=S8STf9i2RCuBseMepJdXP924tTBRYhgd7XXWFXofdOMVO29opKJlMfPVGRjgWTvmf3 v4uKF8y7TVUEiBHAfgVx+mQ1TsnXHGmHmVEy1+kwnSTSKqrJklSuhZ9c7xUVeTM2JeIo QoJ5ivWe44GxIXyo6DZjcznwA2M+UTbjbPJtFuGwK2GjV4ZyzmkhJzBFJNzfXNe1m53e NGrgDWvA05E9g2n9yVSIvg3UoWf0R/2DZQ5/DWR5DcbuFn5GxY6CeO60MLRl7MZ3Bssz 7aSqi+n80wWeOXYS7zh/JEYB++1CgiS/Ew2hqB2m0q1PSMNj3M/Kz2PU5F2CvdnIj3MO Wh5A== X-Gm-Message-State: AGi0PuYgYsOAoshpAArNGCAkQY/iTqPT4Gfif1mtnt+1D6CuyEPK17rc bOXDQdyw8MA+2HqTQOEvsaI= X-Google-Smtp-Source: APiQypLK4tHPYMPuq2cSaOwrtI4imEKVje/al1R0EOqTdKMfdRe0Dz8UxEc++EAv1R+FeNNvPSHdAg== X-Received: by 2002:a2e:7401:: with SMTP id p1mr5574125ljc.279.1585530580279; Sun, 29 Mar 2020 18:09:40 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:39 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs Date: Mon, 30 Mar 2020 04:08:48 +0300 Message-Id: <20200330010904.27643-7-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif From patchwork Mon Mar 30 01:08:49 2020 Content-Type: text/plain; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 07/22] dt-bindings: memory: tegra30: Add memory client IDs Date: Mon, 30 Mar 2020 04:08:49 +0300 Message-Id: <20200330010904.27643-8-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif From patchwork Mon Mar 30 01:08:50 2020 Content-Type: text/plain; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Mon, 30 Mar 2020 04:08:50 +0300 Message-Id: <20200330010904.27643-9-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..974048e83541 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -109,6 +109,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -126,6 +135,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -626,15 +644,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Mon Mar 30 01:08:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=a1imk7xg; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDrs6TPTz9sRN for ; Mon, 30 Mar 2020 12:09:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728201AbgC3BJs (ORCPT ); Sun, 29 Mar 2020 21:09:48 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:33685 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728280AbgC3BJr (ORCPT ); Sun, 29 Mar 2020 21:09:47 -0400 Received: by mail-lf1-f66.google.com with SMTP id x200so5559007lff.0; Sun, 29 Mar 2020 18:09:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FuqLVA2Ch1ge473EwwpJtLsZnteKNfYMkl72ih8U+c=; b=a1imk7xg6DJO18zhcZxKy5O1NJyW/KUhelh4pAugtSE8hQfVKLgMtRH877wdq/fWgk h7lIoG+UfMqesjXLOwCRcodeuhmCpiIjUNFKyaKqzARwS4HyQGNiSS83b6prJu7BCFTc S+h5vOv5N0Ny8mOLu8PPEqggvSHLD6m9LRQ544CdouBZkqSEsqUC27ZYWS86kpCWFIVS 1J9xqFkDRSseaL5bvPt3fsr0x6bbOaaSnqdysNQv50AHhIwklrKWaZWKGTrTelBT7Ah0 qZfuJdVs4Vl7U0EUjDkzylRd44bC4WgaqACYw/jN9627/gWPcuBEqu9iSF99YALsgVoO b82Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FuqLVA2Ch1ge473EwwpJtLsZnteKNfYMkl72ih8U+c=; b=twvzv8xT5gJUJLZMOyGpjS7t0OZlfh7/9gL1PnoZYZYdRZ+B1SPDeKjQ/RusQv7Pue g9ObTL+xTE+7evliTN9883VMbGVepm1bm97+pkujDB/vXhVAX8N7/p8LaVgnEzKZlDG8 9cyBfyig+Eo6CX8LjKP8i+9+WvSvygGkd4Qo3noUHZt8Djd5PjPagb23x2S9Z78ATiE3 kMFxuA7WX7+9MMTWCsWu9szPQVrhUJopJu1w9KsEcMjOZwZlAEXpGP97B1qK3IJgqvpz BzUoK61GQ+JgWxxjSEuRT2YklvJ1aZlGkR6q3VI0X++BCglRaMln9uDEGWQkLjJ8NiO0 yRCA== X-Gm-Message-State: AGi0PuYhzB7WnQX9jraLP24cBtNIcAaYQ4EdDhpnfk0aFhw4LnBxMyhP QtdicEpwliroisN6eR2KaxQ= X-Google-Smtp-Source: APiQypJ4ftA1ZlPdYQYD3PBQIBDGgxEHZTdSa7Dhm9yq5g30pRKLnMIFfBPHXLOVdy0wOQnSfxJX9A== X-Received: by 2002:ac2:41d3:: with SMTP id d19mr6601388lfi.57.1585530583834; Sun, 29 Mar 2020 18:09:43 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:43 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 09/22] ARM: tegra: Add interconnect properties to Tegra30 device-tree Date: Mon, 30 Mar 2020 04:08:51 +0300 Message-Id: <20200330010904.27643-10-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2d05f1da274..2b183025629f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -208,6 +208,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, + <&mc TEGRA30_MC_DISPLAY0B &emc>, + <&mc TEGRA30_MC_DISPLAY0C &emc>, + <&mc TEGRA30_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -227,6 +236,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, + <&mc TEGRA30_MC_DISPLAY0BB &emc>, + <&mc TEGRA30_MC_DISPLAY0CB &emc>, + <&mc TEGRA30_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -733,15 +751,18 @@ mc: memory-controller@7000f000 { #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra30-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Mon Mar 30 01:08:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263656 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=uoReP5o1; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDt24r4Fz9sSb for ; Mon, 30 Mar 2020 12:10:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728330AbgC3BJr (ORCPT ); Sun, 29 Mar 2020 21:09:47 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33862 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728267AbgC3BJr (ORCPT ); Sun, 29 Mar 2020 21:09:47 -0400 Received: by mail-lj1-f193.google.com with SMTP id p10so16076837ljn.1; Sun, 29 Mar 2020 18:09:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EkjouEeBk5eg2E7LoRsCY9DiuMbRBnrdHMJNPQxQEMg=; b=uoReP5o1Wpc4sXErhiwwYzGLqIZG8/HPTnwU7/VbcpDBs0yAOXD5zAtYc5xDmZL1ct UuKYJpRsNORBwC3dD+X3wBa1m8tFRMzhZmWJ4z3Rc0eBrZhJ12T25VLwdECwkkKTHpTP t35MNKIgHpLxPZAP0v8t9xEval1hNjGLep9oSnUp+WEsTqo3QWL+3qc1rn/tvGRi9IUO 0ShuXp9UEK8Dn0YFEW+wn5CZLvlkkxtD6nr09356ror89nA8ngq22tQkpAR/48R88sY6 rDYWrkNZbCJVkZbcjZ42l3Yka9hlLd33sO+pONmsjcbbEBT+NyCKwDos3/c5Tae10v3v gZSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EkjouEeBk5eg2E7LoRsCY9DiuMbRBnrdHMJNPQxQEMg=; b=i6hdEVukkGSZCiQ28xbB5e2ycqBPgDsTN448w9DiPUOslo7Ox1VRXUJRC/Wxr5BtAJ MeDBNEeSSR3UwkTjPjuzzIUDOFsISfnjrytt45neob7d/mnsHe9EzyouekxVJ5S0erHz bcIxld1e7VTo/HxqvmGwsCZhzqJQZdOowggeY2BIiJBf1L2EmYWCoDvw9reKIWv9VTvE Hy1kNZoHSsPKcih686vqS5x0eWa6tn9v/wOtZtIW7k1eN+xWGDIW3emRiL3H85bEVmwA /ObevN9tHJsyEIlsfmyR+YaXc33T1uHExYNIgmUqJtkhcqj/kMG2/zlNhZ+CVnvJPgQv NSUA== X-Gm-Message-State: AGi0PuajMxTSMmju7pKzspM58s6wRdT/35T6htxl6zDCM/k+MtdEHdNn bKI4AriSfOlPtbjMVfdBh8nPGt5O X-Google-Smtp-Source: APiQypIZbS8q+NVKU2VHe5+16UUjZNBYbRLaViehODNF6YSe90cPCBqkF1gsWjim+Yl2LvdHvEowig== X-Received: by 2002:a2e:a412:: with SMTP id p18mr5826456ljn.39.1585530584794; Sun, 29 Mar 2020 18:09:44 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 10/22] interconnect: Relax requirement in of_icc_get_from_provider() Date: Mon, 30 Mar 2020 04:08:52 +0300 Message-Id: <20200330010904.27643-11-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Artur Świgoń This patch relaxes the condition in of_icc_get_from_provider() so that it is no longer required to set #interconnect-cells = <1> in the DT. In case of the devfreq driver for exynos-bus, #interconnect-cells is always zero. Signed-off-by: Artur Świgoń [digetx@gmail.com: added cells_num checking for of_icc_xlate_onecell()] Signed-off-by: Dmitry Osipenko --- drivers/interconnect/core.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 2c6515e3ecf1..7d09656734c1 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -335,7 +335,7 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) struct icc_node *node = ERR_PTR(-EPROBE_DEFER); struct icc_provider *provider; - if (!spec || spec->args_count != 1) + if (!spec) return ERR_PTR(-EINVAL); mutex_lock(&icc_lock); @@ -851,6 +851,15 @@ EXPORT_SYMBOL_GPL(icc_nodes_remove); */ int icc_provider_add(struct icc_provider *provider) { + struct device_node *np = provider->dev->of_node; + u32 cells_num; + int err; + + err = of_property_read_u32(np, "#interconnect-cells", &cells_num); + if (WARN_ON(err)) + return err; + if (WARN_ON(provider->xlate == of_icc_xlate_onecell && cells_num != 1)) + return -EINVAL; if (WARN_ON(!provider->set)) return -EINVAL; if (WARN_ON(!provider->xlate)) From patchwork Mon Mar 30 01:08:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=b5rOMWO+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDsr6Tkrz9sPR for ; Mon, 30 Mar 2020 12:10:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728356AbgC3BJt (ORCPT ); Sun, 29 Mar 2020 21:09:49 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43322 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728309AbgC3BJs (ORCPT ); Sun, 29 Mar 2020 21:09:48 -0400 Received: by mail-lj1-f195.google.com with SMTP id g27so16239083ljn.10; Sun, 29 Mar 2020 18:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X5VcCh6eWMr9J37Xsf4tsyddBbuWfmiDNSVOMhCKemo=; b=b5rOMWO+3GLaJSJN3NaO51/e76l80sUm8FMWOvxcEKGmHEDls6ROUnIqCrEKrzlJcO N3PpRx/tVJZfG5xi/5b5ATmYpg57lHcfXtTWLU2pgwb5yXTMjOkrvCZ9Nl1gS1mFKzX3 kD9TdbPWtKhhH2vQhwAzD+EOvJTYYqf0u/Bk2V0Ic6UCo//nNh3ZvUwh9HoHo5t4Ercp NLfExVyx2nUkXADa1KDkSPQ90e+ZHK9nfVDyUUwJP+WDwkhDTS7Dk12fFIxsk3f4Y4SU /YvXCgp/d5fV2d45rT0Al30tw44Y5tfC+m34Yhtp7+JIUB6Rz11CxmIDyZpPI1mRJ4NC 0iag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X5VcCh6eWMr9J37Xsf4tsyddBbuWfmiDNSVOMhCKemo=; b=t33klstrevJ5eyGOT9LBoUSKml9Ep8El51yk5moXrcwZP+0mhYXzpuCSltf/crxVLK VrtjnYVsmP2IBfieVuIL8BOiNdhzRQOG6Kyw4wi7RX4Nt84cKJshkvwDCY98CBHFySPq SZq8xze/FNbuFyEcppnuSLQbfYmJ+QzmpOIla6B6fuyOb6fBwpn4ujpZ/oY6afGfLqpN OjcaDVLXlRRd8ZlXWXr4/vh2e1CRXi8fUTr908hd+kBMeADEX88OBTqOT837oYFgqOI0 YAGO0pe6gGv0BWYrKp5g/2qy3gmRyOy0iKOwdfSzXJ2X3C1p451j76MLhZX3B3XJ9M3u agsQ== X-Gm-Message-State: AGi0PubkCScq3nk/kc9XBFIGQ0SDoshl1EYtTlH7UKLzZJODuWW3rFiK +V+7oGosU2iedvEJxMFZrSU= X-Google-Smtp-Source: APiQypKhd7xEcrpcg3+qT1NGCf3mvbNjU1UXyNo0WHIQkeyyHkHVYwc+qMtCRcL9+xBspJXRW6opGQ== X-Received: by 2002:a2e:b4f1:: with SMTP id s17mr3231463ljm.283.1585530585762; Sun, 29 Mar 2020 18:09:45 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 11/22] memory: tegra: Register as interconnect provider Date: Mon, 30 Mar 2020 04:08:53 +0300 Message-Id: <20200330010904.27643-12-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now memory controller is a memory interconnection provider. This allows us to use interconnect API in order to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 118 ++++++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 8 +++ include/soc/tegra/mc.h | 3 + 3 files changed, 129 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..bcf0478c5f5a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -591,6 +591,117 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +static int tegra_mc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_onecell_data *data; + struct icc_node *node; + unsigned int num_nodes; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(mc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + num_nodes = mc->soc->num_clients; + + data = devm_kzalloc(mc->dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + mc->provider.dev = mc->dev; + mc->provider.set = tegra_mc_icc_set; + mc->provider.data = data; + mc->provider.xlate = of_icc_xlate_onecell; + mc->provider.aggregate = tegra_mc_icc_aggregate; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < num_nodes; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); + +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -699,6 +810,13 @@ static int tegra_mc_probe(struct platform_device *pdev) } } + if (IS_ENABLED(CONFIG_INTERCONNECT)) { + err = tegra_mc_interconnect_setup(mc); + if (err) + dev_err(&pdev->dev, "failed to initialize ICC: %d\n", + err); + } + return 0; } diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 957c6eb74ff9..bb13747cd96c 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -114,4 +114,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra's ICC, the values are chosen + * such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_EMC 1000 +#define TEGRA_ICC_EMEM 2000 +#define TEGRA_ICC_MC 3000 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..71de023f9f47 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -7,6 +7,7 @@ #define __SOC_TEGRA_MC_H__ #include +#include #include #include @@ -178,6 +179,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; From patchwork Mon Mar 30 01:08:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=D2TtU3gF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDt10503z9sR4 for ; Mon, 30 Mar 2020 12:10:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728347AbgC3BKo (ORCPT ); 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 12/22] memory: tegra20-emc: Use devm_platform_ioremap_resource Date: Mon, 30 Mar 2020 04:08:54 +0300 Message-Id: <20200330010904.27643-13-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Utilize that relatively new helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 60b048ae9982..ef3abc18a3f4 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -654,7 +654,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; int irq, err; /* driver has nothing to do in a case of memory timing absence */ @@ -689,8 +688,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); From patchwork Mon Mar 30 01:08:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=R7kFkFZL; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDsv47Jdz9sPR for ; Mon, 30 Mar 2020 12:10:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728468AbgC3BKj (ORCPT ); Sun, 29 Mar 2020 21:10:39 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:38988 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728347AbgC3BJu (ORCPT ); Sun, 29 Mar 2020 21:09:50 -0400 Received: by mail-lf1-f65.google.com with SMTP id h6so6945021lfp.6; Sun, 29 Mar 2020 18:09:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q4nV204hC2fwmDzQEKB7qIbLyFjMrEPQFeaJnZkMKlE=; b=R7kFkFZL6GQa6/p+lME2mLpX2W5dglEo3Y4GeoORp/vqCkVpf6z+ZPv39VaO1xXro4 mQsaenLZx+2m/AT2NLRsaKlD8CBYxhTQgQgzHClo9305BMfGFgJxD4dkgzyh15zGWPCv /IzIQ00ewvfY0d063gwLr52+/gRpcmjkRIwDc2tqhtjLLIbHKv0FtGFI+LjP0HsKg+rf Rl+Zlv7YoJdhxKyyJ+g7Mv9QTB3wNZMQW0LtU6TlddjA8WCJ9ko4UnHy06YG5xtWVFku RfXAkeNAeblEcDc0KDdlgGHfUG2mmrp8FCN7juWdik7Qa6m1MbxKWSgtCBETnHrSi6cn 52cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q4nV204hC2fwmDzQEKB7qIbLyFjMrEPQFeaJnZkMKlE=; b=uaTkamlzKGHo0izX0OaaKQbxWpUBSbgGznmx5kCwV4/u7dFfIPpun+Hz0gjy3K5WrP D4puUNFX/n4RHmnDTiYnTqoTUOkcs90Q/tFmbvN373NPBMb2Q+80JJiQaOAbDeRt48js zfCWhwglM2u1MgUTqgsxPXy6zfvcvATCoj0r01U22LZaoqFtjdRBNKKIL3DfBaKSjxBw utZjbIxze6lOK2InCCSW3JJyhFeG0kB8uG1ZU79eAuxrY6qcuXhG3XtOwKoExnVGxOGM UhCrj4t0m1uduZfYBVJjtWCfzvHjkmiEFjJ6qx9tBtx6DFv0pPcORmpa8SX7FQ1JkpDm zJLQ== X-Gm-Message-State: AGi0PuafkGjp6+ymHjtOZfq7V9rjuGJAV+q8Pmj2snRcchHN8h8H/G/C +769t3Ywiyg/vqlUEOsBVEA= X-Google-Smtp-Source: APiQypI0tJdoYescE/nvG1PxhKj3scyF/qbpV/MJqUUuemjN7l29mlKc0xbwtcvYsD7sjXssHhQOsA== X-Received: by 2002:a19:ed14:: with SMTP id y20mr6637613lfy.179.1585530587814; Sun, 29 Mar 2020 18:09:47 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:47 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 13/22] memory: tegra20-emc: Continue probing if timings are missing in device-tree Date: Mon, 30 Mar 2020 04:08:55 +0300 Message-Id: <20200330010904.27643-14-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 37 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index ef3abc18a3f4..3a6eb5cc5c29 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -383,6 +383,11 @@ tegra_emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) return of_node_get(dev->of_node); @@ -451,6 +456,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -656,13 +664,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int irq, err; - /* driver has nothing to do in a case of memory timing absence */ - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "EMC device tree node doesn't have memory timings\n"); - return 0; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "interrupt not specified\n"); @@ -670,23 +671,20 @@ static int tegra_emc_probe(struct platform_device *pdev) return irq; } - np = tegra_emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; - err = tegra_emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = tegra_emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) @@ -699,7 +697,8 @@ static int tegra_emc_probe(struct platform_device *pdev) err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, dev_name(&pdev->dev), emc); if (err) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", + irq, err); return err; } From patchwork Mon Mar 30 01:08:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263652 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VcKHNHoj; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:48 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 14/22] memory: tegra20-emc: Register as interconnect provider Date: Mon, 30 Mar 2020 04:08:56 +0300 Message-Id: <20200330010904.27643-15-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now memory controller is a memory interconnection provider. This allows us to use interconnect API in order to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 117 +++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 3a6eb5cc5c29..a2fcff221659 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,8 @@ #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -145,6 +148,7 @@ struct emc_timing { struct tegra_emc { struct device *dev; struct notifier_block clk_nb; + struct icc_provider provider; struct clk *clk; void __iomem *regs; @@ -658,6 +662,112 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node * +emc_of_icc_xlate_onecell(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id == TEGRA_ICC_EMEM) + return node; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long rate = icc_units_to_bps(dst->avg_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + int err; + + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = clk_set_min_rate(emc->clk, rate); + if (err) + return err; + + err = clk_set_rate(emc->clk, rate); + if (err) + return err; + + return 0; +} + +static int emc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + struct icc_node *node; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.xlate = emc_of_icc_xlate_onecell; + emc->provider.aggregate = emc_icc_aggregate; + + err = icc_provider_add(&emc->provider); + if (err) + return err; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); + +del_provider: + icc_provider_del(&emc->provider); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -721,6 +831,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + if (IS_ENABLED(CONFIG_INTERCONNECT)) { + err = tegra_emc_interconnect_init(emc); + if (err) + dev_err(&pdev->dev, "failed to initialize ICC: %d\n", + err); + } + return 0; unset_cb: From patchwork Mon Mar 30 01:08:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 15/22] memory: tegra20-emc: Create tegra20-devfreq device Date: Mon, 30 Mar 2020 04:08:57 +0300 Message-Id: <20200330010904.27643-16-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The tegra20-devfreq driver provides memory frequency scaling functionality and it uses EMC clock for the scaling. Since tegra20-devfreq is a software driver, the device for the driver needs to be created manually. Let's do it from EMC driver since it provides the clk rate-change functionality. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index a2fcff221659..867cd518b32e 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -838,6 +838,9 @@ static int tegra_emc_probe(struct platform_device *pdev) err); } + if (IS_ENABLED(CONFIG_ARM_TEGRA20_DEVFREQ)) + platform_device_register_simple("tegra20-devfreq", -1, NULL, 0); + return 0; unset_cb: From patchwork Mon Mar 30 01:08:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263644 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=IpN+1WW8; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDry68m6z9sSG for ; Mon, 30 Mar 2020 12:09:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbgC3BJx (ORCPT ); Sun, 29 Mar 2020 21:09:53 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:42907 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728220AbgC3BJx (ORCPT ); Sun, 29 Mar 2020 21:09:53 -0400 Received: by mail-lj1-f193.google.com with SMTP id q19so16239391ljp.9; Sun, 29 Mar 2020 18:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1mKtQtW5d+QZO5sS4d1TUhWoxitfV+iMW6pt/UheZUU=; b=IpN+1WW8ChpXXkajbJachp67OlaAqUuv/Zf20DrTCZHaySBU2fAlUgIwqIHczpK8qX +alZPRKVhBmDxBRSkDeVJx1pyCL9DS4AlnNYeaM8ZSBbg2v1/H+yBAki8/3+bomrgcsp PuutNcuikmjNfan5jYP/KkZ7bmSMMDpawtswfi+4UeR/pjKVkLjHeGukwhGRjF8QokQM aBe6Ybf5NyRAur7XkkxgzZ6Sb2r+FfGMJMRHBH0/8lxERqbKev9S6NdEU+Ks2QJnvL6d /Z4BmRD72wxGmVPDnVj8xQq1ekMLRO7NL4ESIm6Ts/wpmgHRIN5tvVNUY/53nX7bMvNp IdMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1mKtQtW5d+QZO5sS4d1TUhWoxitfV+iMW6pt/UheZUU=; b=IzzYR+4GN+Fe4ylgXP/9E7+w87VI5EFuN6/n6pj69cmDpyR9eifyFJusdtAGyNN6ll LhaAxVZdUdZPByBMXV+mWIvzdjcX8k+6i8jU7OY0OwVdVCHWD1ZdJ5JnXi0ivLhWtaBX Jy5JyfUAKUTD9GQPEMPT4QE0DSvGErbG+9v4o943tAvPkE6h5gVikBIoXvtdDt7EpTNq OJ+CGp2jPsP3xJvodJF015o+vf/eBAdbk83EslMK0N1O/vyVSv/fRCFn+JWT7qGgJz1c VqkRW26v3+lujU3/01S/Z7BrJtzxYJtlzAGjonTSowxvu6DUS3KCxuDHDNa5GU19jZZE 3VsQ== X-Gm-Message-State: AGi0PuYzQxJpx9G08Z/A4M46kHwxl672+zhd8Q67O808SxjJtXPWL8dm /EXUvxQ2ED4FmSCIgSgdyUg= X-Google-Smtp-Source: APiQypKABPDN7b8JWZ/OsG7aVs2aEJwYWKVYjc05Q4ZDGuMcNnfRbs7SVkk1TaRzip93+KQTiztvGQ== X-Received: by 2002:a2e:a495:: with SMTP id h21mr5723315lji.123.1585530590977; Sun, 29 Mar 2020 18:09:50 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 16/22] memory: tegra30-emc: Continue probing if timings are missing in device-tree Date: Mon, 30 Mar 2020 04:08:58 +0300 Message-Id: <20200330010904.27643-17-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 900a291803ca..69698665d431 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -988,6 +988,11 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + ram_code = tegra_read_ram_code(); for_each_child_of_node(dev->of_node, np) { @@ -1057,6 +1062,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -1263,12 +1271,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int err; - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "device-tree node doesn't have memory timings\n"); - return -ENODEV; - } - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); if (!np) { dev_err(&pdev->dev, "could not get memory controller node\n"); @@ -1280,10 +1282,6 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!mc) return -ENOENT; - np = emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); if (!emc) { of_node_put(np); @@ -1297,10 +1295,13 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) From patchwork Mon Mar 30 01:08:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=F7nQYiIa; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDs12hW4z9sSG for ; Mon, 30 Mar 2020 12:09:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728503AbgC3BJ4 (ORCPT ); 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider Date: Mon, 30 Mar 2020 04:08:59 +0300 Message-Id: <20200330010904.27643-18-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now external memory controller is a memory interconnection provider. This allows us to use interconnect API to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30-emc.c | 115 +++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 69698665d431..5a4106173a75 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -327,6 +328,7 @@ struct tegra_emc { struct device *dev; struct tegra_mc *mc; struct notifier_block clk_nb; + struct icc_provider provider; struct clk *clk; void __iomem *regs; unsigned int irq; @@ -1264,6 +1266,112 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node * +emc_of_icc_xlate_onecell(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id == TEGRA_ICC_EMEM) + return node; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long rate = icc_units_to_bps(dst->avg_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + int err; + + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = clk_set_min_rate(emc->clk, rate); + if (err) + return err; + + err = clk_set_rate(emc->clk, rate); + if (err) + return err; + + return 0; +} + +static int emc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + struct icc_node *node; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.xlate = emc_of_icc_xlate_onecell; + emc->provider.aggregate = emc_icc_aggregate; + + err = icc_provider_add(&emc->provider); + if (err) + return err; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); + +del_provider: + icc_provider_del(&emc->provider); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct platform_device *mc; @@ -1344,6 +1452,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + if (IS_ENABLED(CONFIG_INTERCONNECT)) { + err = tegra_emc_interconnect_init(emc); + if (err) + dev_err(&pdev->dev, "failed to initialize ICC: %d\n", + err); + } + return 0; unset_cb: From patchwork Mon Mar 30 01:09:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:52 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 18/22] drm/tegra: dc: Support memory bandwidth management Date: Mon, 30 Mar 2020 04:09:00 +0300 Message-Id: <20200330010904.27643-19-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. This patch wires up the interconnect API support to the DC driver. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 271 +++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 8 + drivers/gpu/drm/tegra/drm.c | 19 +++ drivers/gpu/drm/tegra/plane.c | 1 + drivers/gpu/drm/tegra/plane.h | 4 +- 5 files changed, 299 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 1a7b08f35776..b540ac6ffdc4 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -519,6 +519,136 @@ static void tegra_dc_setup_window(struct tegra_plane *plane, tegra_plane_setup_blending(plane, window); } +static unsigned long +tegra_plane_memory_bandwidth(struct drm_plane_state *state, + struct tegra_dc_window *window, + unsigned int num, + unsigned int denum) +{ + struct tegra_plane_state *tegra_state; + struct drm_crtc_state *crtc_state; + const struct drm_format_info *fmt; + struct tegra_dc_window win; + unsigned long long bandwidth; + unsigned int bpp_plane; + unsigned int bpp; + unsigned int mul; + unsigned int i; + + if (!state->fb || !state->visible) + return 0; + + crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); + tegra_state = to_tegra_plane_state(state); + + if (!window) + window = &win; + + window->src.w = drm_rect_width(&state->src) >> 16; + window->src.h = drm_rect_height(&state->src) >> 16; + window->dst.w = drm_rect_width(&state->dst); + window->dst.h = drm_rect_height(&state->dst); + window->tiling = tegra_state->tiling; + + fmt = state->fb->format; + + /* + * Note that real memory bandwidth vary depending on format and + * memory layout, we are not taking that into account because small + * estimation error isn't important since bandwidth is rounded up + * anyway. + */ + for (i = 0, bpp = 0; i < fmt->num_planes; i++) { + bpp_plane = fmt->cpp[i] * 8; + + /* + * Sub-sampling is relevant for chroma planes only and vertical + * readouts are not cached, hence only horizontal sub-sampling + * matters. + */ + if (i > 0) + bpp_plane /= fmt->hsub; + + bpp += bpp_plane; + } + + /* + * Horizontal downscale takes extra bandwidth which roughly depends + * on the scaled width. + */ + if (window->src.w > window->dst.w) + mul = (window->src.w - window->dst.w) * bpp / 2048 + 1; + else + mul = 1; + + /* + * Ignore cursor window if its width is small enough such that + * data-prefetch FIFO will easily help to overcome temporal memory + * pressure. + * + * Window A has a 128bit x 128 deep read FIFO, while windows B/C + * have a 128bit x 64 deep read FIFO. + * + * This allows us to not overestimate memory frequency requirement. + * Even if it will happen that cursor gets a temporal underflow, this + * won't be fatal. + */ + if (state->plane->type == DRM_PLANE_TYPE_CURSOR && + mul == 1 && window->src.w * bpp <= 128 * 16) + return 0; + + /* mode.clock in kHz, bandwidth in kbit/s */ + bandwidth = kbps_to_icc(crtc_state->mode.clock * bpp * mul); + + /* the requested bandwidth should be higher than required */ + bandwidth *= num; + do_div(bandwidth, denum); + + return min_t(u64, bandwidth, ULONG_MAX); +} + +static unsigned long +tegra20_plane_memory_bandwidth(struct drm_plane_state *state) +{ + return tegra_plane_memory_bandwidth(state, NULL, 29, 10); +} + +static unsigned long +tegra30_plane_memory_bandwidth(struct drm_plane_state *state) +{ + struct tegra_dc_window window; + unsigned long bandwidth; + + bandwidth = tegra_plane_memory_bandwidth(state, &window, 29, 10); + + /* x2: memory overfetch for tiled framebuffer and DDR3 */ + if (window.tiling.mode == TEGRA_BO_TILING_MODE_TILED) + bandwidth *= 2; + + return bandwidth; +} + +static unsigned long +tegra114_plane_memory_bandwidth(struct drm_plane_state *state) +{ + struct tegra_dc_window window; + unsigned long bandwidth; + + bandwidth = tegra_plane_memory_bandwidth(state, &window, 12, 10); + + /* x2: memory overfetch for tiled framebuffer and DDR3 */ + if (window.tiling.mode == TEGRA_BO_TILING_MODE_TILED) + bandwidth *= 2; + + return bandwidth; +} + +static unsigned long +tegra124_plane_memory_bandwidth(struct drm_plane_state *state) +{ + return tegra_plane_memory_bandwidth(state, NULL, 12, 10); +} + static const u32 tegra20_primary_formats[] = { DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB1555, @@ -608,8 +738,10 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, int err; /* no need for further checks if the plane is being disabled */ - if (!state->crtc) + if (!state->crtc) { + plane_state->memory_bandwidth = 0; return 0; + } err = tegra_plane_format(state->fb->format->format, &plane_state->format, @@ -662,6 +794,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, if (err < 0) return err; + plane_state->memory_bandwidth = dc->soc->plane_memory_bandwidth(state); + return 0; } @@ -1186,6 +1320,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) copy->pclk = state->pclk; copy->div = state->div; copy->planes = state->planes; + copy->memory_bandwidth = state->memory_bandwidth; return ©->base; } @@ -1777,6 +1912,8 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, err = host1x_client_suspend(&dc->client); if (err < 0) dev_err(dc->dev, "failed to suspend: %d\n", err); + + icc_set_bw(dc->icc_bandwidth, 0, 0); } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, @@ -1788,6 +1925,9 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, u32 value; int err; + icc_set_bw(dc->icc_bandwidth, state->memory_bandwidth, + state->memory_bandwidth); + err = host1x_client_resume(&dc->client); if (err < 0) { dev_err(dc->dev, "failed to resume: %d\n", err); @@ -1901,6 +2041,9 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { + struct tegra_dc_state *dc_old_state = to_dc_state(old_crtc_state); + struct tegra_dc_state *dc_state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); unsigned long flags; if (crtc->state->event) { @@ -1915,6 +2058,25 @@ static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, crtc->state->event = NULL; } + + if (old_crtc_state && old_crtc_state->active) { + /* + * Raise memory bandwidth before changes take effect if it + * goes from low to high. + */ + if (dc_old_state->memory_bandwidth < dc_state->memory_bandwidth) + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); + } else { + /* + * Raise memory bandwidth before changes take effect if + * CRTC is turning on. + */ + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); + } } static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, @@ -1933,7 +2095,80 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); } +static bool +tegra_plane_overlaps_other_plane(struct drm_crtc_state *state, + const struct drm_plane_state *plane_state) +{ + const struct drm_plane_state *other_state; + struct drm_plane *plane; + struct drm_rect rect; + + drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { + rect = plane_state->dst; + + if (other_state == plane_state) + continue; + + if (!other_state->visible || !other_state->fb) + continue; + + if (drm_rect_intersect(&rect, &other_state->dst)) + return true; + } + + return false; +} + +static int tegra_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct tegra_dc_state *dc_state = to_dc_state(state); + const struct drm_plane_state *plane_state; + const struct tegra_plane_state *tegra; + unsigned long long bandwidth = 0; + struct drm_plane *plane; + + /* + * For overlapping planes pixel's data is fetched for each plane at + * the same time, hence bandwidth is accumulated in this case. + */ + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) { + tegra = to_tegra_plane_state(plane_state); + + if (tegra_plane_overlaps_other_plane(state, plane_state)) + bandwidth += tegra->memory_bandwidth; + else + bandwidth = max_t(u64, bandwidth, + tegra->memory_bandwidth); + } + + dc_state->memory_bandwidth = min_t(u64, bandwidth, U32_MAX); + + return 0; +} + +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct tegra_dc_state *dc_old_state = to_dc_state(old_crtc_state); + struct tegra_dc_state *dc_state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (!dc_old_state) + return; + + /* + * Drop memory bandwidth after changes take effect if it goes from + * high to low. + */ + if (dc_old_state->memory_bandwidth > dc_state->memory_bandwidth) + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); +} + static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { + .atomic_check = tegra_crtc_atomic_check, .atomic_begin = tegra_crtc_atomic_begin, .atomic_flush = tegra_crtc_atomic_flush, .atomic_enable = tegra_crtc_atomic_enable, @@ -2225,6 +2460,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = true, .has_win_c_without_vert_filter = true, + .plane_memory_bandwidth = tegra20_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { @@ -2244,6 +2480,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra30_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { @@ -2263,6 +2500,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra114_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra124_dc_soc_info = { @@ -2282,6 +2520,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra210_dc_soc_info = { @@ -2301,6 +2540,7 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { @@ -2349,6 +2589,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra186_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { @@ -2397,6 +2638,7 @@ static const struct tegra_dc_soc_info tegra194_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra194_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct of_device_id tegra_dc_of_match[] = { @@ -2503,6 +2745,7 @@ static int tegra_dc_couple(struct tegra_dc *dc) static int tegra_dc_probe(struct platform_device *pdev) { + const char *level = KERN_ERR; struct tegra_dc *dc; int err; @@ -2571,8 +2814,6 @@ static int tegra_dc_probe(struct platform_device *pdev) err = tegra_dc_rgb_probe(dc); if (err < 0 && err != -ENODEV) { - const char *level = KERN_ERR; - if (err == -EPROBE_DEFER) level = KERN_DEBUG; @@ -2581,6 +2822,25 @@ static int tegra_dc_probe(struct platform_device *pdev) return err; } + /* + * The display controller memory bandwidth management isn't trivial + * because it requires the knowledge about the DC hardware state + * in order to make a proper decisions. It's not easy to convey + * that information to the ICC provider, so we will just use the + * first interconnect path for the memory bandwidth management and + * make all the decisions within the DC driver, for simplicity. + */ + dc->icc_bandwidth = of_icc_get(dc->dev, "display0a"); + err = PTR_ERR_OR_ZERO(dc->icc_bandwidth); + if (err) { + if (err == -EPROBE_DEFER) + level = KERN_DEBUG; + + dev_printk(level, dc->dev, + "failed to get display0a interconnect: %d\n", err); + goto remove_rgb; + } + platform_set_drvdata(pdev, dc); pm_runtime_enable(&pdev->dev); @@ -2599,6 +2859,9 @@ static int tegra_dc_probe(struct platform_device *pdev) disable_pm: pm_runtime_disable(&pdev->dev); + icc_put(dc->icc_bandwidth); + +remove_rgb: tegra_dc_rgb_remove(dc); return err; @@ -2616,6 +2879,8 @@ static int tegra_dc_remove(struct platform_device *pdev) return err; } + icc_put(dc->icc_bandwidth); + err = tegra_dc_rgb_remove(dc); if (err < 0) { dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 3d8ddccd758f..3a0ff57c5169 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -8,6 +8,7 @@ #define TEGRA_DC_H 1 #include +#include #include @@ -23,6 +24,8 @@ struct tegra_dc_state { unsigned int div; u32 planes; + + unsigned long memory_bandwidth; }; static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) @@ -66,6 +69,7 @@ struct tegra_dc_soc_info { const u64 *modifiers; bool has_win_a_without_filters; bool has_win_c_without_vert_filter; + unsigned long (*plane_memory_bandwidth)(struct drm_plane_state *state); }; struct tegra_dc { @@ -90,6 +94,8 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + struct icc_path *icc_bandwidth; }; static inline struct tegra_dc * @@ -150,6 +156,8 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct drm_crtc_state *crtc_state, struct clk *clk, unsigned long pclk, unsigned int div); +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state); /* from rgb.c */ int tegra_dc_rgb_probe(struct tegra_dc *dc); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index bd268028fb3d..44f558adddff 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -20,6 +20,7 @@ #include #include +#include "dc.h" #include "drm.h" #include "gem.h" @@ -59,6 +60,22 @@ static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; +static void tegra_atomic_post_commit(struct drm_device *drm, + struct drm_atomic_state *old_state) +{ + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct drm_crtc *crtc; + unsigned int i; + + for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, + new_crtc_state, i) { + if (!new_crtc_state->active) + continue; + + tegra_crtc_atomic_post_commit(crtc, old_crtc_state); + } +} + static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *drm = old_state->dev; @@ -75,6 +92,8 @@ static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) } else { drm_atomic_helper_commit_tail_rpm(old_state); } + + tegra_atomic_post_commit(drm, old_state); } static const struct drm_mode_config_helper_funcs diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 9ccfb56e9b01..f94925744105 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -63,6 +63,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) copy->swap = state->swap; copy->bottom_up = state->bottom_up; copy->opaque = state->opaque; + copy->memory_bandwidth = state->memory_bandwidth; for (i = 0; i < 2; i++) copy->blending[i] = state->blending[i]; diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h index a158a915109a..5227c7a9ad8b 100644 --- a/drivers/gpu/drm/tegra/plane.h +++ b/drivers/gpu/drm/tegra/plane.h @@ -51,10 +51,12 @@ struct tegra_plane_state { /* used for legacy blending support only */ struct tegra_plane_legacy_blending_state blending[2]; bool opaque; + + unsigned long memory_bandwidth; }; static inline struct tegra_plane_state * -to_tegra_plane_state(struct drm_plane_state *state) +to_tegra_plane_state(const struct drm_plane_state *state) { if (state) return container_of(state, struct tegra_plane_state, base); From patchwork Mon Mar 30 01:09:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GmV6d+mK; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 19/22] drm/tegra: dc: Tune up high priority request controls for Tegra20 Date: Mon, 30 Mar 2020 04:09:01 +0300 Message-Id: <20200330010904.27643-20-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra20 has a high-priority-request control that allows to configure when display's memory client should perform read requests with a higher priority (Tegra30+ uses other means like Latency Allowance). This patch changes the controls configuration in order to get a more aggressive memory prefetching, which allows to reliably avoid FIFO underflow when running on a lower memory frequency. This allow us safely drop the memory bandwidth requirement by about two times in a most popular use-cases (only one display active, video overlay inactive, no scaling is done). Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b540ac6ffdc4..564af302a965 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1980,12 +1980,12 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); /* initialize timer */ - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x70) | + WINDOW_B_THRESHOLD(0x30) | WINDOW_C_THRESHOLD(0x70); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0) | + WINDOW_B_THRESHOLD(0) | WINDOW_C_THRESHOLD(0); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | From patchwork Mon Mar 30 01:09:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=b2Wk9D3n; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDs52S00z9sSH for ; Mon, 30 Mar 2020 12:10:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728557AbgC3BKA (ORCPT ); Sun, 29 Mar 2020 21:10:00 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35046 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728496AbgC3BJ6 (ORCPT ); Sun, 29 Mar 2020 21:09:58 -0400 Received: by mail-lj1-f193.google.com with SMTP id k21so16333361ljh.2; Sun, 29 Mar 2020 18:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vPqDxoQDIqKqbTClKBTFY/GuSR/u7mIa4tRLiNa4khw=; b=b2Wk9D3nd02S1yBEw9VfNDHynpLIG1M19fnbYk4/jKvJE6gnNPd6fx/N9rmAc3h1WJ 0W4cIvLJs4zAoKqlmKnVdTm/7JOiI2jcLsTRUwkogWpygEHuBr7tnXXjJKfMFhu8jCzi YNL7hvXCo/KE3R0Er5Z7L0GQKBMAtnPchxE9PvlT2PvaEMODvg/pRIs15ZIS8BfaXRGD 7qCFNCiqYt3gQNpoHKhM8w1hg292Gntwo2n6q4Cw4K3lczlaaHnH9gTmwB2oxgsIKVAj voa3vghwgz+YfoFB1PGPeHCDGheL2yfhAk0ebY3wbFhZODm3AdVX9swEnK1snhMnnzA5 G39A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vPqDxoQDIqKqbTClKBTFY/GuSR/u7mIa4tRLiNa4khw=; b=U+MSYHN1RurowozjbCw9o9b2SBdqN0fn65m5n44spwJt52qpDkZAnbnV/MAt34AStS c8uKasm4KnwU/CMyg9NrbgmDd0LUCEYC4RS388lCdSG1Stjri4xoF2fDtWxegnxc+fvM w4X0JUShJFzn1PoferHvg47NV3epqQTtA2rFcMIok+Aw5JxoMVA9B2dsrtfbtRwNiNWg Cvi0E6munGHW1GR7E+Yt/QMjNtQTu+NSYYw1WJf3rfnvpkoSYPcbEVDCwTjTXOvDa1jU 7nHi/fsB+nzVhtZdicR8RjSFT4yp282Cijxw5ER/CdV80EaMoLRnWx8yEI4CZ3WhL2nY MGWg== X-Gm-Message-State: AGi0PuZtC5s+NAzpJLlsccWBMM/sWQChDQhHErk7al2HW45cI/3OwOjF bBUwGk0K0u99ayTxT1ccHkQ= X-Google-Smtp-Source: APiQypJKpYIkMoYh3zusIktDsInbffTBT2Ewun8AAXofUfmOfattVIpgibKPpUp/ustF4Zz22EcaHQ== X-Received: by 2002:a2e:740e:: with SMTP id p14mr5716504ljc.290.1585530595270; Sun, 29 Mar 2020 18:09:55 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 20/22] drm/tegra: dc: Extend debug stats with total number of events Date: Mon, 30 Mar 2020 04:09:02 +0300 Message-Id: <20200330010904.27643-21-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get reset. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 10 ++++++++++ drivers/gpu/drm/tegra/dc.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 564af302a965..7112f80ff9e8 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1616,6 +1616,11 @@ static int tegra_dc_show_stats(struct seq_file *s, void *data) seq_printf(s, "underflow: %lu\n", dc->stats.underflow); seq_printf(s, "overflow: %lu\n", dc->stats.overflow); + seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); + seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); + seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); + seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); + return 0; } @@ -2187,6 +2192,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): frame end\n", __func__); */ + dc->stats.frames_total++; dc->stats.frames++; } @@ -2195,6 +2201,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); */ drm_crtc_handle_vblank(&dc->base); + dc->stats.vblank_total++; dc->stats.vblank++; } @@ -2202,6 +2209,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): underflow\n", __func__); */ + dc->stats.underflow_total++; dc->stats.underflow++; } @@ -2209,11 +2217,13 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): overflow\n", __func__); */ + dc->stats.overflow_total++; dc->stats.overflow++; } if (status & HEAD_UF_INT) { dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); + dc->stats.underflow_total++; dc->stats.underflow++; } diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 3a0ff57c5169..3eb4eddc2288 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -41,6 +41,11 @@ struct tegra_dc_stats { unsigned long vblank; unsigned long underflow; unsigned long overflow; + + unsigned long frames_total; + unsigned long vblank_total; + unsigned long underflow_total; + unsigned long overflow_total; }; struct tegra_windowgroup_soc { From patchwork Mon Mar 30 01:09:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dAAbaMon; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDsd5rnQz9sSx for ; Mon, 30 Mar 2020 12:10:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728578AbgC3BKA (ORCPT ); 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 21/22] ARM: tegra: Enable interconnect API in tegra_defconfig Date: Mon, 30 Mar 2020 04:09:03 +0300 Message-Id: <20200330010904.27643-22-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra now has interconnect providers that are used for memory bandwidth allocation. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index aa94369bdd0f..0029259a6bf5 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -268,6 +268,7 @@ CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_TEGRA=y CONFIG_PHY_TEGRA_XUSB=y +CONFIG_INTERCONNECT=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y From patchwork Mon Mar 30 01:09:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1263649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=SHY9Z0Ng; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48rDsk1Bcfz9sSK for ; Mon, 30 Mar 2020 12:10:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728026AbgC3BKa (ORCPT ); Sun, 29 Mar 2020 21:10:30 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:33697 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728391AbgC3BJ7 (ORCPT ); Sun, 29 Mar 2020 21:09:59 -0400 Received: by mail-lf1-f66.google.com with SMTP id x200so5559416lff.0; Sun, 29 Mar 2020 18:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9E7zI2IZnXV4YyjveISOsemm9R4xu7EUE6WXPbYZj5s=; b=SHY9Z0NgudDm+L5mpyLB00o4AL/yhAoKr3QhYv/uGqvjwF4WtUVJvJNV4sfPZp4VYL gQ+u862RKGhEHlNflC6XRFa34GlMpKu7biU4hVlvoZHgIlYg9/0jNqr8zWTVgN/fD+G5 17chke2o76960p5eSNsbEF2fvD5ycrj+Ev4wEpl/k4OCU+JO65D6adaYNKF82XQjdMeV EiVy40M+MMGcC82Z4m+p9h1t5h+REMeOl+LLhVgSz8MDVIJD/RaihQmdSsD7ssnUvOwN i71Pw9XhUawf2Zz+MNMEz+qWo1g2srkUAlnyP1M/sFKBa8wCE+AB2T33wYureSb1X/K7 BkDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9E7zI2IZnXV4YyjveISOsemm9R4xu7EUE6WXPbYZj5s=; b=bSgyBvoQ3aqIYUz/pAQHTl2cdrglX780L9RTCIPv8hruxwYym5Z/GNzAtmY4Qy4FB7 3y7vg4sDO7afm68xhpsMEcZDduz3Grb5pSaV6mKJz2wgyeXc7lLflpgvjEPM703Oc87q kkb/+DD7367rGj3dmzh5AXGa1lDKQ4P5QcAX6PXpVHugbC/b6qOLwKWRu8htWDZ/d7Gc 1TcifQS2e0fw+QHyI2M5Mo//KSbekhu6azpqfen7Z444kJhul86JzWP23AyUJ1UT7byw ZyRLP6U8FwWPt6IyMNdRPFlCHIJfwNkcluc7noIeDGGe5a8QJWPl11+MhafcRQ7nNgve pLkw== X-Gm-Message-State: AGi0PubzB084BeULJoK/piyiELUqTDd9kO2naTG+aGbjWVTygtEBrV6s ygRqhXh3Q04m0/03yUu2vf8= X-Google-Smtp-Source: APiQypJb/KYN7Ausy9RzxNHKtBOMbGpnF36P6KkLPqb8j8gQzwiIUSVwL00ZzzFM4pP1djvb07ArDg== X-Received: by 2002:a05:6512:31d3:: with SMTP id j19mr6551417lfe.178.1585530597501; Sun, 29 Mar 2020 18:09:57 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 22/22] ARM: multi_v7_defconfig: Enable interconnect API Date: Mon, 30 Mar 2020 04:09:04 +0300 Message-Id: <20200330010904.27643-23-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA Tegra now has interconnect providers that are used for memory bandwidth allocation. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f8e45351c3f9..658b5c1892eb 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1085,6 +1085,7 @@ CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m +CONFIG_INTERCONNECT=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y