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Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/cache.c | 28 ++++++++++++++++++++++++++++ common/board_f.c | 28 ---------------------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 007d4ebc49..b8e1e340a1 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. @@ -118,3 +120,29 @@ void invalidate_l2_cache(void) isb(); } #endif + +__weak int reserve_mmu(void) +{ +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->relocaddr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->relocaddr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->relocaddr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* + * Record allocated tlb_addr in case gd->tlb_addr to be overwritten + * with location within secure ram. + */ + gd->arch.tlb_allocated = gd->arch.tlb_addr; +#endif +#endif + + return 0; +} diff --git a/common/board_f.c b/common/board_f.c index 82a164752a..a88bd64630 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -385,34 +385,6 @@ static int reserve_round_4k(void) return 0; } -#ifdef CONFIG_ARM -__weak int reserve_mmu(void) -{ -#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - /* reserve TLB table */ - gd->arch.tlb_size = PGTABLE_SIZE; - gd->relocaddr -= gd->arch.tlb_size; - - /* round down to next 64 kB limit */ - gd->relocaddr &= ~(0x10000 - 1); - - gd->arch.tlb_addr = gd->relocaddr; - debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); - -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - /* - * Record allocated tlb_addr in case gd->tlb_addr to be overwritten - * with location within secure ram. - */ - gd->arch.tlb_allocated = gd->arch.tlb_addr; -#endif -#endif - - return 0; -} -#endif - static int reserve_video(void) { #ifdef CONFIG_DM_VIDEO From patchwork Sun Mar 29 17:57:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 1263518 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=PtZMebCV; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48r3KD6wDdz9sR4 for ; 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It implements the default routine for reserving memory for MMU TLB and needs to be weakly defined in order to allow for machines to override it. Without this decoupling, after introducing arch_reserve_mmu, there would be two weak definitions for it, one in common/board_f.c and one in arch/arm/lib/cache.c. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/include/asm/cache.h | 11 +++++++++++ arch/arm/lib/cache.c | 5 +++++ arch/arm/mach-versal/cpu.c | 3 ++- arch/arm/mach-zynqmp/cpu.c | 3 ++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 950ec1e793..c20e05ec7f 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -49,4 +49,15 @@ void dram_bank_mmu_setup(int bank); */ #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +/* + * arm_reserve_mmu() - Reserve memory for MMU TLB table + * + * Default implementation for reserving memory for MMU TLB table. It is used + * during generic board init sequence in common/board_f.c. Weakly defined, so + * that machines can override it if needed. + * + * Return: 0 if OK + */ +int arm_reserve_mmu(void); + #endif /* _ASM_CACHE_H */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b8e1e340a1..3cbed602eb 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -122,6 +122,11 @@ void invalidate_l2_cache(void) #endif __weak int reserve_mmu(void) +{ + return arm_reserve_mmu(); +} + +__weak int arm_reserve_mmu(void) { #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) /* reserve TLB table */ diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 6ee6cd43ec..c14c5bb39c 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -98,7 +99,7 @@ u64 get_page_table_size(void) } #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) -int reserve_mmu(void) +int arm_reserve_mmu(void) { tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 442427bc11..811684a9f8 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -11,6 +11,7 @@ #include #include #include +#include #define ZYNQ_SILICON_VER_MASK 0xF000 #define ZYNQ_SILICON_VER_SHIFT 12 @@ -116,7 +117,7 @@ void tcm_init(u8 mode) #endif #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -int reserve_mmu(void) +int arm_reserve_mmu(void) { tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; From patchwork Sun Mar 29 17:57:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 1263519 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Sun, 29 Mar 2020 10:59:44 -0700 (PDT) Received: from uidivo.corp.ad.wrs.com ([2a02:2f0e:c308:f100:69c8:7d59:ae44:8d25]) by smtp.googlemail.com with ESMTPSA id h2sm10195243wmb.16.2020.03.29.10.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 10:59:43 -0700 (PDT) From: Ovidiu Panait To: u-boot@lists.denx.de Cc: sjg@chromium.org, trini@konsulko.com, Ovidiu Panait Subject: [PATCH v2 3/3] common/board_f: Make reserve_mmu generic Date: Sun, 29 Mar 2020 20:57:41 +0300 Message-Id: <20200329175741.26297-4-ovpanait@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200329175741.26297-1-ovpanait@gmail.com> References: <20200329175741.26297-1-ovpanait@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu routines. Also, define a weak nop stub for it. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/cache.c | 2 +- common/board_f.c | 9 ++++++--- include/init.h | 13 ++++++++++++- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 3cbed602eb..44dde26065 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -121,7 +121,7 @@ void invalidate_l2_cache(void) } #endif -__weak int reserve_mmu(void) +int arch_reserve_mmu(void) { return arm_reserve_mmu(); } diff --git a/common/board_f.c b/common/board_f.c index a88bd64630..52750dd307 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -385,6 +385,11 @@ static int reserve_round_4k(void) return 0; } +__weak int arch_reserve_mmu(void) +{ + return 0; +} + static int reserve_video(void) { #ifdef CONFIG_DM_VIDEO @@ -942,9 +947,7 @@ static const init_fnc_t init_sequence_f[] = { reserve_pram, #endif reserve_round_4k, -#ifdef CONFIG_ARM - reserve_mmu, -#endif + arch_reserve_mmu, reserve_video, reserve_trace, reserve_uboot, diff --git a/include/init.h b/include/init.h index 2a33a3fd1e..9ef88c966b 100644 --- a/include/init.h +++ b/include/init.h @@ -129,6 +129,18 @@ int testdram(void); */ int arch_reserve_stacks(void); +/** + * arch_reserve_mmu() - Reserve memory for MMU TLB table + * + * Architecture-specific routine for reserving memory for the MMU TLB table. + * This is used in generic board init sequence in common/board_f.c. + * + * If an implementation is not provided, it will just be a nop stub. + * + * Return: 0 if OK + */ +int arch_reserve_mmu(void); + /** * init_cache_f_r() - Turn on the cache in preparation for relocation * @@ -145,7 +157,6 @@ int init_cache_f_r(void); int print_cpuinfo(void); #endif int timer_init(void); -int reserve_mmu(void); int misc_init_f(void); #if defined(CONFIG_DTB_RESELECT)