From patchwork Sat Mar 28 18:23:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ovidiu Panait X-Patchwork-Id: 1263277 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=iGAAXIkT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48qRxh0091z9sRR for ; Sun, 29 Mar 2020 05:26:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6B45B81885; Sat, 28 Mar 2020 19:25:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="iGAAXIkT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C5C2C81888; Sat, 28 Mar 2020 19:25:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1F616813B5 for ; Sat, 28 Mar 2020 19:25:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ovpanait@gmail.com Received: by mail-wm1-x342.google.com with SMTP id w25so9780940wmi.0 for ; Sat, 28 Mar 2020 11:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=LHJOd03pHT3nZFBYW30/zSAvijaEWAqBlweuhruYTC8=; b=iGAAXIkT1baRmsKcupxpUYIcEfNM4wuWxZQmtGIGdPQ4KdQAu6q/BzdN0haHqIT87T icp5s+KYYHE40ACo7hLwHrdiNShoL9w1zveRrHtdoaIu3VxHOovlUnWZiXSz+opiLA2C UXMwGkXN+aoKy20dpHuMtTM3AtJN91AYJxIyPSebP9IQISy3DSnPoDv90gjFygO6RIkv Ab4sgRkChf6tCe+vAbm8kYmvVoUsEmaxfAZCmQErnP6zot2LGrzgUxQEPNq9vb3BesQm KYbiMXek7lO18drCLueU+69gT1gg/iHWnC/X/mlBjbyXw08K3VBwHuc+vdyRplxsI+0c IFFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LHJOd03pHT3nZFBYW30/zSAvijaEWAqBlweuhruYTC8=; b=D83PtS9qqY24ros7jm1E7je9mj6TDGtOa8YidrapwR5ZYf1dbsMbkZbvyjncSDsLpp 8VZGxQ8YPI9KhMH/gBKxumHd8/GjW/fsLw7Pq6IT4CQwLKEfYtP1C45b79GhZSSVGFUv 8lf7fmSkmu/gp5aLqFotq+ef9lmb/ZWpNypDvpow9KxafQ4hDBp/5TI4dIHYrAVuFdYm 4F4ra8ORCuwlchMz/muDvTLyV/5i7pAQgbBJGPRUSgQq95Fzs6KyztK6TtWD/o5EQyDN HSJb2GLtPzaGYH7or1m6WsFKrtvry+0d07ryWtiqELkgK7e6QYzGu0esIVLlyJkWXgnl aEVQ== X-Gm-Message-State: ANhLgQ38OhXqLO1ec9EQD+PaA02t6wZwewbZaka2DU1GMI2TfKeQxZyX MzRsgGsT19cApXcG4kCfQZg0QuMfp0w= X-Google-Smtp-Source: ADFU+vtLDnDBLdhPrEjfkNZxAuk59x0lOL65Lcm6N9hTRE3Jhipl8eAw0J5v2HMeuOKgAUTEugv0OQ== X-Received: by 2002:a05:600c:d4:: with SMTP id u20mr5011025wmm.83.1585419950087; Sat, 28 Mar 2020 11:25:50 -0700 (PDT) Received: from uidivo.corp.ad.wrs.com ([2a02:2f0e:c308:f100:69c8:7d59:ae44:8d25]) by smtp.googlemail.com with ESMTPSA id v7sm11341192wrs.96.2020.03.28.11.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Mar 2020 11:25:49 -0700 (PDT) From: Ovidiu Panait To: u-boot@lists.denx.de Cc: sjg@chromium.org, trini@konsulko.com, Ovidiu Panait Subject: [PATCH] common/board_f: Make reserve_mmu generic Date: Sat, 28 Mar 2020 20:23:00 +0200 Message-Id: <20200328182300.26005-1-ovpanait@gmail.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu routines. For ARM, move the reserve_mmu definition from common/board_f.c to arch/arm/lib/cache.c. Define arm_reserve_mmu and make it a weak define to allow machines to override it (in mach-versal/cpu.c and mach-zynqmp/cpu.c). Signed-off-by: Ovidiu Panait --- arch/arm/include/asm/cache.h | 2 ++ arch/arm/lib/cache.c | 33 +++++++++++++++++++++++++++++++++ arch/arm/mach-versal/cpu.c | 6 +++++- arch/arm/mach-zynqmp/cpu.c | 6 +++++- common/board_f.c | 32 ++++++-------------------------- include/init.h | 2 +- 6 files changed, 52 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 950ec1e793..dbb9c554ae 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -49,4 +49,6 @@ void dram_bank_mmu_setup(int bank); */ #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +int arm_reserve_mmu(void); + #endif /* _ASM_CACHE_H */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 007d4ebc49..76c10a577b 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. @@ -118,3 +120,34 @@ void invalidate_l2_cache(void) isb(); } #endif + +int arch_reserve_mmu(void) +{ + return arm_reserve_mmu(); +} + +__weak int arm_reserve_mmu(void) +{ +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->relocaddr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->relocaddr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->relocaddr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* + * Record allocated tlb_addr in case gd->tlb_addr to be overwritten + * with location within secure ram. + */ + gd->arch.tlb_allocated = gd->arch.tlb_addr; +#endif +#endif + + return 0; +} diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 6ee6cd43ec..6c5da8b29e 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -10,6 +10,10 @@ #include #include +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #define VERSAL_MEM_MAP_USED 5 @@ -98,7 +102,7 @@ u64 get_page_table_size(void) } #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) -int reserve_mmu(void) +int arm_reserve_mmu(void) { tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 442427bc11..363a20b621 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -12,6 +12,10 @@ #include #include +#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU +#include +#endif + #define ZYNQ_SILICON_VER_MASK 0xF000 #define ZYNQ_SILICON_VER_SHIFT 12 @@ -116,7 +120,7 @@ void tcm_init(u8 mode) #endif #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -int reserve_mmu(void) +int arm_reserve_mmu(void) { tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; diff --git a/common/board_f.c b/common/board_f.c index 82a164752a..2ab23cf239 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -385,33 +385,15 @@ static int reserve_round_4k(void) return 0; } -#ifdef CONFIG_ARM -__weak int reserve_mmu(void) +__weak int arch_reserve_mmu(void) { -#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - /* reserve TLB table */ - gd->arch.tlb_size = PGTABLE_SIZE; - gd->relocaddr -= gd->arch.tlb_size; - - /* round down to next 64 kB limit */ - gd->relocaddr &= ~(0x10000 - 1); - - gd->arch.tlb_addr = gd->relocaddr; - debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); - -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - /* - * Record allocated tlb_addr in case gd->tlb_addr to be overwritten - * with location within secure ram. - */ - gd->arch.tlb_allocated = gd->arch.tlb_addr; -#endif -#endif - return 0; } -#endif + +static int reserve_mmu(void) +{ + return arch_reserve_mmu(); +} static int reserve_video(void) { @@ -970,9 +952,7 @@ static const init_fnc_t init_sequence_f[] = { reserve_pram, #endif reserve_round_4k, -#ifdef CONFIG_ARM reserve_mmu, -#endif reserve_video, reserve_trace, reserve_uboot, diff --git a/include/init.h b/include/init.h index 2a33a3fd1e..5700dc7ecb 100644 --- a/include/init.h +++ b/include/init.h @@ -145,7 +145,7 @@ int init_cache_f_r(void); int print_cpuinfo(void); #endif int timer_init(void); -int reserve_mmu(void); +int arch_reserve_mmu(void); int misc_init_f(void); #if defined(CONFIG_DTB_RESELECT)