From patchwork Tue Dec 5 03:19:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 844540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yrRn83bdVz9s7g for ; Tue, 5 Dec 2017 14:19:40 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UHZR7CYi"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yrRn81KC0zDrVv for ; Tue, 5 Dec 2017 14:19:40 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UHZR7CYi"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::241; helo=mail-pf0-x241.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UHZR7CYi"; dkim-atps=neutral Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yrRn12JlDzDrKQ for ; Tue, 5 Dec 2017 14:19:32 +1100 (AEDT) Received: by mail-pf0-x241.google.com with SMTP id d23so10165671pfe.9 for ; Mon, 04 Dec 2017 19:19:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=i5GqzJUGtymEUOJUHEKWAycuxKywVxnSNU8kzOtswIQ=; b=UHZR7CYi7HevJfU2YGkP9gg2z/QyupfJ5B92JfLnn/PTIe4QkgI8ZhIm5cdV62/og4 O1lGuk516RvkRS6l0aMidZm4IJaQv7SRdAVhv+GJbF7gYBESMRXPsCUXifCnn8xOH34l wtc1xBRzvV8PuJEU4S1OkSo/gcvhZynI2YsUrTts6TZ3CPiulfbghZ5zxm9C5A3KXg0Z Zn30Ji9YH+TacaSQk6VKUjnVwXx28qHePPHr7Pqy6jEHQx9WzKnATViJuWyB1aM0yu0r valX8QzWbh7Vvljxd5+MFuo4KTOwexCF+9blQbpUw+RLXXGOZrdpZPRIokIdiS1XkGQm o+/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=i5GqzJUGtymEUOJUHEKWAycuxKywVxnSNU8kzOtswIQ=; b=VlQ7rZiNBU65OHfPdqHT8JTDubfWL289p7l5Bs8GbUSaJg1OPCz5cJCkiLH5gt5Dxo Hy2HIrH/rYr7vHmep/taYeQB/2UbTmX0xIUywPTdJZOU2DReCjB5gvgmAQLmI//UeNeG 51s1VO+yJy4vPoUveaMNciLcbSRenE+GV6lRrtVfPU/Yq3EVwhMWdvnBCMiEehNfGnZr 6NVuOiS/IHo2sr7wEcMJYQFTwrsXA3ZGNhC18XGhuOjJUSLN2hsvcegUGWfGk8ABezGo 8lJV3wbtxSIW5ZZOj5/ylTjdxQgXpJOur+ZLhqwZspmDSHpSJK48ovLLo1sQu2dGniHr pdFQ== X-Gm-Message-State: AJaThX50lNPRchPUuPBhipOsHz4MhyCuT/Oi7aBkGLkrPoaBgabFWdrq +vFcnFbEV5vsjCB+4Wveyu84Tg== X-Google-Smtp-Source: AGs4zMaTfRwPpa9qB+gjCcAbPi14zFjm1mBpOmOumZPPIVT4iBfY/rsrpHSbwg/zstnFn8PnPpJW9w== X-Received: by 10.98.198.73 with SMTP id m70mr21471872pfg.92.1512443970046; Mon, 04 Dec 2017 19:19:30 -0800 (PST) Received: from flat-canetoad.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id l21sm25953715pfg.156.2017.12.04.19.19.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 19:19:29 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 5 Dec 2017 14:19:19 +1100 Message-Id: <20171205031919.26644-1-oohall@gmail.com> X-Mailer: git-send-email 2.9.5 Subject: [Skiboot] [PATCH] chiptod: Keep boot timestamps contiguous X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently we reset the timebase value to (almost) zero when synchronising the timebase of each chip to the Chip TOD network which results in this: [ 42.374813167,5] CPU: All 80 processors called in... [ 2.222791151,5] FLASH: Found system flash: Macronix MXxxL51235F id:0 [ 2.222977933,5] BT: Interface initialized, IO 0x00e4 This patch modifies the chiptod_init() process to use the current timebase value rather than resetting it to zero. This results in the timestamps remaining contigious from the start of hostboot until the petikernel starts. e.g. [ 70.188811484,5] CPU: All 144 processors called in... [ 72.458004252,5] FLASH: Found system flash: id:0 [ 72.458147358,5] BT: Interface initialized, IO 0x00e4 Signed-off-by: Oliver O'Halloran Reviewed-by: Vaidyanathan Srinivasan --- Tested on a Witherspoon and a P8 FSP box. Seems to work ok in both cases. --- core/init.c | 8 +++++--- hw/chiptod.c | 15 +++++++++++---- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/core/init.c b/core/init.c index 89a2758128e2..d008e2dc40f2 100644 --- a/core/init.c +++ b/core/init.c @@ -966,9 +966,11 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) cpu_set_sreset_enable(true); /* - * Synchronize time bases. Thi resets all the TB values to a small - * value (so they appear to go backward at this point), and synchronize - * all core timebases to the global ChipTOD network + * Synchronize time bases. Prior to chiptod_init() the timebase + * is free-running at a frequency based on the core clock rather + * than being synchronised to the ChipTOD network. This means + * that the timestamps in early boot might be a little off compared + * to wall clock time. */ chiptod_init(); diff --git a/hw/chiptod.c b/hw/chiptod.c index b9e47741bf21..3a0940d2b8bc 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -120,9 +120,6 @@ #define LOCAL_CORE_FIR 0x0104000C #define LFIR_SWITCH_COMPLETE PPC_BIT(18) -/* Magic TB value. One step cycle ahead of sync */ -#define INIT_TB 0x000000000001ff0 - /* Number of iterations for the various timeouts */ #define TIMEOUT_LOOPS 20000000 @@ -775,6 +772,7 @@ static void chiptod_reset_tod_errors(void) static void chiptod_sync_master(void *data) { + uint64_t initial_tb_value; bool *result = data; prlog(PR_DEBUG, "Master sync on CPU PIR 0x%04x...\n", @@ -824,8 +822,17 @@ static void chiptod_sync_master(void *data) goto error; } + /* + * Load the master's current timebase value into the Chip TOD + * network. This is so we have sane timestamps across the whole + * IPL process. The Chip TOD documentation says that the loaded + * value needs to be one STEP before a SYNC. In other words, + * set the low bits to 0x1ff0. + */ + initial_tb_value = (mftb() & ~0x1fff) | 0x1ff0; + /* Chip TOD load initial value */ - if (xscom_writeme(TOD_CHIPTOD_LOAD_TB, INIT_TB)) { + if (xscom_writeme(TOD_CHIPTOD_LOAD_TB, initial_tb_value)) { prerror("XSCOM error setting init TB\n"); goto error; }