From patchwork Wed Mar 25 02:28:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1261110 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=flygoat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.a=rsa-sha256 header.s=mail header.b=MU3FYjrn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nBxv5gv3z9sRR for ; Wed, 25 Mar 2020 13:33:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727259AbgCYCdj (ORCPT ); Tue, 24 Mar 2020 22:33:39 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17896 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727272AbgCYCdj (ORCPT ); Tue, 24 Mar 2020 22:33:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1585103431; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=KS7DviC6uXqOtX8AfqQR0mH/vatPhcGamkwIX/ZOMkg=; b=MU3FYjrnq45ynb0Zc2UdaGhxWxjBDG6sY/dasnSIaMi7qjuH8dvPhHut89bTaNiZ UL4FddiDJ8GB8lok4VUk/Q2VAZpdI1cWy9bIq9PfzgKqClidmWq7b+sNGghE9gIlWDn /6osn5j+Q/0aHMgQvVD8kREGqCBg0pOcsMhGBl4I= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1585103429415389.6646407332655; Wed, 25 Mar 2020 10:30:29 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Marc Zyngier , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Jonathan Corbet , Paul Cercueil , John Crispin , Matthias Brugger , Jean Delvare , "David S. Miller" , Mauro Carvalho Chehab , Jonathan Cameron , Greg Kroah-Hartman , Andy Shevchenko , Geert Uytterhoeven , Krzysztof Kozlowski , Miquel Raynal , Andi Kleen , "H. Nikolaus Schaller" , "Eric W. Biederman" , Tiezhu Yang , Yinglu Yang , Allison Randal , Bartlomiej Zolnierkiewicz , Paul Burton , Manuel Lauss , Serge Semin , Matt Redfearn , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-ide@vger.kernel.org Message-ID: <20200325022916.106641-2-jiaxun.yang@flygoat.com> Subject: [PATCH v7 01/12] irqchip: Add driver for Loongson I/O Local Interrupt Controller Date: Wed, 25 Mar 2020 10:28:17 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200325022916.106641-1-jiaxun.yang@flygoat.com> References: <20200325022916.106641-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This controller appeared on Loongson family of chips as the primary package interrupt source. Signed-off-by: Jiaxun Yang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Reviewed-by: Marc Zyngier --- v4-v5: Resolve suggestions from maz: - Remove DT validation - Simplify unnucessary functions & variables --- drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-loongson-liointc.c | 261 +++++++++++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 drivers/irqchip/irq-loongson-liointc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 6d397732138d..c609eaa319d2 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER Say yes here to add support for the IRQ combiner devices embedded in Samsung Exynos chips. +config LOONGSON_LIOINTC + bool "Loongson Local I/O Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson Local I/O Interrupt Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index eae0d78cbf22..5e7678efdfe6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c new file mode 100644 index 000000000000..18de2c09ece4 --- /dev/null +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang + * Loongson Local IO Interrupt Controller support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LIOINTC_CHIP_IRQ 32 +#define LIOINTC_NUM_PARENT 4 + +#define LIOINTC_INTC_CHIP_START 0x20 + +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) + +#define LIOINTC_SHIFT_INTx 4 + +struct liointc_handler_data { + struct liointc_priv *priv; + u32 parent_int_map; +}; + +struct liointc_priv { + struct irq_chip_generic *gc; + struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; + u8 map_cache[LIOINTC_CHIP_IRQ]; +}; + +static void liointc_chained_handle_irq(struct irq_desc *desc) +{ + struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_chip_generic *gc = handler->priv->gc; + u32 pending; + + chained_irq_enter(chip, desc); + + pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); + + if (!pending) + spurious_interrupt(); + + while (pending) { + int bit = __ffs(pending); + + generic_handle_irq(irq_find_mapping(gc->domain, bit)); + pending &= ~BIT(bit); + } + + chained_irq_exit(chip, desc); +} + +static void liointc_set_bit(struct irq_chip_generic *gc, + unsigned int offset, + u32 mask, bool set) +{ + if (set) + writel(readl(gc->reg_base + offset) | mask, + gc->reg_base + offset); + else + writel(readl(gc->reg_base + offset) & ~mask, + gc->reg_base + offset); +} + +static int liointc_set_type(struct irq_data *data, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + u32 mask = data->mask; + unsigned long flags; + + irq_gc_lock_irqsave(gc, flags); + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_LEVEL_LOW: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + case IRQ_TYPE_EDGE_RISING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_EDGE_FALLING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + default: + return -EINVAL; + } + irq_gc_unlock_irqrestore(gc, flags); + + irqd_set_trigger_type(data, type); + return 0; +} + +static void liointc_resume(struct irq_chip_generic *gc) +{ + struct liointc_priv *priv = gc->private; + unsigned long flags; + int i; + + irq_gc_lock_irqsave(gc, flags); + /* Disable all at first */ + writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); + /* Revert map cache */ + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) + writeb(priv->map_cache[i], gc->reg_base + i); + /* Revert mask cache */ + writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); + irq_gc_unlock_irqrestore(gc, flags); +} + +static const char * const parent_names[] = {"int0", "int1", "int2", "int3"}; + +int __init liointc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_domain *domain; + struct irq_chip_type *ct; + struct liointc_priv *priv; + void __iomem *base; + u32 of_parent_int_map[LIOINTC_NUM_PARENT]; + int parent_irq[LIOINTC_NUM_PARENT]; + bool have_parent = FALSE; + int sz, i, err = 0; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = of_iomap(node, 0); + if (!base) { + err = -ENODEV; + goto out_free_priv; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + parent_irq[i] = of_irq_get_byname(node, parent_names[i]); + if (parent_irq[i] > 0) + have_parent = TRUE; + } + if (!have_parent) { + err = -ENODEV; + goto out_iounmap; + } + + sz = of_property_read_variable_u32_array(node, + "loongson,parent_int_map", + &of_parent_int_map[0], + LIOINTC_NUM_PARENT, + LIOINTC_NUM_PARENT); + if (sz < 4) { + pr_err("loongson-liointc: No parent_int_map\n"); + err = -ENODEV; + goto out_iounmap; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) + priv->handler[i].parent_int_map = of_parent_int_map[i]; + + /* Setup IRQ domain */ + domain = irq_domain_add_linear(node, 32, + &irq_generic_chip_ops, priv); + if (!domain) { + pr_err("loongson-liointc: cannot add IRQ domain\n"); + err = -EINVAL; + goto out_iounmap; + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, handle_level_irq, + IRQ_NOPROBE, 0, 0); + if (err) { + pr_err("loongson-liointc: unable to register IRQ domain\n"); + goto out_free_domain; + } + + + /* Disable all IRQs */ + writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE); + /* Set to level triggered */ + writel(0x0, base + LIOINTC_REG_INTC_EDGE); + + /* Generate parent INT part of map cache */ + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + u32 pending = priv->handler[i].parent_int_map; + + while (pending) { + int bit = __ffs(pending); + + priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx; + pending &= ~BIT(bit); + } + } + + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) { + /* Generate core part of map cache */ + priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id); + writeb(priv->map_cache[i], base + i); + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->private = priv; + gc->reg_base = base; + gc->domain = domain; + gc->resume = liointc_resume; + + ct = gc->chip_types; + ct->regs.enable = LIOINTC_REG_INTC_ENABLE; + ct->regs.disable = LIOINTC_REG_INTC_DISABLE; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = liointc_set_type; + + gc->mask_cache = 0xffffffff; + priv->gc = gc; + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + if (parent_irq[i] <= 0) + continue; + + priv->handler[i].priv = priv; + irq_set_chained_handler_and_data(parent_irq[i], + liointc_chained_handle_irq, &priv->handler[i]); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init); +IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init); From patchwork Wed Mar 25 02:28:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1261112 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=flygoat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.a=rsa-sha256 header.s=mail header.b=U3fLccN5; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nBzB0mDvz9sSG for ; Wed, 25 Mar 2020 13:34:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727320AbgCYCel (ORCPT ); Tue, 24 Mar 2020 22:34:41 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17873 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727268AbgCYCel (ORCPT ); Tue, 24 Mar 2020 22:34:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1585103520; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=ptczmo4zdH5SitmdgLb31uq0UnwEPiyg4NeT2CVppvU=; b=U3fLccN5PpEN49FIfATzRjJH80dFiWVFbyS9eIHRHxNtbZ3rggAtvKp3FwKs8mAG q94WljlhqdA05aYmCnLeye4R9VeNNfC8rIUJCz1DVLO3TjEnKUr+4lqC1fmktHctRVd uDRtf6qVragd+LeKaRrQvbOMick44tJkpo0Qj5Yk= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1585103517027656.9551692102889; Wed, 25 Mar 2020 10:31:57 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Marc Zyngier , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Jonathan Corbet , Paul Cercueil , John Crispin , Matthias Brugger , Jean Delvare , "David S. Miller" , Mauro Carvalho Chehab , Jonathan Cameron , Greg Kroah-Hartman , Andy Shevchenko , Krzysztof Kozlowski , Andi Kleen , Geert Uytterhoeven , Kees Cook , Miquel Raynal , "H. Nikolaus Schaller" , "Eric W. Biederman" , Yinglu Yang , Tiezhu Yang , Allison Randal , Paul Burton , Manuel Lauss , Bartlomiej Zolnierkiewicz , Serge Semin , Matt Redfearn , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-ide@vger.kernel.org Message-ID: <20200325022916.106641-4-jiaxun.yang@flygoat.com> Subject: [PATCH v7 02/12] irqchip: loongson-liointc: Workaround LPC IRQ Errata Date: Wed, 25 Mar 2020 10:28:19 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200325022916.106641-1-jiaxun.yang@flygoat.com> References: <20200325022916.106641-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org The 1.0 version of that controller has a bug that status bit of LPC IRQ sometimes doesn't get set correctly. So we can always blame LPC IRQ when spurious interrupt happens at the parent interrupt line which LPC IRQ supposed to route to. Signed-off-by: Jiaxun Yang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Reviewed-by: Marc Zyngier --- drivers/irqchip/irq-loongson-liointc.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index 18de2c09ece4..7d2339e638db 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -32,6 +32,8 @@ #define LIOINTC_SHIFT_INTx 4 +#define LIOINTC_ERRATA_IRQ 10 + struct liointc_handler_data { struct liointc_priv *priv; u32 parent_int_map; @@ -41,6 +43,7 @@ struct liointc_priv { struct irq_chip_generic *gc; struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; u8 map_cache[LIOINTC_CHIP_IRQ]; + bool have_lpc_irq_errata; }; static void liointc_chained_handle_irq(struct irq_desc *desc) @@ -54,8 +57,15 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); - if (!pending) - spurious_interrupt(); + if (!pending) { + /* Always blame LPC IRQ if we have that bug */ + if (handler->priv->have_lpc_irq_errata && + (handler->parent_int_map & ~gc->mask_cache & + BIT(LIOINTC_ERRATA_IRQ))) + pending = BIT(LIOINTC_ERRATA_IRQ); + else + spurious_interrupt(); + } while (pending) { int bit = __ffs(pending); From patchwork Wed Mar 25 02:28:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1261114 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=flygoat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.a=rsa-sha256 header.s=mail header.b=aow0CiwG; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nBzv2r7wz9sST for ; Wed, 25 Mar 2020 13:35:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727376AbgCYCfT (ORCPT ); Tue, 24 Mar 2020 22:35:19 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17890 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727268AbgCYCfT (ORCPT ); Tue, 24 Mar 2020 22:35:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1585103595; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=q3522WmCMcchsrcIlYC+4bPpCWTc6GzKb+1Lr0erI0g=; b=aow0CiwG/hBJpTXuR4X2GcdsbXYILhWzbR25pZEkKL1dnOVaDH2BRyez6/6r2dd2 GjGJmQMVISsaLIHz0qfSOU8kCoB0KQMx+2rbtyEPtJLbhSVAONkI3SkFlJ/VTIJkPCT 907zcU85fxxghl04s5c2HjtqFr3yGfNUyXzMVASQ= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1585103593296580.9934269828649; Wed, 25 Mar 2020 10:33:13 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Rob Herring , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Jonathan Corbet , Paul Cercueil , John Crispin , Matthias Brugger , Jean Delvare , "David S. Miller" , Mauro Carvalho Chehab , Jonathan Cameron , Greg Kroah-Hartman , Andy Shevchenko , Krzysztof Kozlowski , "H. Nikolaus Schaller" , Miquel Raynal , Andi Kleen , "Eric W. Biederman" , Yinglu Yang , Tiezhu Yang , Allison Randal , Bartlomiej Zolnierkiewicz , Paul Burton , Manuel Lauss , Serge Semin , Matt Redfearn , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-ide@vger.kernel.org Message-ID: <20200325022916.106641-6-jiaxun.yang@flygoat.com> Subject: [PATCH v7 03/12] dt-bindings: interrupt-controller: Add Loongson LIOINTC Date: Wed, 25 Mar 2020 10:28:21 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200325022916.106641-1-jiaxun.yang@flygoat.com> References: <20200325022916.106641-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org Document Loongson I/O Interrupt controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen --- .../loongson,liointc.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml new file mode 100644 index 000000000000..9c6b91fee477 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson Local I/O Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips as the primary + package interrupt controller which can route local I/O interrupt to interrupt lines + of cores. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: loongson,liointc-1.0 + - const: loongson,liointc-1.0a + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + description: + Interrupt source of the CPU interrupts. + minItems: 1 + maxItems: 4 + + interrupt-names: + description: List of names for the parent interrupts. + items: + - const: int0 + - const: int1 + - const: int2 + - const: int3 + minItems: 1 + maxItems: 4 + + '#interrupt-cells': + const: 2 + + 'loongson,parent_int_map': + description: | + This property points how the children interrupts will be mapped into CPU + interrupt lines. Each cell refers to a parent interrupt line from 0 to 3 + and each bit in the cell refers to a children interrupt fron 0 to 31. + If a CPU interrupt line didn't connected with liointc, then keep it's + cell with zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 4 + maxItems: 4 + + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - 'loongson,parent_int_map' + + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + +...