From patchwork Sat Mar 21 02:42:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=w1qU6mWX; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLM5vQZz9sR4 for ; Sat, 21 Mar 2020 13:42:51 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 38BD93949F21; Sat, 21 Mar 2020 02:42:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38BD93949F21 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1584758559; bh=XymS70yOAHTMd5+Qp3JH+DAuK12wC1UfeGOx7aez+eo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=w1qU6mWXjCEkE049Y2fzi3kBqIOceoA5yqEsGJ1Q941OYrPxIGyFdvHMnUQuuaKqp dbvxgxUEfhOEIlt5cnOwRmWMp6Jm57nE4oWcrXYlG9R/pzapmyvk+Zt37G+UBpAyh0 U/7/8H4kEwilivrYZ2d/7whGkY+xtW/YdSnwEbY0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by sourceware.org (Postfix) with ESMTPS id 8F77938A1031 for ; Sat, 21 Mar 2020 02:42:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8F77938A1031 Received: by mail-pj1-x1032.google.com with SMTP id nu11so3304209pjb.1 for ; Fri, 20 Mar 2020 19:42:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XymS70yOAHTMd5+Qp3JH+DAuK12wC1UfeGOx7aez+eo=; b=Opk3J9grAaqqsCVLwVTFwqqlxuO2ri4xLtHWGPujTFQdEzE+/vhNA+l4edfaFIQx9g 6MBXDaKNHVPVHDVtb0dikFW2LO29MSnTvWBw9yw01tw+c1fBAtGsHTGRPEyR8UK9VXSU xuafMOC+srBpg2m+N3r5XiwGU8SDBFjS5YUmSF2hXIqLLnVihGog03JSbn5Mh9vCjx+h V+eKquBq0DhSVEPWSNbH97fAON62H7DiUyk2f3kN/lwLrwTp5EgRPRPJ6hI5rQh+cHLj f0SR1hbKmIbNZmcvlTOMfrUdIvAfSrCZspK7abGsvPx9OE2WSlV1Tmg+bF6mzrC6TJEL sFDQ== X-Gm-Message-State: ANhLgQ1c8hxQSBgcFsbGg+zAeC7h6SFuEg7vQBPzEvxAq0q9fgYy8900 zhzNlISbn8fA0fPRXuQjvtJYoPHVRl0= X-Google-Smtp-Source: ADFU+vs4+GlyPeMEyTsElg5I9f6z66tG3ktZt2mO8JYZUPFUogBdDuTUj6e0Egv5ft4wEpvaXZ1mqA== X-Received: by 2002:a17:902:e905:: with SMTP id k5mr10698036pld.274.1584758555059; Fri, 20 Mar 2020 19:42:35 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:34 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 1/9] aarch64: Accept 0 as first argument to compares Date: Fri, 20 Mar 2020 19:42:23 -0700 Message-Id: <20200321024231.13778-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" While cmp (extended register) and cmp (immediate) uses , cmp (shifted register) uses . So we can perform cmp xzr, x0. For ccmp, we only have as an input. * config/aarch64/aarch64.md (cmp): For operand 0, use aarch64_reg_or_zero. Shuffle reg/reg to last alternative and accept Z. (@ccmpcc): For operand 0, use aarch64_reg_or_zero and Z. (@ccmpcc_rev): Likewise. --- gcc/config/aarch64/aarch64.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c7c4d1dd519..b9ae51e48dd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -502,7 +502,7 @@ [(match_operand 0 "cc_register" "") (const_int 0)]) (compare:CC_ONLY - (match_operand:GPI 2 "register_operand" "r,r,r") + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ,rZ,rZ") (match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")) (unspec:CC_ONLY [(match_operand 5 "immediate_operand")] @@ -542,7 +542,7 @@ [(match_operand 5 "immediate_operand")] UNSPEC_NZCV) (compare:CC_ONLY - (match_operand:GPI 2 "register_operand" "r,r,r") + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ,rZ,rZ") (match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn"))))] "" "@ @@ -3961,14 +3961,14 @@ (define_insn "cmp" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:GPI 0 "register_operand" "rk,rk,rk") - (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))] + (compare:CC (match_operand:GPI 0 "aarch64_reg_or_zero" "rk,rk,rkZ") + (match_operand:GPI 1 "aarch64_plus_operand" "I,J,rZ")))] "" "@ - cmp\\t%0, %1 cmp\\t%0, %1 - cmn\\t%0, #%n1" - [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] + cmn\\t%0, #%n1 + cmp\\t%0, %1" + [(set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "fcmp" From patchwork Sat Mar 21 02:42:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=rw3EhFbA; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLQ4v3cz9sR4 for ; Sat, 21 Mar 2020 13:42:54 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFBCD394B01E; Sat, 21 Mar 2020 02:42:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CFBCD394B01E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1584758560; bh=gTM44Z7v2tGSt208SIn9eNRlIeZQqggNp7ME4AXqmJk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=rw3EhFbAoI82TTlqF4d9pJVmCz3YygESTO3/yagc+Y3D2V8Sqysk3thuk1XeV7s0m Vpl5B0J4ZS9DSV7+97+VO3RMg7261c7tUXv70k7S8UZpf2zbowcs27Kwfty0JQA/ta 5tOFoq9fsy2RTZncQjq61B5fejnJKTXJ8DpYGSlc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by sourceware.org (Postfix) with ESMTPS id AA151385F02A for ; Sat, 21 Mar 2020 02:42:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org AA151385F02A Received: by mail-pg1-x530.google.com with SMTP id d17so3443488pgo.0 for ; Fri, 20 Mar 2020 19:42:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gTM44Z7v2tGSt208SIn9eNRlIeZQqggNp7ME4AXqmJk=; b=HbW3ghZ12kFioENbq7spcJEAEEyw5/Gj0nGiPq7nW5HFiRovN9dq81En7Oh3Y8YzJN VCWpDAp10WSXJ0YXHQFj7q+dv6qv+1kajBxV+Dxn4K/7ILSlhsseiMjWOh3xT7N7kpUL XDCWjq69MqkGNW/vv1yV3W098Jez81hpnhlNUH8lLimCx6h7UiOWCsx/7htSEGE5JPO+ GdfuTCir8/V4NGd9yVhJhSOmQr83XRO5jGfEW1DFxIMiqc02M07mTL0VQqxlIRanAE82 KOAbo7xHGI6WZDy4tXUtMF8j1Ic0TVOy0tl4AavwYuJ+dOF4faqHdNKEOIQ+APJivbs4 W3RQ== X-Gm-Message-State: ANhLgQ03aHAmMKSLACT8xUGA0BP2oBZa+x5sfy9EmLxgZpW8v+B0KtMy BSkKrfcYVjbWF7xU6dLVyhTPb2FFj2w= X-Google-Smtp-Source: ADFU+vs3nDKazSUB8hQZPFoGMM9Toxf3NY3EJkToaCL4v+xU64IsTlr+Ew3PVDxy8oM1jp6R6SaoPQ== X-Received: by 2002:a63:f243:: with SMTP id d3mr11383543pgk.254.1584758556269; Fri, 20 Mar 2020 19:42:36 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:35 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 2/9] aarch64: Accept zeros in add3_carryin Date: Fri, 20 Mar 2020 19:42:24 -0700 Message-Id: <20200321024231.13778-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The expander and the insn pattern did not match, leading to recognition failures in expand. * config/aarch64/aarch64.md (*add3_carryin): Accept zeros. --- gcc/config/aarch64/aarch64.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b9ae51e48dd..a996a5f1c39 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2606,16 +2606,17 @@ "" ) -;; Note that add with carry with two zero inputs is matched by cset, -;; and that add with carry with one zero input is matched by cinc. +;; While add with carry with two zero inputs will be folded to cset, +;; and add with carry with one zero input will be folded to cinc, +;; accept the zeros during initial expansion. (define_insn "*add3_carryin" [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") - (match_operand:GPI 1 "register_operand" "r")) - (match_operand:GPI 2 "register_operand" "r")))] + (match_operand:GPI 1 "aarch64_reg_or_zero" "rZ")) + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")))] "" "adc\\t%0, %1, %2" [(set_attr "type" "adc_reg")] From patchwork Sat Mar 21 02:42:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=uoQODePY; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLT2tPcz9sR4 for ; Sat, 21 Mar 2020 13:42:57 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 744B5394B02F; Sat, 21 Mar 2020 02:42:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 744B5394B02F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1584758561; bh=OrDaYLhNUgbiWdeAr1FdN2pIGdu1IlDJEX6KYM6FHD8=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=uoQODePYFkSJp0fQK45d6Cy5soM4uNIYz0WmkRgwa0IFoWD2Cy0jShmavScbgUfEy xMnoEWvC/Tt5RenaodqVFihwPGM1lDYxVoHL1A5rTuiMBWwiPgYPunCoKSRUM1wLW0 FtyzL6TOr6EsKic4H+th9OfuH/FygHRB5OQd90yA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id D2EDA3948A8F for ; Sat, 21 Mar 2020 02:42:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D2EDA3948A8F Received: by mail-pg1-x533.google.com with SMTP id a32so4015352pga.4 for ; Fri, 20 Mar 2020 19:42:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OrDaYLhNUgbiWdeAr1FdN2pIGdu1IlDJEX6KYM6FHD8=; b=aUa8OtuAcVqW1vkrngixzbFal/Jr2Y7h0Cy89AYr++JJKpdO00YRH0bWy90KJzGAH6 xtKFQ4uWwY+AghbMOaBJlNtV0mYkNtACbejbzH3bfyoEMvMgGze9OcIQ+fINJoYgy/dS ecjrx7O0LQr2fa497iIm+kGXtRpiYa95lHkbSqyq18Ct7FjIEqcU2zNqC7227GbIraAt t4Hpq3+fTm+J2OZ9sudDUbV7WsFfmgkX5KXNum4cQnEZjltyNtzf626dWoOxiUq5k7iQ OV7jDWddsOTelnkBJWaNXf1VEghK8I8cAn06k3WNzaZnBhslkz4M+9o0JighdifX9EFR 5UEw== X-Gm-Message-State: ANhLgQ2a89oiSwMP4FpnqHW9CO9aAfTLLdAZK4LYJ1m9nhxhP+jkWtPO bJR97mTzJVCnz++POLrSP2il+VNfOuU= X-Google-Smtp-Source: ADFU+vvPm3tKb8o/V8Dj4XTtx5qi8T9KUty4Agu0LG8j2jFJpSbqZB22RqsqzfZvlV+nbKuEAU9l/A== X-Received: by 2002:a63:112:: with SMTP id 18mr11350922pgb.116.1584758557504; Fri, 20 Mar 2020 19:42:37 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:36 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 3/9] aarch64: Add cmp_*_carryinC patterns Date: Fri, 20 Mar 2020 19:42:25 -0700 Message-Id: <20200321024231.13778-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Duplicate all usub_*_carryinC, but use xzr for the output when we only require the flags output. The signed versions use sign_extend instead of zero_extend for combine's benefit. These will be used shortly for TImode comparisons. * config/aarch64/aarch64.md (cmp3_carryinC): New. (*cmp3_carryinC_z1): New. (*cmp3_carryinC_z2): New. (*cmp3_carryinC): New. --- gcc/config/aarch64/aarch64.md | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a996a5f1c39..9b1c3f797f9 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3440,6 +3440,18 @@ "" ) +(define_expand "cmp3_carryinC" + [(set (reg:CC CC_REGNUM) + (compare:CC + (ANY_EXTEND: + (match_operand:GPI 0 "register_operand")) + (plus: + (ANY_EXTEND: + (match_operand:GPI 1 "register_operand")) + (ltu: (reg:CC CC_REGNUM) (const_int 0)))))] + "" +) + (define_insn "*usub3_carryinC_z1" [(set (reg:CC CC_REGNUM) (compare:CC @@ -3457,6 +3469,19 @@ [(set_attr "type" "adc_reg")] ) +(define_insn "*cmp3_carryinC_z1" + [(set (reg:CC CC_REGNUM) + (compare:CC + (const_int 0) + (plus: + (ANY_EXTEND: + (match_operand:GPI 0 "register_operand" "r")) + (match_operand: 1 "aarch64_borrow_operation" ""))))] + "" + "sbcs\\tzr, zr, %0" + [(set_attr "type" "adc_reg")] +) + (define_insn "*usub3_carryinC_z2" [(set (reg:CC CC_REGNUM) (compare:CC @@ -3472,6 +3497,17 @@ [(set_attr "type" "adc_reg")] ) +(define_insn "*cmp3_carryinC_z2" + [(set (reg:CC CC_REGNUM) + (compare:CC + (ANY_EXTEND: + (match_operand:GPI 0 "register_operand" "r")) + (match_operand: 1 "aarch64_borrow_operation" "")))] + "" + "sbcs\\tzr, %0, zr" + [(set_attr "type" "adc_reg")] +) + (define_insn "*usub3_carryinC" [(set (reg:CC CC_REGNUM) (compare:CC @@ -3490,6 +3526,20 @@ [(set_attr "type" "adc_reg")] ) +(define_insn "*cmp3_carryinC" + [(set (reg:CC CC_REGNUM) + (compare:CC + (ANY_EXTEND: + (match_operand:GPI 0 "register_operand" "r")) + (plus: + (ANY_EXTEND: + (match_operand:GPI 1 "register_operand" "r")) + (match_operand: 2 "aarch64_borrow_operation" ""))))] + "" + "sbcs\\tzr, %0, %1" + [(set_attr "type" "adc_reg")] +) + (define_expand "sub3_carryinV" [(parallel [(set (reg:CC_V CC_REGNUM) From patchwork Sat Mar 21 02:42:26 2020 Content-Type: text/plain; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:38 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 4/9] aarch64: Add cmp_carryinC_m2 Date: Fri, 20 Mar 2020 19:42:26 -0700 Message-Id: <20200321024231.13778-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-26.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Combine will fold immediate -1 differently than the other *cmp*_carryinC* patterns. In this case we can use adcs with an xzr input, and it occurs frequently when comparing 128-bit values to small negative constants. * config/aarch64/aarch64.md (cmp_carryinC_m2): New. --- gcc/config/aarch64/aarch64.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9b1c3f797f9..076158b0071 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3452,6 +3452,7 @@ "" ) +;; Substituting zero into the first input operand. (define_insn "*usub3_carryinC_z1" [(set (reg:CC CC_REGNUM) (compare:CC @@ -3482,6 +3483,7 @@ [(set_attr "type" "adc_reg")] ) +;; Substituting zero into the second input operand. (define_insn "*usub3_carryinC_z2" [(set (reg:CC CC_REGNUM) (compare:CC @@ -3508,6 +3510,19 @@ [(set_attr "type" "adc_reg")] ) +;; Substituting -1 into the second input operand. +(define_insn "*cmp3_carryinC_m2" + [(set (reg:CC CC_REGNUM) + (compare:CC + (neg: + (match_operand: 1 "aarch64_carry_operation" "")) + (ANY_EXTEND: + (match_operand:GPI 0 "register_operand" "r"))))] + "" + "adcs\\tzr, %0, zr" + [(set_attr "type" "adc_reg")] +) + (define_insn "*usub3_carryinC" [(set (reg:CC CC_REGNUM) (compare:CC From patchwork Sat Mar 21 02:42:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=g167kavi; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLd6hNVz9sRN for ; Sat, 21 Mar 2020 13:43:05 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC66E394D81A; Sat, 21 Mar 2020 02:42:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AC66E394D81A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1584758563; bh=U9y+21vqSzmOf9wSGetFTXWhsrwoJ1GaOO1tB2Yn/XM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=g167kavi+iFuTP6D7rmtwPsnjuC+XAYdwPzauKIglx8wxsrAEmMLYo+3Cs1+nozGM 7hNdrL4FkFF9eojXtY/gYPp+Bax4ROpj/4KIJApboLwTuJ3/HvNWP+qFlBpQLUfvCr uSvUr1tTdOT0ZW556KS/NkNUYBWrndLeEyQSj1Sc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) by sourceware.org (Postfix) with ESMTPS id 3DD64394B02D for ; Sat, 21 Mar 2020 02:42:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3DD64394B02D Received: by mail-pg1-x542.google.com with SMTP id z72so4023044pgz.3 for ; Fri, 20 Mar 2020 19:42:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9y+21vqSzmOf9wSGetFTXWhsrwoJ1GaOO1tB2Yn/XM=; b=Rh39K9vT1UOwJprBnu6CxZxdkl0Tol/dDsBITBp5G9Nu9wHFzQf9kdgQ0vXbAPmSnG SUzsBbaBfdWuZDdCidjz16gsSRFWjHctZh31MRH8lO1aJgcUNGhLPEwRtTjZiGhU6C0S NgjNftdK8SJ13qcDVoROYTz8AckGMTfdhTHwMANa74ya07LdW0BgeSgxgc1bpPtifB+q F//UwVR/JpgePJ1KvaWVBqCcXR7XRAv/LKhP3nULmfqcKVgAPgLRF/zntlmmEZwbrbsJ RMJWMJa/tsCn1z6fIhTu3+zK79BKp3C2UcuTWcPmYtxO8knbcJT07sXsxOY9vRAo/4jE qgIw== X-Gm-Message-State: ANhLgQ3rt43frbts6JVQvswz75FS+fnvO7jjTWER1ebOWP8tSQCOu9XQ RyUZk0MQBtBJFsJQo4QdZLaca9uMzkw= X-Google-Smtp-Source: ADFU+vv0NqbBBJkfPTB/oA60h5JjD1NoZ2lb919mj+JbRf1212V60d2bY6LB/9Tb7+gCi+0wgUaCDQ== X-Received: by 2002:a62:19d8:: with SMTP id 207mr13335790pfz.278.1584758559985; Fri, 20 Mar 2020 19:42:39 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:39 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 5/9] aarch64: Provide expander for sub3_compare1 Date: Fri, 20 Mar 2020 19:42:27 -0700 Message-Id: <20200321024231.13778-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-26.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" In a couple of places we open-code a special case of this pattern into the more specific sub3_compare1_imm. Centralize that special case into an expander. * config/aarch64/aarch64.md (*sub3_compare1): Rename from sub3_compare1. (sub3_compare1): New expander. --- gcc/config/aarch64/aarch64.md | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 076158b0071..47eeba7311c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3120,7 +3120,7 @@ [(set_attr "type" "alus_imm")] ) -(define_insn "sub3_compare1" +(define_insn "*sub3_compare1" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:GPI 1 "aarch64_reg_or_zero" "rkZ") @@ -3132,6 +3132,26 @@ [(set_attr "type" "alus_sreg")] ) +(define_expand "sub3_compare1" + [(parallel + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_operand:GPI 1 "aarch64_reg_or_zero") + (match_operand:GPI 2 "aarch64_reg_or_imm"))) + (set (match_operand:GPI 0 "register_operand") + (minus:GPI (match_dup 1) (match_dup 2)))])] + "" +{ + if (aarch64_plus_immediate (operands[2], mode)) + { + emit_insn (gen_sub3_compare1_imm + (operands[0], operands[1], operands[2], + GEN_INT (-INTVAL (operands[2])))); + DONE; + } + operands[2] = force_reg (mode, operands[2]); +}) + (define_peephole2 [(set (match_operand:GPI 0 "aarch64_general_reg") (minus:GPI (match_operand:GPI 1 "aarch64_reg_or_zero") From patchwork Sat Mar 21 02:42:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Zayxe+zM; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLk0bYvz9sRN for ; Sat, 21 Mar 2020 13:43:09 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55376394D8A2; Sat, 21 Mar 2020 02:42:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 55376394D8A2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1584758566; bh=MY1AqQBy22qj+Cov3177AiuQ34gtqSLjd7svXDcrYPQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Zayxe+zM4abWzAlC3/9CsmbNUjXKfvBHWE/gOLIuTCJL2lV9bMHeWug9Nqsc6pRjD zXG5ZvE2ZzYLHJOhPbTavHKdo9DgErGLe1OZpNngQnJGidclnhiU9cqKwCE5mFCDHF uxmoaUGOh4w6hmWJ+ncMQaDZK+rmX6ILYAVCNNDU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by sourceware.org (Postfix) with ESMTPS id E2533394B02D for ; Sat, 21 Mar 2020 02:42:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E2533394B02D Received: by mail-pf1-x441.google.com with SMTP id z5so4287579pfn.5 for ; Fri, 20 Mar 2020 19:42:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MY1AqQBy22qj+Cov3177AiuQ34gtqSLjd7svXDcrYPQ=; b=IVduYSoub1EeQ5+1Km5cIWH+qae7BfCiwrXEf0dc54Rll1dgSVgKqgr7ct6GVXsKGk AJGrj0+BlPUApsxlMOJsqdVJv0mjqxaEzZ6N7lohO02fStZCIInNS+BH+LAPvN8aR+53 EVlcT1pGkJhPrCJFzUxiojey95uaKsnnPxfmJZBZImjuAApuhgZrsB5Dn89LgygYCDMK Eo2urvxQnUgQb4Gee/RzSO9fw5kD5bPx7RaQX2oy9VD6ZyJJJRGXWp5YTO1QZDC37pXx x4MI/ncWS0RFwcY8E4kBd26HZ0jW89gIUIX4rsdSd/YP/1iuZMjgJfrnrN/+vr4Kf3JR W2EQ== X-Gm-Message-State: ANhLgQ0pPm48UhjE5J4+1VKzayFbawW1X7KLaykmMX+BkYQnZ5lSrf66 nHSOkjGGquBDaLjDSReNhxFj95wCG/I= X-Google-Smtp-Source: ADFU+vtNsWiT00ixSh0zcQA+3ar8FlolvX7YnGqJn4f9ZM0PnpWv7KR9TxPO+RtxbdhyAQZOWjQtLg== X-Received: by 2002:a63:1d4:: with SMTP id 203mr11777553pgb.416.1584758561258; Fri, 20 Mar 2020 19:42:41 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:40 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 6/9] aarch64: Introduce aarch64_expand_addsubti Date: Fri, 20 Mar 2020 19:42:28 -0700 Message-Id: <20200321024231.13778-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Modify aarch64_expand_subvti into a form that handles all addition and subtraction, modulo, signed or unsigned overflow. Use expand_insn to put the operands into the proper form, and do not force values into register if not required. * config/aarch64/aarch64.c (aarch64_ti_split) New. (aarch64_addti_scratch_regs): Remove. (aarch64_subvti_scratch_regs): Remove. (aarch64_expand_subvti): Remove. (aarch64_expand_addsubti): New. * config/aarch64/aarch64-protos.h: Update to match. * config/aarch64/aarch64.md (addti3): Use aarch64_expand_addsubti. (addvti4, uaddvti4): Likewise. (subvti4, usubvti4): Likewise. (subti3): Likewise; accept immediates for operand 2. --- gcc/config/aarch64/aarch64-protos.h | 10 +- gcc/config/aarch64/aarch64.c | 136 ++++++++-------------------- gcc/config/aarch64/aarch64.md | 125 ++++++------------------- 3 files changed, 67 insertions(+), 204 deletions(-) diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index d6d668ea920..787085b24d2 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -630,16 +630,8 @@ void aarch64_reset_previous_fndecl (void); bool aarch64_return_address_signing_enabled (void); bool aarch64_bti_enabled (void); void aarch64_save_restore_target_globals (tree); -void aarch64_addti_scratch_regs (rtx, rtx, rtx *, - rtx *, rtx *, - rtx *, rtx *, - rtx *); -void aarch64_subvti_scratch_regs (rtx, rtx, rtx *, - rtx *, rtx *, - rtx *, rtx *, rtx *); -void aarch64_expand_subvti (rtx, rtx, rtx, - rtx, rtx, rtx, rtx, bool); +void aarch64_expand_addsubti (rtx, rtx, rtx, int, int, int); /* Initialize builtins for SIMD intrinsics. */ void init_aarch64_simd_builtins (void); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c90de65de12..6263897c9a0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -20241,117 +20241,61 @@ aarch64_gen_unlikely_cbranch (enum rtx_code code, machine_mode cc_mode, aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); } -/* Generate DImode scratch registers for 128-bit (TImode) addition. +/* Generate DImode scratch registers for 128-bit (TImode) add/sub. + INPUT represents the TImode input operand + LO represents the low half (DImode) of the TImode operand + HI represents the high half (DImode) of the TImode operand. */ - OP1 represents the TImode destination operand 1 - OP2 represents the TImode destination operand 2 - LOW_DEST represents the low half (DImode) of TImode operand 0 - LOW_IN1 represents the low half (DImode) of TImode operand 1 - LOW_IN2 represents the low half (DImode) of TImode operand 2 - HIGH_DEST represents the high half (DImode) of TImode operand 0 - HIGH_IN1 represents the high half (DImode) of TImode operand 1 - HIGH_IN2 represents the high half (DImode) of TImode operand 2. */ - -void -aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest, - rtx *low_in1, rtx *low_in2, - rtx *high_dest, rtx *high_in1, - rtx *high_in2) +static void +aarch64_ti_split (rtx input, rtx *lo, rtx *hi) { - *low_dest = gen_reg_rtx (DImode); - *low_in1 = gen_lowpart (DImode, op1); - *low_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_lowpart_offset (DImode, TImode)); - *high_dest = gen_reg_rtx (DImode); - *high_in1 = gen_highpart (DImode, op1); - *high_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_highpart_offset (DImode, TImode)); + *lo = simplify_gen_subreg (DImode, input, TImode, + subreg_lowpart_offset (DImode, TImode)); + *hi = simplify_gen_subreg (DImode, input, TImode, + subreg_highpart_offset (DImode, TImode)); } -/* Generate DImode scratch registers for 128-bit (TImode) subtraction. - - This function differs from 'arch64_addti_scratch_regs' in that - OP1 can be an immediate constant (zero). We must call - subreg_highpart_offset with DImode and TImode arguments, otherwise - VOIDmode will be used for the const_int which generates an internal - error from subreg_size_highpart_offset which does not expect a size of zero. - - OP1 represents the TImode destination operand 1 - OP2 represents the TImode destination operand 2 - LOW_DEST represents the low half (DImode) of TImode operand 0 - LOW_IN1 represents the low half (DImode) of TImode operand 1 - LOW_IN2 represents the low half (DImode) of TImode operand 2 - HIGH_DEST represents the high half (DImode) of TImode operand 0 - HIGH_IN1 represents the high half (DImode) of TImode operand 1 - HIGH_IN2 represents the high half (DImode) of TImode operand 2. */ - - -void -aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest, - rtx *low_in1, rtx *low_in2, - rtx *high_dest, rtx *high_in1, - rtx *high_in2) -{ - *low_dest = gen_reg_rtx (DImode); - *low_in1 = simplify_gen_subreg (DImode, op1, TImode, - subreg_lowpart_offset (DImode, TImode)); - - *low_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_lowpart_offset (DImode, TImode)); - *high_dest = gen_reg_rtx (DImode); - - *high_in1 = simplify_gen_subreg (DImode, op1, TImode, - subreg_highpart_offset (DImode, TImode)); - *high_in2 = simplify_gen_subreg (DImode, op2, TImode, - subreg_highpart_offset (DImode, TImode)); -} - -/* Generate RTL for 128-bit (TImode) subtraction with overflow. - +/* Generate RTL for 128-bit (TImode) addition or subtraction. OP0 represents the TImode destination operand 0 - LOW_DEST represents the low half (DImode) of TImode operand 0 - LOW_IN1 represents the low half (DImode) of TImode operand 1 - LOW_IN2 represents the low half (DImode) of TImode operand 2 - HIGH_DEST represents the high half (DImode) of TImode operand 0 - HIGH_IN1 represents the high half (DImode) of TImode operand 1 - HIGH_IN2 represents the high half (DImode) of TImode operand 2 - UNSIGNED_P is true if the operation is being performed on unsigned - values. */ + OP1 and OP2 represent the TImode input operands. + + Normal or Overflow behaviour is obtained via the INSN_CODE operands: + CODE_HI_LO0 is used when the low half of OP2 == 0, otherwise + CODE_LO is used on the low halves, + CODE_HI is used on the high halves. */ + void -aarch64_expand_subvti (rtx op0, rtx low_dest, rtx low_in1, - rtx low_in2, rtx high_dest, rtx high_in1, - rtx high_in2, bool unsigned_p) +aarch64_expand_addsubti (rtx op0, rtx op1, rtx op2, + int code_hi_lo0, int code_lo, int code_hi) { - if (low_in2 == const0_rtx) + rtx low_dest, low_op1, low_op2, high_dest, high_op1, high_op2; + struct expand_operand ops[3]; + + aarch64_ti_split (op1, &low_op1, &high_op1); + aarch64_ti_split (op2, &low_op2, &high_op2); + + if (low_op2 == const0_rtx) { - low_dest = low_in1; - high_in2 = force_reg (DImode, high_in2); - if (unsigned_p) - emit_insn (gen_subdi3_compare1 (high_dest, high_in1, high_in2)); - else - emit_insn (gen_subvdi_insn (high_dest, high_in1, high_in2)); + low_dest = low_op1; + code_hi = code_hi_lo0; } else { - if (aarch64_plus_immediate (low_in2, DImode)) - emit_insn (gen_subdi3_compare1_imm (low_dest, low_in1, low_in2, - GEN_INT (-INTVAL (low_in2)))); - else - { - low_in2 = force_reg (DImode, low_in2); - emit_insn (gen_subdi3_compare1 (low_dest, low_in1, low_in2)); - } - high_in2 = force_reg (DImode, high_in2); - - if (unsigned_p) - emit_insn (gen_usubdi3_carryinC (high_dest, high_in1, high_in2)); - else - emit_insn (gen_subdi3_carryinV (high_dest, high_in1, high_in2)); + low_dest = gen_reg_rtx (DImode); + create_output_operand(&ops[0], low_dest, DImode); + create_input_operand(&ops[1], low_op1, DImode); + create_input_operand(&ops[2], low_op2, DImode); + expand_insn ((insn_code)code_lo, 3, ops); } + high_dest = gen_reg_rtx (DImode); + create_output_operand(&ops[0], high_dest, DImode); + create_input_operand(&ops[1], high_op1, DImode); + create_input_operand(&ops[2], high_op2, DImode); + expand_insn ((insn_code)code_hi, 3, ops); + emit_move_insn (gen_lowpart (DImode, op0), low_dest); emit_move_insn (gen_highpart (DImode, op0), high_dest); - } /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 47eeba7311c..c3fb2292d19 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2044,30 +2044,10 @@ (match_operand:TI 2 "aarch64_reg_or_imm")))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_addti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - - if (op2_low == const0_rtx) - { - low_dest = op1_low; - if (!aarch64_pluslong_operand (op2_high, DImode)) - op2_high = force_reg (DImode, op2_high); - emit_insn (gen_adddi3 (high_dest, op1_high, op2_high)); - } - else - { - emit_insn (gen_adddi3_compareC (low_dest, op1_low, - force_reg (DImode, op2_low))); - emit_insn (gen_adddi3_carryin (high_dest, op1_high, - force_reg (DImode, op2_high))); - } - - emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest); - emit_move_insn (gen_highpart (DImode, operands[0]), high_dest); - + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_adddi3, + CODE_FOR_adddi3_compareC, + CODE_FOR_adddi3_carryin); DONE; }) @@ -2078,29 +2058,10 @@ (label_ref (match_operand 3 "" ""))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_addti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - - if (op2_low == const0_rtx) - { - low_dest = op1_low; - emit_insn (gen_adddi3_compareV (high_dest, op1_high, - force_reg (DImode, op2_high))); - } - else - { - emit_insn (gen_adddi3_compareC (low_dest, op1_low, - force_reg (DImode, op2_low))); - emit_insn (gen_adddi3_carryinV (high_dest, op1_high, - force_reg (DImode, op2_high))); - } - - emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest); - emit_move_insn (gen_highpart (DImode, operands[0]), high_dest); - + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_adddi3_compareV, + CODE_FOR_adddi3_compareC, + CODE_FOR_adddi3_carryinV); aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); DONE; }) @@ -2112,32 +2073,13 @@ (label_ref (match_operand 3 "" ""))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_addti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - - if (op2_low == const0_rtx) - { - low_dest = op1_low; - emit_insn (gen_adddi3_compareC (high_dest, op1_high, - force_reg (DImode, op2_high))); - } - else - { - emit_insn (gen_adddi3_compareC (low_dest, op1_low, - force_reg (DImode, op2_low))); - emit_insn (gen_adddi3_carryinC (high_dest, op1_high, - force_reg (DImode, op2_high))); - } - - emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest); - emit_move_insn (gen_highpart (DImode, operands[0]), high_dest); - + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_adddi3_compareC, + CODE_FOR_adddi3_compareC, + CODE_FOR_adddi3_carryinC); aarch64_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]); DONE; - }) +}) (define_insn "add3_compare0" [(set (reg:CC_NZ CC_REGNUM) @@ -2980,20 +2922,13 @@ (define_expand "subti3" [(set (match_operand:TI 0 "register_operand") (minus:TI (match_operand:TI 1 "aarch64_reg_or_zero") - (match_operand:TI 2 "register_operand")))] + (match_operand:TI 2 "aarch64_reg_or_imm")))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_subvti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - - emit_insn (gen_subdi3_compare1 (low_dest, op1_low, op2_low)); - emit_insn (gen_subdi3_carryin (high_dest, op1_high, op2_high)); - - emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest); - emit_move_insn (gen_highpart (DImode, operands[0]), high_dest); + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_subdi3, + CODE_FOR_subdi3_compare1, + CODE_FOR_subdi3_carryin); DONE; }) @@ -3004,14 +2939,10 @@ (label_ref (match_operand 3 "" ""))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_subvti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - aarch64_expand_subvti (operands[0], low_dest, op1_low, op2_low, - high_dest, op1_high, op2_high, false); - + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_subvdi_insn, + CODE_FOR_subdi3_compare1, + CODE_FOR_subdi3_carryinV); aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); DONE; }) @@ -3023,14 +2954,10 @@ (label_ref (match_operand 3 "" ""))] "" { - rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high; - - aarch64_subvti_scratch_regs (operands[1], operands[2], - &low_dest, &op1_low, &op2_low, - &high_dest, &op1_high, &op2_high); - aarch64_expand_subvti (operands[0], low_dest, op1_low, op2_low, - high_dest, op1_high, op2_high, true); - + aarch64_expand_addsubti (operands[0], operands[1], operands[2], + CODE_FOR_subdi3_compare1, + CODE_FOR_subdi3_compare1, + CODE_FOR_usubdi3_carryinC); aarch64_gen_unlikely_cbranch (LTU, CCmode, operands[3]); DONE; }) From patchwork Sat Mar 21 02:42:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:41 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 7/9] aarch64: Adjust result of aarch64_gen_compare_reg Date: Fri, 20 Mar 2020 19:42:29 -0700 Message-Id: <20200321024231.13778-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Return the entire comparison expression, not just the cc_reg. This will allow the routine to adjust the comparison code as needed for TImode comparisons. Note that some users were passing e.g. EQ to aarch64_gen_compare_reg and then using gen_rtx_NE. Pass the proper code in the first place. * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Return the final comparison for code & cc_reg. (aarch64_gen_compare_reg_maybe_ze): Likewise. (aarch64_expand_compare_and_swap): Update to match -- do not build the final comparison here, but PUT_MODE as necessary. (aarch64_split_compare_and_swap): Use prebuilt comparison. * config/aarch64/aarch64-simd.md (aarch64_cmdi): Likewise. (aarch64_cmdi): Likewise. (aarch64_cmtstdi): Likewise. * config/aarch64/aarch64-speculation.cc (aarch64_speculation_establish_tracker): Likewise. * config/aarch64/aarch64.md (cbranch4, cbranch4): Likewise. (mod3, abs2): Likewise. (cstore4, cstore4): Likewise. (cmov6, cmov6): Likewise. (movcc, movcc, movcc): Likewise. (cc): Likewise. (ffs2): Likewise. (cstorecc4): Remove redundant "". --- gcc/config/aarch64/aarch64.c | 26 +++--- gcc/config/aarch64/aarch64-simd.md | 18 ++--- gcc/config/aarch64/aarch64-speculation.cc | 5 +- gcc/config/aarch64/aarch64.md | 96 ++++++++++------------- 4 files changed, 63 insertions(+), 82 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 6263897c9a0..9e7c26a8df2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2328,7 +2328,7 @@ emit_set_insn (rtx x, rtx y) } /* X and Y are two things to compare using CODE. Emit the compare insn and - return the rtx for register 0 in the proper mode. */ + return the rtx for the CCmode comparison. */ rtx aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) { @@ -2359,7 +2359,7 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y)); } - return cc_reg; + return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); } /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */ @@ -2382,7 +2382,7 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y, cc_mode = CC_SWPmode; cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); emit_set_insn (cc_reg, t); - return cc_reg; + return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); } } @@ -18506,7 +18506,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem, newval, mod_s)); - cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode); + PUT_MODE (x, SImode); } else if (TARGET_OUTLINE_ATOMICS) { @@ -18517,7 +18518,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode, oldval, mode, newval, mode, XEXP (mem, 0), Pmode); - cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode); + PUT_MODE (x, SImode); } else { @@ -18529,13 +18531,13 @@ aarch64_expand_compare_and_swap (rtx operands[]) emit_insn (GEN_FCN (code) (rval, mem, oldval, newval, is_weak, mod_s, mod_f)); cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + x = gen_rtx_EQ (SImode, cc_reg, const0_rtx); } if (r_mode != mode) rval = gen_lowpart (mode, rval); emit_move_insn (operands[1], rval); - x = gen_rtx_EQ (SImode, cc_reg, const0_rtx); emit_insn (gen_rtx_SET (bval, x)); } @@ -18610,10 +18612,8 @@ aarch64_split_compare_and_swap (rtx operands[]) if (strong_zero_p) x = gen_rtx_NE (VOIDmode, rval, const0_rtx); else - { - rtx cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); - x = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx); - } + x = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -18626,8 +18626,7 @@ aarch64_split_compare_and_swap (rtx operands[]) { /* Emit an explicit compare instruction, so that we can correctly track the condition codes. */ - rtx cc_reg = aarch64_gen_compare_reg (NE, scratch, const0_rtx); - x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + x = aarch64_gen_compare_reg (NE, scratch, const0_rtx); } else x = gen_rtx_NE (VOIDmode, scratch, const0_rtx); @@ -18722,8 +18721,7 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, { /* Emit an explicit compare instruction, so that we can correctly track the condition codes. */ - rtx cc_reg = aarch64_gen_compare_reg (NE, cond, const0_rtx); - x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + x = aarch64_gen_compare_reg (NE, cond, const0_rtx); } else x = gen_rtx_NE (VOIDmode, cond, const0_rtx); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 24a11fb5040..69e099a2c23 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4800,10 +4800,8 @@ if (GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) { - machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]); - rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); - rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not @@ -4863,10 +4861,8 @@ if (GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) { - machine_mode mode = CCmode; - rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]); - rtx comparison = gen_rtx_ (mode, operands[1], operands[2]); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not @@ -4936,10 +4932,8 @@ && GP_REGNUM_P (REGNO (operands[1]))) { rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); - machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); - rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); - rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not diff --git a/gcc/config/aarch64/aarch64-speculation.cc b/gcc/config/aarch64/aarch64-speculation.cc index f490b64ae61..87d5964871b 100644 --- a/gcc/config/aarch64/aarch64-speculation.cc +++ b/gcc/config/aarch64/aarch64-speculation.cc @@ -162,9 +162,8 @@ aarch64_speculation_establish_tracker () rtx sp = gen_rtx_REG (DImode, SP_REGNUM); rtx tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); start_sequence (); - rtx cc = aarch64_gen_compare_reg (EQ, sp, const0_rtx); - emit_insn (gen_cstoredi_neg (tracker, - gen_rtx_NE (CCmode, cc, const0_rtx), cc)); + rtx x = aarch64_gen_compare_reg (NE, sp, const0_rtx); + emit_insn (gen_cstoredi_neg (tracker, x, XEXP (x, 0))); rtx_insn *seq = get_insns (); end_sequence (); return seq; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c3fb2292d19..0b44c814bae 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -464,12 +464,12 @@ (label_ref (match_operand 3 "" "")) (pc)))] "" - " - operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], +{ + operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], operands[2]); + operands[1] = XEXP (operands[0], 0); operands[2] = const0_rtx; - " -) +}) (define_expand "cbranch4" [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" @@ -478,12 +478,12 @@ (label_ref (match_operand 3 "" "")) (pc)))] "" - " - operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], +{ + operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], operands[2]); + operands[1] = XEXP (operands[0], 0); operands[2] = const0_rtx; - " -) +}) (define_expand "cbranchcc4" [(set (pc) (if_then_else @@ -598,9 +598,8 @@ if (val == 2) { rtx masked = gen_reg_rtx (mode); - rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); + rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); emit_insn (gen_and3 (masked, operands[1], mask)); - rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx); emit_insn (gen_csneg3_insn (operands[0], x, masked, masked)); DONE; } @@ -3634,8 +3633,7 @@ (match_operand:GPI 1 "register_operand")] "" { - rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); - rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx); + rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); emit_insn (gen_csneg3_insn (operands[0], x, operands[1], operands[1])); DONE; } @@ -4049,12 +4047,13 @@ [(match_operand:GPI 2 "register_operand") (match_operand:GPI 3 "aarch64_plus_operand")]))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + PUT_MODE (operands[1], SImode); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_expand "cstorecc4" [(set (match_operand:SI 0 "register_operand") @@ -4062,11 +4061,10 @@ [(match_operand 2 "cc_register") (match_operand 3 "const0_operand")]))] "" -"{ +{ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; -}") - +}) (define_expand "cstore4" [(set (match_operand:SI 0 "register_operand") @@ -4074,12 +4072,13 @@ [(match_operand:GPF 2 "register_operand") (match_operand:GPF 3 "aarch64_fp_compare_operand")]))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + PUT_MODE (operands[1], SImode); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_insn "aarch64_cstore" [(set (match_operand:ALLI 0 "register_operand" "=r") @@ -4165,12 +4164,12 @@ (match_operand:GPI 4 "register_operand") (match_operand:GPI 5 "register_operand")))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_expand "cmov6" [(set (match_operand:GPF 0 "register_operand") @@ -4181,12 +4180,12 @@ (match_operand:GPF 4 "register_operand") (match_operand:GPF 5 "register_operand")))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_insn "*cmov_insn" [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r") @@ -4263,15 +4262,13 @@ (match_operand:ALLI 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4282,15 +4279,13 @@ (match_operand:GPF 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4301,15 +4296,13 @@ (match_operand:GPF 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4320,15 +4313,13 @@ (match_operand:GPI 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4837,8 +4828,7 @@ (match_operand:GPI 1 "register_operand")] "" { - rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx); - rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); + rtx x = aarch64_gen_compare_reg (NE, operands[1], const0_rtx); emit_insn (gen_rbit2 (operands[0], operands[1])); emit_insn (gen_clz2 (operands[0], operands[0])); From patchwork Sat Mar 21 02:42:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:43 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 8/9] aarch64: Implement TImode comparisons Date: Fri, 20 Mar 2020 19:42:30 -0700 Message-Id: <20200321024231.13778-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-27.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Use ccmp to perform all TImode comparisons branchless. * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Expand all of the comparisons for TImode, not just NE. * config/aarch64/aarch64.md (cbranchti4, cstoreti4): New. --- gcc/config/aarch64/aarch64.c | 130 ++++++++++++++++++++++++++++++---- gcc/config/aarch64/aarch64.md | 28 ++++++++ 2 files changed, 144 insertions(+), 14 deletions(-) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9e7c26a8df2..6ae0ea388ce 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2333,32 +2333,134 @@ rtx aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) { machine_mode cmp_mode = GET_MODE (x); - machine_mode cc_mode; rtx cc_reg; if (cmp_mode == TImode) { - gcc_assert (code == NE); - - cc_mode = CCmode; - cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); - rtx x_lo = operand_subword (x, 0, 0, TImode); - rtx y_lo = operand_subword (y, 0, 0, TImode); - emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x_lo, y_lo)); - rtx x_hi = operand_subword (x, 1, 0, TImode); - rtx y_hi = operand_subword (y, 1, 0, TImode); - emit_insn (gen_ccmpccdi (cc_reg, cc_reg, x_hi, y_hi, - gen_rtx_EQ (cc_mode, cc_reg, const0_rtx), - GEN_INT (AARCH64_EQ))); + struct expand_operand ops[2]; + rtx y_lo, y_hi, tmp; + + if (CONST_INT_P (y)) + { + HOST_WIDE_INT y_int = INTVAL (y); + + y_lo = y; + switch (code) + { + case EQ: + case NE: + /* For equality, IOR the two halves together. If this gets + used for a branch, we expect this to fold to cbz/cbnz; + otherwise it's no larger than cmp+ccmp below. Beware of + the compare-and-swap post-reload split and use cmp+ccmp. */ + if (y_int == 0 && can_create_pseudo_p ()) + { + tmp = gen_reg_rtx (DImode); + emit_insn (gen_iordi3 (tmp, x_hi, x_lo)); + emit_insn (gen_cmpdi (tmp, const0_rtx)); + cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + goto done; + } + break; + + case LE: + case GT: + /* Add 1 to Y to convert to LT/GE, which avoids the swap and + keeps the constant operand. The cstoreti and cbranchti + operand predicates require aarch64_plus_operand, which + means this increment cannot overflow. */ + y_lo = gen_int_mode (++y_int, DImode); + code = (code == LE ? LT : GE); + /* fall through */ + + case LT: + case GE: + /* Check only the sign bit using tst, or fold to tbz/tbnz. */ + if (y_int == 0) + { + cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); + tmp = gen_rtx_AND (DImode, x_hi, GEN_INT (INT64_MIN)); + tmp = gen_rtx_COMPARE (CC_NZmode, tmp, const0_rtx); + emit_set_insn (cc_reg, tmp); + code = (code == LT ? NE : EQ); + goto done; + } + break; + + default: + break; + } + y_hi = (y_int < 0 ? constm1_rtx : const0_rtx); + } + else + { + y_lo = operand_subword (y, 0, 0, TImode); + y_hi = operand_subword (y, 1, 0, TImode); + } + + switch (code) + { + case LEU: + case GTU: + case LE: + case GT: + std::swap (x_lo, y_lo); + std::swap (x_hi, y_hi); + code = swap_condition (code); + break; + + default: + break; + } + + /* Emit cmpdi, forcing operands into registers as required. */ + create_input_operand (&ops[0], x_lo, DImode); + create_input_operand (&ops[1], y_lo, DImode); + expand_insn (CODE_FOR_cmpdi, 2, ops); + + cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + switch (code) + { + case EQ: + case NE: + /* For EQ, (x_lo == y_lo) && (x_hi == y_hi). */ + emit_insn (gen_ccmpccdi (cc_reg, cc_reg, x_hi, y_hi, + gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx), + GEN_INT (AARCH64_EQ))); + break; + + case LTU: + case GEU: + /* For LTU, (x - y), as double-word arithmetic. */ + create_input_operand (&ops[0], x_hi, DImode); + create_input_operand (&ops[1], y_hi, DImode); + expand_insn (CODE_FOR_ucmpdi3_carryinC, 2, ops); + /* The result is entirely within the C bit. */ + break; + + case LT: + case GE: + /* For LT, (x - y), as double-word arithmetic. */ + create_input_operand (&ops[0], x_hi, DImode); + create_input_operand (&ops[1], y_hi, DImode); + expand_insn (CODE_FOR_scmpdi3_carryinC, 2, ops); + /* The result is within the N and V bits -- normal LT/GE. */ + break; + + default: + gcc_unreachable (); + } } else { - cc_mode = SELECT_CC_MODE (code, x, y); + machine_mode cc_mode = SELECT_CC_MODE (code, x, y); cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y)); } + + done: return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 0b44c814bae..284a8038e28 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -471,6 +471,20 @@ operands[2] = const0_rtx; }) +(define_expand "cbranchti4" + [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" + [(match_operand:TI 1 "register_operand") + (match_operand:TI 2 "aarch64_plus_operand")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "" +{ + operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], + operands[2]); + operands[1] = XEXP (operands[0], 0); + operands[2] = const0_rtx; +}) + (define_expand "cbranch4" [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" [(match_operand:GPF 1 "register_operand") @@ -4055,6 +4069,20 @@ operands[3] = const0_rtx; }) +(define_expand "cstoreti4" + [(set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand:TI 2 "register_operand") + (match_operand:TI 3 "aarch64_plus_operand")]))] + "" +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + PUT_MODE (operands[1], SImode); + operands[2] = XEXP (operands[1], 0); + operands[3] = const0_rtx; +}) + (define_expand "cstorecc4" [(set (match_operand:SI 0 "register_operand") (match_operator 1 "aarch64_comparison_operator_mode" From patchwork Sat Mar 21 02:42:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1259285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Z8MoFNCe; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48klLx3NtXz9sR4 for ; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c83sm6772831pfb.44.2020.03.20.19.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 19:42:44 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 9/9] aarch64: Implement absti2 Date: Fri, 20 Mar 2020 19:42:31 -0700 Message-Id: <20200321024231.13778-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200321024231.13778-1-richard.henderson@linaro.org> References: <20200321024231.13778-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-26.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Henderson via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: Richard Henderson Cc: richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" * config/aarch64/aarch64.md (absti2): New. --- gcc/config/aarch64/aarch64.md | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 284a8038e28..7a112f89487 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3653,6 +3653,36 @@ } ) +(define_expand "absti2" + [(match_operand:TI 0 "register_operand") + (match_operand:TI 1 "register_operand")] + "" + { + rtx lo_op1 = gen_lowpart (DImode, operands[1]); + rtx hi_op1 = gen_highpart (DImode, operands[1]); + rtx lo_tmp = gen_reg_rtx (DImode); + rtx hi_tmp = gen_reg_rtx (DImode); + rtx x; + + emit_insn (gen_negdi_carryout (lo_tmp, lo_op1)); + emit_insn (gen_negvdi_carryinV (hi_tmp, hi_op1)); + + rtx cc = gen_rtx_REG (CC_NZmode, CC_REGNUM); + + x = gen_rtx_GE (VOIDmode, cc, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (DImode, x, lo_tmp, lo_op1); + emit_insn (gen_rtx_SET (lo_tmp, x)); + + x = gen_rtx_GE (VOIDmode, cc, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (DImode, x, hi_tmp, hi_op1); + emit_insn (gen_rtx_SET (hi_tmp, x)); + + emit_move_insn (gen_lowpart (DImode, operands[0]), lo_tmp); + emit_move_insn (gen_highpart (DImode, operands[0]), hi_tmp); + DONE; + } +) + (define_insn "neg2" [(set (match_operand:GPI 0 "register_operand" "=r,w") (neg:GPI (match_operand:GPI 1 "register_operand" "r,w")))]