From patchwork Fri Mar 20 08:52:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1258712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48kHbk2cRTz9sRf for ; Fri, 20 Mar 2020 19:52:48 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A3B93947C11; Fri, 20 Mar 2020 08:52:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 14AD13945C34 for ; Fri, 20 Mar 2020 08:52:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 14AD13945C34 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6F8B30E; Fri, 20 Mar 2020 01:52:41 -0700 (PDT) Received: from [10.57.19.247] (unknown [10.57.19.247]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F34413F305; Fri, 20 Mar 2020 01:56:43 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" From: "Andre Vieira (lists)" Subject: [PATCH][GCC][Arm]: Revert changes to {get, set}_fpscr Message-ID: Date: Fri, 20 Mar 2020 08:52:40 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 Content-Language: en-US X-Spam-Status: No, score=-24.4 required=5.0 tests=BAYES_00, GARBLED_BODY, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, MVE made changes to {get,set}_fpscr to enable the compiler to optimize unneccesary gets and sets when using these for intrinsics that use and/or write the carry bit.  However, these actually get and set the full FPSCR register and are used by fp env intrinsics to modify the fp context.  So MVE should not be using these. This fixes regressions for gcc.dg/atomic/c11-atomic-exec-5.c Bootstrapped and tested arm-linux-gnueabihf. Is this OK for trunk? gcc/ChangeLog: 2020-03-20  Andre Vieira          * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...         (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.         * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e76609f79418af38b70746336dd43592a1dc8713..f0b1f465de4b63d624510783576700519044717d 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,7 +170,6 @@ (define_c_enum "unspec" [ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. - UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. ]) @@ -217,6 +216,7 @@ (define_c_enum "unspecv" [ VUNSPEC_SLX ; Represent a store-register-release-exclusive. VUNSPEC_LDA ; Represent a store-register-acquire. VUNSPEC_STL ; Represent a store-register-release. + VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index eb6ae7bea7927c666f36219797d54c0127001bc1..dfb1031431af3ec87d9cccdee35db04e0adffe04 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2096,9 +2096,8 @@ (define_insn "3" ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" - [(set (reg:SI VFPCC_REGNUM) - (unspec_volatile:SI - [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] + VUNSPEC_SET_FPSCR)] "TARGET_VFP_BASE" "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" [(set_attr "type" "mrs")]) @@ -2106,7 +2105,7 @@ (define_insn "set_fpscr" ;; Read Floating-point Status and Control Register. (define_insn "get_fpscr" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))] + (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] "TARGET_VFP_BASE" "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" [(set_attr "type" "mrs")])