From patchwork Fri Mar 20 08:48:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1258710 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48kHVR1RzJz9sRf for ; Fri, 20 Mar 2020 19:48:14 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0072039450FB; Fri, 20 Mar 2020 08:48:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id BAC7D3875DFD for ; Fri, 20 Mar 2020 08:48:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org BAC7D3875DFD Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70F9F30E; Fri, 20 Mar 2020 01:48:09 -0700 (PDT) Received: from [10.57.19.247] (unknown [10.57.19.247]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AF38F3F305; Fri, 20 Mar 2020 01:52:11 -0700 (PDT) Subject: [PATCH 1/2][GCC][Arm]: Fix MVE move from GPR -> GPR From: "Andre Vieira (lists)" To: "gcc-patches@gcc.gnu.org" References: <1df1a9b3-c8db-2492-bc80-bc92880755aa@arm.com> Message-ID: <285ba63f-aad4-2701-d0ef-43be0f7106f7@arm.com> Date: Fri, 20 Mar 2020 08:48:07 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <1df1a9b3-c8db-2492-bc80-bc92880755aa@arm.com> Content-Language: en-US X-Spam-Status: No, score=-24.4 required=5.0 tests=BAYES_00, GARBLED_BODY, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch fixes the pattern mve_mov for the case where both MVE vectors are in R registers and the move does not get optimized away.  I use the same approach as we do for NEON, where we use four register moves. Bootstrapped on arm-linux-gnueabihf and ran mve testsuite on arm-none-eabi. Is this OK for trunk? gcc/ChangeLog: 2020-03-20  Andre Vieira          * config/arm/mve.md (mve_mov): Fix R->R case. gcc/testsuite/ChangeLog: 2020-03-**  Andre Vieira          * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3cdb2e71cf04d45d220f6667646d226c8015659a..3015df7a6af0ab50e0ae47894f63597ada8566c5 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -295,7 +295,7 @@ (define_insn "*mve_mov" else return "vldrb.8 %q0, %E1"; case 5: - return output_move_neon (operands); + return output_move_quad (operands); case 7: return "vstrb.8 %q1, %E0"; default: @@ -303,7 +303,7 @@ (define_insn "*mve_mov" return ""; } } - [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store") + [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store") (set_attr "length" "4,8,8,4,8,8,4,4") (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c new file mode 100644 index 0000000000000000000000000000000000000000..791b8529a052dfca42e12648b6967eca3a2a985e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2 -mfloat-abi=softfp" } */ + +#include "arm_mve.h" + +extern int bar (float16x8_t, float16_t); + +extern void foobar (float16_t); + +int +foo (float16x8_t a, float16_t b) +{ + foobar (b); + return bar (a, b); +} + From patchwork Fri Mar 20 08:49:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1258711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48kHX66hyVz9sSN for ; Fri, 20 Mar 2020 19:49:42 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 036E33947421; Fri, 20 Mar 2020 08:49:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 46D7F3877031 for ; Fri, 20 Mar 2020 08:49:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 46D7F3877031 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F12C230E; Fri, 20 Mar 2020 01:49:37 -0700 (PDT) Received: from [10.57.19.247] (unknown [10.57.19.247]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1C3D33F305; Fri, 20 Mar 2020 01:53:39 -0700 (PDT) Subject: [PATCH 2/2][GCC][Arm]: Fix testisms for MVE testsuite From: "Andre Vieira (lists)" To: "gcc-patches@gcc.gnu.org" References: <1df1a9b3-c8db-2492-bc80-bc92880755aa@arm.com> Message-ID: Date: Fri, 20 Mar 2020 08:49:36 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <1df1a9b3-c8db-2492-bc80-bc92880755aa@arm.com> Content-Language: en-US X-Spam-Status: No, score=-24.1 required=5.0 tests=BAYES_00, GARBLED_BODY, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch fixes some testism where -mfpu=auto was missing or where we could end up with -mfloat-abi=hard and soft on the same command-line. Tested on arm-none-eabi. Is this OK for trunk? gcc/testsuite/ChangeLog: 2020-03-20  Andre Vieira          * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms.         * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.         * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.         * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c index 17ba616c041378b88463cb7ef150b70b2e7b95ad..d552fbdffee2ac57092e20ce6a02ab3a4b4bd367 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c index 7b877c4a90c506343d6b4edb750ba06ce3d7a68d..e40b82ec161ac4155c3e38fad1438c296db76486 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb" } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c index 85fbb5767edc3c25ceb4d6da780d47afa1ee416c..e04cb61043859b2c5484f97d1450ef97076d6a2d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c index 23b3683ae559b3f7bf6c3ad11c4070ad2ddb9387..f52c3627551750cbaaf54f0ac94020db7a92c6ca 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb -mfpu=auto" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c index 8f7fa348d130e8456d5300ac25821fd96f9d5a97..1f249ca885faeea58951a702d090d49af525eeed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb" } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { "" } } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb -mfpu=auto" } */ int foo1 (int value) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c index 7c38d3102d26d8d7f6358258018a993df8298b4d..03347d494b9a78c514316e560ee103fcd5ded8b8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ float diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c index 773c8449edbe467dcdfcee260a9a04e2d4a5b0e7..f6291b7ccf7fd7320ceae5c86bc91c42a12fba78 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */ double diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c index ac51f7ff4be1d9a24c9a8657541b2d2273539d50..eac2c845972a828a9b8046c4c644afda8f4b5013 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c index d41900c20ea533519bc0da729ef01bf0925083fa..d5319014d318f72b3b31961edd00a91ee96abb5c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c index f02dd8b5f15e86356512d0f2c02d0f59a53c6d4b..bf39fc6837628c1ac0baef594cc824522ae052e2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c index dfe08b9c9f53db4ee3ae62e1a9eec863675fcba8..3a63b590fcba3984f84f8c9cbb8f62f8eb3d0459 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c index cb96eb8d3ab5ced754ebf12724c0b692be114fd3..e15b10bcbdc185a7fffafd3bba11ae720f9139fe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" @@ -10,7 +11,7 @@ int32x4_t value3; int64x2_t value4; int8x16_t -foo8 () +foo8 (void) { int8x16_t b = value1; return b; @@ -21,7 +22,7 @@ foo8 () /* { dg-final { scan-assembler "vldrb.8*" } } */ int16x8_t -foo16 () +foo16 (void) { int16x8_t b = value2; return b; @@ -32,7 +33,7 @@ foo16 () /* { dg-final { scan-assembler "vldrb.8*" } } */ int32x4_t -foo32 () +foo32 (void) { int32x4_t b = value3; return b; @@ -43,7 +44,7 @@ foo32 () /* { dg-final { scan-assembler "vldrb.8" } } */ int64x2_t -foo64 () +foo64 (void) { int64x2_t b = value4; return b; diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c index 32f589aad528314b7f2bf4cb680ab70b66a19514..a7f66ce9bea88de7b967b693f51970784231f477 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c index 1957d384ca0b5a273d8182e77b592d732694690c..6e2e768146767b623de080f4025ed264678abf17 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c index 0561178a8d3b5c1f4952da62aa6a2c1692fea849..d6dba65167a6a69565b87a2172e9a14097ec4f40 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c index 8b4f4cbb8cde8372044fa39dba96fdf29fd9eeb8..70091970de8cc9f048a8f9526825789b9de38500 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ -/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */ #include "arm_mve.h" diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c index 6c3eda56a17f034f362eb5b7302a8fac5312d2c5..2fe8c5f06977caa0b3ac6fad144a5cdc55ff5b62 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ -/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ #include "arm_mve.h"