From patchwork Fri Dec 1 06:13:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 843369 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="loJzJoIG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yp3rk5rKvz9t2x for ; Fri, 1 Dec 2017 17:14:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751946AbdLAGN7 (ORCPT ); Fri, 1 Dec 2017 01:13:59 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:48443 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752679AbdLAGN2 (ORCPT ); Fri, 1 Dec 2017 01:13:28 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB16Crgh015887; Fri, 1 Dec 2017 00:12:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512108773; bh=wr1b0oi/w/zZImFcYANuwmLJf6SaXNDY8uNYW1dFsx0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=loJzJoIG06dgXGUURQKZO10fdxT4Vy2jEOG6JOnGLaP8ANOlYie+OdXWBjQsx9Gb0 CbA/tRfib6YAeqnEtMgzG0I8JUgxH/DlTVI54DzBy0lry/sJPmAzxVqHNCcC4n1U7V AqFtMW7zkOGk3xFekzmec/OnnQ9F8DMF+GRF2sjA= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16Crox030299; Fri, 1 Dec 2017 00:12:53 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 1 Dec 2017 00:12:53 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 1 Dec 2017 00:12:53 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CjTb013757; Fri, 1 Dec 2017 00:12:50 -0600 From: Vignesh R To: Bjorn Helgaas , Rob Herring , Tony Lindgren , Chris Welch CC: Kishon Vijay Abraham I , Lorenzo Pieralisi , , , , , , Vignesh R Subject: [PATCH 1/4] pci: dwc: pci-dra7xx: Enable errata i870 for both EP and RC mode Date: Fri, 1 Dec 2017 11:43:08 +0530 Message-ID: <20171201061311.16691-2-vigneshr@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171201061311.16691-1-vigneshr@ti.com> References: <20171201061311.16691-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Errata i870 is applicable in both EP and RC mode. Therefore rename function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a common place. So, that errata workaround is applied for both modes of operation. Reported-by: Chris Welch Signed-off-by: Vignesh R --- drivers/pci/dwc/pci-dra7xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index e77a4ceed74c..53f721d1cc40 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -546,7 +546,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { }; /* - * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 + * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 * @dra7xx: the dra7xx device where the workaround should be applied * * Access to the PCIe slave port that are not 32-bit aligned will result @@ -556,7 +556,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { * * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. */ -static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) +static int dra7xx_pcie_unaligned_memaccess(struct device *dev) { int ret; struct device_node *np = dev->of_node; @@ -703,6 +703,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2) dra7xx->link_gen = 2; + ret = dra7xx_pcie_unaligned_memaccess(dev); + if (ret) + goto err_gpio; + switch (mode) { case DW_PCIE_RC_TYPE: dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, @@ -715,10 +719,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP); - ret = dra7xx_pcie_ep_unaligned_memaccess(dev); - if (ret) - goto err_gpio; - ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio; From patchwork Fri Dec 1 06:13:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 843367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="BZpJZLHk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yp3rT1DKgz9t3x for ; Fri, 1 Dec 2017 17:14:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752676AbdLAGOA (ORCPT ); Fri, 1 Dec 2017 01:14:00 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:48441 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752658AbdLAGN2 (ORCPT ); Fri, 1 Dec 2017 01:13:28 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB16Cvrc015895; Fri, 1 Dec 2017 00:12:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512108777; bh=V5xHLwrpnxJREH5iggGobOCm6vTl4MC9kwSJOSKNOnQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BZpJZLHkC/2VUf4AVGJG8Mhs0Gq5fk6roCDgU4fDG7biYMz7hBQdHMg496Sw4I/oi ae4DRdwHKJ3QzcCfs73b8aRfl5O/b8gY1276df+SXOh8TEpZOZaXzuBSsEnFC2nN5r IcT/sv6Es7bEAzOPH5BOqVrF8NrGKmVlNnW4td9o= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CvbG021775; Fri, 1 Dec 2017 00:12:57 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 1 Dec 2017 00:12:56 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 1 Dec 2017 00:12:56 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CjTc013757; Fri, 1 Dec 2017 00:12:53 -0600 From: Vignesh R To: Bjorn Helgaas , Rob Herring , Tony Lindgren , Chris Welch CC: Kishon Vijay Abraham I , Lorenzo Pieralisi , , , , , , Vignesh R Subject: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add bindings for unaligned access in host mode Date: Fri, 1 Dec 2017 11:43:09 +0530 Message-ID: <20171201061311.16691-3-vigneshr@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171201061311.16691-1-vigneshr@ti.com> References: <20171201061311.16691-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update device tree binding documentation of TI's dra7xx PCI controller for enabling unaligned mem access as applicable not just in EP mode but in host mode as well. Signed-off-by: Vignesh R Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 7f7af3044016..452fe48c4fdd 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -26,6 +26,11 @@ HOST MODE ranges, interrupt-map-mask, interrupt-map : as specified in ../designware-pcie.txt + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. DEVICE MODE =========== From patchwork Fri Dec 1 06:13:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 843370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="HqbaQu2y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yp3rm3dtHz9t2x for ; Fri, 1 Dec 2017 17:14:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752688AbdLAGN2 (ORCPT ); Fri, 1 Dec 2017 01:13:28 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:56460 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752647AbdLAGN0 (ORCPT ); Fri, 1 Dec 2017 01:13:26 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB16D12G000595; Fri, 1 Dec 2017 00:13:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512108781; bh=TSFnK7Cfzxp9JSkebwbdYIeGPTKlMVMSd0523nXsesM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HqbaQu2ysjVfkDkwKKNUfX9hsdJCm+zJCrsGMBK+mULYrww4A5bZ47719JDeFDXap ipyIqMxjxNh/Rf8zAhIPKzpvqxEotIerA8GcC+mjXDOThrRAUlMf3Habahk91Mkh4W ReYmZgepgSyCM8kpUT5FFeaG4j9HC3+OKzwC4YgQ= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16D03x021896; Fri, 1 Dec 2017 00:13:00 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 1 Dec 2017 00:13:00 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 1 Dec 2017 00:13:00 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CjTd013757; Fri, 1 Dec 2017 00:12:57 -0600 From: Vignesh R To: Bjorn Helgaas , Rob Herring , Tony Lindgren , Chris Welch CC: Kishon Vijay Abraham I , Lorenzo Pieralisi , , , , , , Vignesh R Subject: [PATCH 3/4] ARM: dts: dra7: Add DT property to allow unaligned mem access to PCIe RC Date: Fri, 1 Dec 2017 11:43:10 +0530 Message-ID: <20171201061311.16691-4-vigneshr@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171201061311.16691-1-vigneshr@ti.com> References: <20171201061311.16691-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add ti,syscon-unaligned-access property to PCIe RC nodes in order to enable workaround for errata i870 in PCIe RC mode as well. Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..e4182f4cc36d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -314,6 +314,7 @@ <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; @@ -367,6 +368,7 @@ <0 0 0 2 &pcie2_intc 2>, <0 0 0 3 &pcie2_intc 3>, <0 0 0 4 &pcie2_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; pcie2_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; From patchwork Fri Dec 1 06:13:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 843366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="tGh6bcSf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yp3r16ZD9z9t2x for ; Fri, 1 Dec 2017 17:13:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752756AbdLAGNi (ORCPT ); Fri, 1 Dec 2017 01:13:38 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:59149 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752638AbdLAGNf (ORCPT ); Fri, 1 Dec 2017 01:13:35 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB16D4vn008406; Fri, 1 Dec 2017 00:13:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512108784; bh=cJ76b5v26c4mtDWRQwgyWbzxZpdVn4l24rVvRMQhShY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tGh6bcSfQJ9Aic/oZ+igAG75SjsqNwpBWJYj/EbuFnjtngKRiPlAYHxNYv7/Qvy0E WkIqbzcpKbMtcSRssjJBeU0CwREZVqaUSnts+HINVGdhY93Tn3OX8B3epF/bX3tyP6 ENig6sB7nC0JKuHsHpKAlu5GL2T4hfDdzX8Gu01s= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16D4rV022153; Fri, 1 Dec 2017 00:13:04 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 1 Dec 2017 00:13:04 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 1 Dec 2017 00:13:04 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB16CjTe013757; Fri, 1 Dec 2017 00:13:01 -0600 From: Vignesh R To: Bjorn Helgaas , Rob Herring , Tony Lindgren , Chris Welch CC: Kishon Vijay Abraham I , Lorenzo Pieralisi , , , , , , Vignesh R Subject: [PATCH 4/4] PCI: dwc: pci-dra7xx: Fix legacy IRQ handling Date: Fri, 1 Dec 2017 11:43:11 +0530 Message-ID: <20171201061311.16691-5-vigneshr@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171201061311.16691-1-vigneshr@ti.com> References: <20171201061311.16691-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Legacy INTD IRQ handling is broken on dra7xx due to fact that driver uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size 4 which is numbered 0-3. Therefore when INTD IRQ line is used with pci-dra7xx driver following warning is seen: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:342 irq_domain_associate+0x12c/0x1c4 error: hwirq 0x4 is too large for dummy Fix this by using pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 as done in other PCIe drivers. Also, iterate over all the INTx bits and call their respective IRQ handlers before clearing the status register. Suggested-by: Bjorn Helgaas Reported-by: Chris Welch Signed-off-by: Vignesh R --- drivers/pci/dwc/pci-dra7xx.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 53f721d1cc40..59e8de34cec6 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -226,6 +226,7 @@ static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, static const struct irq_domain_ops intx_domain_ops = { .map = dra7xx_pcie_intx_map, + .xlate = pci_irqd_intx_xlate, }; static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) @@ -256,7 +257,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) struct dra7xx_pcie *dra7xx = arg; struct dw_pcie *pci = dra7xx->pci; struct pcie_port *pp = &pci->pp; - u32 reg; + unsigned long reg; + u32 virq, bit; reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); @@ -268,8 +270,11 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) case INTB: case INTC: case INTD: - generic_handle_irq(irq_find_mapping(dra7xx->irq_domain, - ffs(reg))); + for_each_set_bit(bit, ®, PCI_NUM_INTX) { + virq = irq_find_mapping(dra7xx->irq_domain, bit); + if (virq) + generic_handle_irq(virq); + } break; }