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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id p5sm23109344wrt.79.2020.02.25.03.42.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Feb 2020 03:42:50 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Cc: Ashok Reddy Soma , Joe Hershberger Subject: [PATCH] net: zynq_gem: Add cache flush to zynq_gem_free_pkt Date: Tue, 25 Feb 2020 12:42:49 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Ashok Reddy Soma Add cache flush to zynq_gem_free_pkt. This is necessary because some net routines would modify this buffer in place. The cache_invalidate in the zynq_gem_recv function would cause the modifications to the buffer to overwrite the DMA from the GEM, if cache coherency is not enabled in the GEM, the next time the buffer is in use. Flushing the cache when the buffer is no longer in use by the net functions ensures that the GEM DMA is going to take place into a clean buffer. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 5f2f87d352c4..cfd14665a70d 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -578,6 +578,7 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; struct emac_bd *first_bd; + dma_addr_t addr; if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { priv->rx_first_buf = priv->rxbd_current; @@ -592,6 +593,17 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) first_bd->status = 0xF0000000; } + /* Flush the cache for the packet as well */ +#if defined(CONFIG_PHYS_64BIT) + addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) + | ((dma_addr_t)current_bd->addr_hi << 32)); +#else + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; +#endif + flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, + ARCH_DMA_MINALIGN)); + barrier(); + if ((++priv->rxbd_current) >= RX_BUF) priv->rxbd_current = 0;