From patchwork Thu Nov 30 15:52:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 843061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ynhkW0NmGz9t2f for ; Fri, 1 Dec 2017 02:52:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LFU1/Ccr"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ynhkV5w0xzDrpc for ; Fri, 1 Dec 2017 02:52:50 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LFU1/Ccr"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LFU1/Ccr"; dkim-atps=neutral Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ynhk80572zDrpc for ; Fri, 1 Dec 2017 02:52:31 +1100 (AEDT) Received: by mail-pg0-x242.google.com with SMTP id g7so3159383pgs.0 for ; Thu, 30 Nov 2017 07:52:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5GWcj5nZ056TFYbzQMURw6vfsCuEsnqnD2FZe7adU3A=; b=LFU1/Ccrfzok9jV2KYe6t97wZupyCfCEIUhDC7vDWqzVNMvg0BQUCywboV59pxEmvk CToFvCjyvafHJcqYsrSQFWEHLkQYD0oELAWDoYuXAxnekMYqC/R3ko0rMg6wnhrA79Bu WWEw8OwZepXyHmYa5eG2buczrixYlHktmnCcNbXEKr47UYObSI1xDTIEliCjeJz3Q8xQ XbQa/d2xjrqMzF+p+115B6rMhQELdkvPJnXQkZ/dCHs2hovAl29+O7saVbWKS7c1zkfg qvKkaxr0qPzHBhByqz1Qb466HZbqwmHEjDsvZegqsNmDQ3/1BHY9/b6QEihI/J+6pDcq UD3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5GWcj5nZ056TFYbzQMURw6vfsCuEsnqnD2FZe7adU3A=; b=AnyrtArOXkqPu28cvfaZEfaHSOiRUPJvD/uHbVtb/gNyDIaX7a8/1JTxFtjadchyLr s7Fs8seYQmwOgAVC8cvCt5yFs+LKqokeKJPQf1z3CQND+6DU1V9W6iVSBpxcRUTBvwDS ZvrVKlj6GmHw5bcnbSuccR7IhaIX4JOdXGQPJcCbpDElO3GJYD4BSvPa8S7Ka0CCFHTY BVtuqBrGMJnKksjT1wzEv5TaV7Tm+UYqZNUFXVJr3GhVW8dWHLUYF+tmUxdKlyEv7WmH YTDb+gt5g5t2hpZewsKcRoDhezjgPJ11KF4LwXBm5Ma3wm2dKIIwC6oHqL4c2PaIdn7y d9Aw== X-Gm-Message-State: AJaThX6JwkwrbtEtsihbHHRKUm64CGCMcQ24HoOn+nvq5zmDb6xxWVSf cxGeQH3WDXxYaNkh1KlTG9Bimg== X-Google-Smtp-Source: AGs4zMaJSWLHgAfRi+BqZLd4hLvhHZ50ViRQ/Pqw3BBrUnRhvHCzLVIawughjmkaoAtTmdLJrfv6MQ== X-Received: by 10.101.66.11 with SMTP id c11mr2728036pgq.169.1512057149858; Thu, 30 Nov 2017 07:52:29 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-195.tpgi.com.au. [27.33.241.195]) by smtp.gmail.com with ESMTPSA id p24sm8037935pfh.170.2017.11.30.07.52.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Nov 2017 07:52:29 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 1 Dec 2017 01:52:14 +1000 Message-Id: <20171130155215.30574-2-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171130155215.30574-1-npiggin@gmail.com> References: <20171130155215.30574-1-npiggin@gmail.com> Subject: [Skiboot] [RFC PATCH 1/2] head: POWER9 initialise MMU registers to boot state for fast-reboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Aneesh Kumar K . V" MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When fast-rebooting, secondaries are sreset into OPAL with their MMU registers (PTCR, PID, etc) still set up by the host OS. Clear them at fastr-reboot time, before loading a new kernel. Signed-off-by: Nicholas Piggin --- asm/head.S | 11 ++++++++++- include/processor.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/asm/head.S b/asm/head.S index eccf0702c..a96c5e4aa 100644 --- a/asm/head.S +++ b/asm/head.S @@ -810,13 +810,22 @@ init_replicated_sprs: 4: /* P9 */ /* LPCR: sane value */ LOAD_IMM64(%r3,0x0040000000000000) + isync mtspr SPR_LPCR, %r3 sync isync + /* Zero out MMU registers */ + li %r3,0 + ptesync + mtspr SPR_PTCR,%r3 + isync + mtspr SPR_LPID,%r3 + isync + mtspr SPR_PID,%r3 + isync /* DSCR: Stride-N Stream Enable */ LOAD_IMM64(%r3,0x0000000000000010) mtspr SPR_DSCR,%r3 - 9: blr .global enter_nap diff --git a/include/processor.h b/include/processor.h index 77110d011..bc02a0f09 100644 --- a/include/processor.h +++ b/include/processor.h @@ -53,6 +53,7 @@ #define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */ #define SPR_CFAR 0x01c /* RW: Come From Address Register */ #define SPR_AMR 0x01d /* RW: Authority Mask Register */ +#define SPR_PID 0x030 /* RW: Process ID */ #define SPR_IAMR 0x03d /* RW: Instruction Authority Mask Register */ #define SPR_RPR 0x0ba /* RW: Relative Priority Register */ #define SPR_TBRL 0x10c /* RO: Timebase low */ @@ -75,9 +76,11 @@ #define SPR_HSRR1 0x13b /* RW: HV Exception save/restore reg 1 */ #define SPR_TFMR 0x13d #define SPR_LPCR 0x13e +#define SPR_LPID 0x13f /* RW: Logical Partition Identifier */ #define SPR_HMER 0x150 /* Hypervisor Maintenance Exception */ #define SPR_HMEER 0x151 /* HMER interrupt enable mask */ #define SPR_AMOR 0x15d +#define SPR_PTCR 0x1d0 /* RW: Partition table control Register */ #define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */ #define SPR_TSCR 0x399 #define SPR_HID0 0x3f0 From patchwork Thu Nov 30 15:52:15 2017 Content-Type: text/plain; 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[27.33.241.195]) by smtp.gmail.com with ESMTPSA id p24sm8037935pfh.170.2017.11.30.07.52.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Nov 2017 07:52:32 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 1 Dec 2017 01:52:15 +1000 Message-Id: <20171130155215.30574-3-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171130155215.30574-1-npiggin@gmail.com> References: <20171130155215.30574-1-npiggin@gmail.com> Subject: [Skiboot] [RFC PATCH 2/2] core/cpu: have opal_reinit_cpus clear MMU registers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Aneesh Kumar K . V" MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When called with an MMU argument, have opal_reinit_cpus zero PIDR and LPID registers as well as flush TLBs. During MMU initialization and over kexec, existing Linux kernels do not clear PIDR, which does not get set until init is executed, which is well after CPUs start running with relocation on. This can result in CPUs incorrectly picking up and caching translations (PWC and PTEs) after the kexec/boot process has done its initial clearing out of TLBs. PTCR can not be cleared entirely here, because opal_reinit_cpus is called with relocation on, so the new kexec kernel always boots with stale PID 0 translations sadly, but in practice they get cleared out before relocation is turned on. Signed-off-by: Nicholas Piggin --- core/cpu.c | 43 +++++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index b94e04ef2..519a60515 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1280,24 +1280,42 @@ void cpu_set_radix_mode(void) cpu_change_all_hid0(&req); } -static void cpu_cleanup_one(void *param __unused) +static void cpu_cleanup_mmu_one(void *param __unused) { + if (proc_gen >= proc_gen_p9) { + mtspr(SPR_PID, 0); + } + mtspr(SPR_LPID, 0); mtspr(SPR_AMR, 0); mtspr(SPR_IAMR, 0); } -static int64_t cpu_cleanup_all(void) +/* + * Clean MMU registers and flush TLBs to prepare for a kexec (or similar + * environment). + */ +static int64_t cpu_cleanup_mmu(void) { struct cpu_thread *cpu; for_each_available_cpu(cpu) { if (cpu == this_cpu()) { - cpu_cleanup_one(NULL); + cpu_cleanup_mmu_one(NULL); continue; } - cpu_wait_job(cpu_queue_job(cpu, "cpu_cleanup", - cpu_cleanup_one, NULL), true); + cpu_wait_job(cpu_queue_job(cpu, "cpu_cleanup_mmu", + cpu_cleanup_mmu_one, NULL), true); } + + /* Cleanup the TLB. After PID and LPID are cleared, we can flush + * TLBs without them being prefetched, with the exception of PID 0, + * unfortunately Linux calls this with the MMU on, so we can't + * clear up the MMU registers completely and flush everything. + * + * This is P9 specific for now. + */ + cleanup_global_tlb(); + return OPAL_SUCCESS; } @@ -1362,7 +1380,10 @@ static int64_t opal_reinit_cpus(uint64_t flags) * transitions. Ideally Linux should do it but doing it * here works around existing broken kernels. */ - cpu_cleanup_all(); + if (flags & (OPAL_REINIT_CPUS_MMU_HASH | + OPAL_REINIT_CPUS_MMU_RADIX)) { + cpu_cleanup_mmu(); + } /* If HILE change via HID0 is supported ... */ if (hile_supported && @@ -1398,16 +1419,6 @@ static int64_t opal_reinit_cpus(uint64_t flags) } } - /* Cleanup the TLB. We do that unconditionally, this works - * around issues where OSes fail to invalidate the PWC in Radix - * mode for example. This only works on P9 and later, but we - * also know we don't have a problem with Linux cleanups on - * P8 so this isn't a problem. If we wanted to cleanup the - * TLB on P8 as well, we'd have to use jobs to do it locally - * on each CPU. - */ - cleanup_global_tlb(); - /* Apply HID bits changes if any */ if (req.set_bits || req.clr_bits) cpu_change_all_hid0(&req);