From patchwork Wed Feb 19 02:08:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TGlnaHQgSHNpZWggKOisneaYjueHiCk=?= X-Patchwork-Id: 1240477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=kEYGXX+H; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48Mh3D1vN1z9sRt for ; Wed, 19 Feb 2020 13:08:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727872AbgBSCIf (ORCPT ); Tue, 18 Feb 2020 21:08:35 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:1395 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726761AbgBSCIe (ORCPT ); Tue, 18 Feb 2020 21:08:34 -0500 X-UUID: e846100145ac4e5f8e9f4c44807a9037-20200219 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=0GGyHWDXgNa0q8vA4vNU5LvM0X7qLDEW7k6yfDyFWXE=; b=kEYGXX+HfY6oTSOXjopSrYqJXyd5psNhjudw/Vf7tkU5ivDHYstaadgJRSwNY/scGjO9o6fAcTz66EQIsag36gHaXHO8kdLH/387VmBg6utnmXvremxJ2iV3l7ETWxxQPD2FzLYLjQUZD9/zmek6DtuKCvP9Idt46lRkl3RKNls=; X-UUID: e846100145ac4e5f8e9f4c44807a9037-20200219 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1952911459; Wed, 19 Feb 2020 10:08:24 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Feb 2020 10:06:39 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 19 Feb 2020 10:07:51 +0800 From: To: CC: , , , , , Light Hsieh Subject: [PATCH v2 1/2] pinctrl: make MediaTek pinctrl v2 driver ready for buidling loadable module Date: Wed, 19 Feb 2020 10:08:21 +0800 Message-ID: <1582078102-26332-1-git-send-email-light.hsieh@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Light Hsieh In the future we want to be able to build the MediaTek pinctrl driver, based on paris, as kernel module. This patch allows pinctrl-paris.c, the external interrupt controller mtk-eint.c, and pinctrl-mtk-common-v2.c to be loadable as module. The following is the rationale for determining whether mtk-eint.c, pinctrl-mtk-common-v2.c, and pinctrl-paris.c are built as loadable module: 1. drivers/pinctrl/mediatek/Kconfig: 1.1 PINCTRL_MTXXXX: change from bool to tristate. It is specified in defconfig file. MTXXXX can only be the user of pinctrl-paris, which can MT6765 or MT8183. The patch for changing PINCTRL_MT6765 from bool to tristate will be given as the next patch of the patch series. 1.2 PINCTRL_MTK_PARIS: change from bool to tristate and select PINCTRL_MTK_V2. No need to specify in defconfig file. * PINCTRL_MTK_PARIS will be y if any PINCTRL_MTXXXX selecting PINCTRL_MTK_PARIS is y. * PINCTRL_MTK_PARIS will be n if all PINCTRL_MTXXXX selecting PINCTRL_MTK_PARIS is n. * PINCTRL_MTK_PARIS will be m if some PINCTRL_MTXXXX selecting PINCTRL_MTK_PARIS are m and other PINCTRL_MTXXXX selecting PINCTRL_MTK_PARIS are n. 1.3 PINCTRL_MTK_MOORE: select EINT_MTK and PINCTRL_MTK_V2. It is make to be ready for building as loadable kernel module because it is not used on Android kernel. 1.4 PINCTRL_MTK_V2: add this tristate config which depends on PINCTRL_MTK_PARIS and PINCTRL_MTK_MOORE. No need to specify in defconfig file. * PINCTRL_MTK_V2 will be y if either PINCTRL_MTK_PARIS or PINCTRL_MTK_MOORE is y. * PINCTRL_MTK_V2 will be n if both PINCTRL_MTK_PARIS and PINCTRL_MTK_MOORE are n. * PINCTRL_MTK_V2 will be m if PINCTRL_MTK_PARIS is m and PINCTRL_MTK_MOORE is n. 1.5 EINT_MTK: change from bool to tristate and add rule for default. No need to specify in defconfig file. * First rule: determine if EINT_MTK is y or n according to selection of PINCTRL_MTK or PINCTRL_MTK_MORE. * Second rule: determine if EINT_MTK is y, m, or n according to selection of PINCTRL_MTK_PARIS. 2. drivers/pinctrl/mediatek/Makefile: Use PINCTRL_MTK_V2 to determine if pinctrl-mtk-common-v2.c is built as loadable module or built-in. Signed-off-by: Light Hsieh --- drivers/pinctrl/mediatek/Kconfig | 13 +++++++++++-- drivers/pinctrl/mediatek/Makefile | 5 +++-- drivers/pinctrl/mediatek/mtk-eint.c | 9 +++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 24 ++++++++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-paris.c | 5 +++++ drivers/pinctrl/pinconf-generic.c | 1 + 6 files changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 701f9af..4cd1109 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -3,10 +3,12 @@ menu "MediaTek pinctrl drivers" depends on ARCH_MEDIATEK || COMPILE_TEST config EINT_MTK - bool "MediaTek External Interrupt Support" + tristate "MediaTek External Interrupt Support" depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST select GPIOLIB select IRQ_DOMAIN + default y if PINCTRL_MTK || PINCTRL_MTK_MOORE + default PINCTRL_MTK_PARIS config PINCTRL_MTK bool @@ -17,23 +19,30 @@ config PINCTRL_MTK select EINT_MTK select OF_GPIO +config PINCTRL_MTK_V2 + tristate + depends on PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS + config PINCTRL_MTK_MOORE bool depends on OF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS + select EINT_MTK select GPIOLIB select OF_GPIO + select PINCTRL_MTK_V2 config PINCTRL_MTK_PARIS - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF select GPIOLIB select EINT_MTK select OF_GPIO + select PINCTRL_MTK_V2 # For ARMv7 SoCs config PINCTRL_MT2701 diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index a74325a..4b71328 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -2,8 +2,9 @@ # Core obj-$(CONFIG_EINT_MTK) += mtk-eint.o obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 7e526bcf..99703a8 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include @@ -379,6 +380,7 @@ int mtk_eint_do_suspend(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); int mtk_eint_do_resume(struct mtk_eint *eint) { @@ -386,6 +388,7 @@ int mtk_eint_do_resume(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_resume); int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, unsigned int debounce) @@ -440,6 +443,7 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_set_debounce); int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) { @@ -451,6 +455,7 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) return irq; } +EXPORT_SYMBOL_GPL(mtk_eint_find_irq); int mtk_eint_do_init(struct mtk_eint *eint) { @@ -495,3 +500,7 @@ int mtk_eint_do_init(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek EINT Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 1da9425..cdf2d69 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include @@ -206,6 +207,7 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_set_value); int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int field, int *value) @@ -225,6 +227,7 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_get_value); static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) { @@ -363,6 +366,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return mtk_eint_do_init(hw->eint); } +EXPORT_SYMBOL_GPL(mtk_build_eint); /* Revision 0 */ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, @@ -382,6 +386,7 @@ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -404,6 +409,7 @@ int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -423,6 +429,7 @@ int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, int *res) @@ -442,6 +449,7 @@ int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); /* Revision 1 */ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, @@ -456,6 +464,7 @@ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -473,6 +482,7 @@ int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -492,6 +502,7 @@ int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -517,6 +528,7 @@ int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_gev1); /* Combo for the following pull register type: * 1. PU + PD @@ -717,6 +729,7 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -737,6 +750,7 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); /* Revision 0 */ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, @@ -766,6 +780,7 @@ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -790,6 +805,7 @@ int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); /* Revision 1 */ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, @@ -811,6 +827,7 @@ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -828,18 +845,21 @@ int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) { return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) { return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -880,6 +900,7 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -922,6 +943,7 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) @@ -948,6 +970,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val) @@ -971,3 +994,4 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 83bf29c..af97794 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -9,6 +9,7 @@ * Hongzhou.Yang */ +#include #include #include #include "pinctrl-paris.h" @@ -1037,3 +1038,7 @@ static int mtk_paris_pinctrl_resume(struct device *device) .suspend_noirq = mtk_paris_pinctrl_suspend, .resume_noirq = mtk_paris_pinctrl_resume, }; +EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris"); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 9eb8630..dfef471 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -286,6 +286,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np, kfree(cfg); return ret; } +EXPORT_SYMBOL_GPL(pinconf_generic_parse_dt_config); int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, From patchwork Wed Feb 19 02:08:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TGlnaHQgSHNpZWggKOisneaYjueHiCk=?= X-Patchwork-Id: 1240476 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=TNA6tUof; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48Mh352ftYz9sRh for ; Wed, 19 Feb 2020 13:08:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727936AbgBSCIc (ORCPT ); Tue, 18 Feb 2020 21:08:32 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:39079 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727872AbgBSCIc (ORCPT ); Tue, 18 Feb 2020 21:08:32 -0500 X-UUID: c1bc2e3e265b484a86280060ac9c3944-20200219 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1qzoJ6EEatPElYiOsXSiqLR5375SqMzBtOAuZFX/AiM=; b=TNA6tUofyYcQArXX4MKw0nqvFHDizn8J8XAFUqbi8y1KEeO1o5SZC0BD80UBKZfXArUWX3fU73sNUPQVcI/Sy7iKUDQZOA7hnrTn7jX3uUJLBlGBEZ8VNvulYk+IFvznd0uy2/Ezgv8x7K+jA82Ogk7w0SaOxJhS6HH8c5S6Vy4=; X-UUID: c1bc2e3e265b484a86280060ac9c3944-20200219 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 838099783; Wed, 19 Feb 2020 10:08:26 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 19 Feb 2020 10:05:56 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 19 Feb 2020 10:07:52 +0800 From: To: CC: , , , , , Light Hsieh Subject: [PATCH v2 2/2] pinctrl: make MediaTek MT6765 pinctrl ready for buidling loadable module Date: Wed, 19 Feb 2020 10:08:22 +0800 Message-ID: <1582078102-26332-2-git-send-email-light.hsieh@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1582078102-26332-1-git-send-email-light.hsieh@mediatek.com> References: <1582078102-26332-1-git-send-email-light.hsieh@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 5F8F33AF66A46C291F16CEF9770660E849AC8E6E373F8FB78901EB26DDD278DC2000:8 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Light Hsieh This patch make pinctrl-mt6765 ready for building as loadable module. Signed-off-by: Light Hsieh --- drivers/pinctrl/mediatek/Kconfig | 2 +- drivers/pinctrl/mediatek/pinctrl-mt6765.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 4cd1109..c645fdb 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -89,7 +89,7 @@ config PINCTRL_MT2712 select PINCTRL_MTK config PINCTRL_MT6765 - bool "Mediatek MT6765 pin control" + tristate "Mediatek MT6765 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 905dae8c..2c59d39 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -6,6 +6,7 @@ * */ +#include #include "pinctrl-mtk-mt6765.h" #include "pinctrl-paris.h" @@ -1103,3 +1104,6 @@ static int __init mt6765_pinctrl_init(void) return platform_driver_register(&mt6765_pinctrl_driver); } arch_initcall(mt6765_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6765 Pinctrl Driver");