From patchwork Wed Nov 29 03:07:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 842437 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hjHEoQDb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ymm6w6pmyz9s7B for ; Wed, 29 Nov 2017 14:22:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8B22CC21DB5; Wed, 29 Nov 2017 03:21:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 075D9C21E4C; Wed, 29 Nov 2017 03:10:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B61BBC21E41; Wed, 29 Nov 2017 03:08:07 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id E445BC21DF4 for ; Wed, 29 Nov 2017 03:08:04 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id b18so869995pgv.10 for ; Tue, 28 Nov 2017 19:08:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=gCnW99gCypKIKsyiqnr3d4N4KIAfgAgZFRIN1LN4xn4=; b=hjHEoQDbZ/sh8yu9pLTIEw876vDcitSukRy24E8op8MYebYZvkxA82hT1mLcog5ug0 1KQySlav9J+bxrnEk0UXaMihejfwFmIwNH2OtgjaigeyE5fSSVd9CK+ad6TCIUbr9T03 Zx4scCWDzzu/XmHkcHU5UOh8ZIi77pB+zqW/RkVEx1xnNQCby9fTIfQ2emHmYo9luEt3 nlhnod3RB1r56B9r94p1TE1WAyb3082rZhZQWBIBdqHNvTpP/UKXygt+IaOPiZZpSSQY 24Yb/ISi0eazL+62N2xp9KUNCFRdfU1woRicrnLJ/OxGdhfrkK26SGJXHtzH6ZSiiKsS PLCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=gCnW99gCypKIKsyiqnr3d4N4KIAfgAgZFRIN1LN4xn4=; b=i+zkho8eZ8I0BWfFQnMxWpzmPnGU+TXISlgPnj7O4yP7P6Pn4WSmohZrK9dLENa89C 6d4asYGkJOojPZwfLCkGCgaGBdkVGkuKkrx/RLmsGUEOtybad8bZa5rXW1aUAM3oY4gN bXaz4nM8U5jbFzn9DE3uJYlFo/gIgYNPC3dJpcL1jtuBpqllYhiz0c+kp0YTKwcxjqe2 UwGpkcmxekJCB9Z/wwe/Imoejrj7OZCfOUYlKkt4Lpnj95EGQrFwFU+tJBt5RegG+dH7 iwwJUvzk8XPknnV0DEyBZkRre837LTaoM75YNWWWUwWdhx0m6QXLcyrV8XJJFONpSXDc ly1w== X-Gm-Message-State: AJaThX6FwK1NwO0mPMwsqgo1CojyUPZawL3hcRPmktNhf8DYHT9c25Q+ xRrRWnDfKLjYGGge3r1nXHOMOfx8 X-Google-Smtp-Source: AGs4zMZLDW5OPJ3/hHTmrSn6URafRgyJ27o6NK75LMOX8FwsptOS3o/7RnN0ZVBHhrg2B9V7fmttIQ== X-Received: by 10.99.126.6 with SMTP id z6mr1371925pgc.305.1511924883329; Tue, 28 Nov 2017 19:08:03 -0800 (PST) Received: from localhost.localdomain ([219.100.137.101]) by smtp.gmail.com with ESMTPSA id h6sm543434pgn.63.2017.11.28.19.08.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 19:08:02 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 29 Nov 2017 04:07:41 +0100 Message-Id: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.0 Cc: Marek Vasut Subject: [U-Boot] [PATCH 1/4] pinctrl: rmobile: Add support for setting single pins X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add code to handle single pins nodes from DT in addition to already support groups handling. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/pfc.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index edaac77f43..2f23d335f9 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -450,6 +450,22 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } +static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, + unsigned func_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; + int idx = sh_pfc_get_pin_index(pfc, pin->pin); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); +} + static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, unsigned func_selector) { @@ -644,6 +660,19 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, return 0; } +static int sh_pfc_pinconf_pin_set(struct udevice *dev, + unsigned int pin_selector, + unsigned int param, unsigned int arg) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector]; + + sh_pfc_pinconf_set(pmx, pin->pin, param, arg); + + return 0; +} static int sh_pfc_pinconf_group_set(struct udevice *dev, unsigned int group_selector, @@ -673,8 +702,10 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCONF) .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), .pinconf_params = sh_pfc_pinconf_params, + .pinconf_set = sh_pfc_pinconf_pin_set, .pinconf_group_set = sh_pfc_pinconf_group_set, #endif + .pinmux_set = sh_pfc_pinctrl_pin_set, .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, }; From patchwork Wed Nov 29 03:07:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 842438 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sI5qMpk3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ymm760pvYz9s7B for ; Wed, 29 Nov 2017 14:22:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D75DEC21DE8; Wed, 29 Nov 2017 03:21:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 49B9CC21DF4; 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Tue, 28 Nov 2017 19:08:04 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 29 Nov 2017 04:07:42 +0100 Message-Id: <20171129030744.7618-2-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> References: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 2/4] pfc: rmobile: Add hook to configure pin as GPIO X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add hook into the PFC driver to allow the GPIO driver to toggle GPSR registers into GPIO mode when GPIO is requested. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/pinctrl/renesas/pfc.c | 29 +++++++++++++++++++++++++++++ drivers/pinctrl/renesas/sh_pfc.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 2f23d335f9..c68c84b82f 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -450,6 +450,35 @@ static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev, return priv->pfc.info->functions[selector].name; } +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + struct sh_pfc_pin_config *cfg; + const struct sh_pfc_pin *pin = NULL; + int i, idx; + + for (i = 1; i < pfc->info->nr_pins; i++) { + if (priv->pfc.info->pins[i].pin != pin_selector) + continue; + + pin = &priv->pfc.info->pins[i]; + break; + } + + if (!pin) + return -EINVAL; + + idx = sh_pfc_get_pin_index(pfc, pin->pin); + cfg = &pmx->configs[idx]; + + if (cfg->type != PINMUX_TYPE_NONE) + return -EBUSY; + + return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); +} + static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, unsigned func_selector) { diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index aefdd5816b..2ce83694f6 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -243,6 +243,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) const struct sh_pfc_bias_info * sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, unsigned int num, unsigned int pin); +int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector); extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; From patchwork Wed Nov 29 03:07:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 842434 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 29 Nov 2017 03:08:10 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id D648DC21DE7 for ; Wed, 29 Nov 2017 03:08:09 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id bd8so1222335plb.9 for ; Tue, 28 Nov 2017 19:08:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=74yA89RifW0WZNi13V3R6uGK8mWYeXTZVVmP5gBVEP8=; b=JTNcI6dPblnkt/bBCBbD6isZBUmAyVfaQu5ekmjGyWJt94ouvnWUbhaFBJ1K0YKb98 Dv3dEYNEaXa+LHlHzc84e1nUOIjl3ir2QBAV04SYNC3HocciTFRSdelQZW6qQ+iUM2y0 +rsmGSuRyy1W3O6Zlg7C7VaH8xF3BwgVA7wshsSZ+uIae8Z233k20fq5nlMKBXsUcxdp 0XEa/OdL+xxGa7eL9prx7hlmBNjlBeeLXkUqWihAOvQIH+tuzqmDcEeyiaJkO9ZmQGF9 YPflpppbctnn0Y5tpXkzkmjW1hqaQwJigkgJspWHJuwcDcacGzam+NqJpbDIzjHONddR Y3/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=74yA89RifW0WZNi13V3R6uGK8mWYeXTZVVmP5gBVEP8=; b=IrC0Ch05o+dKVB27C4jXN19RFQMQmHs3rYzvW8N43/pe3UAOJEj5pzAh2WQAT72DlI uBCtCoBE7HonvzmXiqKPzU7f9Exjr729NwjsB7d7qnwmh5dnC0tnQ/7EuRsp4iBRvk2i UUW4d4pA/ovIxHr5v6rbrMMzEi2LmZa7e+0Ok9zKxs3PBaNZQH/DNFRavoVcdacdBpr8 i8Irji+yPbDPeuhLNSVZPYkrPXWo4TX/YZUp4ERgEODxolBCeeGrXkcoEFm1L7ywmAIO rrcqFO3Q/SoATEFxC1mk1fC9WO3n6ecFxumEtk8R7HgclD9Qy944/r09xXbJkPIYxbQ8 F9Sg== X-Gm-Message-State: AJaThX7XufIabqVsbgm3GyXRPPGypq+1sXyhCRX+YFDVLHgQOC0Sjh8K N0awsJprFeFdKS2cVIcwGifvfz7K X-Google-Smtp-Source: AGs4zMa7VtJTuYaqdM1kcsGHgd9facZjXhDr5gnfvaCWkrjrk4p8ApCtg/n77Om9v9LBmGrCx5bPTg== X-Received: by 10.84.179.3 with SMTP id a3mr1398786plc.25.1511924888292; Tue, 28 Nov 2017 19:08:08 -0800 (PST) Received: from localhost.localdomain ([219.100.137.101]) by smtp.gmail.com with ESMTPSA id h6sm543434pgn.63.2017.11.28.19.08.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 19:08:07 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 29 Nov 2017 04:07:43 +0100 Message-Id: <20171129030744.7618-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> References: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 3/4] gpio: rmobile: Set GPIO mode in GPSR when requested X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When requesting a GPIO, set the PFC GPSR register to GPIO mode, otherwise the GPIO cannot work. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/gpio/gpio-rcar.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index cf2bee7e01..88f1935062 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -10,6 +10,7 @@ #include #include #include +#include "../pinctrl/renesas/sh_pfc.h" #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ @@ -29,7 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; struct rcar_gpio_priv { - void __iomem *regs; + void __iomem *regs; + int pfc_offset; }; static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) @@ -113,7 +115,22 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } +static int rcar_gpio_request(struct udevice *dev, unsigned offset, + const char *label) +{ + struct rcar_gpio_priv *priv = dev_get_priv(dev); + struct udevice *pctldev; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev); + if (ret) + return ret; + + return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset); +} + static const struct dm_gpio_ops rcar_gpio_ops = { + .request = rcar_gpio_request, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, @@ -135,6 +152,7 @@ static int rcar_gpio_probe(struct udevice *dev) ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", NULL, 3, 0, &args); + priv->pfc_offset = ret == 0 ? args.args[1] : -1; uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; ret = clk_get_by_index(dev, 0, &clk); From patchwork Wed Nov 29 03:07:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 842436 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tdrxqY6W"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ymm5W03rkz9ryv for ; Wed, 29 Nov 2017 14:21:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 70188C21E11; Wed, 29 Nov 2017 03:20:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A91CFC21E28; Wed, 29 Nov 2017 03:10:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2EEC6C21DF4; Wed, 29 Nov 2017 03:08:12 +0000 (UTC) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by lists.denx.de (Postfix) with ESMTPS id 623A7C21E30 for ; Wed, 29 Nov 2017 03:08:12 +0000 (UTC) Received: by mail-pl0-f67.google.com with SMTP id b12so1235513plm.3 for ; Tue, 28 Nov 2017 19:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=55W5fc0qRQ4Gwa3ssJx6FEj3/tBQGcQrCWEBoZ3A76w=; b=tdrxqY6WbWUI26c9ho9eDINDF0bgp991ni1P0ESbtYYKQEb51ACbwzBK7ITyh3rCh3 GLk+9882gtdTfZ43DX23dJ0aUeutdsyxy0CDE/nF2oH/Q9ZbB+QiSy0QG4d3ky1VBTZY Icmkkn7F99GLq+i7tQQlLU9ES9IyMyS5ggzrDv3li1OxX2dZCnc8fVwU3vV/RfbGf7Zt kgc5jPVRpRgRLstWtB1N4zSfW1wbVjbwSulgDl6QxH0wVpbRIm2Cq7lu5HcnQkB6gRF9 BFpLme6cIFSEBLVxiaopPyAP3EXmD2hjBPdYk4fzJQrb80nOkNSgl2B78RO//l2I23aa +LIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=55W5fc0qRQ4Gwa3ssJx6FEj3/tBQGcQrCWEBoZ3A76w=; b=SI1Lry6z2dk+g1SZ5lD0M1iKdmUF9eHUFtP6P3QGJRhzhVvuu2AqdWOVpHdmtkul+r S4XvGl1zK5xScpc0A5HE4ET+CZc8HsreDUdQKGp7FHYSLzkmyf5b4qZMmeljZr8LEtEy 9sBqk/RQEm/jldX/tLaLIWFqa1qbj3+wAUnTIBOi5QByyFImTTBLugNQC2kWrj6MKUjU odAL9lSls7gAr1duzqPV5C2wApgNZD+QWPAq5zPbogHG9Mt1Ep0wvRpigx8MU0OIIdsS leyQm71/BJ5gf8kumLHOjTs13PUk5OtUFM4egK917hIfxOAHDC1nlbhRROm3vtsAO6aD prSw== X-Gm-Message-State: AJaThX7+ymOei2D70HzWsnu5RLcLyFo1y7yXnE3nVQYdZc3iCe46HmxA xEyS2PIStmLbZDooF6uFbj4TCR4S X-Google-Smtp-Source: AGs4zMaBW/Q/FiMLlyQcNJpspNcdOAfLIV47Yk8fyGQKgNAYMdoPn9qDfCQo7i0SV0mle/iHpJkyoA== X-Received: by 10.84.129.197 with SMTP id b63mr1424620plb.278.1511924890715; Tue, 28 Nov 2017 19:08:10 -0800 (PST) Received: from localhost.localdomain ([219.100.137.101]) by smtp.gmail.com with ESMTPSA id h6sm543434pgn.63.2017.11.28.19.08.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 19:08:10 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 29 Nov 2017 04:07:44 +0100 Message-Id: <20171129030744.7618-4-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> References: <20171129030744.7618-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 4/4] ARM: rmobile: Rework the ULCB CPLD driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/ulcb.dtsi | 9 ++ board/renesas/ulcb/cpld.c | 212 +++++++++++++++++++++++------------------ configs/r8a7795_ulcb_defconfig | 1 + configs/r8a7796_ulcb_defconfig | 1 + include/configs/ulcb.h | 13 --- 5 files changed, 129 insertions(+), 107 deletions(-) diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index 0ae2bfd289..e81d476367 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,6 +24,15 @@ stdout-path = "serial0:115200n8"; }; + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; + audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c index a1fecf18e5..50de56837e 100644 --- a/board/renesas/ulcb/cpld.c +++ b/board/renesas/ulcb/cpld.c @@ -8,14 +8,12 @@ */ #include -#include -#include #include - -#define SCLK (192 + 8) /* GPIO6 8 */ -#define SSTBZ (64 + 3) /* GPIO2 3 */ -#define MOSI (192 + 7) /* GPIO6 8 */ -#define MISO (192 + 10) /* GPIO6 10 */ +#include +#include +#include +#include +#include #define CPLD_ADDR_MODE 0x00 /* RW */ #define CPLD_ADDR_MUX 0x02 /* RW */ @@ -23,111 +21,89 @@ #define CPLD_ADDR_RESET 0x80 /* RW */ #define CPLD_ADDR_VERSION 0xFF /* R */ -static int cpld_initialized; - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* Always active */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* Always active */ -} - -void ulcb_softspi_sda(int set) -{ - gpio_set_value(MOSI, set); -} +struct renesas_ulcb_sysreset_priv { + struct gpio_desc miso; + struct gpio_desc mosi; + struct gpio_desc sck; + struct gpio_desc sstbz; +}; -void ulcb_softspi_scl(int set) -{ - gpio_set_value(SCLK, set); -} - -unsigned char ulcb_softspi_read(void) -{ - return !!gpio_get_value(MISO); -} - -static void cpld_rw(u8 write) -{ - gpio_set_value(MOSI, write); - gpio_set_value(SSTBZ, 0); - gpio_set_value(SCLK, 1); - gpio_set_value(SCLK, 0); - gpio_set_value(SSTBZ, 1); -} - -static u32 cpld_read(u8 addr) +static u32 cpld_read(struct udevice *dev, u8 addr) { + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); u32 data = 0; + int i; - spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); - - cpld_rw(0); - - spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); - - return swab32(data); -} - -static void cpld_write(u8 addr, u32 data) -{ - data = swab32(data); - - spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); + dm_gpio_set_value(&priv->mosi, 0); /* READ */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); + + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + data |= dm_gpio_get_value(&priv->miso); /* MSB first */ + dm_gpio_set_value(&priv->sck, 0); + } - cpld_rw(1); + return data; } -static void cpld_init(void) +static void cpld_write(struct udevice *dev, u8 addr, u32 data) { - if (cpld_initialized) - return; - - /* PULL-UP on MISO line */ - setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); - - gpio_request(SCLK, NULL); - gpio_request(SSTBZ, NULL); - gpio_request(MOSI, NULL); - gpio_request(MISO, NULL); - - gpio_direction_output(SCLK, 0); - gpio_direction_output(SSTBZ, 1); - gpio_direction_output(MOSI, 0); - gpio_direction_input(MISO); + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < 32; i++) { + dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + data <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - /* Dummy read */ - cpld_read(CPLD_ADDR_VERSION); + for (i = 0; i < 8; i++) { + dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */ + dm_gpio_set_value(&priv->sck, 1); + addr <<= 1; + dm_gpio_set_value(&priv->sck, 0); + } - cpld_initialized = 1; + dm_gpio_set_value(&priv->mosi, 1); /* WRITE */ + dm_gpio_set_value(&priv->sstbz, 0); + dm_gpio_set_value(&priv->sck, 1); + dm_gpio_set_value(&priv->sck, 0); + dm_gpio_set_value(&priv->sstbz, 1); } static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u32 addr, val; + int ret; - cpld_init(); + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_GET_DRIVER(sysreset_renesas_ulcb), + &dev); + if (ret) + return ret; if (argc == 2 && strcmp(argv[1], "info") == 0) { printf("CPLD version:\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_VERSION)); + cpld_read(dev, CPLD_ADDR_VERSION)); printf("H3 Mode setting (MD0..28):\t0x%08x\n", - cpld_read(CPLD_ADDR_MODE)); + cpld_read(dev, CPLD_ADDR_MODE)); printf("Multiplexer settings:\t\t0x%08x\n", - cpld_read(CPLD_ADDR_MUX)); + cpld_read(dev, CPLD_ADDR_MUX)); printf("DIPSW (SW6):\t\t\t0x%08x\n", - cpld_read(CPLD_ADDR_DIPSW6)); + cpld_read(dev, CPLD_ADDR_DIPSW6)); return 0; } @@ -143,10 +119,10 @@ static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (argc == 3 && strcmp(argv[1], "read") == 0) { - printf("0x%x\n", cpld_read(addr)); + printf("0x%x\n", cpld_read(dev, addr)); } else if (argc == 4 && strcmp(argv[1], "write") == 0) { val = simple_strtoul(argv[3], NULL, 16); - cpld_write(addr, val); + cpld_write(dev, addr, val); } return 0; @@ -160,8 +136,56 @@ U_BOOT_CMD( "cpld write addr val\n" ); -void reset_cpu(ulong addr) +static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_ulcb_sysreset_probe(struct udevice *dev) { - cpld_init(); - cpld_write(CPLD_ADDR_RESET, 1); + struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev); + + if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso, + GPIOD_IS_IN)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi, + GPIOD_IS_OUT)) + return -EINVAL; + + /* PULL-UP on MISO line */ + setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); + + /* Dummy read */ + cpld_read(dev, CPLD_ADDR_VERSION); + + return 0; } + +static struct sysreset_ops renesas_ulcb_sysreset = { + .request = renesas_ulcb_sysreset_request, +}; + +static const struct udevice_id renesas_ulcb_sysreset_ids[] = { + { .compatible = "renesas,ulcb-cpld" }, + { } +}; + +U_BOOT_DRIVER(sysreset_renesas_ulcb) = { + .name = "renesas_ulcb_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_ulcb_sysreset, + .probe = renesas_ulcb_sysreset_probe, + .of_match = renesas_ulcb_sysreset_ids, + .priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv), +}; diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 11027ad51e..01fa16d468 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -51,6 +51,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 03c7caae48..ac79dd157b 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -52,6 +52,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 15b82b32d2..35238ff8d7 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -25,19 +25,6 @@ /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* CPLD SPI */ -#define CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define SPI_DELAY udelay(0) -#define SPI_SDA(val) ulcb_softspi_sda(val) -#define SPI_SCL(val) ulcb_softspi_scl(val) -#define SPI_READ ulcb_softspi_read() -#ifndef __ASSEMBLY__ -void ulcb_softspi_sda(int); -void ulcb_softspi_scl(int); -unsigned char ulcb_softspi_read(void); -#endif - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1