From patchwork Wed Nov 29 00:53:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 842374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="PvvPAcdH"; dkim=pass (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="WY01PXoq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ymhqR3jSHz9s7B for ; Wed, 29 Nov 2017 11:53:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752272AbdK2Axh (ORCPT ); Tue, 28 Nov 2017 19:53:37 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55366 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752133AbdK2Axg (ORCPT ); Tue, 28 Nov 2017 19:53:36 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5441860249; Wed, 29 Nov 2017 00:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511916816; bh=AKZXfblBBFl7b7NpzO4FcDVqHNLIG+FtMjS4Yg/D+d0=; h=From:To:Cc:Subject:Date:From; b=PvvPAcdHOHtU8E6m2jNTB9vfFzBSTCSsgmyhhG0jZhS1weeNePZD+joRejfmPCIYW vrz1dzfkrViArr86pN48qbvNaYR/+VGuTtQaqqn7SR2BZeTSP22usAKCeHJ/iWLftY ecbfYRkTOdyGgqEjZQbHHITB92bW1QtlkFCMCwvY= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from sboyd-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 775F060249; Wed, 29 Nov 2017 00:53:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511916815; bh=AKZXfblBBFl7b7NpzO4FcDVqHNLIG+FtMjS4Yg/D+d0=; h=From:To:Cc:Subject:Date:From; b=WY01PXoqwt2Ad/UMUpp/RmZlRhuyN0lkg4vNj7ST7aOgAkq1SV1AWbNj/w74V7sju AbWVY6WTT3S+X2gL3ahdqD2buzzfXGlzHj7sYjuCMxPTmQfsJzWWAGM78wGYUZzu8J ANyog5Vk/T33Ne4FzWjMiHWt9dX61ngah944pXjA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 775F060249 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org From: Stephen Boyd To: Jingoo Han , Joao Pinto Cc: linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org Subject: [PATCH] PCI: dwc: Use {upper,lower}_32_bits() macros for clarity Date: Tue, 28 Nov 2017 16:53:34 -0800 Message-Id: <20171129005334.16425-1-sboyd@codeaurora.org> X-Mailer: git-send-email 2.15.0.374.g5f9953d2c365 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org We have macros for getting the upper or lower 32 bits of a number. Use them here to shave a couple lines off the code. Signed-off-by: Stephen Boyd Acked-by: Jingoo Han --- drivers/pci/dwc/pcie-designware-host.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 157621175147..ae5abfddf8de 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -89,10 +89,8 @@ void dw_pcie_msi_init(struct pcie_port *pp) msi_target = virt_to_phys((void *)pp->msi_data); /* program the msi_data */ - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, - (u32)(msi_target & 0xffffffff)); - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, - (u32)(msi_target >> 32 & 0xffffffff)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, lower_32_bits(msi_target)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(msi_target)); } static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)