From patchwork Thu Jan 30 16:15:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=X2XyrrVh; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lpm51vhz9sR8 for ; Fri, 31 Jan 2020 03:16:31 +1100 (AEDT) Received: from localhost ([::1]:34942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCUX-0005F9-He for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:16:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42975) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTl-0005D1-IV for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTj-0002nh-I9 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:41 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:35687) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTj-0002ms-C9 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:39 -0500 Received: by mail-wr1-x443.google.com with SMTP id g17so4826026wro.2 for ; Thu, 30 Jan 2020 08:15:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=toXoJk3kWKWDO6UmwWx0b6Nlul4ANvuG6q0d24EnKXQ=; b=X2XyrrVhUwOVshAUgEsnyTu9eoKCB57WH0tVejYJhQ5oYqupu2u15o8bcYq8F7ldH0 JgrTwyG2Dtm7+x/GJsCn66wOlOukQxLm9pxTbzrT/NWi/Zyk0KBi0nSsLRsRu5LKpDRP 47DDktESraA4iD8GtPWV2QSlVgFm4HpNcZV4AQSVDq6xQkxXFMZwaBaWx/nhfu3hk9fI SCJ7cLUjW8sZcQcJWswDx9KAMErdwg7uCGLGxOAbhVGRMsSuUKeoZVUnvSMqMfVmkqxN hhyUVa+su2JM3S8uHYWEpmh77gXoFIuzcKHkL4Wm351IjMP0lpFGCzYXr2G1ntpk/Cv/ y2Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=toXoJk3kWKWDO6UmwWx0b6Nlul4ANvuG6q0d24EnKXQ=; b=ass1DmNA24SnhbioEqIcWRwhcn2k6O92u/Dach0QkPmIoLJOAWn2ozydil7/RCjM03 WSkVJfcrUZzIglp3Z2zWP3aZ+k3AfXQBjilAOlaLWa0sUqP0CQRUU4sECFpT0JnOKb6r H19fYDZGoSYDl+E2LaisgEXE+ra4/jBpf6XPIKUtFgoGJ1ZFydKTeCxsCfSkTZETE5+U 5mGcgD4h+z3ybBMtTE4Gb711eKdDtAdBX6oXV6j8ooVvcREtDulel0ub/UZV5+/8Txf6 KdA8pmfaYhcb9eU1a/wZXUlr6tFpcMBeY7v12wKbV7od235bb5xVRI1fbTmPSN8Q1rgA y1bA== X-Gm-Message-State: APjAAAV2E0Y8oe2NMkmC7MSpPmEPrk3EhV87yXVdgV1YBuF82NV9SsV9 zRYbTLMZlA+/RNVETPzXNUzFhXKUkRB8dw== X-Google-Smtp-Source: APXvYqyd8wRwCRMYXC15aGDi6OfNDcsly+vVxS35QozWXkKJL0wi0aUQ10hikWYve1K8R3WpWwZqBQ== X-Received: by 2002:adf:f484:: with SMTP id l4mr6757720wro.207.1580400938111; Thu, 30 Jan 2020 08:15:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr Date: Thu, 30 Jan 2020 16:15:09 +0000 Message-Id: <20200130161533.8180-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The guest can use the semihosting API to open a handle corresponding to QEMU's own stdin, stdout, or stderr. When the guest closes this handle, we should not close the underlying host stdin/stdout/stderr the way we would do if the handle corresponded to a host fd we'd opened on behalf of the guest in SYS_OPEN. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200124172954.28481-1-peter.maydell@linaro.org --- target/arm/arm-semi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 788fe61b51a..8718fd01948 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -403,6 +403,15 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) { CPUARMState *env = &cpu->env; + /* + * Only close the underlying host fd if it's one we opened on behalf + * of the guest in SYS_OPEN. + */ + if (gf->hostfd == STDIN_FILENO || + gf->hostfd == STDOUT_FILENO || + gf->hostfd == STDERR_FILENO) { + return 0; + } return set_swi_errno(env, close(gf->hostfd)); } From patchwork Thu Jan 30 16:15:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231471 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Y92U3Vq/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lpq0HF7z9sRG for ; Fri, 31 Jan 2020 03:16:35 +1100 (AEDT) Received: from localhost ([::1]:34954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCUa-0005MQ-TU for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:16:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42988) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTm-0005D9-43 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTk-0002ok-P6 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:42 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:45339) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTk-0002o5-Il for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:40 -0500 Received: by mail-wr1-x434.google.com with SMTP id a6so4727126wrx.12 for ; Thu, 30 Jan 2020 08:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wkn1AOV8t66g8xUrVaEPWBIHxHvOo4ew4OLKGFBPagg=; b=Y92U3Vq/8+F9aaCQd5GObsJptMvtswkR9yHYa7lYaM9GvLQDeLATHv8WPdVJhu99xt NMoiMl7Y4GHheonndHRW4PzvQHwf9twdZcy0Z/VbJxmQXLDUJFz1wdwmTPIIt9Tn1S+i 3agmceM2+tJXoIakmPwN8neDy/STvzg6wSeC8kTchGhBYMy6Mo3ZxXaug08uWviCW3WB H5dSTlELhFBUeZ5mbN+oLDTibRPzxdsAJXwDZcd7rUeQkUT3TSAxsRBwnZ2heIMgRD7l nsGt2cOgVlP+WUxxMX0MgeFzOsLpqYBqJ/jxBEVOAKWUB4+N5HV3W650Di+ZLzqG9d8r p2KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wkn1AOV8t66g8xUrVaEPWBIHxHvOo4ew4OLKGFBPagg=; b=C3FxozsFMm08YxJcJvuecjpR/3rlw5JoXtQkxuLOXF/xoMiY/pwIMekI9UkE4TMOGx ruzSU/sGEMq/VBCy+Ge0Eg1Qw4c+Me88TUnMmk57ZixwSVjYSkTgFa5nybk7lBZHOQ30 cA2UO6Hy5taLv+WQFVVGeJZK3ONcuYTHkv3CfbV9vVYJq2W9AGsGL23wRNRomFCQwDUH B68brXb4MmoIICeebwIVZdMiaUb9sfll9z8JqPU3ROSsDntblK5JDh8W0tcmZJ5jMHaZ gXp5sYLms3iwdT9rZ0hLyos3KCUtVR0w402CC/49YWqeRyHJVx1uI87DKWBtlH8motfz Mlaw== X-Gm-Message-State: APjAAAV+BnxWcvFBtgQce7vsLb6WI0SL9SHj0kvbqvtrgy98ROPgM55J rRnIHXguAkD/i1i8PIOfmZ0UywG5Bcn2Qw== X-Google-Smtp-Source: APXvYqz1pfazEfbhznFAQG6dJIenf/iz2evA69EAQm9QLdnpIkAdtScXDfsRhjqrup2YTnm1SAFYqg== X-Received: by 2002:a5d:6151:: with SMTP id y17mr6360451wrt.110.1580400939282; Thu, 30 Jan 2020 08:15:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Date: Thu, 30 Jan 2020 16:15:10 +0000 Message-Id: <20200130161533.8180-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jeffery The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Signed-off-by: Cédric Le Goater Message-id: 20200114103433.30534-2-clg@kaod.org [PMM: fixed up to use device_class_set_props()] Signed-off-by: Peter Maydell --- include/hw/sd/aspeed_sdhci.h | 1 + hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 2 ++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index dfdab437902..dffbb46946b 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { SysBusDevice parent; SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; MemoryRegion iomem; qemu_irq irq; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cc06af4fbb3..4174e313cae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -263,7 +263,7 @@ static void aspeed_machine_init(MachineState *machine) amc->i2c_init(bmc); } - for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo = drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 89e4b009504..fb73c4043ea 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -199,6 +199,8 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 99892cbae67..b5e809a1d3f 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -209,6 +209,8 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index cff3eb7dd21..6a039a1d2f1 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS); + sdhci, NULL, sdhci->num_slots); sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); - for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i = 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot = OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = { }, }; +static Property aspeed_sdhci_properties[] = { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) dc->realize = aspeed_sdhci_realize; dc->reset = aspeed_sdhci_reset; dc->vmsd = &vmstate_aspeed_sdhci; + device_class_set_props(dc, aspeed_sdhci_properties); } static TypeInfo aspeed_sdhci_info = { From patchwork Thu Jan 30 16:15:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231476 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller Date: Thu, 30 Jan 2020 16:15:11 +0000 Message-Id: <20200130161533.8180-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jeffery Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater Message-id: 20200114103433.30534-3-clg@kaod.org [ clg : - removed ternary operator from sdhci_attach_drive() - renamed SDHCI objects with a '-controller' prefix ] Signed-off-by: Cédric Le Goater Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 26 +++++++++++++++++--------- hw/arm/aspeed_ast2600.c | 29 ++++++++++++++++++++++++++--- 3 files changed, 45 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e84380984f7..90ac7f7ffa3 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -57,6 +57,7 @@ typedef struct AspeedSoCState { AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; + AspeedSDHCIState emmc; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -126,6 +127,7 @@ enum { ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, + ASPEED_EMMC, }; #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4174e313cae..8702256af1b 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -171,6 +171,19 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, } } +static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) +{ + DeviceState *card; + + card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), + TYPE_SD_CARD); + if (dinfo) { + qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); +} + static void aspeed_machine_init(MachineState *machine) { AspeedBoardState *bmc; @@ -264,16 +277,11 @@ static void aspeed_machine_init(MachineState *machine) } for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { - SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; - DriveInfo *dinfo = drive_get_next(IF_SD); - BlockBackend *blk; - DeviceState *card; + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); + } - blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; - card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), - TYPE_SD_CARD); - qdev_prop_set_drive(card, "drive", blk, &error_fatal); - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); + if (bmc->soc.emmc.num_slots) { + sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); } arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index fb73c4043ea..90cf1c755d3 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_ADC] = 0x1E6E9000, [ASPEED_VIDEO] = 0x1E700000, [ASPEED_SDHCI] = 0x1E740000, + [ASPEED_EMMC] = 0x1E750000, [ASPEED_GPIO] = 0x1E780000, [ASPEED_GPIO_1_8V] = 0x1E780800, [ASPEED_RTC] = 0x1E781000, @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_SOC_AST2600_MAX_IRQ 128 +/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_UART1] = 47, [ASPEED_UART2] = 48, @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_ADC] = 78, [ASPEED_XDMA] = 6, [ASPEED_SDHCI] = 43, + [ASPEED_EMMC] = 15, [ASPEED_GPIO] = 40, [ASPEED_GPIO_1_8V] = 11, [ASPEED_RTC] = 13, @@ -196,16 +199,26 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), sizeof(s->gpio_1_8v), typename); - sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), - TYPE_ASPEED_SDHCI); + sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), + sizeof(s->sdhci), TYPE_ASPEED_SDHCI); object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); /* Init sd card slot class here so that they're under the correct parent */ for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { - sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), + sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", + OBJECT(&s->sdhci.slots[i]), sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); } + + sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), + sizeof(s->emmc), TYPE_ASPEED_SDHCI); + + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); + + sysbus_init_child_obj(obj, "emmc-controller.sdhci", + OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), + TYPE_SYSBUS_SDHCI); } /* @@ -497,6 +510,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_SDHCI)); + + /* eMMC */ + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_soc_get_irq(s, ASPEED_EMMC)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) From patchwork Thu Jan 30 16:15:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231473 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] ftgmac100: check RX and TX buffer alignment Date: Thu, 30 Jan 2020 16:15:12 +0000 Message-Id: <20200130161533.8180-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater These buffers should be aligned on 16 bytes. Ignore invalid RX and TX buffer addresses and log an error. All incoming and outgoing traffic will be dropped because no valid RX or TX descriptors will be available. Signed-off-by: Cédric Le Goater Message-id: 20200114103433.30534-4-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/ftgmac100.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index 4ad2594d3a6..2f92b65d4ef 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -198,6 +198,8 @@ typedef struct { uint32_t des3; } FTGMAC100Desc; +#define FTGMAC100_DESC_ALIGNMENT 16 + /* * Specific RTL8211E MII Registers */ @@ -722,6 +724,12 @@ static void ftgmac100_write(void *opaque, hwaddr addr, s->itc = value; break; case FTGMAC100_RXR_BADR: /* Ring buffer address */ + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%" + HWADDR_PRIx "\n", __func__, value); + return; + } + s->rx_ring = value; s->rx_descriptor = s->rx_ring; break; @@ -731,6 +739,11 @@ static void ftgmac100_write(void *opaque, hwaddr addr, break; case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */ + if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%" + HWADDR_PRIx "\n", __func__, value); + return; + } s->tx_ring = value; s->tx_descriptor = s->tx_ring; break; From patchwork Thu Jan 30 16:15:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=W2hlKuow; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lsB6sWXz9sPJ for ; Fri, 31 Jan 2020 03:18:38 +1100 (AEDT) Received: from localhost ([::1]:35130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCWa-0000SE-OF for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:18:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43057) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTp-0005JT-5H for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTn-0002ri-QV for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:45 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTn-0002qv-It for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:43 -0500 Received: by mail-wr1-x443.google.com with SMTP id z7so4712099wrl.13 for ; Thu, 30 Jan 2020 08:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZWmtOIpfdmdXcrfzwoUW/vZybX7QtXbShko2WRx4PHw=; b=W2hlKuow0Pq4OuC0L4KTU6TjLvhiL+u7gym9QNc7UA/Jbj0oduCZ/2a+yklMW23rD8 MRdzCPqNbNZ5fJsXq3Z6Ms5S+Xvv8wA+a/gs8FbbyL/iD1/tEkqi4Czb7TM/N5l9tfY/ FxCtB6FgDLNpZcIKC0ymfN5dvygy0aXSxC9oIT6mT5CbrZ6/qNRGev2X9boSGYyb0/NH GMsjTvpvNhEU5hRCVqbVSCkQ9QHNDYSXDP71jD68f4ohaZprMeiK9o+uEz2E7jqgEGfC 9s9fY1CvfbkHEFEOmgYfWO1YzK7aB5qO7Qv9ZTD5T+J1K61NqEkdIlgOepTnbXQOwr4H kqjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZWmtOIpfdmdXcrfzwoUW/vZybX7QtXbShko2WRx4PHw=; b=A325niZFF6lAk5p0eiYdHK3WjSHaxrSg37saWRbfqFYbvVLC+B4Ewt6CArnSKVPPu6 Q+bWrZLxa4gHj38tasxpV7kmgagrR9PDzfr6Fi8fsIoeUriUCMOsp+L9h/h8FeuTXL1+ bPymNZ6Tvx8E3Lk/KFDmormcghgqaXrrSOAQdoZtlAzwvRFtBpSulZM8xWymJWQ0oRzj rb+PuiwprbyOnWoaScVxZii+48CCmkMSKs6hM3Ww29PxA6JzYGdBLk0wq9l49tr3d6Ul Nkt0PwNRvIFRZqx9a+75eB5iKr0VK54D5AgVwEFHY8OZEq01+GDug/dfPcNawINUwgr5 W3tQ== X-Gm-Message-State: APjAAAV661Om31d/wn5MAqw6AvRT2xulu4b4G4s5OpX/Q6Y0e7BMwK1m nHbYPZkLpNWZfRRvav8F0wUvQ6WOX5IoBw== X-Google-Smtp-Source: APXvYqzsvymuBcAjsYEheDILVRzyQZ+0kJPpa5CaQo38t1GmvITPG7IQ5BXg74HlbXGsulZz5P9nbQ== X-Received: by 2002:a5d:45c4:: with SMTP id b4mr6274055wrs.303.1580400942292; Thu, 30 Jan 2020 08:15:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0 Date: Thu, 30 Jan 2020 16:15:13 +0000 Message-Id: <20200130161533.8180-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The overhead for the OpenBMC firmware images using the a custom U-Boot is around 2 seconds, which is fine, but with a U-Boot from mainline, it takes an extra 50 seconds or so to reach Linux. A quick survey on the number of reads performed on the flash memory region gives the following figures : OpenBMC U-Boot 922478 (~ 3.5 MBytes) Mainline U-Boot 20569977 (~ 80 MBytes) QEMU must be trashing the TCG TBs and reloading text very often. Some addresses are read more than 250.000 times. Until we find a solution to improve boot time, execution from MMIO is not activated by default. Setting this option also breaks migration compatibility. Signed-off-by: Cédric Le Goater Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200114103433.30534-5-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 4423cd0cda7..18521484b90 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -19,6 +19,8 @@ typedef struct AspeedBoardState AspeedBoardState; typedef struct AspeedMachine { MachineState parent_obj; + + bool mmio_exec; } AspeedMachine; #define ASPEED_MACHINE_CLASS(klass) \ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 8702256af1b..a17843f0d3b 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -261,11 +261,18 @@ static void aspeed_machine_init(MachineState *machine) * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ - memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", - fl->size, &error_abort); - memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, - boot_rom); - write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + if (ASPEED_MACHINE(machine)->mmio_exec) { + memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + &fl->mmio, 0, fl->size); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + } else { + memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", + fl->size, &error_abort); + memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, + boot_rom); + write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); + } } aspeed_board_binfo.ram_size = ram_size; @@ -399,6 +406,30 @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) /* Bus 11: TODO ucd90160@64 */ } +static bool aspeed_get_mmio_exec(Object *obj, Error **errp) +{ + return ASPEED_MACHINE(obj)->mmio_exec; +} + +static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) +{ + ASPEED_MACHINE(obj)->mmio_exec = value; +} + +static void aspeed_machine_instance_init(Object *obj) +{ + ASPEED_MACHINE(obj)->mmio_exec = false; +} + +static void aspeed_machine_class_props_init(ObjectClass *oc) +{ + object_class_property_add_bool(oc, "execute-in-place", + aspeed_get_mmio_exec, + aspeed_set_mmio_exec, &error_abort); + object_class_property_set_description(oc, "execute-in-place", + "boot directly from CE0 flash device", &error_abort); +} + static void aspeed_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -408,6 +439,8 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + + aspeed_machine_class_props_init(oc); } static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) @@ -550,6 +583,7 @@ static const TypeInfo aspeed_machine_types[] = { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(AspeedMachine), + .instance_init = aspeed_machine_instance_init, .class_size = sizeof(AspeedMachineClass), .class_init = aspeed_machine_class_init, .abstract = true, From patchwork Thu Jan 30 16:15:14 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/26] misc/pca9552: Add qom set and get Date: Thu, 30 Jan 2020 16:15:14 +0000 Message-Id: <20200130161533.8180-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Following the pattern of the work recently done with the ASPEED GPIO model, this adds support for inspecting and modifying the PCA9552 LEDs from the monitor. (qemu) qom-set /machine/unattached/device[17] led0 on (qemu) qom-set /machine/unattached/device[17] led0 off (qemu) qom-set /machine/unattached/device[17] led0 pwm0 (qemu) qom-set /machine/unattached/device[17] led0 pwm1 Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20200114103433.30534-6-clg@kaod.org [clg: - removed the "qom-get" examples from the commit log - merged memory leak fixes from Joel ] Signed-off-by: Cédric Le Goater Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/pca9552.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 73be28d9369..efd961e0414 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -15,12 +15,16 @@ #include "hw/misc/pca9552.h" #include "hw/misc/pca9552_regs.h" #include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" #define PCA9552_LED_ON 0x0 #define PCA9552_LED_OFF 0x1 #define PCA9552_LED_PWM0 0x2 #define PCA9552_LED_PWM1 0x3 +static const char *led_state[] = {"on", "off", "pwm0", "pwm1"}; + static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin) { uint8_t reg = PCA9552_LS0 + (pin / 4); @@ -169,6 +173,82 @@ static int pca9552_event(I2CSlave *i2c, enum i2c_event event) return 0; } +static void pca9552_get_led(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9552State *s = PCA9552(obj); + int led, rc, reg; + uint8_t state; + + rc = sscanf(name, "led%2d", &led); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (led < 0 || led > s->nr_leds) { + error_setg(errp, "%s invalid led %s", __func__, name); + return; + } + /* + * Get the LSx register as the qom interface should expose the device + * state, not the modeled 'input line' behaviour which would come from + * reading the INPUTx reg + */ + reg = PCA9552_LS0 + led / 4; + state = (pca9552_read(s, reg) >> (led % 8)) & 0x3; + visit_type_str(v, name, (char **)&led_state[state], errp); +} + +/* + * Return an LED selector register value based on an existing one, with + * the appropriate 2-bit state value set for the given LED number (0-3). + */ +static inline uint8_t pca955x_ledsel(uint8_t oldval, int led_num, int state) +{ + return (oldval & (~(0x3 << (led_num << 1)))) | + ((state & 0x3) << (led_num << 1)); +} + +static void pca9552_set_led(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9552State *s = PCA9552(obj); + Error *local_err = NULL; + int led, rc, reg, val; + uint8_t state; + char *state_str; + + visit_type_str(v, name, &state_str, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + rc = sscanf(name, "led%2d", &led); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (led < 0 || led > s->nr_leds) { + error_setg(errp, "%s invalid led %s", __func__, name); + return; + } + + for (state = 0; state < ARRAY_SIZE(led_state); state++) { + if (!strcmp(state_str, led_state[state])) { + break; + } + } + if (state >= ARRAY_SIZE(led_state)) { + error_setg(errp, "%s invalid led state %s", __func__, state_str); + return; + } + + reg = PCA9552_LS0 + led / 4; + val = pca9552_read(s, reg); + val = pca955x_ledsel(val, led % 4, state); + pca9552_write(s, reg, val); +} + static const VMStateDescription pca9552_vmstate = { .name = "PCA9552", .version_id = 0, @@ -204,6 +284,7 @@ static void pca9552_reset(DeviceState *dev) static void pca9552_initfn(Object *obj) { PCA9552State *s = PCA9552(obj); + int led; /* If support for the other PCA955X devices are implemented, these * constant values might be part of class structure describing the @@ -211,6 +292,15 @@ static void pca9552_initfn(Object *obj) */ s->max_reg = PCA9552_LS3; s->nr_leds = 16; + + for (led = 0; led < s->nr_leds; led++) { + char *name; + + name = g_strdup_printf("led%d", led); + object_property_add(obj, name, "bool", pca9552_get_led, pca9552_set_led, + NULL, NULL, NULL); + g_free(name); + } } static void pca9552_class_init(ObjectClass *klass, void *data) From patchwork Thu Jan 30 16:15:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus' Date: Thu, 30 Jan 2020 16:15:15 +0000 Message-Id: <20200130161533.8180-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Since we enabled parallel TCG code generation for softmmu (see commit 3468b59 "tcg: enable multiple TCG contexts in softmmu") and its subsequent fix (commit 72649619 "add .min_cpus and .default_cpus fields to machine_class"), the raspi machines are restricted to always use their 4 cores: See in hw/arm/raspi2 (with BCM283X_NCPUS set to 4): 222 static void raspi2_machine_init(MachineClass *mc) 223 { 224 mc->desc = "Raspberry Pi 2"; 230 mc->max_cpus = BCM283X_NCPUS; 231 mc->min_cpus = BCM283X_NCPUS; 232 mc->default_cpus = BCM283X_NCPUS; 235 }; 236 DEFINE_MACHINE("raspi2", raspi2_machine_init) We can no longer use the -smp option, as we get: $ qemu-system-arm -M raspi2 -smp 1 qemu-system-arm: Invalid SMP CPUs 1. The min CPUs supported by machine 'raspi2' is 4 Since we can not set the TYPE_BCM283x SOC "enabled-cpus" with -smp, remove the unuseful code. We can achieve the same by using the '-global bcm2836.enabled-cpus=1' option. Reported-by: Laurent Bonnans Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200120235159.18510-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 6a510aafc19..3996f6c63a4 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -192,8 +192,6 @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus", - &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041; object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", &error_abort); From patchwork Thu Jan 30 16:15:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=iyeeVjt1; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lxy6gTdz9sPJ for ; Fri, 31 Jan 2020 03:22:46 +1100 (AEDT) Received: from localhost ([::1]:35338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCaa-0007UM-K5 for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:22:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43119) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTt-0005UT-EY for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTr-0002vP-Gx for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:49 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:50371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTr-0002ud-9N for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:47 -0500 Received: by mail-wm1-x32d.google.com with SMTP id a5so4413202wmb.0 for ; Thu, 30 Jan 2020 08:15:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A81TgHlTRnZzsDa1BQNvoi2SngiMSAXN7zM53gp6FB8=; b=iyeeVjt1Dm9PWBU5eaoG33RIezUAXBTi6+5yjfBS3rbBJ/1UwXCXZ9ng8L3kCav5UY lleHi+WaCbJH9O2KBKTnSjSv5tCVZ1ErHS3FnefVqGfFyFQ8Zioy2/MTeWGzV4ySucpF SmN9OraPm0Ci1r3FhRt4wnJAwVJK+3Ed8deRBFvhqgWll/xzOaz9LwN7/94n7esvvdYV m8/mgLWIDbDV0b9BrmSiUTMDaIObUnbb1m+ExVqNPmDhU+iWE9/pOwYEjY2J4Qip1PNE gQH2+kaPhjN9j90DqJyo4yrBZhnV8ClDIMCod69juoQReVYZRziiXffsYFcCKI3lZj4d v1EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A81TgHlTRnZzsDa1BQNvoi2SngiMSAXN7zM53gp6FB8=; b=kzbg+5ybIdEqZ52Qg51ODsMOpddg6h3DXB713HAhXuV/qehS22iWVlSNq9AUbyN/Lp Gu0nZg904WGIgi3kuEXLkzoWWlKegsq1AOsyWQTgzGNLwlO/vyOL3XpEwhKdV7HE8Kyj JZ2VFO23nP6rbWtDCXjVWJpEpMCoZipZE/Y1ivhNetkGhInfENGVPCLrBsQJIbVUljwS yU0lfiF8+Y9jKcoGdAz1qqZgwV4fvJWdjCJTrLcjTEhkkrqvmF9lo0kVH9ZCxEz7tosr R6+d0SLI8C7sFqWAQXfE7XbxhBJjzIFxJf29JMsC1tYb9+xdgg3Tf/emC4MKEgTC/xrZ m5Wg== X-Gm-Message-State: APjAAAVLdqfnYt7g+1dAY6PYz+i1OedQraNEzDqRIigD+id0hELGaW1d DSeLRUJJh3+x9J8mhlaJnEp0ddgpD9Ecqg== X-Google-Smtp-Source: APXvYqznvuUyI8DACptTpRPkxbvM4Mb7vF0yCBcGp6Vs8pp7JzSb0tSXt4Ph3RxyGIct1uQ96jfo8A== X-Received: by 2002:a05:600c:228f:: with SMTP id 15mr6782165wmf.56.1580400945819; Thu, 30 Jan 2020 08:15:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/26] add device_legacy_reset function to prepare for reset api change Date: Thu, 30 Jan 2020 16:15:16 +0000 Message-Id: <20200130161533.8180-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Provide a temporary device_legacy_reset function doing what device_reset does to prepare for the transition with Resettable API. All occurrence of device_reset in the code tree are also replaced by device_legacy_reset. The new resettable API has different prototype and semantics (resetting child buses as well as the specified device). Subsequent commits will make the changeover for each call site individually; once that is complete device_legacy_reset() will be removed. Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Acked-by: David Gibson Acked-by: Cornelia Huck Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-2-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/qdev-core.h | 4 ++-- hw/audio/intel-hda.c | 2 +- hw/core/qdev.c | 6 +++--- hw/hyperv/hyperv.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/ide/microdrive.c | 8 ++++---- hw/intc/spapr_xive.c | 2 +- hw/ppc/pnv_psi.c | 4 ++-- hw/ppc/spapr_pci.c | 2 +- hw/ppc/spapr_vio.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- hw/scsi/vmw_pvscsi.c | 2 +- hw/sd/omap_mmc.c | 2 +- hw/sd/pl181.c | 2 +- 15 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 5da94f872a8..627d653dc16 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -432,11 +432,11 @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev); void qdev_machine_init(void); /** - * @device_reset + * device_legacy_reset: * * Reset a single device (by calling the reset method). */ -void device_reset(DeviceState *dev); +void device_legacy_reset(DeviceState *dev); void device_class_set_props(DeviceClass *dc, Property *props); diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index e96a707ac50..1bcc3e5cf80 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -1087,7 +1087,7 @@ static void intel_hda_reset(DeviceState *dev) QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { DeviceState *qdev = kid->child; cdev = HDA_CODEC_DEVICE(qdev); - device_reset(DEVICE(cdev)); + device_legacy_reset(DEVICE(cdev)); d->state_sts |= (1 << cdev->cad); } intel_hda_update_irq(d); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 05c31df52d7..00230eecb77 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -298,7 +298,7 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) static int qdev_reset_one(DeviceState *dev, void *opaque) { - device_reset(dev); + device_legacy_reset(dev); return 0; } @@ -867,7 +867,7 @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } if (dev->hotplugged) { - device_reset(dev); + device_legacy_reset(dev); } dev->pending_deleted_event = false; @@ -1101,7 +1101,7 @@ void device_class_set_parent_unrealize(DeviceClass *dc, dc->unrealize = dev_unrealize; } -void device_reset(DeviceState *dev) +void device_legacy_reset(DeviceState *dev) { DeviceClass *klass = DEVICE_GET_CLASS(dev); diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index da8ce82725c..8ca3706f5b0 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -140,7 +140,7 @@ void hyperv_synic_reset(CPUState *cs) SynICState *synic = get_synic(cs); if (synic) { - device_reset(DEVICE(synic)); + device_legacy_reset(DEVICE(synic)); } } diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 827ce29e58f..d23485108d9 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -370,7 +370,7 @@ static void microvm_machine_reset(MachineState *machine) cpu = X86_CPU(cs); if (cpu->apic_state) { - device_reset(cpu->apic_state); + device_legacy_reset(cpu->apic_state); } } } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a6302a772d1..2ddce4230a8 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1879,7 +1879,7 @@ static void pc_machine_reset(MachineState *machine) cpu = X86_CPU(cs); if (cpu->apic_state) { - device_reset(cpu->apic_state); + device_legacy_reset(cpu->apic_state); } } } diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c index b0272ea14b3..6b30e36ed83 100644 --- a/hw/ide/microdrive.c +++ b/hw/ide/microdrive.c @@ -173,7 +173,7 @@ static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value) case 0x00: /* Configuration Option Register */ s->opt = value & 0xcf; if (value & OPT_SRESET) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -316,7 +316,7 @@ static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value) case 0xe: /* Device Control */ s->ctrl = value; if (value & CTRL_SRST) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -541,7 +541,7 @@ static int dscm1xxxx_attach(PCMCIACardState *card) md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8); md->io_base = 0x0; - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); md_interrupt_update(md); return 0; @@ -551,7 +551,7 @@ static int dscm1xxxx_detach(PCMCIACardState *card) { MicroDriveState *md = MICRODRIVE(card); - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); return 0; } diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 024b8ce2852..20c8155557d 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -1766,7 +1766,7 @@ static target_ulong h_int_reset(PowerPCCPU *cpu, return H_PARAMETER; } - device_reset(DEVICE(xive)); + device_legacy_reset(DEVICE(xive)); if (kvm_irqchip_in_kernel()) { Error *local_err = NULL; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 6baf9503a1c..c34a49b000f 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -466,7 +466,7 @@ static void pnv_psi_reset(DeviceState *dev) static void pnv_psi_reset_handler(void *dev) { - device_reset(DEVICE(dev)); + device_legacy_reset(DEVICE(dev)); } static void pnv_psi_realize(DeviceState *dev, Error **errp) @@ -715,7 +715,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, break; case PSIHB9_INTERRUPT_CONTROL: if (val & PSIHB9_IRQ_RESET) { - device_reset(DEVICE(&psi9->source)); + device_legacy_reset(DEVICE(&psi9->source)); } psi->regs[reg] = val; break; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index e82bfc5ca7c..709a52780dd 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2014,7 +2014,7 @@ static int spapr_phb_children_reset(Object *child, void *opaque) DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); if (dev) { - device_reset(dev); + device_legacy_reset(dev); } return 0; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 554de9930dc..f14944e9007 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -304,7 +304,7 @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) static void spapr_vio_quiesce_one(SpaprVioDevice *dev) { if (dev->tcet) { - device_reset(DEVICE(dev->tcet)); + device_legacy_reset(DEVICE(dev->tcet)); } free_crq(dev); } diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 92c7e45df5f..2f7a7d7bd1b 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -243,7 +243,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); goto out; } - device_reset(DEVICE(pbdev)); + device_legacy_reset(DEVICE(pbdev)); pbdev->fh &= ~FH_MASK_ENABLE; pbdev->state = ZPCI_FS_DISABLED; stl_p(&ressetpci->fh, pbdev->fh); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 8f1aaf9c874..e4ee2e66435 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -838,7 +838,7 @@ pvscsi_on_cmd_reset_device(PVSCSIState *s) if (sdev != NULL) { s->resetting++; - device_reset(&sdev->qdev); + device_legacy_reset(&sdev->qdev); s->resetting--; return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; } diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index c6e516b6113..4088a8a80bc 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -318,7 +318,7 @@ void omap_mmc_reset(struct omap_mmc_s *host) * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. */ - device_reset(DEVICE(host->card)); + device_legacy_reset(DEVICE(host->card)); } static uint64_t omap_mmc_read(void *opaque, hwaddr offset, diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index 8033fe455d8..2b3776a6a0f 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -482,7 +482,7 @@ static void pl181_reset(DeviceState *d) /* Since we're still using the legacy SD API the card is not plugged * into any bus, and we must reset it manually. */ - device_reset(DEVICE(s->card)); + device_legacy_reset(DEVICE(s->card)); } static void pl181_init(Object *obj) From patchwork Thu Jan 30 16:15:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231484 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gOwsLBAk; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lxt2ZBpz9sPJ for ; Fri, 31 Jan 2020 03:22:42 +1100 (AEDT) Received: from localhost ([::1]:35330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCaW-0007M1-9o for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:22:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43123) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTt-0005VV-To for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTs-0002wQ-Gx for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:49 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:52554) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTs-0002va-AZ for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:48 -0500 Received: by mail-wm1-x32f.google.com with SMTP id p9so4409378wmc.2 for ; Thu, 30 Jan 2020 08:15:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LRMkbeW5JbDxshKRBpUKtYjp3nf3vc5OCTS76DvNo+w=; b=gOwsLBAkV3EOZS+Q2IB/oBH9hxdrrgWPQj3VGlIhedGB9Fw6qHTTtOmxZfAARaBFOr QmkM4c38cdbCrFr+BnX5JpUTh3FS31Lcg7wMz2kvVULCh/Mn86spHDPaZZNgo65tIE2H BeyvTwFnYA0YBVaKgOzHUF2aqv2/mgHkOuHatVVeTYWzLUF7uhGByGtoDQbcEV4stDIH j0fqiDIW0ruDqRZHGMljC9nM5P3kjzBYXVeLSx5CBK47uWRgGOZvwFwobl3a84vsBRYf ES6zwlDp2F0e/akLVtF5ML1uHsL+AE2ZbkcYlAY+VT79SjVn8jDn/Yw5oqurEfds/CCv fPVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LRMkbeW5JbDxshKRBpUKtYjp3nf3vc5OCTS76DvNo+w=; b=ZuzJ5Z+ORwIyBfjmp0VPWnAuBpIzljkxzWW4j82MvSy+H5KU14MY8H//TFBQhqySeO HHkEDzUCi/MTjd3P5vq+PzEWNtOqSsdmYnT/T8ZadE9n56hosHuX82IG5rnF5PQCEPR0 aURApZK6u+uzUf9QakjiuHHe2JPqkLAAwen1nngs/aU/+heeRS12YESB4aRlXfPXP7H2 7uWXGzqLI8qytGj3b+SPdmmuzY8+d66pvOFbIDGwaMLzVHCXpKSnHj9UtuGaNN0OoHt2 7wcdzfvJiOEcTmmPkLbV4Zdx23V3dfuEAJZCCmFZn7HcJYiaXYYjop83QcSXZYi1xGMb 0tlA== X-Gm-Message-State: APjAAAXcU8Zxpi+MjJSUD6scCExg69UwYZacn29+tdv3NDDZEuBaq9il wmHrelKaSD2f4K/CPYXXS3t7JGQ16E90zw== X-Google-Smtp-Source: APXvYqxVzdGkxH04DhP+yFcCKsYsyajvGowfEm9V5Ck7O1UaelXFMJvIjjsLrxGNT4Pl0v4bTkwgwg== X-Received: by 2002:a05:600c:21c6:: with SMTP id x6mr6453435wmj.177.1580400946862; Thu, 30 Jan 2020 08:15:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition Date: Thu, 30 Jan 2020 16:15:17 +0000 Message-Id: <20200130161533.8180-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Adds trace events to reset procedure and when updating the parent bus of a device. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cornelia Huck Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-3-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/core/qdev.c | 29 ++++++++++++++++++++++++++--- hw/core/trace-events | 9 +++++++++ 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 00230eecb77..29e8c6b8dfc 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -38,6 +38,7 @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "trace.h" bool qdev_hotplug = false; static bool qdev_hot_added = false; @@ -98,7 +99,11 @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) bool replugging = dev->parent_bus != NULL; if (replugging) { - /* Keep a reference to the device while it's not plugged into + trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), + dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), + OBJECT(bus), object_get_typename(OBJECT(bus))); + /* + * Keep a reference to the device while it's not plugged into * any bus, to avoid it potentially evaporating when it is * dereffed in bus_remove_child(). */ @@ -296,6 +301,18 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) return hotplug_ctrl; } +static int qdev_prereset(DeviceState *dev, void *opaque) +{ + trace_qdev_reset_tree(dev, object_get_typename(OBJECT(dev))); + return 0; +} + +static int qbus_prereset(BusState *bus, void *opaque) +{ + trace_qbus_reset_tree(bus, object_get_typename(OBJECT(bus))); + return 0; +} + static int qdev_reset_one(DeviceState *dev, void *opaque) { device_legacy_reset(dev); @@ -306,6 +323,7 @@ static int qdev_reset_one(DeviceState *dev, void *opaque) static int qbus_reset_one(BusState *bus, void *opaque) { BusClass *bc = BUS_GET_CLASS(bus); + trace_qbus_reset(bus, object_get_typename(OBJECT(bus))); if (bc->reset) { bc->reset(bus); } @@ -314,7 +332,9 @@ static int qbus_reset_one(BusState *bus, void *opaque) void qdev_reset_all(DeviceState *dev) { - qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + trace_qdev_reset_all(dev, object_get_typename(OBJECT(dev))); + qdev_walk_children(dev, qdev_prereset, qbus_prereset, + qdev_reset_one, qbus_reset_one, NULL); } void qdev_reset_all_fn(void *opaque) @@ -324,7 +344,9 @@ void qdev_reset_all_fn(void *opaque) void qbus_reset_all(BusState *bus) { - qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + trace_qbus_reset_all(bus, object_get_typename(OBJECT(bus))); + qbus_walk_children(bus, qdev_prereset, qbus_prereset, + qdev_reset_one, qbus_reset_one, NULL); } void qbus_reset_all_fn(void *opaque) @@ -1105,6 +1127,7 @@ void device_legacy_reset(DeviceState *dev) { DeviceClass *klass = DEVICE_GET_CLASS(dev); + trace_qdev_reset(dev, object_get_typename(OBJECT(dev))); if (klass->reset) { klass->reset(dev); } diff --git a/hw/core/trace-events b/hw/core/trace-events index fe47a9c8cb1..a375aa88a48 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -1,2 +1,11 @@ # loader.c loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d" + +# qdev.c +qdev_reset(void *obj, const char *objtype) "obj=%p(%s)" +qdev_reset_all(void *obj, const char *objtype) "obj=%p(%s)" +qdev_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" +qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" +qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" From patchwork Thu Jan 30 16:15:18 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/26] hw/core: create Resettable QOM interface Date: Thu, 30 Jan 2020 16:15:18 +0000 Message-Id: <20200130161533.8180-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde This commit defines an interface allowing multi-phase reset. This aims to solve a problem of the actual single-phase reset (built in DeviceClass and BusClass): reset behavior is dependent on the order in which reset handlers are called. In particular doing external side-effect (like setting an qemu_irq) is problematic because receiving object may not be reset yet. The Resettable interface divides the reset in 3 well defined phases. To reset an object tree, all 1st phases are executed then all 2nd then all 3rd. See the comments in include/hw/resettable.h for a more complete description. The interface defines 3 phases to let the future possibility of holding an object into reset for some time. The qdev/qbus reset in DeviceClass and BusClass will be modified in following commits to use this interface. A mechanism is provided to allow executing a transitional reset handler in place of the 2nd phase which is executed in children-then-parent order inside a tree. This will allow to transition devices and buses smoothly while keeping the exact current qdev/qbus reset behavior for now. Documentation will be added in a following commit. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-4-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/core/Makefile.objs | 1 + include/hw/resettable.h | 211 +++++++++++++++++++++++++++++++++++ hw/core/resettable.c | 238 ++++++++++++++++++++++++++++++++++++++++ hw/core/trace-events | 17 +++ 4 files changed, 467 insertions(+) create mode 100644 include/hw/resettable.h create mode 100644 hw/core/resettable.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index a522b7297d3..9e41ec9a15d 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -2,6 +2,7 @@ common-obj-y += qdev.o qdev-properties.o common-obj-y += bus.o common-obj-y += cpu.o +common-obj-y += resettable.o common-obj-y += hotplug.o common-obj-y += vmstate-if.o # irq.o needed for qdev GPIO handling: diff --git a/include/hw/resettable.h b/include/hw/resettable.h new file mode 100644 index 00000000000..c0b9fc6ad62 --- /dev/null +++ b/include/hw/resettable.h @@ -0,0 +1,211 @@ +/* + * Resettable interface header. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_RESETTABLE_H +#define HW_RESETTABLE_H + +#include "qom/object.h" + +#define TYPE_RESETTABLE_INTERFACE "resettable" + +#define RESETTABLE_CLASS(class) \ + OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE_INTERFACE) + +#define RESETTABLE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE_INTERFACE) + +typedef struct ResettableState ResettableState; + +/** + * ResetType: + * Types of reset. + * + * + Cold: reset resulting from a power cycle of the object. + * + * TODO: Support has to be added to handle more types. In particular, + * ResettableState structure needs to be expanded. + */ +typedef enum ResetType { + RESET_TYPE_COLD, +} ResetType; + +/* + * ResettableClass: + * Interface for resettable objects. + * + * See docs/devel/reset.rst for more detailed information about how QEMU models + * reset. This whole API must only be used when holding the iothread mutex. + * + * All objects which can be reset must implement this interface; + * it is usually provided by a base class such as DeviceClass or BusClass. + * Every Resettable object must maintain some state tracking the + * progress of a reset operation by providing a ResettableState structure. + * The functions defined in this module take care of updating the + * state of the reset. + * The base class implementation of the interface provides this + * state and implements the associated method: get_state. + * + * Concrete object implementations (typically specific devices + * such as a UART model) should provide the functions + * for the phases.enter, phases.hold and phases.exit methods, which + * they can set in their class init function, either directly or + * by calling resettable_class_set_parent_phases(). + * The phase methods are guaranteed to only only ever be called once + * for any reset event, in the order 'enter', 'hold', 'exit'. + * An object will always move quickly from 'enter' to 'hold' + * but might remain in 'hold' for an arbitrary period of time + * before eventually reset is deasserted and the 'exit' phase is called. + * Object implementations should be prepared for functions handling + * inbound connections from other devices (such as qemu_irq handler + * functions) to be called at any point during reset after their + * 'enter' method has been called. + * + * Users of a resettable object should not call these methods + * directly, but instead use the function resettable_reset(). + * + * @phases.enter: This phase is called when the object enters reset. It + * should reset local state of the object, but it must not do anything that + * has a side-effect on other objects, such as raising or lowering a qemu_irq + * line or reading or writing guest memory. It takes the reset's type as + * argument. + * + * @phases.hold: This phase is called for entry into reset, once every object + * in the system which is being reset has had its @phases.enter method called. + * At this point devices can do actions that affect other objects. + * + * @phases.exit: This phase is called when the object leaves the reset state. + * Actions affecting other objects are permitted. + * + * @get_state: Mandatory method which must return a pointer to a + * ResettableState. + * + * @get_transitional_function: transitional method to handle Resettable objects + * not yet fully moved to this interface. It will be removed as soon as it is + * not needed anymore. This method is optional and may return a pointer to a + * function to be used instead of the phases. If the method exists and returns + * a non-NULL function pointer then that function is executed as a replacement + * of the 'hold' phase method taking the object as argument. The two other phase + * methods are not executed. + * + * @child_foreach: Executes a given callback on every Resettable child. Child + * in this context means a child in the qbus tree, so the children of a qbus + * are the devices on it, and the children of a device are all the buses it + * owns. This is not the same as the QOM object hierarchy. The function takes + * additional opaque and ResetType arguments which must be passed unmodified to + * the callback. + */ +typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); +typedef void (*ResettableHoldPhase)(Object *obj); +typedef void (*ResettableExitPhase)(Object *obj); +typedef ResettableState * (*ResettableGetState)(Object *obj); +typedef void (*ResettableTrFunction)(Object *obj); +typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); +typedef void (*ResettableChildCallback)(Object *, void *opaque, + ResetType type); +typedef void (*ResettableChildForeach)(Object *obj, + ResettableChildCallback cb, + void *opaque, ResetType type); +typedef struct ResettablePhases { + ResettableEnterPhase enter; + ResettableHoldPhase hold; + ResettableExitPhase exit; +} ResettablePhases; +typedef struct ResettableClass { + InterfaceClass parent_class; + + /* Phase methods */ + ResettablePhases phases; + + /* State access method */ + ResettableGetState get_state; + + /* Transitional method for legacy reset compatibility */ + ResettableGetTrFunction get_transitional_function; + + /* Hierarchy handling method */ + ResettableChildForeach child_foreach; +} ResettableClass; + +/** + * ResettableState: + * Structure holding reset related state. The fields should not be accessed + * directly; the definition is here to allow further inclusion into other + * objects. + * + * @count: Number of reset level the object is into. It is incremented when + * the reset operation starts and decremented when it finishes. + * @hold_phase_pending: flag which indicates that we need to invoke the 'hold' + * phase handler for this object. + * @exit_phase_in_progress: true if we are currently in the exit phase + */ +struct ResettableState { + unsigned count; + bool hold_phase_pending; + bool exit_phase_in_progress; +}; + +/** + * resettable_reset: + * Trigger a reset on an object @obj of type @type. @obj must implement + * Resettable interface. + * + * Calling this function is equivalent to calling @resettable_assert_reset() + * then @resettable_release_reset(). + */ +void resettable_reset(Object *obj, ResetType type); + +/** + * resettable_assert_reset: + * Put an object @obj into reset. @obj must implement Resettable interface. + * + * @resettable_release_reset() must eventually be called after this call. + * There must be one call to @resettable_release_reset() per call of + * @resettable_assert_reset(), with the same type argument. + * + * NOTE: Until support for migration is added, the @resettable_release_reset() + * must not be delayed. It must occur just after @resettable_assert_reset() so + * that migration cannot be triggered in between. Prefer using + * @resettable_reset() for now. + */ +void resettable_assert_reset(Object *obj, ResetType type); + +/** + * resettable_release_reset: + * Release the object @obj from reset. @obj must implement Resettable interface. + * + * See @resettable_assert_reset() description for details. + */ +void resettable_release_reset(Object *obj, ResetType type); + +/** + * resettable_is_in_reset: + * Return true if @obj is under reset. + * + * @obj must implement Resettable interface. + */ +bool resettable_is_in_reset(Object *obj); + +/** + * resettable_class_set_parent_phases: + * + * Save @rc current reset phases into @parent_phases and override @rc phases + * by the given new methods (@enter, @hold and @exit). + * Each phase is overridden only if the new one is not NULL allowing to + * override a subset of phases. + */ +void resettable_class_set_parent_phases(ResettableClass *rc, + ResettableEnterPhase enter, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_phases); + +#endif diff --git a/hw/core/resettable.c b/hw/core/resettable.c new file mode 100644 index 00000000000..91332084870 --- /dev/null +++ b/hw/core/resettable.c @@ -0,0 +1,238 @@ +/* + * Resettable interface. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "hw/resettable.h" +#include "trace.h" + +/** + * resettable_phase_enter/hold/exit: + * Function executing a phase recursively in a resettable object and its + * children. + */ +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type); +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type); +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); + +/** + * enter_phase_in_progress: + * True if we are currently in reset enter phase. + * + * Note: This flag is only used to guarantee (using asserts) that the reset + * API is used correctly. We can use a global variable because we rely on the + * iothread mutex to ensure only one reset operation is in a progress at a + * given time. + */ +static bool enter_phase_in_progress; + +void resettable_reset(Object *obj, ResetType type) +{ + trace_resettable_reset(obj, type); + resettable_assert_reset(obj, type); + resettable_release_reset(obj, type); +} + +void resettable_assert_reset(Object *obj, ResetType type) +{ + /* TODO: change this assert when adding support for other reset types */ + assert(type == RESET_TYPE_COLD); + trace_resettable_reset_assert_begin(obj, type); + assert(!enter_phase_in_progress); + + enter_phase_in_progress = true; + resettable_phase_enter(obj, NULL, type); + enter_phase_in_progress = false; + + resettable_phase_hold(obj, NULL, type); + + trace_resettable_reset_assert_end(obj); +} + +void resettable_release_reset(Object *obj, ResetType type) +{ + /* TODO: change this assert when adding support for other reset types */ + assert(type == RESET_TYPE_COLD); + trace_resettable_reset_release_begin(obj, type); + assert(!enter_phase_in_progress); + + resettable_phase_exit(obj, NULL, type); + + trace_resettable_reset_release_end(obj); +} + +bool resettable_is_in_reset(Object *obj) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + + return s->count > 0; +} + +/** + * resettable_child_foreach: + * helper to avoid checking the existence of the method. + */ +static void resettable_child_foreach(ResettableClass *rc, Object *obj, + ResettableChildCallback cb, + void *opaque, ResetType type) +{ + if (rc->child_foreach) { + rc->child_foreach(obj, cb, opaque, type); + } +} + +/** + * resettable_get_tr_func: + * helper to fetch transitional reset callback if any. + */ +static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc, + Object *obj) +{ + ResettableTrFunction tr_func = NULL; + if (rc->get_transitional_function) { + tr_func = rc->get_transitional_function(obj); + } + return tr_func; +} + +static void resettable_phase_enter(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + bool action_needed = false; + + /* exit phase has to finish properly before entering back in reset */ + assert(!s->exit_phase_in_progress); + + trace_resettable_phase_enter_begin(obj, obj_typename, s->count, type); + + /* Only take action if we really enter reset for the 1st time. */ + /* + * TODO: if adding more ResetType support, some additional checks + * are probably needed here. + */ + if (s->count++ == 0) { + action_needed = true; + } + /* + * We limit the count to an arbitrary "big" value. The value is big + * enough not to be triggered normally. + * The assert will stop an infinite loop if there is a cycle in the + * reset tree. The loop goes through resettable_foreach_child below + * which at some point will call us again. + */ + assert(s->count <= 50); + + /* + * handle the children even if action_needed is at false so that + * child counts are incremented too + */ + resettable_child_foreach(rc, obj, resettable_phase_enter, NULL, type); + + /* execute enter phase for the object if needed */ + if (action_needed) { + trace_resettable_phase_enter_exec(obj, obj_typename, type, + !!rc->phases.enter); + if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) { + rc->phases.enter(obj, type); + } + s->hold_phase_pending = true; + } + trace_resettable_phase_enter_end(obj, obj_typename, s->count); +} + +static void resettable_phase_hold(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + + /* exit phase has to finish properly before entering back in reset */ + assert(!s->exit_phase_in_progress); + + trace_resettable_phase_hold_begin(obj, obj_typename, s->count, type); + + /* handle children first */ + resettable_child_foreach(rc, obj, resettable_phase_hold, NULL, type); + + /* exec hold phase */ + if (s->hold_phase_pending) { + s->hold_phase_pending = false; + ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj); + trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); + if (tr_func) { + trace_resettable_transitional_function(obj, obj_typename); + tr_func(obj); + } else if (rc->phases.hold) { + rc->phases.hold(obj); + } + } + trace_resettable_phase_hold_end(obj, obj_typename, s->count); +} + +static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + const char *obj_typename = object_get_typename(obj); + + assert(!s->exit_phase_in_progress); + trace_resettable_phase_exit_begin(obj, obj_typename, s->count, type); + + /* exit_phase_in_progress ensures this phase is 'atomic' */ + s->exit_phase_in_progress = true; + resettable_child_foreach(rc, obj, resettable_phase_exit, NULL, type); + + assert(s->count > 0); + if (s->count == 1) { + trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); + if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { + rc->phases.exit(obj); + } + s->count = 0; + } + s->exit_phase_in_progress = false; + trace_resettable_phase_exit_end(obj, obj_typename, s->count); +} + +void resettable_class_set_parent_phases(ResettableClass *rc, + ResettableEnterPhase enter, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_phases) +{ + *parent_phases = rc->phases; + if (enter) { + rc->phases.enter = enter; + } + if (hold) { + rc->phases.hold = hold; + } + if (exit) { + rc->phases.exit = exit; + } +} + +static const TypeInfo resettable_interface_info = { + .name = TYPE_RESETTABLE_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(ResettableClass), +}; + +static void reset_register_types(void) +{ + type_register_static(&resettable_interface_info); +} + +type_init(reset_register_types) diff --git a/hw/core/trace-events b/hw/core/trace-events index a375aa88a48..77d61cb66e6 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -9,3 +9,20 @@ qbus_reset(void *obj, const char *objtype) "obj=%p(%s)" qbus_reset_all(void *obj, const char *objtype) "obj=%p(%s)" qbus_reset_tree(void *obj, const char *objtype) "obj=%p(%s)" qdev_update_parent_bus(void *obj, const char *objtype, void *oldp, const char *oldptype, void *newp, const char *newptype) "obj=%p(%s) old_parent=%p(%s) new_parent=%p(%s)" + +# resettable.c +resettable_reset(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_assert_end(void *obj) "obj=%p" +resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" +resettable_reset_release_end(void *obj) "obj=%p" +resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" +resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_phase_hold_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_hold_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" +resettable_phase_hold_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_phase_exit_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" +resettable_phase_exit_exec(void *obj, const char *objtype, int has_method) "obj=%p(%s) method=%d" +resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" +resettable_transitional_function(void *obj, const char *objtype) "obj=%p(%s)" From patchwork Thu Jan 30 16:15:19 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass Date: Thu, 30 Jan 2020 16:15:19 +0000 Message-Id: <20200130161533.8180-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde This commit adds support of Resettable interface to buses and devices: + ResettableState structure is added in the Bus/Device state + Resettable methods are implemented. + device/bus_is_in_reset function defined This commit allows to transition the objects to the new multi-phase interface without changing the reset behavior at all. Object single reset method can be split into the 3 different phases but the 3 phases are still executed in a row for a given object. From the qdev/qbus reset api point of view, nothing is changed. qdev_reset_all() and qbus_reset_all() are not modified as well as device_legacy_reset(). Transition of an object must be done from parent class to child class. Care has been taken to allow the transition of a parent class without requiring the child classes to be transitioned at the same time. Note that SysBus and SysBusDevice class do not need any transition because they do not override the legacy reset method. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-5-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- tests/Makefile.include | 1 + include/hw/qdev-core.h | 27 ++++++++++++ hw/core/bus.c | 97 ++++++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 93 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 218 insertions(+) diff --git a/tests/Makefile.include b/tests/Makefile.include index c6827ce8c29..a1bff5dcce0 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -429,6 +429,7 @@ tests/fp/%: tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ hw/core/bus.o \ + hw/core/resettable.o \ hw/core/irq.o \ hw/core/fw-path-provider.o \ hw/core/reset.o \ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 627d653dc16..09b7a441eb6 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -5,6 +5,7 @@ #include "qemu/bitmap.h" #include "qom/object.h" #include "hw/hotplug.h" +#include "hw/resettable.h" enum { DEV_NVECTORS_UNSPECIFIED = -1, @@ -122,6 +123,11 @@ typedef struct DeviceClass { bool hotpluggable; /* callbacks */ + /* + * Reset method here is deprecated and replaced by methods in the + * resettable class interface to implement a multi-phase reset. + * TODO: remove once every reset callback is unused + */ DeviceReset reset; DeviceRealize realize; DeviceUnrealize unrealize; @@ -146,6 +152,7 @@ struct NamedGPIOList { /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. + * @reset: ResettableState for the device; handled by Resettable interface. * * This structure should not be accessed directly. We declare it here * so that it can be embedded in individual device state structures. @@ -168,6 +175,7 @@ struct DeviceState { int num_child_bus; int instance_id_alias; int alias_required_for_version; + ResettableState reset; }; struct DeviceListener { @@ -220,6 +228,7 @@ typedef struct BusChild { /** * BusState: * @hotplug_handler: link to a hotplug handler associated with bus. + * @reset: ResettableState for the bus; handled by Resettable interface. */ struct BusState { Object obj; @@ -231,6 +240,7 @@ struct BusState { int num_children; QTAILQ_HEAD(, BusChild) children; QLIST_ENTRY(BusState) sibling; + ResettableState reset; }; /** @@ -417,6 +427,18 @@ void qdev_reset_all_fn(void *opaque); void qbus_reset_all(BusState *bus); void qbus_reset_all_fn(void *opaque); +/** + * device_is_in_reset: + * Return true if the device @dev is currently being reset. + */ +bool device_is_in_reset(DeviceState *dev); + +/** + * bus_is_in_reset: + * Return true if the bus @bus is currently being reset. + */ +bool bus_is_in_reset(BusState *bus); + /* This should go away once we get rid of the NULL bus hack */ BusState *sysbus_get_default(void); @@ -440,6 +462,11 @@ void device_legacy_reset(DeviceState *dev); void device_class_set_props(DeviceClass *dc, Property *props); +/** + * device_class_set_parent_reset: + * TODO: remove the function when DeviceClass's reset method + * is not used anymore. + */ void device_class_set_parent_reset(DeviceClass *dc, DeviceReset dev_reset, DeviceReset *parent_reset); diff --git a/hw/core/bus.c b/hw/core/bus.c index 7f3d2a3dbda..2698f715bd7 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -68,6 +68,28 @@ int qbus_walk_children(BusState *bus, return 0; } +bool bus_is_in_reset(BusState *bus) +{ + return resettable_is_in_reset(OBJECT(bus)); +} + +static ResettableState *bus_get_reset_state(Object *obj) +{ + BusState *bus = BUS(obj); + return &bus->reset; +} + +static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb, + void *opaque, ResetType type) +{ + BusState *bus = BUS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + cb(OBJECT(kid->child), opaque, type); + } +} + static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) { const char *typename = object_get_typename(OBJECT(bus)); @@ -199,12 +221,83 @@ static char *default_bus_get_fw_dev_path(DeviceState *dev) return g_strdup(object_get_typename(OBJECT(dev))); } +/** + * bus_phases_reset: + * Transition reset method for buses to allow moving + * smoothly from legacy reset method to multi-phases + */ +static void bus_phases_reset(BusState *bus) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(bus); + + if (rc->phases.enter) { + rc->phases.enter(OBJECT(bus), RESET_TYPE_COLD); + } + if (rc->phases.hold) { + rc->phases.hold(OBJECT(bus)); + } + if (rc->phases.exit) { + rc->phases.exit(OBJECT(bus)); + } +} + +static void bus_transitional_reset(Object *obj) +{ + BusClass *bc = BUS_GET_CLASS(obj); + + /* + * This will call either @bus_phases_reset (for multi-phases transitioned + * buses) or a bus's specific method for not-yet transitioned buses. + * In both case, it does not reset children. + */ + if (bc->reset) { + bc->reset(BUS(obj)); + } +} + +/** + * bus_get_transitional_reset: + * check if the bus's class is ready for multi-phase + */ +static ResettableTrFunction bus_get_transitional_reset(Object *obj) +{ + BusClass *dc = BUS_GET_CLASS(obj); + if (dc->reset != bus_phases_reset) { + /* + * dc->reset has been overridden by a subclass, + * the bus is not ready for multi phase yet. + */ + return bus_transitional_reset; + } + return NULL; +} + static void bus_class_init(ObjectClass *class, void *data) { BusClass *bc = BUS_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = bus_unparent; bc->get_fw_dev_path = default_bus_get_fw_dev_path; + + rc->get_state = bus_get_reset_state; + rc->child_foreach = bus_reset_child_foreach; + + /* + * @bus_phases_reset is put as the default reset method below, allowing + * to do the multi-phase transition from base classes to leaf classes. It + * allows a legacy-reset Bus class to extend a multi-phases-reset + * Bus class for the following reason: + * + If a base class B has been moved to multi-phase, then it does not + * override this default reset method and may have defined phase methods. + * + A child class C (extending class B) which uses + * bus_class_set_parent_reset() (or similar means) to override the + * reset method will still work as expected. @bus_phases_reset function + * will be registered as the parent reset method and effectively call + * parent reset phases. + */ + bc->reset = bus_phases_reset; + rc->get_transitional_function = bus_get_transitional_reset; } static void qbus_finalize(Object *obj) @@ -223,6 +316,10 @@ static const TypeInfo bus_info = { .instance_init = qbus_initfn, .instance_finalize = qbus_finalize, .class_init = bus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_RESETTABLE_INTERFACE }, + { } + }, }; static void bus_register_types(void) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 29e8c6b8dfc..b2affd8f92b 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -355,6 +355,28 @@ void qbus_reset_all_fn(void *opaque) qbus_reset_all(bus); } +bool device_is_in_reset(DeviceState *dev) +{ + return resettable_is_in_reset(OBJECT(dev)); +} + +static ResettableState *device_get_reset_state(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + return &dev->reset; +} + +static void device_reset_child_foreach(Object *obj, ResettableChildCallback cb, + void *opaque, ResetType type) +{ + DeviceState *dev = DEVICE(obj); + BusState *bus; + + QLIST_FOREACH(bus, &dev->child_bus, sibling) { + cb(OBJECT(bus), opaque, type); + } +} + /* can be used as ->unplug() callback for the simple cases */ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) @@ -1057,10 +1079,62 @@ device_vmstate_if_get_id(VMStateIf *obj) return qdev_get_dev_path(dev); } +/** + * device_phases_reset: + * Transition reset method for devices to allow moving + * smoothly from legacy reset method to multi-phases + */ +static void device_phases_reset(DeviceState *dev) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(dev); + + if (rc->phases.enter) { + rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); + } + if (rc->phases.hold) { + rc->phases.hold(OBJECT(dev)); + } + if (rc->phases.exit) { + rc->phases.exit(OBJECT(dev)); + } +} + +static void device_transitional_reset(Object *obj) +{ + DeviceClass *dc = DEVICE_GET_CLASS(obj); + + /* + * This will call either @device_phases_reset (for multi-phases transitioned + * devices) or a device's specific method for not-yet transitioned devices. + * In both case, it does not reset children. + */ + if (dc->reset) { + dc->reset(DEVICE(obj)); + } +} + +/** + * device_get_transitional_reset: + * check if the device's class is ready for multi-phase + */ +static ResettableTrFunction device_get_transitional_reset(Object *obj) +{ + DeviceClass *dc = DEVICE_GET_CLASS(obj); + if (dc->reset != device_phases_reset) { + /* + * dc->reset has been overridden by a subclass, + * the device is not ready for multi phase yet. + */ + return device_transitional_reset; + } + return NULL; +} + static void device_class_init(ObjectClass *class, void *data) { DeviceClass *dc = DEVICE_CLASS(class); VMStateIfClass *vc = VMSTATE_IF_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = device_unparent; @@ -1073,6 +1147,24 @@ static void device_class_init(ObjectClass *class, void *data) dc->hotpluggable = true; dc->user_creatable = true; vc->get_id = device_vmstate_if_get_id; + rc->get_state = device_get_reset_state; + rc->child_foreach = device_reset_child_foreach; + + /* + * @device_phases_reset is put as the default reset method below, allowing + * to do the multi-phase transition from base classes to leaf classes. It + * allows a legacy-reset Device class to extend a multi-phases-reset + * Device class for the following reason: + * + If a base class B has been moved to multi-phase, then it does not + * override this default reset method and may have defined phase methods. + * + A child class C (extending class B) which uses + * device_class_set_parent_reset() (or similar means) to override the + * reset method will still work as expected. @device_phases_reset function + * will be registered as the parent reset method and effectively call + * parent reset phases. + */ + dc->reset = device_phases_reset; + rc->get_transitional_function = device_get_transitional_reset; object_class_property_add_bool(class, "realized", device_get_realized, device_set_realized, @@ -1157,6 +1249,7 @@ static const TypeInfo device_type_info = { .class_size = sizeof(DeviceClass), .interfaces = (InterfaceInfo[]) { { TYPE_VMSTATE_IF }, + { TYPE_RESETTABLE_INTERFACE }, { } } }; From patchwork Thu Jan 30 16:15:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231488 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lq/Wwa8P; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lzq3tZVz9s1x for ; Fri, 31 Jan 2020 03:24:23 +1100 (AEDT) Received: from localhost ([::1]:35384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCc9-0002J8-DL for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:24:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43172) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCTz-0005fi-Ip for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCTw-0002zq-9m for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:55 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:45334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCTw-0002zD-2Y for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:52 -0500 Received: by mail-wr1-x42c.google.com with SMTP id a6so4728157wrx.12 for ; Thu, 30 Jan 2020 08:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lt09TXjdWWSldnue6vzLMA5nWkuFv0K0sVt7j6VTK2g=; b=lq/Wwa8PQTiGlBWdKJ86IcAHXKH2UI3ET0KyypKmT3iExA5FE58a5apPTvbp7s3kF/ bZXvBKpKdx7saumGBtmOwLWOgqaWvUi6WUCTdAvpw9BC0Bd6cJ7u0WrNbNCIaAYS8fZl Xnt5QmWIB+cEYC2PjfqTUt+2i4rPE2y0zwUhEl9P2SAbpHNZgml+gQ3ooikoBUDP5iiB gqBqWvFBz4SRZp1wfcNWLw8lK5OcuTWgUUzZLBUzMkh+6bCRcCHo9A4IcXjOv/UgirII V08qhhhRaLg+d9D1ZcdU7SV0qrB771JYRUqHlJyQ58A7t753SMkBSFyxhGCfVqivGNvo sZdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lt09TXjdWWSldnue6vzLMA5nWkuFv0K0sVt7j6VTK2g=; b=P19j5cXqm7S+O24sVVm1RgtXnj29N96pu5IrcD6wDC0u7k2aIfiBCyIqKWHFCdxN94 1GDa6bTKEGx+/+cR6HYylc6lOI393Keqad5dwcYQk/OYshUCfAF82pJ9FNklRk0ZC7BN Zl81y2PWblDxts8qtn0aWHpmACE3YTA4yi/KRYVLlcc5zYJWFtP6JVJAxtGq7G7O2myD jTXt3CEy1JJeGxju4mMJ2OSQtWd8ekHPOLkpNSpPbnIevMOJBimjGrJiyZsr8+xtZJ5q iStqM3NxiJaT6ur1xDJ6FQzLGo2fCAYjoS/3AqNaTuluXggNnYE4mA0OveeF35Z3e4ev w6yQ== X-Gm-Message-State: APjAAAV/9gNVGOBj3a9f9O567VhB0inYriZv2Dg9+bbXsZxDGlRSwlZh dKFAkdwWmtbyqG2hxgLcB12H7GHa0Dlmfg== X-Google-Smtp-Source: APXvYqwg5kbXwMR0uDG009TUkg3urwxTOX11ezOG7/OitzP4dMVUmdi3I1ydwwBTjekTZ7b2t6PiOQ== X-Received: by 2002:a05:6000:1201:: with SMTP id e1mr511292wrx.386.1580400950665; Thu, 30 Jan 2020 08:15:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] hw/core/resettable: add support for changing parent Date: Thu, 30 Jan 2020 16:15:20 +0000 Message-Id: <20200130161533.8180-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Add a function resettable_change_parent() to do the required plumbing when changing the parent a of Resettable object. We need to make sure that the reset state of the object remains coherent with the reset state of the new parent. We make the 2 following hypothesis: + when an object is put in a parent under reset, the object goes in reset. + when an object is removed from a parent under reset, the object leaves reset. The added function avoids any glitch if both old and new parent are already in reset. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-6-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/resettable.h | 16 +++++++++++ hw/core/resettable.c | 62 +++++++++++++++++++++++++++++++++++++++-- hw/core/trace-events | 1 + 3 files changed, 77 insertions(+), 2 deletions(-) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index c0b9fc6ad62..96073354fd6 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -194,6 +194,22 @@ void resettable_release_reset(Object *obj, ResetType type); */ bool resettable_is_in_reset(Object *obj); +/** + * resettable_change_parent: + * Indicate that the parent of Ressettable @obj is changing from @oldp to @newp. + * All 3 objects must implement resettable interface. @oldp or @newp may be + * NULL. + * + * This function will adapt the reset state of @obj so that it is coherent + * with the reset state of @newp. It may trigger @resettable_assert_reset() + * or @resettable_release_reset(). It will do such things only if the reset + * state of @newp and @oldp are different. + * + * When using this function during reset, it must only be called during + * a hold phase method. Calling this during enter or exit phase is an error. + */ +void resettable_change_parent(Object *obj, Object *newp, Object *oldp); + /** * resettable_class_set_parent_phases: * diff --git a/hw/core/resettable.c b/hw/core/resettable.c index 91332084870..6e0b0f492f1 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -28,12 +28,16 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type); * enter_phase_in_progress: * True if we are currently in reset enter phase. * - * Note: This flag is only used to guarantee (using asserts) that the reset - * API is used correctly. We can use a global variable because we rely on the + * exit_phase_in_progress: + * count the number of exit phase we are in. + * + * Note: These flags are only used to guarantee (using asserts) that the reset + * API is used correctly. We can use global variables because we rely on the * iothread mutex to ensure only one reset operation is in a progress at a * given time. */ static bool enter_phase_in_progress; +static unsigned exit_phase_in_progress; void resettable_reset(Object *obj, ResetType type) { @@ -65,7 +69,9 @@ void resettable_release_reset(Object *obj, ResetType type) trace_resettable_reset_release_begin(obj, type); assert(!enter_phase_in_progress); + exit_phase_in_progress += 1; resettable_phase_exit(obj, NULL, type); + exit_phase_in_progress -= 1; trace_resettable_reset_release_end(obj); } @@ -206,6 +212,58 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) trace_resettable_phase_exit_end(obj, obj_typename, s->count); } +/* + * resettable_get_count: + * Get the count of the Resettable object @obj. Return 0 if @obj is NULL. + */ +static unsigned resettable_get_count(Object *obj) +{ + if (obj) { + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + return rc->get_state(obj)->count; + } + return 0; +} + +void resettable_change_parent(Object *obj, Object *newp, Object *oldp) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + ResettableState *s = rc->get_state(obj); + unsigned newp_count = resettable_get_count(newp); + unsigned oldp_count = resettable_get_count(oldp); + + /* + * Ensure we do not change parent when in enter or exit phase. + * During these phases, the reset subtree being updated is partly in reset + * and partly not in reset (it depends on the actual position in + * resettable_child_foreach()s). We are not able to tell in which part is a + * leaving or arriving device. Thus we cannot set the reset count of the + * moving device to the proper value. + */ + assert(!enter_phase_in_progress && !exit_phase_in_progress); + trace_resettable_change_parent(obj, oldp, oldp_count, newp, newp_count); + + /* + * At most one of the two 'for' loops will be executed below + * in order to cope with the difference between the two counts. + */ + /* if newp is more reset than oldp */ + for (unsigned i = oldp_count; i < newp_count; i++) { + resettable_assert_reset(obj, RESET_TYPE_COLD); + } + /* + * if obj is leaving a bus under reset, we need to ensure + * hold phase is not pending. + */ + if (oldp_count && s->hold_phase_pending) { + resettable_phase_hold(obj, NULL, RESET_TYPE_COLD); + } + /* if oldp is more reset than newp */ + for (unsigned i = newp_count; i < oldp_count; i++) { + resettable_release_reset(obj, RESET_TYPE_COLD); + } +} + void resettable_class_set_parent_phases(ResettableClass *rc, ResettableEnterPhase enter, ResettableHoldPhase hold, diff --git a/hw/core/trace-events b/hw/core/trace-events index 77d61cb66e6..aecd8e160eb 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -16,6 +16,7 @@ resettable_reset_assert_begin(void *obj, int cold) "obj=%p cold=%d" resettable_reset_assert_end(void *obj) "obj=%p" resettable_reset_release_begin(void *obj, int cold) "obj=%p cold=%d" resettable_reset_release_end(void *obj) "obj=%p" +resettable_change_parent(void *obj, void *o, unsigned oc, void *n, unsigned nc) "obj=%p from=%p(%d) to=%p(%d)" resettable_phase_enter_begin(void *obj, const char *objtype, unsigned count, int type) "obj=%p(%s) count=%d type=%d" resettable_phase_enter_exec(void *obj, const char *objtype, int type, int has_method) "obj=%p(%s) type=%d method=%d" resettable_phase_enter_end(void *obj, const char *objtype, unsigned count) "obj=%p(%s) count=%d" From patchwork Thu Jan 30 16:15:21 2020 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable Date: Thu, 30 Jan 2020 16:15:21 +0000 Message-Id: <20200130161533.8180-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde In qdev_set_parent_bus(), when changing the parent bus of a realized device, if the source and destination buses are not in the same reset state, some adaptations are required. This patch adds needed call to resettable_change_parent() to make sure a device reset state stays coherent with its parent bus. The addition is a no-op if: 1. the device being parented is not realized. 2. the device is realized, but both buses are not under reset. Case 2 means that as long as qdev_set_parent_bus() is called during the machine realization procedure (which is before the machine reset so nothing is in reset), it is a no op. There are 52 call sites of qdev_set_parent_bus(). All but one fall into the no-op case: + 29 trivial calls related to virtio (in hw/{s390x,display,virtio}/ {vhost,virtio}-xxx.c) to set a vdev(or vgpu) composing device parent bus just before realizing the same vdev(vgpu). + hw/core/qdev.c: when creating a device in qdev_try_create() + hw/core/sysbus.c: when initializing a device in the sysbus + hw/i386/amd_iommu.c: before realizing AMDVIState/pci + hw/isa/piix4.c: before realizing PIIX4State/rtc + hw/misc/auxbus.c: when creating an AUXBus + hw/misc/auxbus.c: when creating an AUXBus child + hw/misc/macio/macio.c: when initializing a MACIOState child + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/pmu + hw/misc/macio/macio.c: before realizing NewWorldMacIOState/cuda + hw/net/virtio-net.c: Used for migration when using the failover mechanism to migration a vfio-pci/net. It is a no-op because at this point the device is already on the bus. + hw/pci-host/designware.c: before realizing DesignwarePCIEHost/root + hw/pci-host/gpex.c: before realizing GPEXHost/root + hw/pci-host/prep.c: when initialiazing PREPPCIState/pci_dev + hw/pci-host/q35.c: before realizing Q35PCIHost/mch + hw/pci-host/versatile.c: when initializing PCIVPBState/pci_dev + hw/pci-host/xilinx-pcie.c: before realizing XilinxPCIEHost/root + hw/s390x/event-facility.c: when creating SCLPEventFacility/ TYPE_SCLP_QUIESCE + hw/s390x/event-facility.c: ditto with SCLPEventFacility/ TYPE_SCLP_CPU_HOTPLUG + hw/s390x/sclp.c: Not trivial because it is called on a SLCPDevice just after realizing it. Ok because at this point the destination bus (sysbus) is not in reset; the realize step is before the machine reset. + hw/sd/core.c: Not OK. Used in sdbus_reparent_card(). See below. + hw/ssi/ssi.c: Used to put spi slave on spi bus and connect the cs line in ssi_auto_connect_slave(). Ok because this function is only used in realize step in hw/ssi/aspeed_smc.ci, hw/ssi/imx_spi.c, hw/ssi/mss-spi.c, hw/ssi/xilinx_spi.c and hw/ssi/xilinx_spips.c. + hw/xen/xen-legacy-backend.c: when creating a XenLegacyDevice device + qdev-monitor.c: in device hotplug creation procedure before realize Note that this commit alone will have no effect, right now there is no use of resettable API to reset anything. So a bus will never be tagged as in-reset by this same API. The one place where side-effect will occurs is in hw/sd/core.c in sdbus_reparent_card(). This function is only used in the raspi machines, including during the sysbus reset procedure. This case will be carrefully handled when doing the multiple phase reset transition. Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-7-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/core/qdev.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index b2affd8f92b..28fc93b1074 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -96,25 +96,31 @@ static void bus_add_child(BusState *bus, DeviceState *child) void qdev_set_parent_bus(DeviceState *dev, BusState *bus) { - bool replugging = dev->parent_bus != NULL; + BusState *old_parent_bus = dev->parent_bus; - if (replugging) { + if (old_parent_bus) { trace_qdev_update_parent_bus(dev, object_get_typename(OBJECT(dev)), - dev->parent_bus, object_get_typename(OBJECT(dev->parent_bus)), + old_parent_bus, object_get_typename(OBJECT(old_parent_bus)), OBJECT(bus), object_get_typename(OBJECT(bus))); /* * Keep a reference to the device while it's not plugged into * any bus, to avoid it potentially evaporating when it is * dereffed in bus_remove_child(). + * Also keep the ref of the parent bus until the end, so that + * we can safely call resettable_change_parent() below. */ object_ref(OBJECT(dev)); bus_remove_child(dev->parent_bus, dev); - object_unref(OBJECT(dev->parent_bus)); } dev->parent_bus = bus; object_ref(OBJECT(bus)); bus_add_child(bus, dev); - if (replugging) { + if (dev->realized) { + resettable_change_parent(OBJECT(dev), OBJECT(bus), + OBJECT(old_parent_bus)); + } + if (old_parent_bus) { + object_unref(OBJECT(old_parent_bus)); object_unref(OBJECT(dev)); } } From patchwork Thu Jan 30 16:15:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] hw/core/qdev: update hotplug reset regarding resettable Date: Thu, 30 Jan 2020 16:15:22 +0000 Message-Id: <20200130161533.8180-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde This commit make use of the resettable API to reset the device being hotplugged when it is realized. Also it ensures it is put in a reset state coherent with the parent it is plugged into. Note that there is a difference in the reset. Instead of resetting only the hotplugged device, we reset also its subtree (switch to resettable API). This is not expected to be a problem because sub-buses are just realized too. If a hotplugged device has any sub-buses it is logical to reset them too at this point. The recently added should_be_hidden and PCI's partially_hotplugged mechanisms do not interfere with realize operation: + In the should_be_hidden use case, device creation is delayed. + The partially_hotplugged mechanism prevents a device to be unplugged and unrealized from qdev POV and unrealized. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/resettable.h | 11 +++++++++++ hw/core/qdev.c | 15 ++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/hw/resettable.h b/include/hw/resettable.h index 96073354fd6..5e215d94e42 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -153,6 +153,17 @@ struct ResettableState { bool exit_phase_in_progress; }; +/** + * resettable_state_clear: + * Clear the state. It puts the state to the initial (zeroed) state required + * to reuse an object. Typically used in realize step of base classes + * implementing the interface. + */ +static inline void resettable_state_clear(ResettableState *state) +{ + memset(state, 0, sizeof(ResettableState)); +} + /** * resettable_reset: * Trigger a reset on an object @obj of type @type. @obj must implement diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 28fc93b1074..7697f033b19 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -909,6 +909,12 @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } + /* + * Clear the reset state, in case the object was previously unrealized + * with a dirty state. + */ + resettable_state_clear(&dev->reset); + QLIST_FOREACH(bus, &dev->child_bus, sibling) { object_property_set_bool(OBJECT(bus), true, "realized", &local_err); @@ -917,7 +923,14 @@ static void device_set_realized(Object *obj, bool value, Error **errp) } } if (dev->hotplugged) { - device_legacy_reset(dev); + /* + * Reset the device, as well as its subtree which, at this point, + * should be realized too. + */ + resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD); + resettable_change_parent(OBJECT(dev), OBJECT(dev->parent_bus), + NULL); + resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD); } dev->pending_deleted_event = false; From patchwork Thu Jan 30 16:15:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=R2H81Piv; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487m2C1Pvzz9s1x for ; Fri, 31 Jan 2020 03:26:27 +1100 (AEDT) Received: from localhost ([::1]:35452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCe8-0005lo-PH for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:26:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43239) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCU5-0005it-Ky for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU3-00035a-G1 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:01 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46973) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU1-00033a-Ht for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:15:57 -0500 Received: by mail-wr1-x42d.google.com with SMTP id z7so4713297wrl.13 for ; Thu, 30 Jan 2020 08:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1jUSJvJpc6/xZHAejsMbUNB1llqeZQaXh0iGP/56VKU=; b=R2H81PivjVHu58X+bBtVqRCcUoVHZ6smZOVqe8POH/aK12fFD6IqC2AcVcVAyHn0yf pZ5j9pe4wF4gQIBJf62YwzpjpcVA3JLR25Bb5T2kgqbnwmY7p6S00x6LZFXAWCr1tMhO 1E7M9PHI8Puwi6Cg/NcV4ldcj31KQXc5rgqKOB770rTocaG/SOHU14Cr3UcECbIE9LB6 lIvk8YcZmmPq+kLK7yVkJeTG3pNzcA4lsWuzdE8ZehU9DH/5sDRAmWZgM4RKppOfCl7N AUve0H4b/Q1JRuI9LQEOD4bOn0342us9ge3DODP1U7bf61z6gtd34QGA8rsDYr8qJvTw Ob8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1jUSJvJpc6/xZHAejsMbUNB1llqeZQaXh0iGP/56VKU=; b=dgWlzuRhQXpplaFnPgPtxfuogUHiPXeyziaI+Iobq5y6B0h80/YxZrrNurx0QpK/p7 E95w9vds2FVyzIwC5r13GzOZfOcRpPIklRBoXmOZMenwcpNzeCWxQRN0D6Hyqjee+0jR vPE6apaVfDjOOIzFDi2Lm4u80OSq7wqnbSrozn4NKb1hOrvAgN4T+e9k/iJwmA9lkYvg V45SQMfo4nP0BJkNtjXTldWi6F/Md7v8BC7aD+PjKpci3fFCQ83oD2rOfouphzWoDlgS hAt7fZJQmsFsnCpG6DJ0pq6jwCJlQUyDy4CKboItzExyodOUgBDxB8aT90GjC5bvoUd0 nQtQ== X-Gm-Message-State: APjAAAUmMd7ApfytZrJDeJ6lwVNd1MWh8BnpMG8wy6Ks3vtsAiTEG0e2 EVm7dbmQuiZXifG/oM1RsGcb9J0/BpDO2A== X-Google-Smtp-Source: APXvYqxiWqaZt4Icon4vOKuDW1sQ2sGobeGTwVQCXS/SFC3x60UiITfP/5xrUH4oqdLVqhrsH6IxHQ== X-Received: by 2002:a05:6000:12ce:: with SMTP id l14mr6781509wrx.342.1580400954423; Thu, 30 Jan 2020 08:15:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones Date: Thu, 30 Jan 2020 16:15:23 +0000 Message-Id: <20200130161533.8180-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Deprecate device_legacy_reset(), qdev_reset_all() and qbus_reset_all() to be replaced by new functions device_cold_reset() and bus_cold_reset() which uses resettable API. Also introduce resettable_cold_reset_fn() which may be used as a replacement for qdev_reset_all_fn and qbus_reset_all_fn(). Following patches will be needed to look at legacy reset call sites and switch to resettable api. The legacy functions will be removed when unused. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-9-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/qdev-core.h | 27 +++++++++++++++++++++++++++ include/hw/resettable.h | 9 +++++++++ hw/core/bus.c | 5 +++++ hw/core/qdev.c | 5 +++++ hw/core/resettable.c | 5 +++++ 5 files changed, 51 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 09b7a441eb6..1405b8a990a 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -411,6 +411,13 @@ int qdev_walk_children(DeviceState *dev, qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn, void *opaque); +/** + * @qdev_reset_all: + * Reset @dev. See @qbus_reset_all() for more details. + * + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use device_cold_reset() now. + */ void qdev_reset_all(DeviceState *dev); void qdev_reset_all_fn(void *opaque); @@ -423,10 +430,28 @@ void qdev_reset_all_fn(void *opaque); * hard reset means that qbus_reset_all will reset all state of the device. * For PCI devices, for example, this will include the base address registers * or configuration space. + * + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use bus_cold_reset() now. */ void qbus_reset_all(BusState *bus); void qbus_reset_all_fn(void *opaque); +/** + * device_cold_reset: + * Reset device @dev and perform a recursive processing using the resettable + * interface. It triggers a RESET_TYPE_COLD. + */ +void device_cold_reset(DeviceState *dev); + +/** + * bus_cold_reset: + * + * Reset bus @bus and perform a recursive processing using the resettable + * interface. It triggers a RESET_TYPE_COLD. + */ +void bus_cold_reset(BusState *bus); + /** * device_is_in_reset: * Return true if the device @dev is currently being reset. @@ -457,6 +482,8 @@ void qdev_machine_init(void); * device_legacy_reset: * * Reset a single device (by calling the reset method). + * Note: This function is deprecated and will be removed when it becomes unused. + * Please use device_cold_reset() now. */ void device_legacy_reset(DeviceState *dev); diff --git a/include/hw/resettable.h b/include/hw/resettable.h index 5e215d94e42..f4c4bab0eff 100644 --- a/include/hw/resettable.h +++ b/include/hw/resettable.h @@ -221,6 +221,15 @@ bool resettable_is_in_reset(Object *obj); */ void resettable_change_parent(Object *obj, Object *newp, Object *oldp); +/** + * resettable_cold_reset_fn: + * Helper to call resettable_reset((Object *) opaque, RESET_TYPE_COLD). + * + * This function is typically useful to register a reset handler with + * qemu_register_reset. + */ +void resettable_cold_reset_fn(void *opaque); + /** * resettable_class_set_parent_phases: * diff --git a/hw/core/bus.c b/hw/core/bus.c index 2698f715bd7..3dc0a825f09 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -68,6 +68,11 @@ int qbus_walk_children(BusState *bus, return 0; } +void bus_cold_reset(BusState *bus) +{ + resettable_reset(OBJECT(bus), RESET_TYPE_COLD); +} + bool bus_is_in_reset(BusState *bus) { return resettable_is_in_reset(OBJECT(bus)); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 7697f033b19..3937d1eb1a5 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -361,6 +361,11 @@ void qbus_reset_all_fn(void *opaque) qbus_reset_all(bus); } +void device_cold_reset(DeviceState *dev) +{ + resettable_reset(OBJECT(dev), RESET_TYPE_COLD); +} + bool device_is_in_reset(DeviceState *dev) { return resettable_is_in_reset(OBJECT(dev)); diff --git a/hw/core/resettable.c b/hw/core/resettable.c index 6e0b0f492f1..96a99ce39ea 100644 --- a/hw/core/resettable.c +++ b/hw/core/resettable.c @@ -264,6 +264,11 @@ void resettable_change_parent(Object *obj, Object *newp, Object *oldp) } } +void resettable_cold_reset_fn(void *opaque) +{ + resettable_reset((Object *) opaque, RESET_TYPE_COLD); +} + void resettable_class_set_parent_phases(ResettableClass *rc, ResettableEnterPhase enter, ResettableHoldPhase hold, From patchwork Thu Jan 30 16:15:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YmTW6cUl; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lwV1Njxz9sRG for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/26] docs/devel/reset.rst: add doc about Resettable interface Date: Thu, 30 Jan 2020 16:15:24 +0000 Message-Id: <20200130161533.8180-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200123132823.1117486-10-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- docs/devel/index.rst | 1 + docs/devel/reset.rst | 289 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 290 insertions(+) create mode 100644 docs/devel/reset.rst diff --git a/docs/devel/index.rst b/docs/devel/index.rst index ac862152dcb..4dc2ca8d715 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -24,3 +24,4 @@ Contents: tcg tcg-plugins bitops + reset diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst new file mode 100644 index 00000000000..abea1102dc4 --- /dev/null +++ b/docs/devel/reset.rst @@ -0,0 +1,289 @@ + +======================================= +Reset in QEMU: the Resettable interface +======================================= + +The reset of qemu objects is handled using the resettable interface declared +in ``include/hw/resettable.h``. + +This interface allows objects to be grouped (on a tree basis); so that the +whole group can be reset consistently. Each individual member object does not +have to care about others; in particular, problems of order (which object is +reset first) are addressed. + +As of now DeviceClass and BusClass implement this interface. + + +Triggering reset +---------------- + +This section documents the APIs which "users" of a resettable object should use +to control it. All resettable control functions must be called while holding +the iothread lock. + +You can apply a reset to an object using ``resettable_assert_reset()``. You need +to call ``resettable_release_reset()`` to release the object from reset. To +instantly reset an object, without keeping it in reset state, just call +``resettable_reset()``. These functions take two parameters: a pointer to the +object to reset and a reset type. + +Several types of reset will be supported. For now only cold reset is defined; +others may be added later. The Resettable interface handles reset types with an +enum: + +``RESET_TYPE_COLD`` + Cold reset is supported by every resettable object. In QEMU, it means we reset + to the initial state corresponding to the start of QEMU; this might differ + from what is a real hardware cold reset. It differs from other resets (like + warm or bus resets) which may keep certain parts untouched. + +Calling ``resettable_reset()`` is equivalent to calling +``resettable_assert_reset()`` then ``resettable_release_reset()``. It is +possible to interleave multiple calls to these three functions. There may +be several reset sources/controllers of a given object. The interface handles +everything and the different reset controllers do not need to know anything +about each others. The object will leave reset state only when each other +controllers end their reset operation. This point is handled internally by +maintaining a count of in-progress resets; it is crucial to call +``resettable_release_reset()`` one time and only one time per +``resettable_assert_reset()`` call. + +For now migration of a device or bus in reset is not supported. Care must be +taken not to delay ``resettable_release_reset()`` after its +``resettable_assert_reset()`` counterpart. + +Note that, since resettable is an interface, the API takes a simple Object as +parameter. Still, it is a programming error to call a resettable function on a +non-resettable object and it will trigger a run time assert error. Since most +calls to resettable interface are done through base class functions, such an +error is not likely to happen. + +For Devices and Buses, the following helper functions exist: + +- ``device_cold_reset()`` +- ``bus_cold_reset()`` + +These are simple wrappers around resettable_reset() function; they only cast the +Device or Bus into an Object and pass the cold reset type. When possible +prefer to use these functions instead of ``resettable_reset()``. + +Device and bus functions co-exist because there can be semantic differences +between resetting a bus and resetting the controller bridge which owns it. +For example, consider a SCSI controller. Resetting the controller puts all +its registers back to what reset state was as well as reset everything on the +SCSI bus, whereas resetting just the SCSI bus only resets everything that's on +it but not the controller. + + +Multi-phase mechanism +--------------------- + +This section documents the internals of the resettable interface. + +The resettable interface uses a multi-phase system to relieve objects and +machines from reset ordering problems. To address this, the reset operation +of an object is split into three well defined phases. + +When resetting several objects (for example the whole machine at simulation +startup), all first phases of all objects are executed, then all second phases +and then all third phases. + +The three phases are: + +1. The **enter** phase is executed when the object enters reset. It resets only + local state of the object; it must not do anything that has a side-effect + on other objects, such as raising or lowering a qemu_irq line or reading or + writing guest memory. + +2. The **hold** phase is executed for entry into reset, once every object in the + group which is being reset has had its *enter* phase executed. At this point + devices can do actions that affect other objects. + +3. The **exit** phase is executed when the object leaves the reset state. + Actions affecting other objects are permitted. + +As said in previous section, the interface maintains a count of reset. This +count is used to ensure phases are executed only when required. *enter* and +*hold* phases are executed only when asserting reset for the first time +(if an object is already in reset state when calling +``resettable_assert_reset()`` or ``resettable_reset()``, they are not +executed). +The *exit* phase is executed only when the last reset operation ends. Therefore +the object does not need to care how many of reset controllers it has and how +many of them have started a reset. + + +Handling reset in a resettable object +------------------------------------- + +This section documents the APIs that an implementation of a resettable object +must provide and what functions it has access to. It is intended for people +who want to implement or convert a class which has the resettable interface; +for example when specializing an existing device or bus. + +Methods to implement +.................... + +Three methods should be defined or left empty. Each method corresponds to a +phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and +``phases.exit()``. They all take the object as parameter. The *enter* method +also take the reset type as second parameter. + +When extending an existing class, these methods may need to be extended too. +The ``resettable_class_set_parent_phases()`` class function may be used to +backup parent class methods. + +Here follows an example to implement reset for a Device which sets an IO while +in reset. + +:: + + static void mydev_reset_enter(Object *obj, ResetType type) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class enter phase */ + if (myclass->parent_phases.enter) { + myclass->parent_phases.enter(obj, type); + } + /* initialize local state only */ + mydev->var = 0; + } + + static void mydev_reset_hold(Object *obj) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class hold phase */ + if (myclass->parent_phases.hold) { + myclass->parent_phases.hold(obj); + } + /* set an IO */ + qemu_set_irq(mydev->irq, 1); + } + + static void mydev_reset_exit(Object *obj) + { + MyDevClass *myclass = MYDEV_GET_CLASS(obj); + MyDevState *mydev = MYDEV(obj); + /* call parent class exit phase */ + if (myclass->parent_phases.exit) { + myclass->parent_phases.exit(obj); + } + /* clear an IO */ + qemu_set_irq(mydev->irq, 0); + } + + typedef struct MyDevClass { + MyParentClass parent_class; + /* to store eventual parent reset methods */ + ResettablePhases parent_phases; + } MyDevClass; + + static void mydev_class_init(ObjectClass *class, void *data) + { + MyDevClass *myclass = MYDEV_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); + resettable_class_set_parent_reset_phases(rc, + mydev_reset_enter, + mydev_reset_hold, + mydev_reset_exit, + &myclass->parent_phases); + } + +In the above example, we override all three phases. It is possible to override +only some of them by passing NULL instead of a function pointer to +``resettable_class_set_parent_reset_phases()``. For example, the following will +only override the *enter* phase and leave *hold* and *exit* untouched:: + + resettable_class_set_parent_reset_phases(rc, mydev_reset_enter, + NULL, NULL, + &myclass->parent_phases); + +This is equivalent to providing a trivial implementation of the hold and exit +phases which does nothing but call the parent class's implementation of the +phase. + +Polling the reset state +....................... + +Resettable interface provides the ``resettable_is_in_reset()`` function. +This function returns true if the object parameter is currently under reset. + +An object is under reset from the beginning of the *init* phase to the end of +the *exit* phase. During all three phases, the function will return that the +object is in reset. + +This function may be used if the object behavior has to be adapted +while in reset state. For example if a device has an irq input, +it will probably need to ignore it while in reset; then it can for +example check the reset state at the beginning of the irq callback. + +Note that until migration of the reset state is supported, an object +should not be left in reset. So apart from being currently executing +one of the reset phases, the only cases when this function will return +true is if an external interaction (like changing an io) is made during +*hold* or *exit* phase of another object in the same reset group. + +Helpers ``device_is_in_reset()`` and ``bus_is_in_reset()`` are also provided +for devices and buses and should be preferred. + + +Base class handling of reset +---------------------------- + +This section documents parts of the reset mechanism that you only need to know +about if you are extending it to work with a new base class other than +DeviceClass or BusClass, or maintaining the existing code in those classes. Most +people can ignore it. + +Methods to implement +.................... + +There are two other methods that need to exist in a class implementing the +interface: ``get_state()`` and ``child_foreach()``. + +``get_state()`` is simple. *resettable* is an interface and, as a consequence, +does not have any class state structure. But in order to factorize the code, we +need one. This method must return a pointer to ``ResettableState`` structure. +The structure must be allocated by the base class; preferably it should be +located inside the object instance structure. + +``child_foreach()`` is more complex. It should execute the given callback on +every reset child of the given resettable object. All children must be +resettable too. Additional parameters (a reset type and an opaque pointer) must +be passed to the callback too. + +In ``DeviceClass`` and ``BusClass`` the ``ResettableState`` is located +``DeviceState`` and ``BusState`` structure. ``child_foreach()`` is implemented +to follow the bus hierarchy; for a bus, it calls the function on every child +device; for a device, it calls the function on every bus child. When we reset +the main system bus, we reset the whole machine bus tree. + +Changing a resettable parent +............................ + +One thing which should be taken care of by the base class is handling reset +hierarchy changes. + +The reset hierarchy is supposed to be static and built during machine creation. +But there are actually some exceptions. To cope with this, the resettable API +provides ``resettable_change_parent()``. This function allows to set, update or +remove the parent of a resettable object after machine creation is done. As +parameters, it takes the object being moved, the old parent if any and the new +parent if any. + +This function can be used at any time when not in a reset operation. During +a reset operation it must be used only in *hold* phase. Using it in *enter* or +*exit* phase is an error. +Also it should not be used during machine creation, although it is harmless to +do so: the function is a no-op as long as old and new parent are NULL or not +in reset. + +There is currently 2 cases where this function is used: + +1. *device hotplug*; it means a new device is introduced on a live bus. + +2. *hot bus change*; it means an existing live device is added, moved or + removed in the bus hierarchy. At the moment, it occurs only in the raspi + machines for changing the sdbus used by sd card. From patchwork Thu Jan 30 16:15:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=T6Ax4MNC; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487m6D5FHpz9sPn for ; Fri, 31 Jan 2020 03:29:56 +1100 (AEDT) Received: from localhost ([::1]:35534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixChW-0003wj-MQ for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:29:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43271) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCU7-0005ms-3G for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU5-00037G-KJ for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:02 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52560) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU4-00035o-EQ for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:01 -0500 Received: by mail-wm1-x333.google.com with SMTP id p9so4410436wmc.2 for ; Thu, 30 Jan 2020 08:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dtQiX/MRRlIpxjI4PpXQAgny+XholocDWMM4mNtP8hw=; b=T6Ax4MNCp9n7ti4kobHPMF/yOGEiWv9V7JaWdtm4ioLfDHOmNzS1LCd2Q4XfOxDkcu Smegi6DCUKdLZ5ZFlpYZ1iLYOskjl8K7TfBJ7Ayy9UyR/t5zi0XCmO4T3ikjlPSpR5ot b3D3JMI/RsKy+CmXepquAaJxBLV0znsIF1689K9d88g1YSCj38XIyatiWR+lC9b4xB2k ohnfu9d3e9t2BkPAptFhTS94fOcCXOGw4jlZViY0F47uHfUAwYetrcWL59i9nf5DW6Xh 2255QPqraAdIsbjz3YzfdPwoHXfmsvBBhkaTVxgI4jjUlA9Wlv5juMl8pYa94SbBufkE DqTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dtQiX/MRRlIpxjI4PpXQAgny+XholocDWMM4mNtP8hw=; b=CbbaVF7PSE6f8xNMpQYDxh09tLUqmP6+iD1nmohlCd9TL7oeSKN6dc9XbWjCG/QPaU uvQDunwnmhXKjB34qyZye1DOLfKhW/L5y0xOC7zeMBbsjMPSfWKZJVnwv0IeOmVuRLOH NMcmqCISK8gz70M6RRVPAH+IYs0Vgsk73q7bm4SgYHXSb4fa97diNrT05CPi8cUUZOk0 XieNKfiXUj6yteVTo2W/U2ukOQO4V81UruQhsagH0NjAhmVJVFizXc0B7Bo6rRxSszc5 L2vLpWfGIEq6yJqYNTnadhCwnNXVZTfL4wHMzwuN5iUQ/DRMhAYhmEZWxrfaOWnr8KOt dz7A== X-Gm-Message-State: APjAAAWqYUGpWMEqHGYQYF1/W58gmolROwNVCFdMn/dbsgov1JlXZXwt aLJLsqBQShhdE4aQs9OcaqxnerY/a1wKSg== X-Google-Smtp-Source: APXvYqy4jR7M/6lz0hTdCYGP8OANqsvE2q/Z9PPEFSBj5I13sYNsfILwtYpkyn3nHBFV80FFP1Rxtw== X-Received: by 2002:a05:600c:21c6:: with SMTP id x6mr6454258wmj.177.1580400958718; Thu, 30 Jan 2020 08:15:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] vl: replace deprecated qbus_reset_all registration Date: Thu, 30 Jan 2020 16:15:25 +0000 Message-Id: <20200130161533.8180-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Replace deprecated qbus_reset_all by resettable_cold_reset_fn for the sysbus reset registration. Apart for the raspi machines, this does not impact the behavior because: + at this point resettable just calls the old reset methods of devices and buses in the same order as qdev/qbus. + resettable handlers registered with qemu_register_reset are serialized; there is no interleaving. + eventual explicit calls to legacy reset API (device_reset or qdev/qbus_reset) inside this reset handler will not be masked out by resettable mechanism; they do not go through resettable api. For the raspi machines, during the sysbus reset the sd-card is not reset twice anymore but only once. This is a consequence of switching both sysbus reset and changing parent to resettable; it detects the second reset is not needed. This has no impact on the state after reset; the sd-card reset method only reset local state and query information from the block backend. The raspi reset change can be observed by using the following command (reset will occurs, then do Ctrl-C to end qemu; no firmware is given here). qemu-system-aarch64 -M raspi3 \ -trace resettable_phase_hold_exec \ -trace qdev_update_parent_bus \ -trace resettable_change_parent \ -trace qdev_reset -trace qbus_reset Before the patch, the qdev/qbus_reset traces show when reset method are called. After the patch, the resettable_phase_hold_exec show when reset method are called. The traced reset order of the raspi3 is listed below. I've added empty lines and the tree structure. +->bcm2835-peripherals reset | | +->sd-card reset | +->sd-bus reset +->bcm2835_gpio reset | -> dev_update_parent_bus (move the sd-card on the sdhci-bus) | -> resettable_change_parent | +->bcm2835-dma reset | | +->bcm2835-sdhost-bus reset +->bcm2835-sdhost reset | | +->sd-card (reset ONLY BEFORE BEFORE THE PATCH) | +->sdhci-bus reset +->generic-sdhci reset | +->bcm2835-rng reset +->bcm2835-property reset +->bcm2835-fb reset +->bcm2835-mbox reset +->bcm2835-aux reset +->pl011 reset +->bcm2835-ic reset +->bcm2836-control reset System reset In both case, the sd-card is reset (being on bcm2835_gpio/sd-bus) then moved to generic-sdhci/sdhci-bus by the bcm2835_gpio reset method. Before the patch, it is then reset again being part of generic-sdhci/sdhci-bus. After the patch, it considered again for reset but its reset method is not called because it is already flagged as reset. Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20200123132823.1117486-11-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- vl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/vl.c b/vl.c index b0f52c4d6e0..24951b51a94 100644 --- a/vl.c +++ b/vl.c @@ -4381,7 +4381,15 @@ int main(int argc, char **argv, char **envp) /* TODO: once all bus devices are qdevified, this should be done * when bus is created by qdev.c */ - qemu_register_reset(qbus_reset_all_fn, sysbus_get_default()); + /* + * TODO: If we had a main 'reset container' that the whole system + * lived in, we could reset that using the multi-phase reset + * APIs. For the moment, we just reset the sysbus, which will cause + * all devices hanging off it (and all their child buses, recursively) + * to be reset. Note that this will *not* reset any Device objects + * which are not attached to some part of the qbus tree! + */ + qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); qemu_run_machine_init_done_notifiers(); if (rom_check_and_register_reset() != 0) { From patchwork Thu Jan 30 16:15:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=s6IwLRQH; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487m4K1y08z9sPn for ; Fri, 31 Jan 2020 03:28:17 +1100 (AEDT) Received: from localhost ([::1]:35494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCfv-0000fT-5Z for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:28:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43268) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCU6-0005mY-W4 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU5-00037f-Q6 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:02 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:34160) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU5-00036W-IU for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:01 -0500 Received: by mail-wr1-x42f.google.com with SMTP id t2so4820547wrr.1 for ; Thu, 30 Jan 2020 08:16:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aB8sogKHzqSo+5j5JJF7r8R8zdumzJOaE75J49k/efw=; b=s6IwLRQHFNAyMMZuzbcLOY6WLQGB9B1kyq4dyaiH3rsHxUI6RUA3sKinBGzUN4jr+M 14inPlUQe+UqNJ1r8F4/W/krG7qPkKlfbpuS/9G4rnHu6scw4SoXET7s030o3tMB5zsv lSoxd7favoVl3fvWzb0USLomV665bOK2/zzX6p7RiZFe5ohsv29xNZSyWgSgpo7Axc0T ULMJwPlmFDzE1OZDY0KrBklQ8evBV21XNxnTJqrZLrWYmAV4CjRybeT8qJBUyhQKfH8H pr9ds+KrXL+PeNC8krqAdseOean0g9TGn647KTfNaxOO1daoK6fHo2HnFvCAN18IqmWF lwig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aB8sogKHzqSo+5j5JJF7r8R8zdumzJOaE75J49k/efw=; b=Ej2K+Z+8hTPXuYctPC5BGqtegD2Y/atWPQVkLdsFKzBbYikRLSEFT+DeTfN07HqCg9 hyeqcOdLblmP97QLZ5zKH8uYQXct9ljkuUeKc/jIJso1NBsUX/h9Xq1rOtz/5OgUKNze 3yARF2mK3fjA+9UvB0LVkmBMWs5MQPelnS8lOuHWIPoAS0fY3A0zZhifeGX4P6MfmSvQ J/GyCt2yW+oiTK10QPNeu93YrKwKg71Ixi8Z4bTPTGQAXQsCrQsOlfZGaruy9pCElmk6 EeqAPo2wkwRKErTl+KdItd5jzbofB46jF9zjDuyfT++W57Z/bT5NagTVga0cTMtm2XiC z88g== X-Gm-Message-State: APjAAAULEUUsDOan72iK/g0rDDnfI/u14rMro9MK41BPfugW4EDxBG7f 1mNzw5tZC9jn7zPKJTzrBLu+bHweQZxwWw== X-Google-Smtp-Source: APXvYqwBSaBMT7SHiU3SiAe6Qhe/eHUNKbA7fcUyorCIvmd5T+XfQp9R83E7AD0oqP+nghFrHuGjLw== X-Received: by 2002:a5d:5706:: with SMTP id a6mr6474203wrv.108.1580400959993; Thu, 30 Jan 2020 08:15:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.15.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:15:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration Date: Thu, 30 Jan 2020 16:15:26 +0000 Message-Id: <20200130161533.8180-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Damien Hedde Replace deprecated qdev_reset_all by resettable_cold_reset_fn for the ipl registration in the main reset handlers. This does not impact the behavior for the following reasons: + at this point resettable just call the old reset methods of devices and buses in the same order than qdev/qbus. + resettable handlers registered with qemu_register_reset are serialized; there is no interleaving. + eventual explicit calls to legacy reset API (device_reset or qdev/qbus_reset) inside this reset handler will not be masked out by resettable mechanism; they do not go through resettable api. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Cornelia Huck Reviewed-by: Richard Henderson Message-id: 20200123132823.1117486-12-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/s390x/ipl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index ca8e7db4672..7773499d7f7 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -237,7 +237,15 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp) */ ipl->compat_start_addr = ipl->start_addr; ipl->compat_bios_start_addr = ipl->bios_start_addr; - qemu_register_reset(qdev_reset_all_fn, dev); + /* + * Because this Device is not on any bus in the qbus tree (it is + * not a sysbus device and it's not on some other bus like a PCI + * bus) it will not be automatically reset by the 'reset the + * sysbus' hook registered by vl.c like most devices. So we must + * manually register a reset hook for it. + * TODO: there should be a better way to do this. + */ + qemu_register_reset(resettable_cold_reset_fn, dev); error: error_propagate(errp, err); } From patchwork Thu Jan 30 16:15:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=F+unshtH; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lyb1RTCz9sRX for ; Fri, 31 Jan 2020 03:23:19 +1100 (AEDT) Received: from localhost ([::1]:35356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCb6-0000EE-TT for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43289) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCU8-0005nJ-0h for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU6-00038A-CF for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:03 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:36101) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU6-00037D-5Q for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:02 -0500 Received: by mail-wr1-x443.google.com with SMTP id z3so4816357wru.3 for ; Thu, 30 Jan 2020 08:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FudFrPLs/FW28wgW4YGWYEJ4ys1uBPtYGVZ/qV1IY/0=; b=F+unshtH700rv40WL/rt6Kk1EVMPrfMuA2LZV+2W3UYilLAG7Oc4xZkOXSB1HmvxQz QEXu6gqBaSZ4cp0Z5l2tPHrE2Tkhtv/qqzpowWZTeWdpbrcROtz9KM/WBdaqBW09nB+K Xg8fHXWKpWxqLJXZtUcmPE+IJfIm8voLaguOGvTxe49jP2EMmcqpERCzrIWw9YyG6JMU crXD5qmBC/URL4kO7UPQu/ZnGB/PoScPjQuc8//Vf2JiorKJb977AOrDJFp5pwkR5VZ3 A3Vvn6Qv1CLY6a3/XBir/RRFp/3PNYcafWHDpQNnI6UNEoOVfvOeTtxWl5DV3hbxQxrz 4VkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FudFrPLs/FW28wgW4YGWYEJ4ys1uBPtYGVZ/qV1IY/0=; b=YgX/esXk8zx42FvF6DrWhin/kkWy1HBHtpPW70sjFDVAEkvSJCBXWbm9Y9OepzYrwm BHZKW1XDAfAm+RS/FiWEUETiQwrNYKm2GjPY6PcwYRAuAfSnHAydAS5YYvis7dU+FF4w J5UWYi+OkOnuOM3WUg5v8F5QnrjBMz7FA2nQ2OoW5xh0sA2T+eajaWyuuVxefqUa5/D+ W/+vyBmd9zhb0jo5bb3lyhe4lvAWF9EkAvvVBoMqk4sU24Fgu6iJkJ314LmdcnQmJH53 /SmQi2RZsjP0p077rAxIe2FIh0JPHUK9j6rkteknihv+YDgxvwJFk+EnZkmOHYZpm5Sy 3zAw== X-Gm-Message-State: APjAAAWEpy0oalTT7Y4T5G1+fXKsBsQ6FqSAriT+zVxBpDnfPmDdZBzw Fgz632uN1V+PUXFgiPy14V7z88k5g2RFlA== X-Google-Smtp-Source: APXvYqyILcGWB3J8Izj0T7GaH0f4bzA9t1BC7YsWMz1Eeabpk/ttdMjuhkuq0csvcrmZBQT8Aa0f/Q== X-Received: by 2002:adf:f484:: with SMTP id l4mr6759498wro.207.1580400960970; Thu, 30 Jan 2020 08:16:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/26] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit Date: Thu, 30 Jan 2020 16:15:27 +0000 Message-Id: <20200130161533.8180-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Zenghui Yu If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC initialization time". And what's worse, PTZ is generally programmed by guest to indicate to the Redistributor whether the LPI Pending table is zero when enabling LPIs. If migration is triggered when the PTZ has just been cleared by guest (and before enabling LPIs), we will see PTZ==1 on the destination side, which is not as expected. Let's just drop this hackish userspace behavior. Also take this chance to refine the comment a bit. Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu Message-id: 20200119133051.642-1-yuzenghui@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 9c7f4ab8711..49304ca589d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -336,7 +336,10 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicd_access(s, GICD_CTLR, ®, true); if (redist_typer & GICR_TYPER_PLPIS) { - /* Set base addresses before LPIs are enabled by GICR_CTLR write */ + /* + * Restore base addresses before LPIs are potentially enabled by + * GICR_CTLR write + */ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { GICv3CPUState *c = &s->cpu[ncpu]; @@ -347,12 +350,6 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); reg64 = c->gicr_pendbaser; - if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { - /* Setting PTZ is advised if LPIs are disabled, to reduce - * GIC initialization time. - */ - reg64 |= GICR_PENDBASER_PTZ; - } regl = (uint32_t)reg64; kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); regh = (uint32_t)(reg64 >> 32); From patchwork Thu Jan 30 16:15:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=G2ZBCJG/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487lsv71ygz9sPJ for ; Fri, 31 Jan 2020 03:19:15 +1100 (AEDT) Received: from localhost ([::1]:35138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCXB-0001Xz-R2 for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:19:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43305) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCU9-0005nZ-Dx for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU8-0003Bf-0S for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:05 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:34167) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU7-000393-6p for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:03 -0500 Received: by mail-wr1-x436.google.com with SMTP id t2so4820711wrr.1 for ; Thu, 30 Jan 2020 08:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ERHeiWskVVmxjb2Ajc2jvjv2vBrDDeE9YX+KaKuyjf4=; b=G2ZBCJG/iYrMNladcfXdCekpZM8jYd1JHHFsWOilQ73Zefd2vOrGz4D9oVVfgezEoT QdH9rb9sLwRJdef78rgD+8b87AhR2qn7Fl5hnLuq2xcqsKE4tu0fdkfY2NKZnDwqxVf7 0bwQBMmB4A7QtinzWmeYJpoF+aBkN9OXwYWMP6kRQg/rPrVOvk5crkwgxmCLi+MQLo+K hFtSChMurGr47H+J7HnEhDpV/0T8l3lRFSEpWWV+D/BdDmlinBPFY+sXFOeQiAf8yjur NhONlTvhbylsGOav9fSKo9I9fnkNgOHoIkNed6cW4NVI/uzTb0iFT6D5meFzAc4xptJb h9Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ERHeiWskVVmxjb2Ajc2jvjv2vBrDDeE9YX+KaKuyjf4=; b=TDWAY3Rv2hxOd/ql2hVDa+TBdYLC8BoqXfRNcUCZMQFM2ErDQv8oS+vJ3hAfm/1kYB Cn2VOuTGw2kcwUzidjacm1wbdT1LMYIBvsgPkIyMA11PyNvXwtfC9xaRvQEtps2sAu1/ rVdoWdHlseTyNhIlBYujqt1/kIaP81Sk3JJdJUNoNSuZJNZ1+MGtLsQ1J55asJOkn+sS 7ervGYK/eJLrKxfYFnr/QBOyXFEHYCoEN6fXTvSuyxZzBww67L4JUS/9tBQ9YyLhfvQg LgZaGGndyJCH0sxIMA7qV+pqZGf9mxquscwc5efNtGsvPc8l1LdZXBYWE4BajB0Ntr9w k3vg== X-Gm-Message-State: APjAAAXw8a0Z3X/AfNExtxU8hiV4DEfdSKQkmHwaaLv+8fpB2PEiz7JV M65E4ibczZUwB6Trst9Kbpnd1X4iCMscFg== X-Google-Smtp-Source: APXvYqw6nhgPa2OpCgzJK0y/GBDhjbzAQ+QY1I6gtECFgi9WFYA6PPkRVOtrepqHOfavu2n9Tt+TLQ== X-Received: by 2002:a05:6000:1201:: with SMTP id e1mr512122wrx.386.1580400961981; Thu, 30 Jan 2020 08:16:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] target/arm/kvm: trivial: Clean up header documentation Date: Thu, 30 Jan 2020 16:15:28 +0000 Message-Id: <20200130161533.8180-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Signed-off-by: Andrew Jones Message-id: 20200120101023.16030-2-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 46 ++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8e14d400e8a..b48a9c95573 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -28,9 +28,9 @@ int kvm_arm_vcpu_init(CPUState *cs); /** - * kvm_arm_vcpu_finalize + * kvm_arm_vcpu_finalize: * @cs: CPUState - * @feature: int + * @feature: feature to finalize * * Finalizes the configuration of the specified VCPU feature by * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring @@ -75,8 +75,8 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, int kvm_arm_init_cpreg_list(ARMCPU *cpu); /** - * kvm_arm_reg_syncs_via_cpreg_list - * regidx: KVM register index + * kvm_arm_reg_syncs_via_cpreg_list: + * @regidx: KVM register index * * Return true if this KVM register should be synchronized via the * cpreg list of arbitrary system registers, false if it is synchronized @@ -85,8 +85,8 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); /** - * kvm_arm_cpreg_level - * regidx: KVM register index + * kvm_arm_cpreg_level: + * @regidx: KVM register index * * Return the level of this coprocessor/system register. Return value is * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. @@ -148,6 +148,8 @@ void kvm_arm_init_serror_injection(CPUState *cs); * @cpu: ARMCPU * * Get VCPU related state from kvm. + * + * Returns: 0 if success else < 0 error code */ int kvm_get_vcpu_events(ARMCPU *cpu); @@ -156,6 +158,8 @@ int kvm_get_vcpu_events(ARMCPU *cpu); * @cpu: ARMCPU * * Put VCPU related state to kvm. + * + * Returns: 0 if success else < 0 error code */ int kvm_put_vcpu_events(ARMCPU *cpu); @@ -205,10 +209,12 @@ typedef struct ARMHostCPUFeatures { /** * kvm_arm_get_host_cpu_features: - * @ahcc: ARMHostCPUClass to fill in + * @ahcf: ARMHostCPUClass to fill in * * Probe the capabilities of the host kernel's preferred CPU and fill * in the ARMHostCPUClass struct accordingly. + * + * Returns true on success and false otherwise. */ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); @@ -242,7 +248,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); bool kvm_arm_aarch32_supported(CPUState *cs); /** - * bool kvm_arm_pmu_supported: + * kvm_arm_pmu_supported: * @cs: CPUState * * Returns: true if the KVM VCPU can enable its PMU @@ -251,7 +257,7 @@ bool kvm_arm_aarch32_supported(CPUState *cs); bool kvm_arm_pmu_supported(CPUState *cs); /** - * bool kvm_arm_sve_supported: + * kvm_arm_sve_supported: * @cs: CPUState * * Returns true if the KVM VCPU can enable SVE and false otherwise. @@ -259,26 +265,30 @@ bool kvm_arm_pmu_supported(CPUState *cs); bool kvm_arm_sve_supported(CPUState *cs); /** - * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the - * IPA address space supported by KVM - * + * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle + * + * Returns the number of bits in the IPA address space supported by KVM */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms); /** - * kvm_arm_sync_mpstate_to_kvm + * kvm_arm_sync_mpstate_to_kvm: * @cpu: ARMCPU * * If supported set the KVM MP_STATE based on QEMU's model. + * + * Returns 0 on success and -1 on failure. */ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); /** - * kvm_arm_sync_mpstate_to_qemu + * kvm_arm_sync_mpstate_to_qemu: * @cpu: ARMCPU * * If supported get the MP_STATE from KVM and store in QEMU's model. + * + * Returns 0 on success and aborts on failure. */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); @@ -292,7 +302,8 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { - /* This should never actually be called in the "not KVM" case, + /* + * This should never actually be called in the "not KVM" case, * but set up the fields to indicate an error anyway. */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; @@ -377,23 +388,20 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); * * Return: TRUE if any hardware breakpoints in use. */ - bool kvm_arm_hw_debug_active(CPUState *cs); /** * kvm_arm_copy_hw_debug_data: - * * @ptr: kvm_guest_debug_arch structure * * Copy the architecture specific debug registers into the * kvm_guest_debug ioctl structure. */ struct kvm_guest_debug_arch; - void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); /** - * its_class_name + * its_class_name: * * Return the ITS class name to use depending on whether KVM acceleration * and KVM CAP_SIGNAL_MSI are supported From patchwork Thu Jan 30 16:15:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hz+/JARD; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/26] hw/arm/virt: Add missing 5.0 options call to 4.2 options Date: Thu, 30 Jan 2020 16:15:29 +0000 Message-Id: <20200130161533.8180-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Signed-off-by: Andrew Jones Message-id: 20200120101023.16030-3-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 656b0081c2c..91d4b838b2e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2153,6 +2153,7 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) static void virt_machine_4_2_options(MachineClass *mc) { + virt_machine_5_0_options(mc); compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } DEFINE_VIRT_MACHINE(4, 2) From patchwork Thu Jan 30 16:15:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Z09bGIAJ; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487m9j4y3cz9s1x for ; Fri, 31 Jan 2020 03:32:57 +1100 (AEDT) Received: from localhost ([::1]:35598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCkR-0006t3-Iu for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:32:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43325) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCUA-0005nf-St for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCU9-0003Eb-IV for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:06 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCU9-0003Cn-Cm for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:05 -0500 Received: by mail-wm1-x343.google.com with SMTP id p9so4410870wmc.2 for ; Thu, 30 Jan 2020 08:16:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mqPGs4XNEvxPX2EtaQrvJmfPijwJDTsAZANFfzH5G5A=; b=Z09bGIAJlfDJyyCxeXyPnMAWgPDWnxxCZGqs7adw5mR42gBukizBXxo3obb7DaLjtv t8CHNvZfJ5u23CCOwZXJrMP9Lw99ts/XTm69gJC7wwQTHIOq+nWVHNRpr++QimFkYvSH kI4pzFyq+rU4RCJj2RANhYWIgChmHN1VHrSX7oGn3XROJr+egPuk0+cMNi2w6nkAvTiz Lp3N52wdWOBq97nYKyKfvcpJwn7qcy7iA9juH8Xqcrbjeuxeun3JvbK54qOav64sstvU zIFl6NYtEoaeMatzlpd1jlGEyMTAxF+/w4dL2ORB7oVOjUrMct4fbKpknZrrnmRpiNKJ p1Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mqPGs4XNEvxPX2EtaQrvJmfPijwJDTsAZANFfzH5G5A=; b=YjpzQii47IrXUKqiXTmOQT7gCN2bTdl03EKHq6y2GflXRvsBOR3mMTBnehdyc0XPQr gCuBCrqHKDFt/0w+R+3rrgdj3GceIYfO7m86nmJShX7uoWzCySFnc3mjUt0Vfo83c3CP PaQUOCKepNBkIXklMSK3jW0jmUoB43yg95v7WwZs5Pm8PDpom6IWUeBeGIAZ2k5j3mh4 GNYYYTKE5kxn5J1PhIUHlI7zDyzA1J+x4tbA2BhdKd/B6tnVZidEDhddgU4G9MZoBKLC w69xerXQPzbHfY97bIMevQuF72kXcOBzkQt2ba0bAenuvcs15gE6+uNfAk80uN9F7G8F dr9Q== X-Gm-Message-State: APjAAAXKT79YzbbgrnLCNsYth61GVBCycccNRyc8/GyD1hoZ1n1SdRUA KouxisUzVSqssQSie2HKW7vWamsULy1lYw== X-Google-Smtp-Source: APXvYqxOT6QHWq6RX8rKssGjkiRCfY4N4IO4Z7d4GVJyurrViQorWpC4D5AWUmSKBPZ7EcaHglyCYw== X-Received: by 2002:a1c:7317:: with SMTP id d23mr6601607wmb.165.1580400963959; Thu, 30 Jan 2020 08:16:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/26] target/arm/kvm64: kvm64 cpus have timer registers Date: Thu, 30 Jan 2020 16:15:30 +0000 Message-Id: <20200130161533.8180-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Add the missing GENERIC_TIMER feature to kvm64 cpus. We don't currently use these registers when KVM is enabled, but it's probably best we add the feature flag for consistency and potential future use. There's also precedent, as we add the PMU feature flag to KVM enabled guests, even though we don't use those registers either. This change was originally posted as a hunk of a different, never merged patch from Bijan Mottahedeh. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Message-id: 20200120101023.16030-4-drjones@redhat.com Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6344113a680..8955d23affd 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -604,6 +604,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); + set_feature(&features, ARM_FEATURE_GENERIC_TIMER); ahcf->features = features; From patchwork Thu Jan 30 16:15:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=wVrfV6c3; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 487mDm1Y6Pz9s1x for ; Fri, 31 Jan 2020 03:35:36 +1100 (AEDT) Received: from localhost ([::1]:35700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCn0-0001is-28 for incoming@patchwork.ozlabs.org; Thu, 30 Jan 2020 11:35:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43369) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixCUD-0005qw-7p for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixCUB-0003H2-2a for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:08 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:34862) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixCUA-0003Eh-R2 for qemu-devel@nongnu.org; Thu, 30 Jan 2020 11:16:07 -0500 Received: by mail-wr1-x430.google.com with SMTP id g17so4828289wro.2 for ; Thu, 30 Jan 2020 08:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jCTq+59n1kUdQU8gu/KWOGZ9LyXQo5qog/dLshBHXPE=; b=wVrfV6c3SfEc2Hm69gJte442h7q7AFg/qTYiiiEXwB4j9Dh0Grngz2cQuG+r2j3Zds eW7vRAaR0eF+ES9st8Cv0I0m5dWCmilOc4GlE4eLx58qNhjlrZ6cn2FZOxdD7D7/pBW0 aG9ySu3ovdAl/ytnkowezKUkjZUyzEonoU/qy0XAbYCDS8D5g50UsPei4Rg2fU2PjNlH 7lH3jUJs6QT3hvp41DFO83qqNBVgb1F/Ri3PV7ihLAppegCjO2O5Fkkg9+gr6dXlXN9F Eq4OfKd/TDagfdSaJonXNPMk2uu2w7Xzp6BG7HYX8ToROuRgnZHQkyp+Dz88VRYOPmJm +GRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jCTq+59n1kUdQU8gu/KWOGZ9LyXQo5qog/dLshBHXPE=; b=TU8+NzX3vbLECPSGPn060FxGfvAxhxHn06yQNlmQotYPflv6PY2+yjNMjO+vq1YFpr hgc3M6pFwfoo7JKP0/z/Sw2ULGHy5AK6Kyik89xsZwHcb7u9DrFMhRJfHInbeG49wxxA 5QBxLdlx2fBr1XY7nbw+yXYDKpUkhQVdmMjNz5z7/gt4BpIgEkQFNTOq4JLiFb9mx4Yk 26s0/Y31yKEf8qC5zEqpVftWmCTeVvrDhybfBJ0wAcawUXJWopymohjpZOtp5HFOiEn3 3DOupat/TrCJ5ppMojj8NUWzJCNMLZXwRF6Z8Q7SEG+wwSC1FYVPflIQooVE5BCD0/H1 Ihqw== X-Gm-Message-State: APjAAAXHHvLl92GzKrHPtKUJHo4TFD42qg5wTX7XN+SX1mX+49pHiDcW oqCsrHaZswjyr//UXyTospWMRK5x27d9rw== X-Google-Smtp-Source: APXvYqy/gAg/xJE+bfHIX9bvTbaxNlQF4NjSB8SBi+lnBv3L4uNLVS3mLJo7NSx9gZPJrb0oaVEISg== X-Received: by 2002:a5d:45c4:: with SMTP id b4mr6275654wrs.303.1580400965057; Thu, 30 Jan 2020 08:16:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/26] tests/arm-cpu-features: Check feature default values Date: Thu, 30 Jan 2020 16:15:31 +0000 Message-Id: <20200130161533.8180-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones If we know what the default value should be then we can test for that as well as the feature existence. Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson Message-id: 20200120101023.16030-5-drjones@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/arm-cpu-features.c | 37 +++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bef3ed24b60..a039e3c8d72 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -159,6 +159,25 @@ static bool resp_get_feature(QDict *resp, const char *feature) qobject_unref(_resp); \ }) +#define assert_feature(qts, cpu_type, feature, expected_value) \ +({ \ + QDict *_resp, *_props; \ + \ + _resp = do_query_no_props(qts, cpu_type); \ + g_assert(_resp); \ + g_assert(resp_has_props(_resp)); \ + _props = resp_get_props(_resp); \ + g_assert(qdict_get(_props, feature)); \ + g_assert(qdict_get_bool(_props, feature) == (expected_value)); \ + qobject_unref(_resp); \ +}) + +#define assert_has_feature_enabled(qts, cpu_type, feature) \ + assert_feature(qts, cpu_type, feature, true) + +#define assert_has_feature_disabled(qts, cpu_type, feature) \ + assert_feature(qts, cpu_type, feature, false) + static void assert_type_full(QTestState *qts) { const char *error; @@ -405,16 +424,16 @@ static void test_query_cpu_model_expansion(const void *data) assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL); /* Test expected feature presence/absence for some cpu types */ - assert_has_feature(qts, "max", "pmu"); - assert_has_feature(qts, "cortex-a15", "pmu"); + assert_has_feature_enabled(qts, "max", "pmu"); + assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); if (g_str_equal(qtest_get_arch(), "aarch64")) { - assert_has_feature(qts, "max", "aarch64"); - assert_has_feature(qts, "max", "sve"); - assert_has_feature(qts, "max", "sve128"); - assert_has_feature(qts, "cortex-a57", "pmu"); - assert_has_feature(qts, "cortex-a57", "aarch64"); + assert_has_feature_enabled(qts, "max", "aarch64"); + assert_has_feature_enabled(qts, "max", "sve"); + assert_has_feature_enabled(qts, "max", "sve128"); + assert_has_feature_enabled(qts, "cortex-a57", "pmu"); + assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); sve_tests_default(qts, "max"); @@ -451,8 +470,8 @@ static void test_query_cpu_model_expansion_kvm(const void *data) QDict *resp; char *error; - assert_has_feature(qts, "host", "aarch64"); - assert_has_feature(qts, "host", "pmu"); + assert_has_feature_enabled(qts, "host", "aarch64"); + assert_has_feature_enabled(qts, "host", "pmu"); assert_error(qts, "cortex-a15", "We cannot guarantee the CPU type 'cortex-a15' works " From patchwork Thu Jan 30 16:15:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/26] target/arm/kvm: Implement virtual time adjustment Date: Thu, 30 Jan 2020 16:15:32 +0000 Message-Id: <20200130161533.8180-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones When a VM is stopped (such as when it's paused) guest virtual time should stop counting. Otherwise, when the VM is resumed it will experience time jumps and its kernel may report soft lockups. Not counting virtual time while the VM is stopped has the side effect of making the guest's time appear to lag when compared with real time, and even with time derived from the physical counter. For this reason, this change, which is enabled by default, comes with a KVM CPU feature allowing it to be disabled, restoring legacy behavior. This patch only provides the implementation of the virtual time adjustment. A subsequent patch will provide the CPU property allowing the change to be enabled and disabled. Reported-by: Bijan Mottahedeh Signed-off-by: Andrew Jones Message-id: 20200120101023.16030-6-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 ++++ target/arm/kvm_arm.h | 38 ++++++++++++++++++ target/arm/kvm.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 3 ++ target/arm/kvm64.c | 3 ++ target/arm/machine.c | 7 ++++ 6 files changed, 150 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1aedbeac0d..608fcbd0b75 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -821,6 +821,13 @@ struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* KVM CPU state */ + + /* KVM virtual time adjustment */ + bool kvm_adjvtime; + bool kvm_vtime_dirty; + uint64_t kvm_vtime; + /* Uniprocessor system with MP extensions */ bool mp_is_up; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b48a9c95573..01a9a182785 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -127,6 +127,23 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level); */ bool write_kvmstate_to_list(ARMCPU *cpu); +/** + * kvm_arm_cpu_pre_save: + * @cpu: ARMCPU + * + * Called after write_kvmstate_to_list() from cpu_pre_save() to update + * the cpreg list with KVM CPU state. + */ +void kvm_arm_cpu_pre_save(ARMCPU *cpu); + +/** + * kvm_arm_cpu_post_load: + * @cpu: ARMCPU + * + * Called from cpu_post_load() to update KVM CPU state from the cpreg list. + */ +void kvm_arm_cpu_post_load(ARMCPU *cpu); + /** * kvm_arm_reset_vcpu: * @cpu: ARMCPU @@ -292,6 +309,24 @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); +/** + * kvm_arm_get_virtual_time: + * @cs: CPUState + * + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. + */ +void kvm_arm_get_virtual_time(CPUState *cs); + +/** + * kvm_arm_put_virtual_time: + * @cs: CPUState + * + * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. + */ +void kvm_arm_put_virtual_time(CPUState *cs); + +void kvm_arm_vm_state_change(void *opaque, int running, RunState state); + int kvm_arm_vgic_probe(void); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); @@ -339,6 +374,9 @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} static inline void kvm_arm_pmu_init(CPUState *cs) {} static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} + +static inline void kvm_arm_get_virtual_time(CPUState *cs) {} +static inline void kvm_arm_put_virtual_time(CPUState *cs) {} #endif static inline const char *gic_class_name(void) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8d828891506..e36ab0b38bf 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -357,6 +357,22 @@ static int compare_u64(const void *a, const void *b) return 0; } +/* + * cpreg_values are sorted in ascending order by KVM register ID + * (see kvm_arm_init_cpreg_list). This allows us to cheaply find + * the storage for a KVM register by ID with a binary search. + */ +static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) +{ + uint64_t *res; + + res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, + sizeof(uint64_t), compare_u64); + assert(res); + + return &cpu->cpreg_values[res - cpu->cpreg_indexes]; +} + /* Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). @@ -510,6 +526,23 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) return ok; } +void kvm_arm_cpu_pre_save(ARMCPU *cpu) +{ + /* KVM virtual time adjustment */ + if (cpu->kvm_vtime_dirty) { + *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; + } +} + +void kvm_arm_cpu_post_load(ARMCPU *cpu) +{ + /* KVM virtual time adjustment */ + if (cpu->kvm_adjvtime) { + cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); + cpu->kvm_vtime_dirty = true; + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -577,6 +610,50 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } +void kvm_arm_get_virtual_time(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + struct kvm_one_reg reg = { + .id = KVM_REG_ARM_TIMER_CNT, + .addr = (uintptr_t)&cpu->kvm_vtime, + }; + int ret; + + if (cpu->kvm_vtime_dirty) { + return; + } + + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); + abort(); + } + + cpu->kvm_vtime_dirty = true; +} + +void kvm_arm_put_virtual_time(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + struct kvm_one_reg reg = { + .id = KVM_REG_ARM_TIMER_CNT, + .addr = (uintptr_t)&cpu->kvm_vtime, + }; + int ret; + + if (!cpu->kvm_vtime_dirty) { + return; + } + + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + if (ret) { + error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); + abort(); + } + + cpu->kvm_vtime_dirty = false; +} + int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -688,6 +765,21 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) return MEMTXATTRS_UNSPECIFIED; } +void kvm_arm_vm_state_change(void *opaque, int running, RunState state) +{ + CPUState *cs = opaque; + ARMCPU *cpu = ARM_CPU(cs); + + if (running) { + if (cpu->kvm_adjvtime) { + kvm_arm_put_virtual_time(cs); + } + } else { + if (cpu->kvm_adjvtime) { + kvm_arm_get_virtual_time(cs); + } + } +} int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 32bf8d6757c..3a8b437eef0 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -16,6 +16,7 @@ #include "qemu-common.h" #include "cpu.h" #include "qemu/timer.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "kvm_arm.h" #include "internals.h" @@ -198,6 +199,8 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 8955d23affd..fb21ab9e737 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -23,6 +23,7 @@ #include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "exec/gdbstub.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -734,6 +735,8 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); if (cpu->start_powered_off) { diff --git a/target/arm/machine.c b/target/arm/machine.c index eb28b2381bb..241890ac8cf 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -642,6 +642,12 @@ static int cpu_pre_save(void *opaque) /* This should never fail */ abort(); } + + /* + * kvm_arm_cpu_pre_save() must be called after + * write_kvmstate_to_list() + */ + kvm_arm_cpu_pre_save(cpu); } else { if (!write_cpustate_to_list(cpu, false)) { /* This should never fail. */ @@ -744,6 +750,7 @@ static int cpu_post_load(void *opaque, int version_id) * we're using it. */ write_list_to_cpustate(cpu); + kvm_arm_cpu_post_load(cpu); } else { if (!write_list_to_cpustate(cpu)) { return -1; From patchwork Thu Jan 30 16:15:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1231495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=oyOxrW9u; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a22sm6994442wmd.20.2020.01.30.08.16.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 08:16:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/26] target/arm/cpu: Add the kvm-no-adjvtime CPU property Date: Thu, 30 Jan 2020 16:15:33 +0000 Message-Id: <20200130161533.8180-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200130161533.8180-1-peter.maydell@linaro.org> References: <20200130161533.8180-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones kvm-no-adjvtime is a KVM specific CPU property and a first of its kind. To accommodate it we also add kvm_arm_add_vcpu_properties() and a KVM specific CPU properties description to the CPU features document. Signed-off-by: Andrew Jones Message-id: 20200120101023.16030-7-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + target/arm/kvm_arm.h | 11 ++++++++++ hw/arm/virt.c | 8 ++++++++ target/arm/cpu.c | 2 ++ target/arm/cpu64.c | 1 + target/arm/kvm.c | 28 +++++++++++++++++++++++++ target/arm/monitor.c | 1 + tests/qtest/arm-cpu-features.c | 4 ++++ docs/arm-cpu-features.rst | 37 +++++++++++++++++++++++++++++++++- 9 files changed, 92 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 38f0c33c77c..71508bf40c3 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -109,6 +109,7 @@ typedef struct { bool smbios_old_sys_ver; bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ + bool kvm_no_adjvtime; } VirtMachineClass; typedef struct { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 01a9a182785..ae9e075d754 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -255,6 +255,15 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); */ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); +/** + * kvm_arm_add_vcpu_properties: + * @obj: The CPU object to add the properties to + * + * Add all KVM specific CPU properties to the CPU object. These + * are the CPU properties with "kvm-" prefixed names. + */ +void kvm_arm_add_vcpu_properties(Object *obj); + /** * kvm_arm_aarch32_supported: * @cs: CPUState @@ -345,6 +354,8 @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->host_cpu_probe_failed = true; } +static inline void kvm_arm_add_vcpu_properties(Object *obj) {} + static inline bool kvm_arm_aarch32_supported(CPUState *cs) { return false; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91d4b838b2e..f788fe27d63 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1663,6 +1663,11 @@ static void machvirt_init(MachineState *machine) } } + if (vmc->kvm_no_adjvtime && + object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { + object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); + } + if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { object_property_set_bool(cpuobj, false, "pmu", NULL); } @@ -2153,8 +2158,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) static void virt_machine_4_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_0_options(mc); compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); + vmc->kvm_no_adjvtime = true; } DEFINE_VIRT_MACHINE(4, 2) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 06907b36d7d..f86e71a260d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2551,6 +2551,7 @@ static void arm_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { cortex_a15_initfn(obj); @@ -2743,6 +2744,7 @@ static void arm_host_initfn(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } + kvm_arm_add_vcpu_properties(obj); arm_cpu_post_init(obj); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 61fd0ade29a..2d97bf45e1e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -605,6 +605,7 @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_add_vcpu_properties(obj); } else { uint64_t t; uint32_t u; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e36ab0b38bf..85860e6f954 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -17,6 +17,8 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "qom/object.h" +#include "qapi/error.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -179,6 +181,32 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features = arm_host_cpu_features.features; } +static bool kvm_no_adjvtime_get(Object *obj, Error **errp) +{ + return !ARM_CPU(obj)->kvm_adjvtime; +} + +static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) +{ + ARM_CPU(obj)->kvm_adjvtime = !value; +} + +/* KVM VCPU properties should be prefixed with "kvm-". */ +void kvm_arm_add_vcpu_properties(Object *obj) +{ + if (!kvm_enabled()) { + return; + } + + ARM_CPU(obj)->kvm_adjvtime = true; + object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, + kvm_no_adjvtime_set, &error_abort); + object_property_set_description(obj, "kvm-no-adjvtime", + "Set on to disable the adjustment of " + "the virtual counter. VM stopped time " + "will be counted.", &error_abort); +} + bool kvm_arm_pmu_supported(CPUState *cpu) { return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index fa054f8a369..9725dfff16d 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -103,6 +103,7 @@ static const char *cpu_model_advertised_features[] = { "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", + "kvm-no-adjvtime", NULL }; diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index a039e3c8d72..46921736766 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -428,6 +428,8 @@ static void test_query_cpu_model_expansion(const void *data) assert_has_feature_enabled(qts, "cortex-a15", "pmu"); assert_has_not_feature(qts, "cortex-a15", "aarch64"); + assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { assert_has_feature_enabled(qts, "max", "aarch64"); assert_has_feature_enabled(qts, "max", "sve"); @@ -462,6 +464,8 @@ static void test_query_cpu_model_expansion_kvm(const void *data) return; } + assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); + if (g_str_equal(qtest_get_arch(), "aarch64")) { bool kvm_supports_sve; char max_name[8], name[8]; diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst index 9b537a75e69..dbf3b7cf42c 100644 --- a/docs/arm-cpu-features.rst +++ b/docs/arm-cpu-features.rst @@ -31,7 +31,9 @@ supporting the feature or only supporting the feature under certain configurations. For example, the `aarch64` CPU feature, which, when disabled, enables the optional AArch32 CPU feature, is only supported when using the KVM accelerator and when running on a host CPU type that -supports the feature. +supports the feature. While `aarch64` currently only works with KVM, +it could work with TCG. CPU features that are specific to KVM are +prefixed with "kvm-" and are described in "KVM VCPU Features". CPU Feature Probing =================== @@ -171,6 +173,39 @@ disabling many SVE vector lengths would be quite verbose, the `sve` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). +KVM VCPU Features +================= + +KVM VCPU features are CPU features that are specific to KVM, such as +paravirt features or features that enable CPU virtualization extensions. +The features' CPU properties are only available when KVM is enabled and +are named with the prefix "kvm-". KVM VCPU features may be probed, +enabled, and disabled in the same way as other CPU features. Below is +the list of KVM VCPU features and their descriptions. + + kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This + means that by default the virtual time + adjustment is enabled (vtime is *not not* + adjusted). + + When virtual time adjustment is enabled each + time the VM transitions back to running state + the VCPU's virtual counter is updated to ensure + stopped time is not counted. This avoids time + jumps surprising guest OSes and applications, + as long as they use the virtual counter for + timekeeping. However it has the side effect of + the virtual and physical counters diverging. + All timekeeping based on the virtual counter + will appear to lag behind any timekeeping that + does not subtract VM stopped time. The guest + may resynchronize its virtual counter with + other time sources as needed. + + Enable kvm-no-adjvtime to disable virtual time + adjustment, also restoring the legacy (pre-5.0) + behavior. + SVE CPU Properties ==================