From patchwork Tue Nov 28 02:29:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Chen X-Patchwork-Id: 841955 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Wo+I8hMA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ym8Cp645Wz9sNx for ; Tue, 28 Nov 2017 14:24:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 69BEDC21DA5; Tue, 28 Nov 2017 03:20:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 03699C21DE7; Tue, 28 Nov 2017 03:18:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8BEA7C21D56; Tue, 28 Nov 2017 02:54:07 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id A2663C21C29 for ; Tue, 28 Nov 2017 02:54:05 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id t69so18318279pfg.4 for ; Mon, 27 Nov 2017 18:54:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fm3jkbHCrLmvpByXkh/GyF5+a23nc2D4wBnoBQbM9kQ=; b=Wo+I8hMA3LuPSjj1RDTOqFoW5IAgUkUkBhT30rVzBelAnaQTMhVnbSqPmSn2ljNvDS Xnid7/zH0dppDCeZpBV3ri/2TqaTADAowpajWidoimnYZ7VITf6eVuTrMg9inQKofhOr J2FZbDOabE8MnSZKU/4GWROXGcHRFrNOyGr/M678fMkEETSy5PZkyvYGwPNg1u/xJjmF jvCv9O/pbA3tNDQcPaqWIXqH2/l2UQBCNcDgm1zmGt2/b9z9kIXJlEeAnby8Rp+sBOXg g2t1OEvKPIy6U4x7yjLtG2GVqatF+y/b/7x9dBuAtq8Mr0U0z/Ysne7miqLfLWt9KE/Z TaDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fm3jkbHCrLmvpByXkh/GyF5+a23nc2D4wBnoBQbM9kQ=; b=JQoAROD6eTUXSUqA7O1KcisArGli/z/H+W0IOzZhlGaqEQldjMOBssALVq0VwQ7Mrf L0R2LfCBiXkVMF/1b8sQgO6+9lvwYL8Ee4AmqG9/4COvTRqCrohIOE11L6QxdS+xMgne u+fuosIRp7//D9yOVSoDnaDDZ29ftlGHMMbrGMepjhtFvVmwFbinTaiJmDWG6mObI7BE rJ+2M6u2mnNRE3lHznuGQVVaVpckmDPZHdKTFqnwbZKWoiWH2DPM8C7PCFFLGmvmlDpv TRHW02JdmiBbDLPXRMt6qpyy//ZtvM30UyUmJzSqdaEO5Qxkwa/bWil9pZiCr0cGvB45 Nb9g== X-Gm-Message-State: AJaThX49P8jluZORQZIc/qE2SDsj2wG1xRyNNYSuoncpK7qkwo2MUHxU xlPTYwW1fMP9Vsmdkf97M0Ro3w== X-Google-Smtp-Source: AGs4zMaG4sKrt0fKrjMWHGSkHSpOetObczPIaBBntBeQ/u94KaCyywiP7TAWxAMZJT4Jg2WBsRoS2A== X-Received: by 10.101.74.200 with SMTP id c8mr38403815pgu.369.1511837644160; Mon, 27 Nov 2017 18:54:04 -0800 (PST) Received: from app09.andestech.com ([118.163.51.199]) by smtp.gmail.com with ESMTPSA id d81sm24329254pfj.163.2017.11.27.18.54.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Nov 2017 18:54:03 -0800 (PST) From: Rick Chen To: u-boot@lists.denx.de, wd@denx.de, sjg@chromium.org Date: Tue, 28 Nov 2017 10:29:20 +0800 Message-Id: <1511836163-17728-2-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> References: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> X-Mailman-Approved-At: Tue, 28 Nov 2017 03:18:33 +0000 Subject: [U-Boot] [PATCH v3 1/4] ae3xx: timer: Rename AE3XX to ATCPIT100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick Signed-off-by: Rick Chen Reviewed-by: Simon Glass --- configs/adp-ae3xx_defconfig | 2 +- drivers/timer/Kconfig | 7 +-- drivers/timer/Makefile | 2 +- drivers/timer/ae3xx_timer.c | 117 ---------------------------------------- drivers/timer/atcpit100_timer.c | 117 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 123 insertions(+), 122 deletions(-) delete mode 100644 drivers/timer/ae3xx_timer.c create mode 100644 drivers/timer/atcpit100_timer.c diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index a3a40bf..337cee1 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -35,4 +35,4 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_NDS_AE3XX_SPI=y CONFIG_TIMER=y -CONFIG_AE3XX_TIMER=y +CONFIG_ATCPIT100_TIMER=y diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6305bbf..fcfdf4e 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -105,11 +105,12 @@ config AG101P_TIMER help Select this to enable a timer for AG01P devices. -config AE3XX_TIMER - bool "AE3XX timer support" +config ATCPIT100_TIMER + bool "ATCPIT100 timer support" depends on TIMER && NDS32 help - Select this to enable a timer for AE3XX devices. + Select this to enable a ATCPIT100 timer which will be embeded + in AE3XX, AE250 boards. config ROCKCHIP_TIMER bool "Rockchip timer support" diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 69e8961..15e5154 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,6 @@ obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o -obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o +obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/ae3xx_timer.c deleted file mode 100644 index b710c28..0000000 --- a/drivers/timer/ae3xx_timer.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Andestech ATCPIT100 timer driver - * - * (C) Copyright 2016 - * Rick Chen, NDS32 Software Engineering, rick@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) - -/* - * Definition of register offsets - */ - -/* ID and Revision Register */ -#define ID_REV 0x0 - -/* Configuration Register */ -#define CFG 0x10 - -/* Interrupt Enable Register */ -#define INT_EN 0x14 -#define CH_INT_EN(c , i) ((1<platdata; - u32 val; - val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); - *count = timer_conv_64(val); - return 0; -} - -static int atctmr_timer_probe(struct udevice *dev) -{ - struct atftmr_timer_platdata *plat = dev->platdata; - REG32_TMR(CH_REL(1)) = 0xffffffff; - REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; - REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); - return 0; -} - -static int atctme_timer_ofdata_to_platdata(struct udevice *dev) -{ - struct atftmr_timer_platdata *plat = dev_get_platdata(dev); - plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); - return 0; -} - -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, -}; - -static const struct udevice_id ag101p_timer_ids[] = { - { .compatible = "andestech,atcpit100" }, - {} -}; - -U_BOOT_DRIVER(altera_timer) = { - .name = "ae3xx_timer", - .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), - .probe = atctmr_timer_probe, - .ops = &ag101p_timer_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c new file mode 100644 index 0000000..b710c28 --- /dev/null +++ b/drivers/timer/atcpit100_timer.c @@ -0,0 +1,117 @@ +/* + * Andestech ATCPIT100 timer driver + * + * (C) Copyright 2016 + * Rick Chen, NDS32 Software Engineering, rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) + +/* + * Definition of register offsets + */ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN(c , i) ((1<platdata; + u32 val; + val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); + *count = timer_conv_64(val); + return 0; +} + +static int atctmr_timer_probe(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + REG32_TMR(CH_REL(1)) = 0xffffffff; + REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; + REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); + return 0; +} + +static int atctme_timer_ofdata_to_platdata(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); + return 0; +} + +static const struct timer_ops ag101p_timer_ops = { + .get_count = atftmr_timer_get_count, +}; + +static const struct udevice_id ag101p_timer_ids[] = { + { .compatible = "andestech,atcpit100" }, + {} +}; + +U_BOOT_DRIVER(altera_timer) = { + .name = "ae3xx_timer", + .id = UCLASS_TIMER, + .of_match = ag101p_timer_ids, + .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), + .probe = atctmr_timer_probe, + .ops = &ag101p_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Nov 28 02:29:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Chen X-Patchwork-Id: 841957 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UUtWJO2V"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ym8Cx65Qkz9sNx for ; Tue, 28 Nov 2017 14:24:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 88EEEC21DCE; Tue, 28 Nov 2017 03:20:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 805F0C21E06; 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Mon, 27 Nov 2017 18:54:05 -0800 (PST) From: Rick Chen To: u-boot@lists.denx.de, wd@denx.de, sjg@chromium.org Date: Tue, 28 Nov 2017 10:29:21 +0800 Message-Id: <1511836163-17728-3-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> References: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> X-Mailman-Approved-At: Tue, 28 Nov 2017 03:18:33 +0000 Subject: [U-Boot] [PATCH v3 2/4] cosmetic: atcpit100_timer: Rename function name as atcpit100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: rick Signed-off-by: Rick Chen --- drivers/timer/atcpit100_timer.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c index b710c28..d5146dd 100644 --- a/drivers/timer/atcpit100_timer.c +++ b/drivers/timer/atcpit100_timer.c @@ -67,51 +67,51 @@ struct atctmr_timer_regs { u32 int_mask; /* 0x38 */ }; -struct atftmr_timer_platdata { +struct atcpit_timer_platdata { u32 *regs; }; -static int atftmr_timer_get_count(struct udevice *dev, u64 *count) +static int atcpit_timer_get_count(struct udevice *dev, u64 *count) { - struct atftmr_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev->platdata; u32 val; val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); *count = timer_conv_64(val); return 0; } -static int atctmr_timer_probe(struct udevice *dev) +static int atcpit_timer_probe(struct udevice *dev) { - struct atftmr_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev->platdata; REG32_TMR(CH_REL(1)) = 0xffffffff; REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); return 0; } -static int atctme_timer_ofdata_to_platdata(struct udevice *dev) +static int atcpit_timer_ofdata_to_platdata(struct udevice *dev) { - struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE); return 0; } -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, +static const struct timer_ops atcpit_timer_ops = { + .get_count = atcpit_timer_get_count, }; -static const struct udevice_id ag101p_timer_ids[] = { +static const struct udevice_id atcpit_timer_ids[] = { { .compatible = "andestech,atcpit100" }, {} }; -U_BOOT_DRIVER(altera_timer) = { - .name = "ae3xx_timer", +U_BOOT_DRIVER(atcpit100_timer) = { + .name = "atcpit100_timer", .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), - .probe = atctmr_timer_probe, - .ops = &ag101p_timer_ops, + .of_match = atcpit_timer_ids, + .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata), + .probe = atcpit_timer_probe, + .ops = &atcpit_timer_ops, .flags = DM_FLAG_PRE_RELOC, }; From patchwork Tue Nov 28 02:29:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Chen X-Patchwork-Id: 841953 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VWFwM4XT"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ym8BH06HGz9sNx for ; Tue, 28 Nov 2017 14:23:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B28A1C21DB2; Tue, 28 Nov 2017 03:21:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2D4E6C21DB9; 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Mon, 27 Nov 2017 18:54:06 -0800 (PST) From: Rick Chen To: u-boot@lists.denx.de, wd@denx.de, sjg@chromium.org Date: Tue, 28 Nov 2017 10:29:22 +0800 Message-Id: <1511836163-17728-4-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> References: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> X-Mailman-Approved-At: Tue, 28 Nov 2017 03:18:33 +0000 Subject: [U-Boot] [PATCH v3 3/4] cosmetic: atcpit100_timer: Use device api to get platdata X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use dev_get_platdata to get private platdata. Signed-off-by: rick Signed-off-by: Rick Chen Reviewed-by: Simon Glass --- drivers/timer/atcpit100_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c index d5146dd..963f978 100644 --- a/drivers/timer/atcpit100_timer.c +++ b/drivers/timer/atcpit100_timer.c @@ -73,7 +73,7 @@ struct atcpit_timer_platdata { static int atcpit_timer_get_count(struct udevice *dev, u64 *count) { - struct atcpit_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); u32 val; val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); *count = timer_conv_64(val); @@ -82,7 +82,7 @@ static int atcpit_timer_get_count(struct udevice *dev, u64 *count) static int atcpit_timer_probe(struct udevice *dev) { - struct atcpit_timer_platdata *plat = dev->platdata; + struct atcpit_timer_platdata *plat = dev_get_platdata(dev); REG32_TMR(CH_REL(1)) = 0xffffffff; REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); 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Mon, 27 Nov 2017 18:54:08 -0800 (PST) From: Rick Chen To: u-boot@lists.denx.de, wd@denx.de, sjg@chromium.org Date: Tue, 28 Nov 2017 10:29:23 +0800 Message-Id: <1511836163-17728-5-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> References: <1511836163-17728-1-git-send-email-rickchen36@gmail.com> X-Mailman-Approved-At: Tue, 28 Nov 2017 03:18:33 +0000 Subject: [U-Boot] [PATCH v3 4/4] dt-bindings: timer: Add andestech atcpit100 timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a document to describe Andestech atcpit100 timer and binding information. Signed-off-by: rick Signed-off-by: Rick Chen Reviewed-by: Simon Glass --- doc/device-tree-bindings/timer/atcpit100_timer.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 doc/device-tree-bindings/timer/atcpit100_timer.txt diff --git a/doc/device-tree-bindings/timer/atcpit100_timer.txt b/doc/device-tree-bindings/timer/atcpit100_timer.txt new file mode 100644 index 0000000..620814e --- /dev/null +++ b/doc/device-tree-bindings/timer/atcpit100_timer.txt @@ -0,0 +1,31 @@ +Andestech ATCPIT100 timer +------------------------------------------------------------------ +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX, AE250 platforms and other designs. + +This timer is a set of compact multi-function timers, which can be +used as pulse width modulators (PWM) as well as simple timers. + +It supports up to 4 PIT channels. Each PIT channel is a +multi-function timer and provide the following usage scenarios: +One 32-bit timer +Two 16-bit timers +Four 8-bit timers +One 16-bit PWM +One 16-bit timer and one 8-bit PWM +Two 8-bit timer and one 8-bit PWM + +Required properties: +- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer + +Examples: + +timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <30000000>; +}: