From patchwork Tue Jan 21 07:28:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1226267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4820XL27Jmz9sPJ for ; Tue, 21 Jan 2020 18:29:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mUg/mou+; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4820XL1cvSzDqTx for ; Tue, 21 Jan 2020 18:29:06 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mUg/mou+; dkim-atps=neutral Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4820X75lBTzDqTJ for ; Tue, 21 Jan 2020 18:28:53 +1100 (AEDT) Received: by mail-pf1-x444.google.com with SMTP id i6so1042498pfc.1 for ; Mon, 20 Jan 2020 23:28:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b9/6clzKCyggaW6BV//9KX6hHKPow/bX4HKCAa7jf8Y=; b=mUg/mou+f87b2+2RXbXLrMaYY4H50eVjdUL74WC5Afdg5Gy9zA9FLgKNQjTfdsXgQ/ VQuMYZTmWeHfLMEnOKoTQTixlX/CPMhM7wuJMwn7jwNF61qPNrM75xOteBw4T57UHD74 cLyVGkyVHvZPWJw3qaJr380I9CtI5oEnHFzbzZig+sDByfTneeBg7+R6EBe69NdfF6yC GNb9j6zQgcEUhexqDognI7ipM9ZZdQG1NJuNM4VluyQ02p+EtEmflfIUZUO5Gv7Hv/ms LXuneicTc7/t7eBSkk9QZWft8jbSc0e1Qr4RXwMYJeKFSChLZjtkQY0Jrf5RmnTFdvDE p/qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b9/6clzKCyggaW6BV//9KX6hHKPow/bX4HKCAa7jf8Y=; b=ZadQMJkGc6BSTHa2PoNpx7UDoPAaXHN4w2AMwcphdRQxFy6kPMT3ccRFeffrrq10Ri Vq6v7yxi2qezYnDPg9fRdJ7beYnISgMzs6G1LUmvk0qVPcYURho2ID4cFB0JBg7TxfhH mdcyXmCkgAA6WUiZ7QVnXLe/8xyVXUk7mhUgd2e9nn3SaLfnfJ2ZvtV7eIByGh97ryzo 5BDNVSV7QAVBLZIbdnYMDJFI+V4o12z1IE19I4h5lQP0STuJczL4p4wl+pnsBr1A3jXb RitazKeKfxrrRUHcr7Hm1Xd+theVDYMjLE0LE0DRZFK84ambw5rNiGsl4FpQ+CEdP1JH hhTg== X-Gm-Message-State: APjAAAVj3fzm7drbygJgVLHDlKzVc8bUVmXQmvvOViJ/RBNu4EIet0+U 176Sd0mJrPJvKqFAHIdDjdmBuu3w X-Google-Smtp-Source: APXvYqzVvLCjjApuEtZF8ow0nEQDx103kH+AWVYhPID50UWu9uiI3NFpS9i5hi9e1fH3UVddsuQrSA== X-Received: by 2002:a63:3196:: with SMTP id x144mr3924481pgx.319.1579591729729; Mon, 20 Jan 2020 23:28:49 -0800 (PST) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id u3sm41027750pga.72.2020.01.20.23.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 23:28:49 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 21 Jan 2020 18:28:34 +1100 Message-Id: <20200121072838.2771-1-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 Subject: [Skiboot] [PATCH 1/5] hw/phb4: Make error interrupt handler compile X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When phb4.c was copied from phb3.c the error interrupts were disabled by default and apparently never re-enabled. Remove the #if 0 block and call phb4_set_err_pending() rather than the phb3 version. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index ed7f4e5c4756..0b7bf778a50e 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5585,7 +5585,6 @@ static void phb4_err_interrupt(struct irq_source *is, uint32_t isn) PHBDBG(p, "Got interrupt 0x%08x\n", isn); -#if 0 /* Update pending event */ opal_update_pending_evt(OPAL_EVENT_PCI_ERROR, OPAL_EVENT_PCI_ERROR); @@ -5598,8 +5597,7 @@ static void phb4_err_interrupt(struct irq_source *is, uint32_t isn) * Mark the PHB has pending error so that the OS * can handle it at late point. */ - phb3_set_err_pending(p, true); -#endif + phb4_set_err_pending(p, true); } static uint64_t phb4_lsi_attributes(struct irq_source *is __unused, From patchwork Tue Jan 21 07:28:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1226268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4820Xf53LPz9sPJ for ; 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Mon, 20 Jan 2020 23:28:51 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 21 Jan 2020 18:28:35 +1100 Message-Id: <20200121072838.2771-2-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200121072838.2771-1-oohall@gmail.com> References: <20200121072838.2771-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/5] hw/phb4: Fix interrupt names X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Linux doesn't seem to parse the interrupt-names property when there are unnamed (zero length string) interrupts. Add a name callback to the interrupt source and go from there. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 0b7bf778a50e..2591c0390d5f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5613,9 +5613,26 @@ static uint64_t phb4_lsi_attributes(struct irq_source *is __unused, return IRQ_ATTR_TARGET_LINUX; } +static char *phb4_lsi_name(struct irq_source *is, uint32_t isn) +{ + struct phb4 *p = is->data; + uint32_t idx = isn - p->base_lsi; + char buf[32]; + + if (idx == PHB4_LSI_PCIE_INF) + snprintf(buf, 32, "phb#%04x-inf", p->phb.opal_id); + else if (idx == PHB4_LSI_PCIE_ER) + snprintf(buf, 32, "phb#%04x-err", p->phb.opal_id); + else + assert(0); /* PCIe LSIs should never be directed to OPAL */ + + return strdup(buf); +} + static const struct irq_source_ops phb4_lsi_ops = { .interrupt = phb4_err_interrupt, .attributes = phb4_lsi_attributes, + .name = phb4_lsi_name, }; static __be64 lane_eq_default[8] = { From patchwork Tue Jan 21 07:28:36 2020 Content-Type: text/plain; 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Mon, 20 Jan 2020 23:28:53 -0800 (PST) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id u3sm41027750pga.72.2020.01.20.23.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2020 23:28:53 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 21 Jan 2020 18:28:36 +1100 Message-Id: <20200121072838.2771-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200121072838.2771-1-oohall@gmail.com> References: <20200121072838.2771-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/5] hw/phb4: Don't disable TXE(12) interrupt if on P9 DD2.0 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Commit 7dbf80d1db45 ("phb4: Generate checkstop on AIB ECC corr/uncorr for DD2.0 parts") changed the PHB inits so that on DD2.0 TXE error bit 12 would cause a checkstop. The patch also changes the TXE_ERR_IRQ_ENABLE settings to prevent this bit from causing a PHB error interrupt. However, there's not much point in doing this since the system is going to checkstop anyway. Removing the code to disable the interrupt simplifies the situation a bit and avoids conflating FIR propagation with the normal PHB error interrupts. The PHB spec is actively confusing in this area since it describes the TXE Error summary bit in the LEM FIR as an "interrupt" even though it's completely seperate to the PHB's LSI error reporting interrupt. Cc: Michael Neuling Signed-off-by: Oliver O'Halloran --- Mikey, please check if I'm speaking crap. I might have missed something. --- hw/phb4.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 2591c0390d5f..7bbed8a8a829 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5303,10 +5303,7 @@ static void phb4_init_hw(struct phb4 *p) /* Init_126..130 - Re-enable error interrupts */ out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0xca8880cc00000000ull); - if (phb4_is_dd20(p)) - out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2000400e08200000ull); - else - out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2008400e08200000ull); + out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2008400e08200000ull); out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE, 0xc40038fc01804070ull); out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE, 0x00006100008000a8ull); out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE, 0x60510050c0000000ull); From patchwork Tue Jan 21 07:28:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1226270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4820YH2tJQz9sPJ for ; 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Mon, 20 Jan 2020 23:28:55 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 21 Jan 2020 18:28:37 +1100 Message-Id: <20200121072838.2771-4-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200121072838.2771-1-oohall@gmail.com> References: <20200121072838.2771-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 4/5] hw/phb4: Factor out interrupt setup X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move the unmasking (enabling) of the various PHB error and informational interrupts out of the main init sequence. We'll need this elsewhere to enable the PHB error interrupts. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 7bbed8a8a829..5f8b9b8f7ac8 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3501,6 +3501,16 @@ static struct pci_slot *phb4_slot_create(struct phb *phb) return slot; } +static void phb4_int_unmask_all(struct phb4 *p) +{ + /* Init_126..130 - Re-enable error interrupts */ + out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0xca8880cc00000000ull); + out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE, 0x2008400e08200000ull); + out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE, 0xc40038fc01804070ull); + out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE, 0x00006100008000a8ull); + out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE, 0x60510050c0000000ull); +} + static uint64_t phb4_get_pesta(struct phb4 *p, uint64_t pe_number) { uint64_t pesta; @@ -5302,11 +5312,7 @@ static void phb4_init_hw(struct phb4 *p) PCI_CFG_STAT_RECV_PERR); /* Init_126..130 - Re-enable error interrupts */ - out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0xca8880cc00000000ull); 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Mon, 20 Jan 2020 23:28:57 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 21 Jan 2020 18:28:38 +1100 Message-Id: <20200121072838.2771-5-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200121072838.2771-1-oohall@gmail.com> References: <20200121072838.2771-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 5/5] hw/phb4: Enable error interrupts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" In PHB4 the PHB's error and informational interrupts were changed to behave more like actual LSIs. On PHB3 these interrupts would be only be raised on a 0 -> 1 transition of an error status bits (i.e. they were rising edge triggered). On PHB4 the error interrupts are "true" LSIs and will be re-raised as long the underlying error status bit is set. This causes a headache for us because OPAL's PHB error handling model requires Skiboot to preserve the state of the PHB (including errors) until the kernel is ready to handle the error. As a result we can't do anything in Skiboot to handle the interrupt condition and we need to mask the error internally. We can do this by clearing the relevant bits in the IRQ_ENABLE registers of the PHB. It's worth pointing out that we don't want to mask the interrupt by setting the Q bit in the XIVE ESBs. The ESBs are owned by the OS which may be masking and unmasking the interrupt for its own reasons (e.g. migrating IRQs). Skiboot modifying the ESB state could potentially cause problems and should be avoided. Cc: Cédric Le Goater Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/hw/phb4.c b/hw/phb4.c index 5f8b9b8f7ac8..da3a965903b4 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -114,7 +114,7 @@ #include /* Enable this to disable error interrupts for debug purposes */ -#define DISABLE_ERR_INTS +#undef DISABLE_ERR_INTS static void phb4_init_hw(struct phb4 *p); @@ -3511,6 +3511,33 @@ static void phb4_int_unmask_all(struct phb4 *p) out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE, 0x60510050c0000000ull); } +/* + * Mask the IRQ for any currently set error bits. This prevents the PHB's ERR + * and INF interrupts from being re-fired before the kernel can handle the + * underlying condition. + */ +static void phb4_int_mask_active(struct phb4 *p) +{ + const uint64_t error_regs[] = { + PHB_ERR_STATUS, + PHB_TXE_ERR_STATUS, + PHB_RXE_ARB_ERR_STATUS, + PHB_RXE_MRG_ERR_STATUS, + PHB_RXE_TCE_ERR_STATUS + }; + int i; + + for (i = 0; i < ARRAY_SIZE(error_regs); i++) { + uint64_t stat, mask; + + /* The IRQ mask reg is always offset 0x20 from the status reg */ + stat = phb4_read_reg(p, error_regs[i]); + mask = phb4_read_reg(p, error_regs[i] + 0x20); + + phb4_write_reg(p, error_regs[i] + 0x20, mask & ~stat); + } +} + static uint64_t phb4_get_pesta(struct phb4 *p, uint64_t pe_number) { uint64_t pesta; @@ -3828,6 +3855,14 @@ static int64_t phb4_eeh_next_error(struct phb *phb, *severity = OPAL_EEH_SEV_NO_ERROR; phb4_set_err_pending(p, false); } + + /* + * Unmask all our error interrupts once all pending errors + * have been handled. + */ + if (!phb4_err_pending(p)) + phb4_int_unmask_all(p); + return OPAL_SUCCESS; } @@ -5588,6 +5623,9 @@ static void phb4_err_interrupt(struct irq_source *is, uint32_t isn) PHBDBG(p, "Got interrupt 0x%08x\n", isn); + /* mask the interrupt conditions to prevent it from re-firing */ + phb4_int_mask_active(p); + /* Update pending event */ opal_update_pending_evt(OPAL_EVENT_PCI_ERROR, OPAL_EVENT_PCI_ERROR);