From patchwork Sat Nov 25 19:32:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjxP6k36z9s71 for ; Sun, 26 Nov 2017 06:36:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752054AbdKYTgu (ORCPT ); Sat, 25 Nov 2017 14:36:50 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13824 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751631AbdKYTcp (ORCPT ); Sat, 25 Nov 2017 14:32:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sat, 25 Nov 2017 11:32:16 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:27 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:27 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:26 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:26 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:26 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:25 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 1/9] genirq: Export irq_set_msi_desc() Date: Sun, 26 Nov 2017 01:02:05 +0530 Message-ID: <1511638333-22951-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCI MSI driver allocates MSI entry for each pci dev which creates msi_desc, host driver maps each msi domain with hwirq and then sets msi_desc for that irq number. Need to export irq_set_msi_desc() to allow Tegra PCIe driver to be compiled as a loadable kernel module. Signed-off-by: Manikanta Maddireddy --- V2: * commit message update kernel/irq/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 043bfc35b353..0e74b1051267 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -136,6 +136,7 @@ int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) { return irq_set_msi_desc_off(irq, 0, entry); } +EXPORT_SYMBOL(irq_set_msi_desc); /** * irq_set_chip_data - set irq chip data for an irq From patchwork Sat Nov 25 19:32:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841293 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjxG471Dz9s7G for ; Sun, 26 Nov 2017 06:36:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751970AbdKYTgr (ORCPT ); Sat, 25 Nov 2017 14:36:47 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19026 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751666AbdKYTcp (ORCPT ); Sat, 25 Nov 2017 14:32:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:33 -0800 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:30 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:30 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:30 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:30 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:29 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 2/9] of: Export of_pci_range_to_resource() Date: Sun, 26 Nov 2017 01:02:06 +0530 Message-ID: <1511638333-22951-3-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra PCIe host driver parses of_pci_range from device tree and converts to resource. Export of_pci_range_to_resource() to allow Tegra PCIe host driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy Acked-by: Rob Herring --- V2: * commit message update drivers/of/address.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/address.c b/drivers/of/address.c index fa6cabfc3cb9..8d9b93f8701a 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -361,6 +361,7 @@ int of_pci_range_to_resource(struct of_pci_range *range, res->end = (resource_size_t)OF_BAD_ADDR; return err; } +EXPORT_SYMBOL(of_pci_range_to_resource); #endif /* CONFIG_PCI */ /* From patchwork Sat Nov 25 19:32:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjxM4GnCz9s4s for ; Sun, 26 Nov 2017 06:36:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751631AbdKYTgw (ORCPT ); Sat, 25 Nov 2017 14:36:52 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19019 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751630AbdKYTcp (ORCPT ); Sat, 25 Nov 2017 14:32:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:40 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:38 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:38 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:38 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:33 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:33 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 3/9] ARM: tegra: Export tegra_cpuidle_pcie_irqs_in_use() Date: Sun, 26 Nov 2017 01:02:07 +0530 Message-ID: <1511638333-22951-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra20 has a HW bug where PCIe interrupts are lost when LP2 (Tegra idle state) is enabled. tegra_cpuidle_pcie_irqs_in_use() disables LP2 when PCIe irq is mapped. EXPORT tegra_cpuidle_pcie_irqs_in_use() to allow Tegra PCIe driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy --- V2: * commit message update arch/arm/mach-tegra/cpuidle.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 316563141add..7d7e6d3ce32d 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -57,3 +57,4 @@ void tegra_cpuidle_pcie_irqs_in_use(void) break; } } +EXPORT_SYMBOL(tegra_cpuidle_pcie_irqs_in_use); From patchwork Sat Nov 25 19:32:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjxY5t7Kz9s7G for ; Sun, 26 Nov 2017 06:37:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751664AbdKYThD (ORCPT ); Sat, 25 Nov 2017 14:37:03 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13816 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbdKYTcp (ORCPT ); Sat, 25 Nov 2017 14:32:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sat, 25 Nov 2017 11:32:27 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:37 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:37 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:37 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:37 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 4/9] PCI: Export pci_find_host_bridge() Date: Sun, 26 Nov 2017 01:02:08 +0530 Message-ID: <1511638333-22951-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCI subsystem pass pci_bus pointer to pci_ops callback functions, Tegra host driver use pci_find_host_bridge() to get pci_host_bridge from pci_bus. Export pci_find_host_bridge() to allow Tegra PCIe driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy --- V2: * commit message update drivers/pci/host-bridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c index add66236215c..e0942fc086ad 100644 --- a/drivers/pci/host-bridge.c +++ b/drivers/pci/host-bridge.c @@ -22,6 +22,7 @@ struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus) return to_pci_host_bridge(root_bus->bridge); } +EXPORT_SYMBOL(pci_find_host_bridge); struct device *pci_get_host_bridge_device(struct pci_dev *dev) { From patchwork Sat Nov 25 19:32:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjx84HcSz9s4s for ; Sun, 26 Nov 2017 06:36:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751976AbdKYTgn (ORCPT ); Sat, 25 Nov 2017 14:36:43 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13821 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684AbdKYTcs (ORCPT ); Sat, 25 Nov 2017 14:32:48 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sat, 25 Nov 2017 11:32:31 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:33:21 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 25 Nov 2017 11:33:21 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:41 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:41 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:41 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:40 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 5/9] PCI: Export pci_flags Date: Sun, 26 Nov 2017 01:02:09 +0530 Message-ID: <1511638333-22951-6-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org pci_flags variable is used in inline functions in 'pci.h', Tegra PCIe driver use one of these functions pci_add_flags() and includes 'pci.h'. Export pci_flags to allow Tegra PCIe host controller driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy --- V2: * commit message update drivers/pci/setup-bus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b1ad466199ad..3567e1c4e340 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -29,6 +29,7 @@ #include "pci.h" unsigned int pci_flags; +EXPORT_SYMBOL(pci_flags); struct pci_dev_resource { struct list_head list; From patchwork Sat Nov 25 19:32:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjxH3Z67z9s4s for ; Sun, 26 Nov 2017 06:36:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752008AbdKYTgt (ORCPT ); Sat, 25 Nov 2017 14:36:49 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19025 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751664AbdKYTcp (ORCPT ); Sat, 25 Nov 2017 14:32:45 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:47 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:33:25 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 25 Nov 2017 11:33:25 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:45 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:44 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:44 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 6/9] PCI: tegra: free resources on probe failure Date: Sun, 26 Nov 2017 01:02:10 +0530 Message-ID: <1511638333-22951-7-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org tegra_pcie_probe() can fail in multiple instances, this patch takes care of freeing the resources which are allocated before probe fail. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 102 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 86 insertions(+), 16 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e9b3ff95e259..7f7b8c9c1e84 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -701,14 +701,25 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie) pci_add_resource(windows, &pcie->busn); err = devm_request_pci_bus_resources(dev, windows); - if (err < 0) + if (err < 0) { + pci_free_resource_list(windows); return err; + } pci_remap_iospace(&pcie->pio, pcie->io.start); return 0; } +static void tegra_pcie_free_resources(struct tegra_pcie *pcie) +{ + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct list_head *windows = &host->windows; + + pci_unmap_iospace(&pcie->pio); + pci_free_resource_list(windows); +} + static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) { struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); @@ -1109,29 +1120,40 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) return 0; } -static void tegra_pcie_power_off(struct tegra_pcie *pcie) +static void tegra_pcie_disable_controller(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; const struct tegra_pcie_soc *soc = pcie->soc; int err; - /* TODO: disable and unprepare clocks? */ - if (soc->program_uphy) { err = tegra_pcie_phy_power_off(pcie); if (err < 0) dev_err(dev, "failed to power off PHY(s): %d\n", err); } +} + +static void tegra_pcie_power_off(struct tegra_pcie *pcie) +{ + struct device *dev = pcie->dev; + const struct tegra_pcie_soc *soc = pcie->soc; + int err; reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); - if (!dev->pm_domain) - tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); + clk_disable_unprepare(pcie->pll_e); + if (soc->has_cml_clk) + clk_disable_unprepare(pcie->cml_clk); + clk_disable_unprepare(pcie->afi_clk); + clk_disable_unprepare(pcie->pex_clk); err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); if (err < 0) dev_warn(dev, "failed to disable regulators: %d\n", err); + + if (!dev->pm_domain) + tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); } static int tegra_pcie_power_on(struct tegra_pcie *pcie) @@ -1262,6 +1284,15 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_phys_put_legacy(struct tegra_pcie *pcie) +{ + int err; + + err = phy_exit(pcie->phy); + if (err < 0) + dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); +} + static struct phy *devm_of_phy_optional_get_index(struct device *dev, struct device_node *np, const char *consumer, @@ -1315,6 +1346,19 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port) return 0; } +static void tegra_pcie_port_put_phys(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + unsigned int i; + int err; + + for (i = 0; i < port->lanes; i++) { + err = phy_exit(port->phys[i]); + if (err < 0) + dev_err(dev, "failed to teardown PHY#%u: %d\n", i, err); + } +} + static int tegra_pcie_phys_get(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -1334,6 +1378,19 @@ static int tegra_pcie_phys_get(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_phys_put(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + struct device_node *np = pcie->dev->of_node; + struct tegra_pcie_port *port; + + if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL) + tegra_pcie_phys_put_legacy(pcie); + + list_for_each_entry(port, &pcie->ports, list) + tegra_pcie_port_put_phys(port); +} + static int tegra_pcie_get_resources(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; @@ -1366,7 +1423,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = tegra_pcie_power_on(pcie); if (err) { dev_err(dev, "failed to power up: %d\n", err); - return err; + goto phys_put; } pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); @@ -1424,25 +1481,23 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) poweroff: tegra_pcie_power_off(pcie); +phys_put: + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); return err; } static int tegra_pcie_put_resources(struct tegra_pcie *pcie) { - struct device *dev = pcie->dev; const struct tegra_pcie_soc *soc = pcie->soc; - int err; if (pcie->irq > 0) free_irq(pcie->irq, pcie); tegra_pcie_power_off(pcie); - if (soc->program_uphy) { - err = phy_exit(pcie->phy); - if (err < 0) - dev_err(dev, "failed to teardown PHY: %d\n", err); - } + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); return 0; } @@ -2371,6 +2426,16 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_disable_ports(struct tegra_pcie *pcie) +{ + struct tegra_pcie_port *port, *tmp; + + reset_control_assert(pcie->pcie_xrst); + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_port_disable(port); +} + static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, struct pci_dev *pci_dev) { @@ -2691,7 +2756,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_request_resources(pcie); if (err) - goto put_resources; + goto disable_controller; /* setup the AFI address translations */ tegra_pcie_setup_translations(pcie); @@ -2700,7 +2765,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_enable_msi(pcie); if (err < 0) { dev_err(dev, "failed to enable MSI support: %d\n", err); - goto put_resources; + goto free_resources; } } @@ -2741,6 +2806,11 @@ static int tegra_pcie_probe(struct platform_device *pdev) disable_msi: if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + tegra_pcie_disable_ports(pcie); +free_resources: + tegra_pcie_free_resources(pcie); +disable_controller: + tegra_pcie_disable_controller(pcie); put_resources: tegra_pcie_put_resources(pcie); return err; From patchwork Sat Nov 25 19:32:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjx071XSz9s4s for ; Sun, 26 Nov 2017 06:36:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751888AbdKYTge (ORCPT ); Sat, 25 Nov 2017 14:36:34 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19027 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751698AbdKYTct (ORCPT ); Sat, 25 Nov 2017 14:32:49 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:51 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:49 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:48 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:48 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 7/9] PCI: tegra: Add loadable kernel module support Date: Sun, 26 Nov 2017 01:02:11 +0530 Message-ID: <1511638333-22951-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Implement remove callback function for Tegra PCIe driver to add loadable kernel module support. Change PCI_TEGRA config to tristate to allow pci-tegra driver to be build as a module. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-tegra.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 38d12980db0f..6fd2a5937804 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -34,7 +34,7 @@ config PCI_FTPCI100 default ARCH_GEMINI config PCI_TEGRA - bool "NVIDIA Tegra PCIe controller" + tristate "NVIDIA Tegra PCIe controller" depends on ARCH_TEGRA help Say Y here if you want support for the PCIe host controller found diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 7f7b8c9c1e84..bbc2807bcd4a 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -2720,6 +2721,12 @@ static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) return -ENOMEM; } +static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie) +{ + debugfs_remove_recursive(pcie->debugfs); + pcie->debugfs = NULL; +} + static int tegra_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2734,6 +2741,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) return -ENOMEM; pcie = pci_host_bridge_priv(host); + platform_set_drvdata(pdev, pcie); pcie->soc = of_device_get_match_data(dev); INIT_LIST_HEAD(&pcie->buses); @@ -2816,6 +2824,25 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } +static int tegra_pcie_remove(struct platform_device *pdev) +{ + struct tegra_pcie *pcie = platform_get_drvdata(pdev); + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + + if (IS_ENABLED(CONFIG_DEBUG_FS)) + tegra_pcie_debugfs_exit(pcie); + pci_stop_root_bus(host->bus); + pci_remove_root_bus(host->bus); + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + tegra_pcie_disable_ports(pcie); + tegra_pcie_free_resources(pcie); + tegra_pcie_disable_controller(pcie); + tegra_pcie_put_resources(pcie); + + return 0; +} + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", @@ -2823,5 +2850,7 @@ static struct platform_driver tegra_pcie_driver = { .suppress_bind_attrs = true, }, .probe = tegra_pcie_probe, + .remove = tegra_pcie_remove, }; -builtin_platform_driver(tegra_pcie_driver); +module_platform_driver(tegra_pcie_driver); +MODULE_LICENSE("GPL"); From patchwork Sat Nov 25 19:32:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjry74F0z9s71 for ; Sun, 26 Nov 2017 06:33:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbdKYTdA (ORCPT ); Sat, 25 Nov 2017 14:33:00 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19033 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751634AbdKYTcx (ORCPT ); Sat, 25 Nov 2017 14:32:53 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:55 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:53 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:53 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:52 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:52 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:51 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 8/9] PCI: tegra: Broadcast PME_turn_Off message before link goes to L2 Date: Sun, 26 Nov 2017 01:02:12 +0530 Message-ID: <1511638333-22951-9-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast PME_turn_Off message before PCIe link goes to L2. PME_turn_Off broadcast mechanism is implemented in AFI module. Each Tegra PCIe root port has its own PME_turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this register to broadcast PME_turn_Off message. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index bbc2807bcd4a..b380958a3deb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -155,6 +155,8 @@ #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_PCIE_PME 0xf0 + #define AFI_PCIE_CONFIG 0x0f8 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe @@ -315,6 +317,7 @@ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ #define LINK_RETRAIN_TIMEOUT 100000 +#define PME_ACK_TIMEOUT 10000 struct tegra_msi { struct msi_controller chip; @@ -1503,6 +1506,76 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) return 0; } +static inline u32 get_pme_turnoff_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 0; + case 1: + ret = 8; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 16; + else + ret = 12; + } + return ret; +} + +static inline u32 get_pme_ack_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 5; + case 1: + ret = 10; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 18; + else + ret = 14; + } + return ret; +} + +static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port) +{ + struct tegra_pcie *pcie = port->pcie; + ktime_t deadline; + unsigned int data; + + data = afi_readl(pcie, AFI_PCIE_PME); + data |= (0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); + + deadline = ktime_add_us(ktime_get(), PME_ACK_TIMEOUT); + do { + data = afi_readl(pcie, AFI_PCIE_PME); + data &= (0x1 << get_pme_ack_bitmap(port)); + udelay(1); + if (ktime_after(ktime_get(), deadline)) + break; + } while (!data); + + if (data) + dev_err(pcie->dev, "PME Ack is not receieved on port: %d\n", + port->index); + + usleep_range(10000, 11000); + + data = afi_readl(pcie, AFI_PCIE_PME); + data &= ~(0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); +} + static int tegra_msi_alloc(struct tegra_msi *chip) { int msi; @@ -2828,6 +2901,7 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); @@ -2835,6 +2909,8 @@ static int tegra_pcie_remove(struct platform_device *pdev) pci_remove_root_bus(host->bus); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); tegra_pcie_free_resources(pcie); tegra_pcie_disable_controller(pcie); From patchwork Sat Nov 25 19:32:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjs615JPz9s4s for ; Sun, 26 Nov 2017 06:33:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751569AbdKYTdL (ORCPT ); Sat, 25 Nov 2017 14:33:11 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11111 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751237AbdKYTc5 (ORCPT ); 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Sat, 25 Nov 2017 11:32:55 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 9/9] PCI: tegra: Add power management support Date: Sun, 26 Nov 2017 01:02:13 +0530 Message-ID: <1511638333-22951-10-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra186 powergate driver is implemented as power domain driver, power partition ungate/gate are registered as power_on/power_off callback functions. There are no direct functions to power gate/ungate host controller in Tegra186. Host controller driver should add "power-domains" property in device tree and implement runtime suspend and resume callback functons. Power gate and ungate is taken care by power domain driver when host controller driver calls pm_runtime_put_sync and pm_runtime_get_sync respectively. Register suspend_noirq & resume_noirq callback functions to allow PCIe to come up after resume from RAM. Both runtime and noirq pm ops share same callback functions. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 174 ++++++++++++++++++++++++++----------------- 1 file changed, 106 insertions(+), 68 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b380958a3deb..1bfdfcc8d2c1 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1424,31 +1424,25 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) } } - err = tegra_pcie_power_on(pcie); - if (err) { - dev_err(dev, "failed to power up: %d\n", err); - goto phys_put; - } - pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); pcie->pads = devm_ioremap_resource(dev, pads); if (IS_ERR(pcie->pads)) { err = PTR_ERR(pcie->pads); - goto poweroff; + goto phys_put; } afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); pcie->afi = devm_ioremap_resource(dev, afi); if (IS_ERR(pcie->afi)) { err = PTR_ERR(pcie->afi); - goto poweroff; + goto phys_put; } /* request configuration space, but remap later, on demand */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); if (!res) { err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } axi_addr = pcie->soc->use_4k_conf_space ? @@ -1456,21 +1450,21 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) pcie->cs = devm_request_mem_region(dev, axi_addr, SZ_4K, res->name); if (!pcie->cs) { err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } pcie->cfg_va_base = devm_ioremap(dev, pcie->cs->start, SZ_4K); if (!pcie->cfg_va_base) { dev_err(pcie->dev, "failed to ioremap config space\n"); err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } /* request interrupt */ err = platform_get_irq_byname(pdev, "intr"); if (err < 0) { dev_err(dev, "failed to get IRQ: %d\n", err); - goto poweroff; + goto phys_put; } pcie->irq = err; @@ -1478,13 +1472,11 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); if (err) { dev_err(dev, "failed to register IRQ: %d\n", err); - goto poweroff; + goto phys_put; } return 0; -poweroff: - tegra_pcie_power_off(pcie); phys_put: if (soc->program_uphy) tegra_pcie_phys_put(pcie); @@ -1498,8 +1490,6 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) if (pcie->irq > 0) free_irq(pcie->irq, pcie); - tegra_pcie_power_off(pcie); - if (soc->program_uphy) tegra_pcie_phys_put(pcie); @@ -1722,37 +1712,41 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) int err; u32 reg; - mutex_init(&msi->lock); + if (!msi->phys) { + mutex_init(&msi->lock); - msi->chip.dev = dev; - msi->chip.setup_irq = tegra_msi_setup_irq; - msi->chip.teardown_irq = tegra_msi_teardown_irq; + msi->chip.dev = dev; + msi->chip.setup_irq = tegra_msi_setup_irq; + msi->chip.teardown_irq = tegra_msi_teardown_irq; - msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, - &msi_domain_ops, &msi->chip); - if (!msi->domain) { - dev_err(dev, "failed to create IRQ domain\n"); - return -ENOMEM; - } + msi->domain = irq_domain_add_linear(dev->of_node, + INT_PCI_MSI_NR, + &msi_domain_ops, + &msi->chip); + if (!msi->domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } - err = platform_get_irq_byname(pdev, "msi"); - if (err < 0) { - dev_err(dev, "failed to get IRQ: %d\n", err); - goto err; - } + err = platform_get_irq_byname(pdev, "msi"); + if (err < 0) { + dev_err(dev, "failed to get IRQ: %d\n", err); + goto err; + } - msi->irq = err; + msi->irq = err; - err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, - tegra_msi_irq_chip.name, pcie); - if (err < 0) { - dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; - } + err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, + tegra_msi_irq_chip.name, pcie); + if (err < 0) { + dev_err(dev, "failed to request IRQ: %d\n", err); + goto err; + } - /* setup AFI/FPCI range */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); - msi->phys = virt_to_phys((void *)msi->pages); + /* setup AFI/FPCI range */ + msi->pages = __get_free_pages(GFP_KERNEL, 0); + msi->phys = virt_to_phys((void *)msi->pages); + } afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); @@ -2831,26 +2825,16 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } - err = tegra_pcie_enable_controller(pcie); - if (err) + pm_runtime_enable(pcie->dev); + err = pm_runtime_get_sync(pcie->dev); + if (err) { + dev_err(dev, "fail to enable pcie controller: %d\n", err); goto put_resources; + } err = tegra_pcie_request_resources(pcie); if (err) - goto disable_controller; - - /* setup the AFI address translations */ - tegra_pcie_setup_translations(pcie); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - err = tegra_pcie_enable_msi(pcie); - if (err < 0) { - dev_err(dev, "failed to enable MSI support: %d\n", err); - goto free_resources; - } - } - - tegra_pcie_enable_ports(pcie); + goto pm_runtime_put; pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); host->busnr = pcie->busn.start; @@ -2862,7 +2846,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = pci_scan_root_bus_bridge(host); if (err < 0) { dev_err(dev, "failed to register host: %d\n", err); - goto disable_msi; + goto free_resources; } pci_bus_size_bridges(host->bus); @@ -2884,14 +2868,13 @@ static int tegra_pcie_probe(struct platform_device *pdev) return 0; -disable_msi: - if (IS_ENABLED(CONFIG_PCI_MSI)) - tegra_pcie_disable_msi(pcie); - tegra_pcie_disable_ports(pcie); free_resources: tegra_pcie_free_resources(pcie); -disable_controller: - tegra_pcie_disable_controller(pcie); +pm_runtime_put: + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); put_resources: tegra_pcie_put_resources(pcie); return err; @@ -2901,7 +2884,6 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); - struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); @@ -2909,21 +2891,77 @@ static int tegra_pcie_remove(struct platform_device *pdev) pci_remove_root_bus(host->bus); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + tegra_pcie_free_resources(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); + tegra_pcie_put_resources(pcie); + + return 0; +} + +static int tegra_pcie_pm_suspend(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + struct tegra_pcie_port *port, *tmp; + list_for_each_entry_safe(port, tmp, &pcie->ports, list) tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); - tegra_pcie_free_resources(pcie); tegra_pcie_disable_controller(pcie); - tegra_pcie_put_resources(pcie); + tegra_pcie_power_off(pcie); return 0; } +static int tegra_pcie_pm_resume(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + int err; + + err = tegra_pcie_power_on(pcie); + if (err) { + dev_err(dev, "tegra pcie power on fail: %d\n", err); + return err; + } + err = tegra_pcie_enable_controller(pcie); + if (err) { + dev_err(dev, "tegra pcie controller enable fail: %d\n", err); + goto poweroff; + } + tegra_pcie_setup_translations(pcie); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err = tegra_pcie_enable_msi(pcie); + if (err < 0) { + dev_err(dev, "failed to enable MSI support: %d\n", err); + goto disable_controller; + } + } + + tegra_pcie_enable_ports(pcie); + + return 0; + +disable_controller: + tegra_pcie_disable_controller(pcie); +poweroff: + tegra_pcie_power_off(pcie); + + return err; +} + +static const struct dev_pm_ops tegra_pcie_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_pcie_pm_suspend, tegra_pcie_pm_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_pcie_pm_suspend, + tegra_pcie_pm_resume) +}; + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", .of_match_table = tegra_pcie_of_match, .suppress_bind_attrs = true, + .pm = &tegra_pcie_pm_ops, }, .probe = tegra_pcie_probe, .remove = tegra_pcie_remove,