From patchwork Tue Dec 31 17:24:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1216797 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="a8Agfw/b"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47nLlq3hNxz9sRC for ; Wed, 1 Jan 2020 04:25:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727186AbfLaRZJ (ORCPT ); Tue, 31 Dec 2019 12:25:09 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:42219 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727183AbfLaRZI (ORCPT ); Tue, 31 Dec 2019 12:25:08 -0500 Received: by mail-lj1-f195.google.com with SMTP id y4so22511409ljj.9 for ; Tue, 31 Dec 2019 09:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fhHaMdsl7JAy+548H7ISCjeA4TVpvL94fbTYt3aY5T4=; b=a8Agfw/bmt/RK9nlv1f2EZRwM6/cbfI0eDNPwWykfBNLLESFyHXKTrWBAcL30mMkSe WupmEqAdhg/mA+REdV+Ea1X+2T0RDxQoOyqOlc0y+JM1tjtU1qFJqce7Lds2VN+4cnhW SZlDqMRDKCYh75dt45cap31A8/8sVqxU5VXIoxjZDMqSDaSi9oIDo42AdUKwmempYU32 DZdd0hcyURjPL1To+aOnkFe8Zm+DWEghy7Rs15jJ+0NOCblFdvRGQjnwnjDfFFGbJuTs WAIfHGIW7+WX/16iTsY+p0u/Lb+5PmzZ844XgS7gyqNVU92TDdL8UEPGAsfL208we5tq N4gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fhHaMdsl7JAy+548H7ISCjeA4TVpvL94fbTYt3aY5T4=; b=P/UqSvJtARiJD3xOmmM4U8l6XWBuneNsVzk5Ny9pK6yTfj0KAfnY+RG4suxDUt0QDA g2fVo4xfOVoTMSiRXBo7YFqJY+XDPEbGI+U8sMfyvudCIRlAjDDK+zqKfwMhYp3rmbUb ZCt+K57+L5nufpJMgFD8ip37sbZ7b8NgAPk0F1mcQh9gxo3nJYlsEAHDX8HLTFR/h47m i/tNn9/IUIQRV2WouDIdSpafAcZf+X3GbEnS6jVOkrkN0II2hgMNx/vKPUuoh1qbdq6E Jjh7FeQ3essSwGhm/YZMscEpbh0jt6DvdaVxNNR5iHMNyna7hRYX8Fs0mtM6nYPPjkpc 2h9g== X-Gm-Message-State: APjAAAUFEtQ6v1H51XXclr+O2X9d0DmPwl9VVmpjci/bHGCnhOHHHVEC sas47u8RpR6uR/nzfMTT3ydwrA== X-Google-Smtp-Source: APXvYqyNpB7yMhQIz8oykFMFhw+p+ksiyFW/WfgEwgZ1ze8tq0wowFVAUFMg1vflalcrsHVdK7thUQ== X-Received: by 2002:a2e:814e:: with SMTP id t14mr41616001ljg.149.1577813107026; Tue, 31 Dec 2019 09:25:07 -0800 (PST) Received: from localhost.bredbandsbolaget (c-5ac9225c.014-348-6c756e10.bbcust.telenor.se. [92.34.201.90]) by smtp.gmail.com with ESMTPSA id z11sm16991572ljc.97.2019.12.31.09.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 09:25:06 -0800 (PST) From: Linus Walleij To: Rob Herring , devicetree@vger.kernel.org, Jens Axboe Cc: linux-ide@vger.kernel.org, Linus Walleij Subject: [PATCH 1/2] dt-bindings: Create DT bindings for [PS]ATA controllers Date: Tue, 31 Dec 2019 18:24:57 +0100 Message-Id: <20191231172458.25984-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org I need to create subnodes for drives connected to PATA or SATA host controllers, and this needs to be supported generally, so create a common YAML binding for "pata-controller" or "sata-controller" that will support subnodes with drives. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- .../bindings/ata/pata-sata-common.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/pata-sata-common.yaml diff --git a/Documentation/devicetree/bindings/ata/pata-sata-common.yaml b/Documentation/devicetree/bindings/ata/pata-sata-common.yaml new file mode 100644 index 000000000000..d94aa20a29e3 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/pata-sata-common.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/pata-sata-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Parallel and Serial AT attachment controllers + +maintainers: + - Linus Walleij + +description: | + This document defines device tree properties common to most Parallel + (PATA) and Serial (SATA) AT attachment storage devices. It doesn't + constitue a device tree binding specification by itself but is meant to + be referenced by device tree bindings. + + The PATA/SATA controller device tree bindings are responsible for + defining whether each property is required or optional. + +properties: + $nodename: + pattern: "^[ps]ata-controller(@.*)?$" + description: + Specifies the host controller node. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^drive@[0-1]$": + description: | + DT nodes for drives connected on the PATA or SATA host. The master drive + will have ID number 0 and the slave drive will have ID number 1. + type: object + + properties: + reg: + minimum: 0 + maximum: 1 + description: + The ID number of the drive, 0 for the master and 1 for the slave. + +... From patchwork Tue Dec 31 17:24:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1216798 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XpsqTVOB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47nLlv1MZ0z9sPc for ; Wed, 1 Jan 2020 04:25:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726060AbfLaRZM (ORCPT ); Tue, 31 Dec 2019 12:25:12 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:38519 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727198AbfLaRZL (ORCPT ); Tue, 31 Dec 2019 12:25:11 -0500 Received: by mail-lf1-f68.google.com with SMTP id r14so27385788lfm.5 for ; Tue, 31 Dec 2019 09:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nfsW3RUqmm/72dG11g9WAVGCUYY87NQrPwAvjG+FAtQ=; b=XpsqTVOBlVSZBnmN/YNvyt2AnhiG8XFh3zasQySOFZgn2QK8mLXa5cQaP1lSLaAzMi t8f6fhwvARcymcAanndNLA00kee16kM22/ZEpG4J8kD2MOzMCvZiRTNXuRQV2UrfFz3r MHITETyi3Sjtp3Ah/3N1xjoHK4lJ95260E8DoDSuObK+fcsu5PNSn37dMBRl2qXiGjw2 6hPVCPeaH6Vt4udGvBt6YGI3eYoLZ06UEOJ8Xhndt8aFPxBbrAQFCmKH0lnuicaGe3vT KFnFCtywlONYSenB93XFdE51/NwUjBvAlh/K2OokkRZicPVz//zQaNpsgtsqnKLlk1kS XHIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nfsW3RUqmm/72dG11g9WAVGCUYY87NQrPwAvjG+FAtQ=; b=DdxkP6vBMavBU/rX/AyOayzV7rMRYFC/eWdnluMdU37tPt7fdEdHY9d3g1yuVOi/pY xvSa7ABSA40v2smvAA+nAW3aLveSH8msMXsUk9p5Im0x22IhSKo7kIUZvwzTpRGYDmC7 /qfM0SSlMf1YEGhup63l/4UuJWmgtoI0yteHnksEH1g9ssC93QP3ff6blGzjhZsFlcVF yq/kSKAgzW0qn+liHs66EdQWa+rZfauvpmhcWX24egdZS3BJsxXlX1pYgdh9HgnYbF22 GfOmgrtiLyZFRyHGICxscLKQYNVs+7NrKwBKhLo2ZhkkHwNGVMR+jeevo9HbgumqHpYp WjMw== X-Gm-Message-State: APjAAAUQ1RNRlKqZH6R091ymbh362720IokOKnbpdoQzhKjVbqEusVEe Gl52a9lC+MPyvuIr3hAB+2dB1w== X-Google-Smtp-Source: APXvYqzI2BeV4Lak3m84HE1MJwkwyNnwfHdnCTF541buzJ56jhmNHVFPPY5c+sMBNMRRo7tuNSEIQQ== X-Received: by 2002:ac2:51de:: with SMTP id u30mr41227104lfm.69.1577813109720; Tue, 31 Dec 2019 09:25:09 -0800 (PST) Received: from localhost.bredbandsbolaget (c-5ac9225c.014-348-6c756e10.bbcust.telenor.se. [92.34.201.90]) by smtp.gmail.com with ESMTPSA id z11sm16991572ljc.97.2019.12.31.09.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 09:25:09 -0800 (PST) From: Linus Walleij To: Rob Herring , devicetree@vger.kernel.org, Jens Axboe Cc: linux-ide@vger.kernel.org, Linus Walleij , device@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: Convert Faraday FTIDE010 to DT schema Date: Tue, 31 Dec 2019 18:24:58 +0100 Message-Id: <20191231172458.25984-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191231172458.25984-1-linus.walleij@linaro.org> References: <20191231172458.25984-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This uses the new pata-sata-controller.yaml schema to convert the Faraday FTIDE010 to DT schema. Cc: Rob Herring Cc: device@vger.kernel.org Signed-off-by: Linus Walleij --- .../bindings/ata/faraday,ftide010.txt | 38 -------- .../bindings/ata/faraday,ftide010.yaml | 89 +++++++++++++++++++ 2 files changed, 89 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.txt create mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.yaml diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt deleted file mode 100644 index a0c64a29104d..000000000000 --- a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Faraday Technology FTIDE010 PATA controller - -This controller is the first Faraday IDE interface block, used in the -StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini -platform. The controller can do PIO modes 0 through 4, Multi-word DMA -(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. - -On the Gemini platform, this PATA block is accompanied by a PATA to -SATA bridge in order to support SATA. This is why a phandle to that -controller is compulsory on that platform. - -The timing properties are unique per-SoC, not per-board. - -Required properties: -- compatible: should be one of - "cortina,gemini-pata", "faraday,ftide010" - "faraday,ftide010" -- interrupts: interrupt for the block -- reg: registers and size for the block - -Optional properties: -- clocks: a SoC clock running the peripheral. -- clock-names: should be set to "PCLK" for the peripheral clock. - -Required properties for "cortina,gemini-pata" compatible: -- sata: a phande to the Gemini PATA to SATA bridge, see - cortina,gemini-sata-bridge.txt for details. - -Example: - -ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x100>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; -}; diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml new file mode 100644 index 000000000000..65be218382e4 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTIDE010 PATA controller + +maintainers: + - Linus Walleij + +description: | + This controller is the first Faraday IDE interface block, used in the + StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini + platform. The controller can do PIO modes 0 through 4, Multi-word DMA + (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. + + On the Gemini platform, this PATA block is accompanied by a PATA to + SATA bridge in order to support SATA. This is why a phandle to that + controller is compulsory on that platform. + + The timing properties are unique per-SoC, not per-board. + +properties: + compatible: + oneOf: + - const: faraday,ftide010 + - items: + - const: cortina,gemini-pata + - const: faraday,ftide010 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-names: + const: PCLK + + sata: + description: + phandle to the Gemini PATA to SATA bridge, if available + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: pata-sata-common.yaml# + + - if: + properties: + compatible: + contains: + const: cortina,gemini-pata + + then: + required: + - sata + +examples: + - | + #include + #include + + pata-controller@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x100>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + #address-cells = <1>; + #size-cells = <0>; + drive@0 { + reg = <0>; + }; + drive@1 { + reg = <1>; + }; + }; + +...