From patchwork Sun Dec 29 22:44:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216184 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jxr4a0bc"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47mFzG39M3z9s29 for ; Mon, 30 Dec 2019 09:46:16 +1100 (AEDT) Received: from localhost ([::1]:55690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilhK8-0002N9-Dc for incoming@patchwork.ozlabs.org; Sun, 29 Dec 2019 17:46:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52634) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilhJA-0002Li-0e for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilhJ8-0001WH-U1 for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:11 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39569) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilhJ8-0001Tj-NU for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:10 -0500 Received: by mail-wm1-x343.google.com with SMTP id 20so12878981wmj.4 for ; Sun, 29 Dec 2019 14:45:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kfmw6Uf2kP9Qr8LqH5cHUDPYAsKSSyoM6o3xZGkGFTM=; b=Jxr4a0bc7gGJivbli8bljZC1sWLcb4p5io3X93/G1wdR1f4zh7Y67ir+sS69cWCKe9 UKDUMl24brFKsatSpSkOPW/y7HURDrhrcKUUMs3TlXFRZM1wmY1r2XwB7rAqH3Yxa3qe qA8suf9RchR/yTBmUO3s2NF0AbuFxeLR0ZvqLTB1XggknvX54z014AgcLNz7gDbyebkO 92ta6MYxkVEbVg8outDbeRqORmkSDBcSaaXY2zAt8undcvCnRJGQQ3bMtpv1hBwTbjSC Q0frYEJK4NYeP48/DMwxQIpNDBQ+4o5PYCmZ3jrbOpytvwZSCCp+G/ytoBZtGKoB5ePh fRqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kfmw6Uf2kP9Qr8LqH5cHUDPYAsKSSyoM6o3xZGkGFTM=; b=r0JNJZusglIm0khFif51+P04xzDQLNV3Re1RrwoiX5H49D1iIrwPDWBOkSYgSh333O Xd+GijsUj4hcWNzCir4MFvxL2D58w9rffCnO5CdMZWhpzXUQ8bzBhMlfUC3dbhWRO2d4 3q5yZwj2+JNw3/l8+1Ytyyzeq2jzY2Two/TJ3V84BcbVCf3E06eg4vihAf4l7rj8lfMR Hf/O5rZexrRXoOpaqfpbC/41twVAxNxUNY0mOwpwsEkkmvU0NpczE2M8vPCQi4/M4Xkp YbweEKm3cX5OUqcxFsQCx24H4PDMk86favhtrHN9tdlvbY8lx63E2Q9QSgFC/dKyM/dJ U1iQ== X-Gm-Message-State: APjAAAVRxpuWDwIp2D6tDt/Q4/p1pR+5KScbXAOd0PaEZQfDhBzndQuh LF0BZI0oi5PpZ4pKnOyob1NS8baQzOY= X-Google-Smtp-Source: APXvYqwD0gZKzxZjRnJ4/a1YGtmSFfXQ4b8fCSXbjGBbJxI9vcAt9SJpfbnHmCrHCX3hS5AveoRGwg== X-Received: by 2002:a7b:cb91:: with SMTP id m17mr31182649wmi.146.1577659509642; Sun, 29 Dec 2019 14:45:09 -0800 (PST) Received: from x1w.home ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id x1sm42709188wru.50.2019.12.29.14.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Dec 2019 14:45:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 1/8] hw/char/avr: Reduce USART I/O size Date: Sun, 29 Dec 2019 23:44:58 +0100 Message-Id: <20191229224505.24466-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Per the datasheet the USART uses 7 consecutive 8-bit registers. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/avr_usart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c index cb307fe23d..becdb87847 100644 --- a/hw/char/avr_usart.c +++ b/hw/char/avr_usart.c @@ -280,7 +280,7 @@ static void avr_usart_init(Object *obj) sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rxc_irq); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->dre_irq); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->txc_irq); - memory_region_init_io(&s->mmio, obj, &avr_usart_ops, s, TYPE_AVR_USART, 8); + memory_region_init_io(&s->mmio, obj, &avr_usart_ops, s, TYPE_AVR_USART, 7); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); qdev_init_gpio_in(DEVICE(s), avr_usart_pr, 1); s->enabled = true; From patchwork Sun Dec 29 22:44:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216182 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 29 Dec 2019 14:45:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 2/8] hw/timer/avr_timer16: Rename memory region debugging name Date: Sun, 29 Dec 2019 23:44:59 +0100 Message-Id: <20191229224505.24466-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This device expose 3 different I/O regions. Name them differently to have a clearer 'info mtree' output. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/avr_timer16.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c index aea1bf009e..a27933a18a 100644 --- a/hw/timer/avr_timer16.c +++ b/hw/timer/avr_timer16.c @@ -563,11 +563,11 @@ static void avr_timer16_init(Object *obj) sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->ovf_irq); memory_region_init_io(&s->iomem, obj, &avr_timer16_ops, - s, TYPE_AVR_TIMER16, 0xe); + s, "avr-timer16", 0xe); memory_region_init_io(&s->imsk_iomem, obj, &avr_timer16_imsk_ops, - s, TYPE_AVR_TIMER16, 0x1); + s, "avr-timer16-intmask", 0x1); memory_region_init_io(&s->ifr_iomem, obj, &avr_timer16_ifr_ops, - s, TYPE_AVR_TIMER16, 0x1); + s, "avr-timer16-intflag", 0x1); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->imsk_iomem); From patchwork Sun Dec 29 22:45:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216185 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 29 Dec 2019 14:45:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 3/8] hw/avr: Add some ATmega microcontrollers Date: Sun, 29 Dec 2019 23:45:00 +0100 Message-Id: <20191229224505.24466-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Igor Mammedov , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add some microcontrollers from the megaAVR family (ATmega series): - middle range: ATmega168 and ATmega328 - high range: ATmega1280 and ATmega2560 For product comparison: https://www.microchip.com/wwwproducts/ProductCompare/ATmega168P/ATmega328P https://www.microchip.com/wwwproducts/ProductCompare/ATmega1280/ATmega2560 Datasheets: http://ww1.microchip.com/downloads/en/DeviceDoc/ATmega48A-PA-88A-PA-168A-PA-328-P-DS-DS40002061A.pdf http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf Signed-off-by: Philippe Mathieu-Daudé --- v2: - Reword description adding more information (Aleksandar) - Use DEFINE_TYPES and memory_region_init_ram (Igor) Cc: Igor Mammedov --- hw/avr/atmega.h | 48 +++++ hw/avr/atmega.c | 464 +++++++++++++++++++++++++++++++++++++++++++ hw/avr/Makefile.objs | 1 + 3 files changed, 513 insertions(+) create mode 100644 hw/avr/atmega.h create mode 100644 hw/avr/atmega.c diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h new file mode 100644 index 0000000000..aac09f7957 --- /dev/null +++ b/hw/avr/atmega.h @@ -0,0 +1,48 @@ +/* + * QEMU ATmega MCU + * + * Copyright (c) 2019 Philippe Mathieu-Daudé + * + * This work is licensed under the terms of the GNU GPLv2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_AVR_ATMEGA_H +#define HW_AVR_ATMEGA_H + +#include "hw/char/avr_usart.h" +#include "hw/timer/avr_timer16.h" +#include "hw/misc/avr_mask.h" +#include "target/avr/cpu.h" + +#define TYPE_ATMEGA_MCU "ATmega" +#define TYPE_ATMEGA168_MCU "ATmega168" +#define TYPE_ATMEGA328_MCU "ATmega328" +#define TYPE_ATMEGA1280_MCU "ATmega1280" +#define TYPE_ATMEGA2560_MCU "ATmega2560" + +#define ATMEGA_MCU(obj) OBJECT_CHECK(AtmegaMcuState, (obj), TYPE_ATMEGA_MCU) + +#define POWER_MAX 2 +#define USART_MAX 4 +#define TIMER_MAX 6 +#define GPIO_MAX 12 + +typedef struct AtmegaMcuState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + AVRCPU cpu; + MemoryRegion flash; + MemoryRegion eeprom; + MemoryRegion sram; + DeviceState *io; + AVRMaskState pwr[POWER_MAX]; + AVRUsartState usart[USART_MAX]; + AVRTimer16State timer[TIMER_MAX]; + uint64_t xtal_freq_hz; +} AtmegaMcuState; + +#endif /* HW_AVR_ATMEGA_H */ diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c new file mode 100644 index 0000000000..81d20847a4 --- /dev/null +++ b/hw/avr/atmega.c @@ -0,0 +1,464 @@ +/* + * QEMU ATmega MCU + * + * Copyright (c) 2019 Philippe Mathieu-Daudé + * + * This work is licensed under the terms of the GNU GPLv2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/boards.h" /* FIXME memory_region_allocate_system_memory for sram */ +#include "hw/misc/unimp.h" +#include "atmega.h" + +enum AtmegaPeripheral { + POWER0, POWER1, + GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, + GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL, + USART0, USART1, USART2, USART3, + TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5, + PERIFMAX +}; + +#define GPIO(n) (n + GPIOA) +#define USART(n) (n + USART0) +#define TIMER(n) (n + TIMER0) +#define POWER(n) (n + POWER0) + +typedef struct { + uint16_t addr; + enum AtmegaPeripheral power_index; + uint8_t power_bit; + /* timer specific */ + uint16_t intmask_addr; + uint16_t intflag_addr; + bool is_timer16; +} peripheral_cfg; + +typedef struct AtmegaMcuClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + const char *uc_name; + const char *cpu_type; + size_t flash_size; + size_t eeprom_size; + size_t sram_size; + size_t io_size; + size_t gpio_count; + size_t adc_count; + const uint8_t *irq; + const peripheral_cfg *dev; +} AtmegaMcuClass; + +#define ATMEGA_MCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(AtmegaMcuClass, (klass), TYPE_ATMEGA_MCU) +#define ATMEGA_MCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AtmegaMcuClass, (obj), TYPE_ATMEGA_MCU) + +static const peripheral_cfg dev168_328[PERIFMAX] = { + [USART0] = { 0xc0, POWER0, 1 }, + [TIMER2] = { 0xb0, POWER0, 6, 0x70, 0x37, false }, + [TIMER1] = { 0x80, POWER0, 3, 0x6f, 0x36, true }, + [POWER0] = { 0x64 }, + [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false }, + [GPIOD] = { 0x29 }, + [GPIOC] = { 0x26 }, + [GPIOB] = { 0x23 }, +}, dev1280_2560[PERIFMAX] = { + [USART3] = { 0x130, POWER1, 2 }, + [TIMER5] = { 0x120, POWER1, 5, 0x73, 0x3a, true }, + [GPIOL] = { 0x109 }, + [GPIOK] = { 0x106 }, + [GPIOJ] = { 0x103 }, + [GPIOH] = { 0x100 }, + [USART2] = { 0xd0, POWER1, 1 }, + [USART1] = { 0xc8, POWER1, 0 }, + [USART0] = { 0xc0, POWER0, 1 }, + [TIMER2] = { 0xb0, POWER0, 6, 0x70, 0x37, false }, /* TODO async */ + [TIMER4] = { 0xa0, POWER1, 4, 0x72, 0x39, true }, + [TIMER3] = { 0x90, POWER1, 3, 0x71, 0x38, true }, + [TIMER1] = { 0x80, POWER0, 3, 0x6f, 0x36, true }, + [POWER1] = { 0x65 }, + [POWER0] = { 0x64 }, + [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false }, + [GPIOG] = { 0x32 }, + [GPIOF] = { 0x2f }, + [GPIOE] = { 0x2c }, + [GPIOD] = { 0x29 }, + [GPIOC] = { 0x26 }, + [GPIOB] = { 0x23 }, + [GPIOA] = { 0x20 }, +}; + +enum AtmegaIrq { + USART0_RXC_IRQ, USART0_DRE_IRQ, USART0_TXC_IRQ, + USART1_RXC_IRQ, USART1_DRE_IRQ, USART1_TXC_IRQ, + USART2_RXC_IRQ, USART2_DRE_IRQ, USART2_TXC_IRQ, + USART3_RXC_IRQ, USART3_DRE_IRQ, USART3_TXC_IRQ, + TIMER0_CAPT_IRQ, TIMER0_COMPA_IRQ, TIMER0_COMPB_IRQ, + TIMER0_COMPC_IRQ, TIMER0_OVF_IRQ, + TIMER1_CAPT_IRQ, TIMER1_COMPA_IRQ, TIMER1_COMPB_IRQ, + TIMER1_COMPC_IRQ, TIMER1_OVF_IRQ, + TIMER2_CAPT_IRQ, TIMER2_COMPA_IRQ, TIMER2_COMPB_IRQ, + TIMER2_COMPC_IRQ, TIMER2_OVF_IRQ, + TIMER3_CAPT_IRQ, TIMER3_COMPA_IRQ, TIMER3_COMPB_IRQ, + TIMER3_COMPC_IRQ, TIMER3_OVF_IRQ, + TIMER4_CAPT_IRQ, TIMER4_COMPA_IRQ, TIMER4_COMPB_IRQ, + TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ, + TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ, + TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ, + IRQ_COUNT +}; + +#define USART_IRQ_COUNT 3 +#define USART_RXC_IRQ(n) (n * USART_IRQ_COUNT + USART0_RXC_IRQ) +#define USART_DRE_IRQ(n) (n * USART_IRQ_COUNT + USART0_DRE_IRQ) +#define USART_TXC_IRQ(n) (n * USART_IRQ_COUNT + USART0_TXC_IRQ) +#define TIMER_IRQ_COUNT 5 +#define TIMER_CAPT_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_CAPT_IRQ) +#define TIMER_COMPA_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPA_IRQ) +#define TIMER_COMPB_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPB_IRQ) +#define TIMER_COMPC_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_COMPC_IRQ) +#define TIMER_OVF_IRQ(n) (n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ) + +static const uint8_t irq168_328[IRQ_COUNT] = { + [TIMER2_COMPA_IRQ] = 8, + [TIMER2_COMPB_IRQ] = 9, + [TIMER2_OVF_IRQ] = 10, + [TIMER1_CAPT_IRQ] = 11, + [TIMER1_COMPA_IRQ] = 12, + [TIMER1_COMPB_IRQ] = 13, + [TIMER1_OVF_IRQ] = 14, + [TIMER0_COMPA_IRQ] = 15, + [TIMER0_COMPB_IRQ] = 16, + [TIMER0_OVF_IRQ] = 17, + [USART0_RXC_IRQ] = 19, + [USART0_DRE_IRQ] = 20, + [USART0_TXC_IRQ] = 21, +}, irq1280_2560[IRQ_COUNT] = { + [TIMER2_COMPA_IRQ] = 14, + [TIMER2_COMPB_IRQ] = 15, + [TIMER2_OVF_IRQ] = 16, + [TIMER1_CAPT_IRQ] = 17, + [TIMER1_COMPA_IRQ] = 18, + [TIMER1_COMPB_IRQ] = 19, + [TIMER1_COMPC_IRQ] = 20, + [TIMER1_OVF_IRQ] = 21, + [TIMER0_COMPA_IRQ] = 22, + [TIMER0_COMPB_IRQ] = 23, + [TIMER0_OVF_IRQ] = 24, + [USART0_RXC_IRQ] = 26, + [USART0_DRE_IRQ] = 27, + [USART0_TXC_IRQ] = 28, + [TIMER3_CAPT_IRQ] = 32, + [TIMER3_COMPA_IRQ] = 33, + [TIMER3_COMPB_IRQ] = 34, + [TIMER3_COMPC_IRQ] = 35, + [TIMER3_OVF_IRQ] = 36, + [USART1_RXC_IRQ] = 37, + [USART1_DRE_IRQ] = 38, + [USART1_TXC_IRQ] = 39, + [TIMER4_CAPT_IRQ] = 42, + [TIMER4_COMPA_IRQ] = 43, + [TIMER4_COMPB_IRQ] = 44, + [TIMER4_COMPC_IRQ] = 45, + [TIMER4_OVF_IRQ] = 46, + [TIMER5_CAPT_IRQ] = 47, + [TIMER5_COMPA_IRQ] = 48, + [TIMER5_COMPB_IRQ] = 49, + [TIMER5_COMPC_IRQ] = 50, + [TIMER5_OVF_IRQ] = 51, + [USART2_RXC_IRQ] = 52, + [USART2_DRE_IRQ] = 53, + [USART2_TXC_IRQ] = 54, + [USART3_RXC_IRQ] = 55, + [USART3_DRE_IRQ] = 56, + [USART3_TXC_IRQ] = 57, +}; + +static void connect_peripheral_irq(const AtmegaMcuClass *mc, + SysBusDevice *sbd, + DeviceState *dev, int n, + unsigned peripheral_irq) +{ + int irq = mc->irq[peripheral_irq]; + + if (!irq) { + return; + } + /* FIXME move that to avr_cpu_set_int() once 'sample' board is removed */ + assert(irq >= 2); + irq -= 2; + + sysbus_connect_irq(sbd, n, qdev_get_gpio_in(dev, irq)); +} + +static void connect_power_reduction_gpio(AtmegaMcuState *s, + const AtmegaMcuClass *mc, + DeviceState *dev, + int peripheral_index) +{ + unsigned power_index = mc->dev[peripheral_index].power_index; + assert(mc->dev[power_index].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwr[power_index - POWER0]), + mc->dev[peripheral_index].power_bit, + qdev_get_gpio_in(dev, 0)); +} + +static void atmega_realize(DeviceState *dev, Error **errp) +{ + AtmegaMcuState *s = ATMEGA_MCU(dev); + const AtmegaMcuClass *mc = ATMEGA_MCU_GET_CLASS(dev); + DeviceState *cpudev; + SysBusDevice *sbd; + Error *err = NULL; + char *devname; + size_t i; + + assert(mc->io_size <= 0x200); + + if (!s->xtal_freq_hz) { + error_setg(errp, "\"xtal-frequency-hz\" property must be provided."); + return; + } + + /* CPU */ + object_initialize_child(OBJECT(dev), "cpu", &s->cpu, sizeof(s->cpu), + mc->cpu_type, &err, NULL); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_abort); + cpudev = DEVICE(&s->cpu); + + /* SRAM */ + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, + &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x200, &s->sram); + + /* Flash */ + memory_region_init_rom(&s->flash, OBJECT(dev), + "flash", mc->flash_size, &error_fatal); + memory_region_add_subregion(get_system_memory(), OFFSET_CODE, &s->flash); + + /* I/O */ + s->io = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(s->io, "name", "I/O"); + qdev_prop_set_uint64(s->io, "size", mc->io_size); + qdev_init_nofail(s->io); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, OFFSET_DATA, -1234); + + /* Power Reduction */ + for (i = 0; i < POWER_MAX; i++) { + int idx = POWER(i); + if (!mc->dev[idx].addr) { + continue; + } + devname = g_strdup_printf("power%zu", i); + object_initialize_child(OBJECT(dev), devname, + &s->pwr[i], sizeof(s->pwr[i]), + TYPE_AVR_MASK, &error_abort, NULL); + object_property_set_bool(OBJECT(&s->pwr[i]), true, "realized", + &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwr[i]), 0, + OFFSET_DATA + mc->dev[idx].addr); + g_free(devname); + } + + /* GPIO */ + for (i = 0; i < GPIO_MAX; i++) { + int idx = GPIO(i); + if (!mc->dev[idx].addr) { + continue; + } + devname = g_strdup_printf("avr-gpio-%c", 'a' + (char)i); + create_unimplemented_device(devname, + OFFSET_DATA + mc->dev[idx].addr, 3); + g_free(devname); + } + + /* USART */ + for (i = 0; i < USART_MAX; i++) { + int idx = USART(i); + if (!mc->dev[idx].addr) { + continue; + } + devname = g_strdup_printf("usart%zu", i); + object_initialize_child(OBJECT(dev), devname, + &s->usart[i], sizeof(s->usart[i]), + TYPE_AVR_USART, &error_abort, NULL); + qdev_prop_set_chr(DEVICE(&s->usart[i]), "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", + &error_abort); + sbd = SYS_BUS_DEVICE(&s->usart[i]); + sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr); + connect_peripheral_irq(mc, sbd, cpudev, 0, USART_RXC_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 1, USART_DRE_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 2, USART_TXC_IRQ(i)); + connect_power_reduction_gpio(s, mc, DEVICE(&s->usart[i]), idx); + g_free(devname); + } + + /* Timer */ + for (i = 0; i < TIMER_MAX; i++) { + int idx = TIMER(i); + if (!mc->dev[idx].addr) { + continue; + } + if (!mc->dev[idx].is_timer16) { + create_unimplemented_device("avr-timer8", + OFFSET_DATA + mc->dev[idx].addr, 5); + create_unimplemented_device("avr-timer8-intmask", + OFFSET_DATA + + mc->dev[idx].intmask_addr, 1); + create_unimplemented_device("avr-timer8-intflag", + OFFSET_DATA + + mc->dev[idx].intflag_addr, 1); + continue; + } + devname = g_strdup_printf("timer%zu", i); + object_initialize_child(OBJECT(dev), devname, + &s->timer[i], sizeof(s->timer[i]), + TYPE_AVR_TIMER16, &error_abort, NULL); + object_property_set_uint(OBJECT(&s->timer[i]), s->xtal_freq_hz, + "cpu-frequency-hz", &error_abort); + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", + &error_abort); + sbd = SYS_BUS_DEVICE(&s->timer[i]); + sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr); + sysbus_mmio_map(sbd, 1, OFFSET_DATA + mc->dev[idx].intmask_addr); + sysbus_mmio_map(sbd, 2, OFFSET_DATA + mc->dev[idx].intflag_addr); + connect_peripheral_irq(mc, sbd, cpudev, 0, TIMER_CAPT_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 1, TIMER_COMPA_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 2, TIMER_COMPB_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 3, TIMER_COMPC_IRQ(i)); + connect_peripheral_irq(mc, sbd, cpudev, 4, TIMER_OVF_IRQ(i)); + connect_power_reduction_gpio(s, mc, DEVICE(&s->timer[i]), idx); + g_free(devname); + } + + create_unimplemented_device("avr-twi", OFFSET_DATA + 0x0b8, 6); + create_unimplemented_device("avr-adc", OFFSET_DATA + 0x078, 8); + create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2); + create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1); + create_unimplemented_device("avr-spi", OFFSET_DATA + 0x04c, 3); + create_unimplemented_device("avr-eeprom", OFFSET_DATA + 0x03f, 3); +} + +static Property atmega_props[] = { + DEFINE_PROP_UINT64("xtal-frequency-hz", AtmegaMcuState, + xtal_freq_hz, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void atmega_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = atmega_realize; + dc->props = atmega_props; + /* Reason: Mapped at fixed location on the system bus */ + dc->user_creatable = false; +} + +static void atmega168_class_init(ObjectClass *oc, void *data) +{ + AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc); + + amc->cpu_type = AVR_CPU_TYPE_NAME("avr5"); + amc->flash_size = 16 * KiB; + amc->eeprom_size = 512; + amc->sram_size = 1 * KiB; + amc->io_size = 256; + amc->gpio_count = 23; + amc->adc_count = 6; + amc->irq = irq168_328; + amc->dev = dev168_328; +}; + +static void atmega328_class_init(ObjectClass *oc, void *data) +{ + AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc); + + amc->cpu_type = AVR_CPU_TYPE_NAME("avr5"); + amc->flash_size = 32 * KiB; + amc->eeprom_size = 1 * KiB; + amc->sram_size = 2 * KiB; + amc->io_size = 256; + amc->gpio_count = 23; + amc->adc_count = 6; + amc->irq = irq168_328; + amc->dev = dev168_328; +}; + +static void atmega1280_class_init(ObjectClass *oc, void *data) +{ + AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc); + + amc->cpu_type = AVR_CPU_TYPE_NAME("avr6"); + amc->flash_size = 128 * KiB; + amc->eeprom_size = 4 * KiB; + amc->sram_size = 8 * KiB; + amc->io_size = 512; + amc->gpio_count = 86; + amc->adc_count = 16; + amc->irq = irq1280_2560; + amc->dev = dev1280_2560; +}; + +static void atmega2560_class_init(ObjectClass *oc, void *data) +{ + AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc); + + amc->cpu_type = AVR_CPU_TYPE_NAME("avr6"); + amc->flash_size = 256 * KiB; + amc->eeprom_size = 4 * KiB; + amc->sram_size = 8 * KiB; + amc->io_size = 512; + amc->gpio_count = 54; + amc->adc_count = 16; + amc->irq = irq1280_2560; + amc->dev = dev1280_2560; +}; + +static const TypeInfo atmega_mcu_types[] = { + { + .name = TYPE_ATMEGA168_MCU, + .parent = TYPE_ATMEGA_MCU, + .class_init = atmega168_class_init, + }, { + .name = TYPE_ATMEGA328_MCU, + .parent = TYPE_ATMEGA_MCU, + .class_init = atmega328_class_init, + }, { + .name = TYPE_ATMEGA1280_MCU, + .parent = TYPE_ATMEGA_MCU, + .class_init = atmega1280_class_init, + }, { + .name = TYPE_ATMEGA2560_MCU, + .parent = TYPE_ATMEGA_MCU, + .class_init = atmega2560_class_init, + }, { + .name = TYPE_ATMEGA_MCU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AtmegaMcuState), + .class_size = sizeof(AtmegaMcuClass), + .class_init = atmega_class_init, + .abstract = true, + } +}; + +DEFINE_TYPES(atmega_mcu_types) diff --git a/hw/avr/Makefile.objs b/hw/avr/Makefile.objs index 626b7064b3..4b6b911820 100644 --- a/hw/avr/Makefile.objs +++ b/hw/avr/Makefile.objs @@ -1 +1,2 @@ obj-y += sample.o +obj-y += atmega.o From patchwork Sun Dec 29 22:45:01 2019 Content-Type: text/plain; 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Sun, 29 Dec 2019 14:45:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 4/8] hw/avr: Add some Arduino boards Date: Sun, 29 Dec 2019 23:45:01 +0100 Message-Id: <20191229224505.24466-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Igor Mammedov , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , Phillip Stevens Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Arduino boards are build with AVR chipsets. Add some of the popular boards: - Arduino Duemilanove - Arduino Uno - Arduino Mega For more information: https://www.arduino.cc/en/Main/Products https://store.arduino.cc/arduino-genuino/most-popular Signed-off-by: Philippe Mathieu-Daudé --- v2: - Reword description adding more information (Aleksandar) - Use DEFINE_TYPES (Igor) Cc: Phillip Stevens Cc: Igor Mammedov --- hw/avr/arduino.c | 177 +++++++++++++++++++++++++++++++++++++++++++ hw/avr/Makefile.objs | 1 + 2 files changed, 178 insertions(+) create mode 100644 hw/avr/arduino.c diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c new file mode 100644 index 0000000000..ecaaa295d8 --- /dev/null +++ b/hw/avr/arduino.c @@ -0,0 +1,177 @@ +/* + * QEMU Arduino boards + * + * Copyright (c) 2019 Philippe Mathieu-Daudé + * + * This work is licensed under the terms of the GNU GPLv2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* TODO: Implement the use of EXTRAM */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "elf.h" +#include "atmega.h" + +typedef struct ArduinoMachineState { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + AtmegaMcuState mcu; + MemoryRegion extram; +} ArduinoMachineState; + +typedef struct ArduinoMachineClass { + /*< private >*/ + MachineClass parent_class; + /*< public >*/ + const char *mcu_type; + uint64_t xtal_hz; + size_t extram_size; +} ArduinoMachineClass; + +#define TYPE_ARDUINO_MACHINE \ + MACHINE_TYPE_NAME("arduino") +#define ARDUINO_MACHINE(obj) \ + OBJECT_CHECK(ArduinoMachineState, (obj), TYPE_ARDUINO_MACHINE) +#define ARDUINO_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(ArduinoMachineClass, (klass), TYPE_ARDUINO_MACHINE) +#define ARDUINO_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ArduinoMachineClass, (obj), TYPE_ARDUINO_MACHINE) + +static void load_firmware(const char *firmware, uint64_t flash_size) +{ + const char *filename; + int bytes_loaded; + + /* Load firmware (contents of flash) trying to auto-detect format */ + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware); + if (filename == NULL) { + error_report("Unable to find %s", firmware); + exit(1); + } + + bytes_loaded = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, + 0, EM_NONE, 0, 0); + if (bytes_loaded < 0) { + bytes_loaded = load_image_targphys(filename, OFFSET_CODE, flash_size); + } + if (bytes_loaded < 0) { + error_report("Unable to load firmware image %s as ELF or raw binary", + firmware); + exit(1); + } +} + +static void arduino_machine_init(MachineState *machine) +{ + ArduinoMachineClass *amc = ARDUINO_MACHINE_GET_CLASS(machine); + ArduinoMachineState *ams = ARDUINO_MACHINE(machine); + + sysbus_init_child_obj(OBJECT(machine), "mcu", &ams->mcu, sizeof(ams->mcu), + amc->mcu_type); + object_property_set_uint(OBJECT(&ams->mcu), amc->xtal_hz, + "xtal-frequency-hz", &error_abort); + object_property_set_bool(OBJECT(&ams->mcu), true, "realized", + &error_abort); + + if (machine->firmware) { + load_firmware(machine->firmware, memory_region_size(&ams->mcu.flash)); + } +} + +static void arduino_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->init = arduino_machine_init; + mc->default_cpus = 1; + mc->min_cpus = mc->default_cpus; + mc->max_cpus = mc->default_cpus; + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_parallel = 1; +} + +static void arduino_duemilanove_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + + /* https://www.arduino.cc/en/Main/ArduinoBoardDuemilanove */ + mc->desc = "Arduino Duemilanove (ATmega168)", + mc->alias = "2009"; + amc->mcu_type = TYPE_ATMEGA168_MCU; + amc->xtal_hz = 16 * 1000 * 1000; +}; + +static void arduino_uno_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + + /* https://store.arduino.cc/arduino-uno-rev3 */ + mc->desc = "Arduino UNO (ATmega328P)"; + mc->alias = "uno"; + amc->mcu_type = TYPE_ATMEGA328_MCU; + amc->xtal_hz = 16 * 1000 * 1000; +}; + +static void arduino_mega_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + + /* https://www.arduino.cc/en/Main/ArduinoBoardMega */ + mc->desc = "Arduino Mega (ATmega1280)"; + mc->alias = "mega"; + amc->mcu_type = TYPE_ATMEGA1280_MCU; + amc->xtal_hz = 16 * 1000 * 1000; +}; + +static void arduino_mega2560_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc); + + /* https://store.arduino.cc/arduino-mega-2560-rev3 */ + mc->desc = "Arduino Mega 2560 (ATmega2560)"; + mc->alias = "mega2560"; + mc->is_default = true; + amc->mcu_type = TYPE_ATMEGA2560_MCU; + amc->xtal_hz = 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */ +}; + +static const TypeInfo arduino_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("arduino-duemilanove"), + .parent = TYPE_ARDUINO_MACHINE, + .class_init = arduino_duemilanove_class_init, + }, { + .name = MACHINE_TYPE_NAME("arduino-uno"), + .parent = TYPE_ARDUINO_MACHINE, + .class_init = arduino_uno_class_init, + }, { + .name = MACHINE_TYPE_NAME("arduino-mega"), + .parent = TYPE_ARDUINO_MACHINE, + .class_init = arduino_mega_class_init, + }, { + .name = MACHINE_TYPE_NAME("arduino-mega-2560-v3"), + .parent = TYPE_ARDUINO_MACHINE, + .class_init = arduino_mega2560_class_init, + }, { + .name = TYPE_ARDUINO_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(ArduinoMachineState), + .class_size = sizeof(ArduinoMachineClass), + .class_init = arduino_machine_class_init, + .abstract = true, + } +}; + +DEFINE_TYPES(arduino_machine_types) diff --git a/hw/avr/Makefile.objs b/hw/avr/Makefile.objs index 4b6b911820..39ee3c32b2 100644 --- a/hw/avr/Makefile.objs +++ b/hw/avr/Makefile.objs @@ -1,2 +1,3 @@ obj-y += sample.o obj-y += atmega.o +obj-y += arduino.o From patchwork Sun Dec 29 22:45:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f0SWyQB9"; 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Sun, 29 Dec 2019 14:45:15 -0800 (PST) Received: from x1w.home ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id x1sm42709188wru.50.2019.12.29.14.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Dec 2019 14:45:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 5/8] tests/boot-serial-test: Test some Arduino boards (AVR based) Date: Sun, 29 Dec 2019 23:45:02 +0100 Message-Id: <20191229224505.24466-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Arduino Duemilanove is based on a AVR5 CPU, while the Arduino MEGA2560 on a AVR6 CPU. Signed-off-by: Philippe Mathieu-Daudé --- tests/boot-serial-test.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index e556f09db8..582a497963 100644 --- a/tests/boot-serial-test.c +++ b/tests/boot-serial-test.c @@ -113,6 +113,8 @@ typedef struct testdef { static testdef_t tests[] = { { "alpha", "clipper", "", "PCI:" }, { "avr", "sample", "", "T", sizeof(bios_avr), NULL, bios_avr }, + { "avr", "arduino-duemilanove", "", "T", sizeof(bios_avr), NULL, bios_avr }, + { "avr", "arduino-mega-2560-v3", "", "T", sizeof(bios_avr), NULL, bios_avr}, { "ppc", "ppce500", "", "U-Boot" }, { "ppc", "40p", "-vga none -boot d", "Trying cd:," }, { "ppc", "g3beige", "", "PowerPC,750" }, From patchwork Sun Dec 29 22:45:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216188 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 29 Dec 2019 14:45:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 6/8] tests/acceptance: Do not set the machine type manually Date: Sun, 29 Dec 2019 23:45:03 +0100 Message-Id: <20191229224505.24466-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Cleber Rosa , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since commit ba21bde93 we don't need to set the machine type manually, the one set by the ":avocado: tags=machine" will be used. Suggested-by: Cleber Rosa Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Wainer dos Santos Moschetta --- tests/acceptance/machine_avr6.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py index 7a7d8afc29..394b3d4f8f 100644 --- a/tests/acceptance/machine_avr6.py +++ b/tests/acceptance/machine_avr6.py @@ -45,7 +45,6 @@ class AVR6Machine(Test): rom_hash = '7eb521f511ca8f2622e0a3c5e8dd686efbb911d4' rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash) - self.vm.set_machine('sample') self.vm.add_args('-bios', rom_path) self.vm.add_args('-nographic') self.vm.launch() From patchwork Sun Dec 29 22:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ObGk/PUA"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47mG6J3Mspz9sPc for ; Mon, 30 Dec 2019 09:52:24 +1100 (AEDT) Received: from localhost ([::1]:55760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilhQ6-0000d8-38 for incoming@patchwork.ozlabs.org; Sun, 29 Dec 2019 17:52:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53019) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilhJJ-0002Y9-AA for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ilhJI-0001uN-1H for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:21 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ilhJH-0001s4-Qh for qemu-devel@nongnu.org; Sun, 29 Dec 2019 17:45:19 -0500 Received: by mail-wm1-x343.google.com with SMTP id m24so12697833wmc.3 for ; Sun, 29 Dec 2019 14:45:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WbsYV4ckQ40btqTMEBkjwx7LsODZXE9rDBJDw8lKkHU=; b=ObGk/PUA+VRy1VWfG79MUOdLxzvHkvPqzvpEfLC/oJUBTBJPlbubicuQz6SXYrtKfj L+zVKeFQpgal0SNICSfm853cqP2XWea9NcMNJMyYxtcTItPP+EPxwuOe2c+A7qpDZxx9 Iryq/J9ikj95s4MFxxpTyc2HS+Hh3Sut/WK6oT6Vhi+Q4eRIR3s3sSY2Iylr6kek5oR/ K/KGGPmfN4Bp8Grxr5XOEwDakhigrTm3dHek+8GqQrxxKst415xwhDpWCoBTHRmsV6IL wXUJ3TP8Qxpc4vvIfgFg88x3mARl5Hl+va3m5dSO1uQ4YJbM++G2n93H/DBvRbx4EK32 mxNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=WbsYV4ckQ40btqTMEBkjwx7LsODZXE9rDBJDw8lKkHU=; b=VjRVRCl9JDQT6wDvs1iUk/BV8fT//7xFy0WVNCSe/b19T/hgLqsjYtcqOYBpcRkgGb uFCS64SrbEfQnz9WtduMLfL0rtXDvlktly0JO/M5c07BIOkp4tCeUkfvftYUC8XYb0Ut uk06jvWlkiMSXg/ft/4pw6Ukkyx9kq35lDX5qoh2XQ03OyFvmjwujEYgLOAGZ+DD1xVh VqNliR3vC+ooLmlzsR6vuURB6zQ73VQOPWCit2TsaIYozXybr5ZqXA2CFCvEjYDQ/1Qt xtZe2T9SEabKaozXDfMOj68SaWsOorxHYr5E30dPwokhKoFHJSbxPSSQLyWqLgDgj3Kp TgwQ== X-Gm-Message-State: APjAAAUn+RHIsGGCz1YIaqWNFoI9m0mIcRQYWQsbC6jG7CV1YLfyodth uu+7e7OjcoonpfsT+sXc0usXCn7gQ2E= X-Google-Smtp-Source: APXvYqwbvTkpndl0rqG8FlDyQ7o8pOn0oQssSevxrqyy0cX6rNY/b14si84IrqlPYET7aT2w8EH2ow== X-Received: by 2002:a1c:1fd0:: with SMTP id f199mr31249698wmf.113.1577659518666; Sun, 29 Dec 2019 14:45:18 -0800 (PST) Received: from x1w.home ([2a01:cb18:8372:6b00:691b:aac5:8837:d4da]) by smtp.gmail.com with ESMTPSA id x1sm42709188wru.50.2019.12.29.14.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Dec 2019 14:45:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 7/8] tests/acceptance: Keep multilines comment consistent with other tests Date: Sun, 29 Dec 2019 23:45:04 +0100 Message-Id: <20191229224505.24466-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé --- note to maintainer: squash before merge? --- tests/acceptance/machine_avr6.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py index 394b3d4f8f..94a8004e94 100644 --- a/tests/acceptance/machine_avr6.py +++ b/tests/acceptance/machine_avr6.py @@ -37,11 +37,9 @@ class AVR6Machine(Test): https://github.com/seharris/qemu-avr-tests/raw/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf constantly prints out 'ABCDEFGHIJKLMNOPQRSTUVWXABCDEFGHIJKLMNOPQRSTUVWX' """ - rom_url = 'https://github.com/seharris/qemu-avr-tests' - rom_sha1= '36c3e67b8755dcf37e06af6730ef5d477b8ed16d' - rom_url += '/raw/' - rom_url += rom_sha1 - rom_url += '/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf' + rom_url = ('https://github.com/seharris/qemu-avr-tests' + '/raw/36c3e67b8755dcf/free-rtos/Demo' + '/AVR_ATMega2560_GCC/demo.elf') rom_hash = '7eb521f511ca8f2622e0a3c5e8dd686efbb911d4' rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash) From patchwork Sun Dec 29 22:45:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1216192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="B/Ej2aeA"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47mG7f5dlVz9sPJ for ; Mon, 30 Dec 2019 09:53:34 +1100 (AEDT) Received: from localhost ([::1]:55766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ilhRE-0001W6-Lc for incoming@patchwork.ozlabs.org; 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Sun, 29 Dec 2019 14:45:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 8/8] tests/acceptance: Test the Arduino MEGA2560 board Date: Sun, 29 Dec 2019 23:45:05 +0100 Message-Id: <20191229224505.24466-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191229224505.24466-1-f4bug@amsat.org> References: <20191229224505.24466-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" As the path name demonstrates, the FreeRTOS tests target a board based on a ATMega2560 MCU. We have one, the Arduino MEGA2560. Complementary documentation: https://feilipu.me/2012/01/15/ethermega-arduino-mega-2560-and-freertos/ https://feilipu.me/2015/11/24/arduino_freertos/ (see 'Compatibility') Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/machine_avr6.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/acceptance/machine_avr6.py b/tests/acceptance/machine_avr6.py index 94a8004e94..c5ff423e50 100644 --- a/tests/acceptance/machine_avr6.py +++ b/tests/acceptance/machine_avr6.py @@ -31,7 +31,7 @@ class AVR6Machine(Test): def test_freertos(self): """ :avocado: tags=arch:avr - :avocado: tags=machine:sample + :avocado: tags=machine:arduino-mega-2560-v3 """ """ https://github.com/seharris/qemu-avr-tests/raw/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf