From patchwork Fri Nov 24 15:53:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841112 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk12r3YdGz9s4s for ; Sat, 25 Nov 2017 02:54:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753773AbdKXPyK (ORCPT ); Fri, 24 Nov 2017 10:54:10 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3845 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753646AbdKXPyJ (ORCPT ); Fri, 24 Nov 2017 10:54:09 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 24 Nov 2017 07:54:03 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:54:08 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:54:08 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:08 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:54:08 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:54:07 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 01/10] genirq: Export irq_set_msi_desc() Date: Fri, 24 Nov 2017 21:23:11 +0530 Message-ID: <1511538800-8275-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCI bus support MSI interrupts, allow PCI host driver to set MSI descriptor data for an irq. Signed-off-by: Manikanta Maddireddy --- kernel/irq/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 5a2ef92c2782..bfbd17386bc4 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -136,6 +136,7 @@ int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) { return irq_set_msi_desc_off(irq, 0, entry); } +EXPORT_SYMBOL(irq_set_msi_desc); /** * irq_set_chip_data - set irq chip data for an irq From patchwork Fri Nov 24 15:53:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk13C2m8tz9sBZ for ; Sat, 25 Nov 2017 02:54:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753824AbdKXPy1 (ORCPT ); Fri, 24 Nov 2017 10:54:27 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14739 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753795AbdKXPyW (ORCPT ); Fri, 24 Nov 2017 10:54:22 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 24 Nov 2017 07:54:24 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:54:22 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:54:22 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:20 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:54:20 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:54:19 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 02/10] of: Export of_pci_range_to_resource() Date: Fri, 24 Nov 2017 21:23:12 +0530 Message-ID: <1511538800-8275-3-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Allow PCI host driver to use of_pci_range_to_resource() to create a resource from an of_pci_range. Signed-off-by: Manikanta Maddireddy --- drivers/of/address.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/address.c b/drivers/of/address.c index 792722e7d458..9c7b2071bf2f 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -348,6 +348,7 @@ int of_pci_range_to_resource(struct of_pci_range *range, res->end = (resource_size_t)OF_BAD_ADDR; return err; } +EXPORT_SYMBOL(of_pci_range_to_resource); #endif /* CONFIG_PCI */ /* From patchwork Fri Nov 24 15:53:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk13F1vrxz9s4s for ; Sat, 25 Nov 2017 02:54:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753832AbdKXPyc (ORCPT ); Fri, 24 Nov 2017 10:54:32 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3853 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753795AbdKXPya (ORCPT ); Fri, 24 Nov 2017 10:54:30 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 24 Nov 2017 07:54:25 -0800 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:54:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:54:30 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:29 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:54:28 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:54:28 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 03/10] PM / QoS: Fix device resume latency for non PM QoS devices Date: Fri, 24 Nov 2017 21:23:13 +0530 Message-ID: <1511538800-8275-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org In 'commit 0cc2b4e5a020 ("PM / QoS: Fix device resume latency PM QoS")' PM QoS resume latency modified 0 as "no latency at all". However dev_pm_qos_raw_read_value() returns 0 for devices which doesn't have PM QoS constraints. This is blocking runtime suspend for these devices in rpm_check_suspend_allowed(). Return PM_QOS_RESUME_LATENCY_NO_CONSTRAINT when PM QoS constraints are not available for a particular device. Fixes: 0cc2b4e5a020 ("PM / QoS: Fix device resume latency PM QoS") Signed-off-by: Manikanta Maddireddy --- include/linux/pm_qos.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/pm_qos.h b/include/linux/pm_qos.h index 6737a8c9e8c6..d68b0569a5eb 100644 --- a/include/linux/pm_qos.h +++ b/include/linux/pm_qos.h @@ -175,7 +175,8 @@ static inline s32 dev_pm_qos_requested_flags(struct device *dev) static inline s32 dev_pm_qos_raw_read_value(struct device *dev) { return IS_ERR_OR_NULL(dev->power.qos) ? - 0 : pm_qos_read_value(&dev->power.qos->resume_latency); + PM_QOS_RESUME_LATENCY_NO_CONSTRAINT : + pm_qos_read_value(&dev->power.qos->resume_latency); } #else static inline enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, From patchwork Fri Nov 24 15:53:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk13b1380z9s7f for ; Sat, 25 Nov 2017 02:54:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753666AbdKXPys (ORCPT ); Fri, 24 Nov 2017 10:54:48 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3860 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753540AbdKXPyq (ORCPT ); Fri, 24 Nov 2017 10:54:46 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 24 Nov 2017 07:54:41 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:54:46 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:54:46 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:45 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:54:45 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:54:45 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:54:44 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 04/10] ARM: tegra: EXPORT tegra_cpuidle_pcie_irqs_in_use() Date: Fri, 24 Nov 2017 21:23:14 +0530 Message-ID: <1511538800-8275-5-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org EXPORT tegra_cpuidle_pcie_irqs_in_use() to allow Tegra PCIe driver to be compiled as loadable kernel module. Signed-off-by: Manikanta Maddireddy --- arch/arm/mach-tegra/cpuidle.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 316563141add..7d7e6d3ce32d 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -57,3 +57,4 @@ void tegra_cpuidle_pcie_irqs_in_use(void) break; } } +EXPORT_SYMBOL(tegra_cpuidle_pcie_irqs_in_use); From patchwork Fri Nov 24 15:53:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk13t3NyDz9s76 for ; Sat, 25 Nov 2017 02:55:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753783AbdKXPzE (ORCPT ); Fri, 24 Nov 2017 10:55:04 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3870 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753570AbdKXPzD (ORCPT ); Fri, 24 Nov 2017 10:55:03 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 24 Nov 2017 07:54:57 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:55:02 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:55:02 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:55:01 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:55:00 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 05/10] PCI: Export pci_find_host_bridge() Date: Fri, 24 Nov 2017 21:23:15 +0530 Message-ID: <1511538800-8275-6-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Allow PCI host driver to use pci_find_host_bridge() to get pci_host_bridge from pci_bus. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host-bridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c index add66236215c..e0942fc086ad 100644 --- a/drivers/pci/host-bridge.c +++ b/drivers/pci/host-bridge.c @@ -22,6 +22,7 @@ struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus) return to_pci_host_bridge(root_bus->bridge); } +EXPORT_SYMBOL(pci_find_host_bridge); struct device *pci_get_host_bridge_device(struct pci_dev *dev) { From patchwork Fri Nov 24 15:53:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk14V5hyKz9s7f for ; Sat, 25 Nov 2017 02:55:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753848AbdKXPzg (ORCPT ); Fri, 24 Nov 2017 10:55:36 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7493 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753727AbdKXPzK (ORCPT ); Fri, 24 Nov 2017 10:55:10 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 24 Nov 2017 07:54:58 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:55:07 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:55:07 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:07 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:55:07 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:55:07 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 06/10] PCI: Export pci_flags Date: Fri, 24 Nov 2017 21:23:16 +0530 Message-ID: <1511538800-8275-7-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org pci_flags is used in pci.h, export pci_flags for the driver which is including pci.h Signed-off-by: Manikanta Maddireddy --- drivers/pci/setup-bus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 958da7db9033..2d0e8588710a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -29,6 +29,7 @@ #include "pci.h" unsigned int pci_flags; +EXPORT_SYMBOL(pci_flags); struct pci_dev_resource { struct list_head list; From patchwork Fri Nov 24 15:53:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk14C0vXtz9s76 for ; Sat, 25 Nov 2017 02:55:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753736AbdKXPzS (ORCPT ); Fri, 24 Nov 2017 10:55:18 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14827 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753867AbdKXPzO (ORCPT ); Fri, 24 Nov 2017 10:55:14 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 24 Nov 2017 07:55:16 -0800 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:55:14 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:55:14 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:13 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:55:13 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:55:13 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 07/10] PCI: tegra: free resources on probe failure Date: Fri, 24 Nov 2017 21:23:17 +0530 Message-ID: <1511538800-8275-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org tegra_pcie_probe() can fail in multiple instances, this patch takes care of freeing the resources which are allocated before probe fail. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 102 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 86 insertions(+), 16 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b52bdd941249..09f52cd569c6 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -681,14 +681,25 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie) pci_add_resource(windows, &pcie->busn); err = devm_request_pci_bus_resources(dev, windows); - if (err < 0) + if (err < 0) { + pci_free_resource_list(windows); return err; + } pci_remap_iospace(&pcie->pio, pcie->io.start); return 0; } +static void tegra_pcie_free_resources(struct tegra_pcie *pcie) +{ + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct list_head *windows = &host->windows; + + pci_unmap_iospace(&pcie->pio); + pci_free_resource_list(windows); +} + static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) { struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); @@ -1089,29 +1100,40 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) return 0; } -static void tegra_pcie_power_off(struct tegra_pcie *pcie) +static void tegra_pcie_disable_controller(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; const struct tegra_pcie_soc *soc = pcie->soc; int err; - /* TODO: disable and unprepare clocks? */ - if (soc->program_uphy) { err = tegra_pcie_phy_power_off(pcie); if (err < 0) dev_err(dev, "failed to power off PHY(s): %d\n", err); } +} + +static void tegra_pcie_power_off(struct tegra_pcie *pcie) +{ + struct device *dev = pcie->dev; + const struct tegra_pcie_soc *soc = pcie->soc; + int err; reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); - if (!dev->pm_domain) - tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); + clk_disable_unprepare(pcie->pll_e); + if (soc->has_cml_clk) + clk_disable_unprepare(pcie->cml_clk); + clk_disable_unprepare(pcie->afi_clk); + clk_disable_unprepare(pcie->pex_clk); err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); if (err < 0) dev_warn(dev, "failed to disable regulators: %d\n", err); + + if (!dev->pm_domain) + tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); } static int tegra_pcie_power_on(struct tegra_pcie *pcie) @@ -1242,6 +1264,15 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_phys_put_legacy(struct tegra_pcie *pcie) +{ + int err; + + err = phy_exit(pcie->phy); + if (err < 0) + dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); +} + static struct phy *devm_of_phy_optional_get_index(struct device *dev, struct device_node *np, const char *consumer, @@ -1295,6 +1326,19 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port) return 0; } +static void tegra_pcie_port_put_phys(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + unsigned int i; + int err; + + for (i = 0; i < port->lanes; i++) { + err = phy_exit(port->phys[i]); + if (err < 0) + dev_err(dev, "failed to teardown PHY#%u: %d\n", i, err); + } +} + static int tegra_pcie_phys_get(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -1314,6 +1358,19 @@ static int tegra_pcie_phys_get(struct tegra_pcie *pcie) return 0; } +static void tegra_pcie_phys_put(struct tegra_pcie *pcie) +{ + const struct tegra_pcie_soc *soc = pcie->soc; + struct device_node *np = pcie->dev->of_node; + struct tegra_pcie_port *port; + + if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL) + tegra_pcie_phys_put_legacy(pcie); + + list_for_each_entry(port, &pcie->ports, list) + tegra_pcie_port_put_phys(port); +} + static int tegra_pcie_get_resources(struct tegra_pcie *pcie) { struct device *dev = pcie->dev; @@ -1346,7 +1403,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = tegra_pcie_power_on(pcie); if (err) { dev_err(dev, "failed to power up: %d\n", err); - return err; + goto phys_put; } pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); @@ -1404,25 +1461,23 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) poweroff: tegra_pcie_power_off(pcie); +phys_put: + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); return err; } static int tegra_pcie_put_resources(struct tegra_pcie *pcie) { - struct device *dev = pcie->dev; const struct tegra_pcie_soc *soc = pcie->soc; - int err; if (pcie->irq > 0) free_irq(pcie->irq, pcie); tegra_pcie_power_off(pcie); - if (soc->program_uphy) { - err = phy_exit(pcie->phy); - if (err < 0) - dev_err(dev, "failed to teardown PHY: %d\n", err); - } + if (soc->program_uphy) + tegra_pcie_phys_put(pcie); return 0; } @@ -2351,6 +2406,16 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_disable_ports(struct tegra_pcie *pcie) +{ + struct tegra_pcie_port *port, *tmp; + + reset_control_assert(pcie->pcie_xrst); + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_port_disable(port); +} + static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, struct pci_dev *pci_dev) { @@ -2671,7 +2736,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_request_resources(pcie); if (err) - goto put_resources; + goto disable_controller; /* setup the AFI address translations */ tegra_pcie_setup_translations(pcie); @@ -2680,7 +2745,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = tegra_pcie_enable_msi(pcie); if (err < 0) { dev_err(dev, "failed to enable MSI support: %d\n", err); - goto put_resources; + goto free_resources; } } @@ -2721,6 +2786,11 @@ static int tegra_pcie_probe(struct platform_device *pdev) disable_msi: if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + tegra_pcie_disable_ports(pcie); +free_resources: + tegra_pcie_free_resources(pcie); +disable_controller: + tegra_pcie_disable_controller(pcie); put_resources: tegra_pcie_put_resources(pcie); return err; From patchwork Fri Nov 24 15:53:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841124 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk14F0dYGz9s4s for ; Sat, 25 Nov 2017 02:55:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753759AbdKXPzX (ORCPT ); Fri, 24 Nov 2017 10:55:23 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7511 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753768AbdKXPzU (ORCPT ); Fri, 24 Nov 2017 10:55:20 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 24 Nov 2017 07:55:10 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:55:20 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:55:20 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:20 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:55:19 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:55:19 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 08/10] PCI: tegra: Add loadable kernel module support Date: Fri, 24 Nov 2017 21:23:18 +0530 Message-ID: <1511538800-8275-9-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Implement remove call back function for Tegra PCIe driver to add loadable kernel module support. Change PCI_TEGRA config to tristate to allow pci-tegra driver to build as a module. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-tegra.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index b868803792d8..15eb265461b2 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -34,7 +34,7 @@ config PCI_FTPCI100 default ARCH_GEMINI config PCI_TEGRA - bool "NVIDIA Tegra PCIe controller" + tristate "NVIDIA Tegra PCIe controller" depends on ARCH_TEGRA help Say Y here if you want support for the PCIe host controller found diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 09f52cd569c6..2ff1ac3aefc1 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -2700,6 +2701,12 @@ static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) return -ENOMEM; } +static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie) +{ + debugfs_remove_recursive(pcie->debugfs); + pcie->debugfs = NULL; +} + static int tegra_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2714,6 +2721,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) return -ENOMEM; pcie = pci_host_bridge_priv(host); + platform_set_drvdata(pdev, pcie); pcie->soc = of_device_get_match_data(dev); INIT_LIST_HEAD(&pcie->buses); @@ -2796,6 +2804,25 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } +static int tegra_pcie_remove(struct platform_device *pdev) +{ + struct tegra_pcie *pcie = platform_get_drvdata(pdev); + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + + if (IS_ENABLED(CONFIG_DEBUG_FS)) + tegra_pcie_debugfs_exit(pcie); + pci_stop_root_bus(host->bus); + pci_remove_root_bus(host->bus); + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + tegra_pcie_disable_ports(pcie); + tegra_pcie_free_resources(pcie); + tegra_pcie_disable_controller(pcie); + tegra_pcie_put_resources(pcie); + + return 0; +} + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", @@ -2803,5 +2830,7 @@ static struct platform_driver tegra_pcie_driver = { .suppress_bind_attrs = true, }, .probe = tegra_pcie_probe, + .remove = tegra_pcie_remove, }; -builtin_platform_driver(tegra_pcie_driver); +module_platform_driver(tegra_pcie_driver); +MODULE_LICENSE("GPL"); From patchwork Fri Nov 24 15:53:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk14N52qcz9s4s for ; Sat, 25 Nov 2017 02:55:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753883AbdKXPz3 (ORCPT ); Fri, 24 Nov 2017 10:55:29 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3887 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753880AbdKXPz0 (ORCPT ); Fri, 24 Nov 2017 10:55:26 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 24 Nov 2017 07:55:21 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 24 Nov 2017 07:55:26 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 24 Nov 2017 07:55:26 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 24 Nov 2017 15:55:25 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 24 Nov 2017 15:55:25 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 24 Nov 2017 07:55:25 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 09/10] PCI: tegra: Broadcast PME_turn_Off message before link goes to L2 Date: Fri, 24 Nov 2017 21:23:19 +0530 Message-ID: <1511538800-8275-10-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast PME_turn_Off message before PCIe link goes to L2. PME_turn_Off broadcast mechanism is implemented in AFI module. Each Tegra PCIe root port has its own PME_turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this register to broadcast PME_turn_Off message. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 2ff1ac3aefc1..af999c650941 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -155,6 +155,8 @@ #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_PCIE_PME 0xf0 + #define AFI_PCIE_CONFIG 0x0f8 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe @@ -315,6 +317,7 @@ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ #define LINK_RETRAIN_TIMEOUT 100000 +#define PME_ACK_TIMEOUT 10000 struct tegra_msi { struct msi_controller chip; @@ -1483,6 +1486,76 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) return 0; } +static inline u32 get_pme_turnoff_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 0; + case 1: + ret = 8; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 16; + else + ret = 12; + } + return ret; +} + +static inline u32 get_pme_ack_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 5; + case 1: + ret = 10; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 18; + else + ret = 14; + } + return ret; +} + +static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port) +{ + struct tegra_pcie *pcie = port->pcie; + ktime_t deadline; + unsigned int data; + + data = afi_readl(pcie, AFI_PCIE_PME); + data |= (0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); + + deadline = ktime_add_us(ktime_get(), PME_ACK_TIMEOUT); + do { + data = afi_readl(pcie, AFI_PCIE_PME); + data &= (0x1 << get_pme_ack_bitmap(port)); + udelay(1); + if (ktime_after(ktime_get(), deadline)) + break; + } while (!data); + + if (data) + dev_err(pcie->dev, "PME Ack is not receieved on port: %d\n", + port->index); + + usleep_range(10000, 11000); + + data = afi_readl(pcie, AFI_PCIE_PME); + data &= ~(0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); +} + static int tegra_msi_alloc(struct tegra_msi *chip) { int msi; @@ -2808,6 +2881,7 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); @@ -2815,6 +2889,8 @@ static int tegra_pcie_remove(struct platform_device *pdev) pci_remove_root_bus(host->bus); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); tegra_pcie_free_resources(pcie); tegra_pcie_disable_controller(pcie); From patchwork Fri Nov 24 15:53:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841130 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yk14X5V8Mz9s4s for ; Sat, 25 Nov 2017 02:55:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753892AbdKXPzf (ORCPT ); Fri, 24 Nov 2017 10:55:35 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7529 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753612AbdKXPzd (ORCPT ); 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Fri, 24 Nov 2017 07:55:31 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH 10/10] PCI: tegra: Add power management support Date: Fri, 24 Nov 2017 21:23:20 +0530 Message-ID: <1511538800-8275-11-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> References: <1511538800-8275-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra186 powergate driver is implemented as power domain driver, power partition ungate/gate are registered as power_on/power_off callback functions. There are no direct functions to power gate/ungate host controller in Tegra186. Host controller driver should add "power-domains" property in device tree and implement runtime suspend and resume callback functons. Power gate and ungate is taken care by power domain driver when host controller driver calls pm_runtime_put_sync and pm_runtime_get_sync respectively. Register suspend_noirq & resume_noirq callback functions to allow PCIe to come up after resume from RAM. Both runtime and noirq pm ops share same callback functions. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 174 ++++++++++++++++++++++++++----------------- 1 file changed, 106 insertions(+), 68 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index af999c650941..e443b3ebc4b5 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1404,31 +1404,25 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) } } - err = tegra_pcie_power_on(pcie); - if (err) { - dev_err(dev, "failed to power up: %d\n", err); - goto phys_put; - } - pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); pcie->pads = devm_ioremap_resource(dev, pads); if (IS_ERR(pcie->pads)) { err = PTR_ERR(pcie->pads); - goto poweroff; + goto phys_put; } afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); pcie->afi = devm_ioremap_resource(dev, afi); if (IS_ERR(pcie->afi)) { err = PTR_ERR(pcie->afi); - goto poweroff; + goto phys_put; } /* request configuration space, but remap later, on demand */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); if (!res) { err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } axi_addr = pcie->soc->use_4k_conf_space ? @@ -1436,21 +1430,21 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) pcie->cs = devm_request_mem_region(dev, axi_addr, SZ_4K, res->name); if (!pcie->cs) { err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } pcie->cfg_va_base = devm_ioremap(dev, pcie->cs->start, SZ_4K); if (!pcie->cfg_va_base) { dev_err(pcie->dev, "failed to ioremap config space\n"); err = -EADDRNOTAVAIL; - goto poweroff; + goto phys_put; } /* request interrupt */ err = platform_get_irq_byname(pdev, "intr"); if (err < 0) { dev_err(dev, "failed to get IRQ: %d\n", err); - goto poweroff; + goto phys_put; } pcie->irq = err; @@ -1458,13 +1452,11 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); if (err) { dev_err(dev, "failed to register IRQ: %d\n", err); - goto poweroff; + goto phys_put; } return 0; -poweroff: - tegra_pcie_power_off(pcie); phys_put: if (soc->program_uphy) tegra_pcie_phys_put(pcie); @@ -1478,8 +1470,6 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) if (pcie->irq > 0) free_irq(pcie->irq, pcie); - tegra_pcie_power_off(pcie); - if (soc->program_uphy) tegra_pcie_phys_put(pcie); @@ -1702,37 +1692,41 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) int err; u32 reg; - mutex_init(&msi->lock); + if (!msi->phys) { + mutex_init(&msi->lock); - msi->chip.dev = dev; - msi->chip.setup_irq = tegra_msi_setup_irq; - msi->chip.teardown_irq = tegra_msi_teardown_irq; + msi->chip.dev = dev; + msi->chip.setup_irq = tegra_msi_setup_irq; + msi->chip.teardown_irq = tegra_msi_teardown_irq; - msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, - &msi_domain_ops, &msi->chip); - if (!msi->domain) { - dev_err(dev, "failed to create IRQ domain\n"); - return -ENOMEM; - } + msi->domain = irq_domain_add_linear(dev->of_node, + INT_PCI_MSI_NR, + &msi_domain_ops, + &msi->chip); + if (!msi->domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } - err = platform_get_irq_byname(pdev, "msi"); - if (err < 0) { - dev_err(dev, "failed to get IRQ: %d\n", err); - goto err; - } + err = platform_get_irq_byname(pdev, "msi"); + if (err < 0) { + dev_err(dev, "failed to get IRQ: %d\n", err); + goto err; + } - msi->irq = err; + msi->irq = err; - err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, - tegra_msi_irq_chip.name, pcie); - if (err < 0) { - dev_err(dev, "failed to request IRQ: %d\n", err); - goto err; - } + err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, + tegra_msi_irq_chip.name, pcie); + if (err < 0) { + dev_err(dev, "failed to request IRQ: %d\n", err); + goto err; + } - /* setup AFI/FPCI range */ - msi->pages = __get_free_pages(GFP_KERNEL, 0); - msi->phys = virt_to_phys((void *)msi->pages); + /* setup AFI/FPCI range */ + msi->pages = __get_free_pages(GFP_KERNEL, 0); + msi->phys = virt_to_phys((void *)msi->pages); + } afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); @@ -2811,26 +2805,16 @@ static int tegra_pcie_probe(struct platform_device *pdev) return err; } - err = tegra_pcie_enable_controller(pcie); - if (err) + pm_runtime_enable(pcie->dev); + err = pm_runtime_get_sync(pcie->dev); + if (err) { + dev_err(dev, "fail to enable pcie controller: %d\n", err); goto put_resources; + } err = tegra_pcie_request_resources(pcie); if (err) - goto disable_controller; - - /* setup the AFI address translations */ - tegra_pcie_setup_translations(pcie); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - err = tegra_pcie_enable_msi(pcie); - if (err < 0) { - dev_err(dev, "failed to enable MSI support: %d\n", err); - goto free_resources; - } - } - - tegra_pcie_enable_ports(pcie); + goto pm_runtime_put; pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); host->busnr = pcie->busn.start; @@ -2842,7 +2826,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) err = pci_scan_root_bus_bridge(host); if (err < 0) { dev_err(dev, "failed to register host: %d\n", err); - goto disable_msi; + goto free_resources; } pci_bus_size_bridges(host->bus); @@ -2864,14 +2848,13 @@ static int tegra_pcie_probe(struct platform_device *pdev) return 0; -disable_msi: - if (IS_ENABLED(CONFIG_PCI_MSI)) - tegra_pcie_disable_msi(pcie); - tegra_pcie_disable_ports(pcie); free_resources: tegra_pcie_free_resources(pcie); -disable_controller: - tegra_pcie_disable_controller(pcie); +pm_runtime_put: + if (IS_ENABLED(CONFIG_PCI_MSI)) + tegra_pcie_disable_msi(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); put_resources: tegra_pcie_put_resources(pcie); return err; @@ -2881,7 +2864,6 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); - struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); @@ -2889,21 +2871,77 @@ static int tegra_pcie_remove(struct platform_device *pdev) pci_remove_root_bus(host->bus); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + tegra_pcie_free_resources(pcie); + pm_runtime_put_sync(pcie->dev); + pm_runtime_disable(pcie->dev); + tegra_pcie_put_resources(pcie); + + return 0; +} + +static int tegra_pcie_pm_suspend(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + struct tegra_pcie_port *port, *tmp; + list_for_each_entry_safe(port, tmp, &pcie->ports, list) tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); - tegra_pcie_free_resources(pcie); tegra_pcie_disable_controller(pcie); - tegra_pcie_put_resources(pcie); + tegra_pcie_power_off(pcie); return 0; } +static int tegra_pcie_pm_resume(struct device *dev) +{ + struct tegra_pcie *pcie = dev_get_drvdata(dev); + int err; + + err = tegra_pcie_power_on(pcie); + if (err) { + dev_err(dev, "tegra pcie power on fail: %d\n", err); + return err; + } + err = tegra_pcie_enable_controller(pcie); + if (err) { + dev_err(dev, "tegra pcie controller enable fail: %d\n", err); + goto poweroff; + } + tegra_pcie_setup_translations(pcie); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err = tegra_pcie_enable_msi(pcie); + if (err < 0) { + dev_err(dev, "failed to enable MSI support: %d\n", err); + goto disable_controller; + } + } + + tegra_pcie_enable_ports(pcie); + + return 0; + +disable_controller: + tegra_pcie_disable_controller(pcie); +poweroff: + tegra_pcie_power_off(pcie); + + return err; +} + +static const struct dev_pm_ops tegra_pcie_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_pcie_pm_suspend, tegra_pcie_pm_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_pcie_pm_suspend, + tegra_pcie_pm_resume) +}; + static struct platform_driver tegra_pcie_driver = { .driver = { .name = "tegra-pcie", .of_match_table = tegra_pcie_of_match, .suppress_bind_attrs = true, + .pm = &tegra_pcie_pm_ops, }, .probe = tegra_pcie_probe, .remove = tegra_pcie_remove,