From patchwork Fri Nov 24 14:08:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841044 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyjk4h4Vz9s8J for ; Sat, 25 Nov 2017 01:09:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QlZ5PKjH"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyjj5DDrzDrpS for ; Sat, 25 Nov 2017 01:09:13 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QlZ5PKjH"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QlZ5PKjH"; dkim-atps=neutral Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjH2G3vzDrbq for ; Sat, 25 Nov 2017 01:08:51 +1100 (AEDT) Received: by mail-pl0-x243.google.com with SMTP id l16so4518768pli.6 for ; Fri, 24 Nov 2017 06:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cKqvsXccyJ6Nlm/4rQnwTvaNBLGfvNFsc3Nauy5CAuo=; b=QlZ5PKjHUorFvuO9yi8q59fdgOodzJGMYmAYQIfYs3Ud5pAAOi+blYmWB4TCNCL3py d2B9aGLnXRISqVqDRdi5G0svG/XhX3LLirLdKQYYdzR/l4s86hzeXYZaxbekJL5m2CPt sYZ4fppFpm3gZzVEe8zo9qMB0b7w+cHrprfipErX/i9kxS/EsHINVFG1AUM4wHVu/ZEn YKQ7WdKVXUKaoPUekOw6pC3Kg98MGnNYadfmD66IEJWJvihvJHHH7rjvse4W8yMEzE1t W1YRqAKXW3oUyIeJa82j333H/g0m5teBmw86pgrQfxeDGWYm4m3pfAEOxl0KPWluBbKA vfhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cKqvsXccyJ6Nlm/4rQnwTvaNBLGfvNFsc3Nauy5CAuo=; b=kRtZR5Ww+geMMtMNCdWP6YlQ9YbQgY5Raufk2/N1KAi+89YYkM7K9gGVkX6hmx8J2R JIxR0pRKeQUcrlhdrIsk/dCbmDN5U30penxsxkN67Coq2jwLOxcU4HFnAdOnWP8Z0NgQ mRRN/fbmlcVZWgEfsojZpV7PEN79N5g5EXrgeabZadKL13EN8hKNsUZpRKxZilc6jkX8 fLdfLmdv0sHbpY0U7eZZYJA+rDUJy5/bqqQz7mveS3bKc6sUGPz7/5EIuWnw0N4vIsu8 QdMZZM9qdkNcwlupyysC1VeQ1rah7mV/ldVTmxN4F3Y5DBX0/yc7QoEc+zG1Ol1B80o2 qKYg== X-Gm-Message-State: AJaThX7JNi08TqjxZowV7BgKURk7qlf90B2kKFyxpxo49jIpIo0oB7BA Sv6EV2JNGKTt8q3nzUB3zuDWJA== X-Google-Smtp-Source: AGs4zMYPzkaPiUKCyrpgMRbMvcj0o+BzYBEpvjNfAkQwrK9xh58CNzbduPDEudYRrbUtqHAiksqllg== X-Received: by 10.84.204.136 with SMTP id b8mr28648942ple.319.1511532528775; Fri, 24 Nov 2017 06:08:48 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:08:47 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:10 +1000 Message-Id: <20171124140834.7099-2-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 01/25] fast-reboot: restore SMT priority on spin loop exit X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 8af5c590a..f63a6454b 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -535,6 +535,7 @@ void __noreturn fast_reboot_entry(void) smt_lowest(); sync(); } + smt_medium(); } prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); From patchwork Fri Nov 24 14:08:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841045 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyk53SVWz9sBd for ; Sat, 25 Nov 2017 01:09:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="q7qxIT2V"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyk42V8bzDrnw for ; Sat, 25 Nov 2017 01:09:32 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="q7qxIT2V"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="q7qxIT2V"; dkim-atps=neutral Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjL32KHzDrbq for ; Sat, 25 Nov 2017 01:08:54 +1100 (AEDT) Received: by mail-pf0-x242.google.com with SMTP id k24so5134602pfb.1 for ; Fri, 24 Nov 2017 06:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ko3op72yDjypuNDAXu/dqSHTwKxocq7iTB74FMTlWNM=; b=q7qxIT2VAovdVZe/uERuoCiLtUHOAMrCejlzT11v6nlBHZQVATwKqfzsnUqLLTo3eD gLvzjTD2DYLA4WHUGo8u2ZBwQVW4oJv35NIsAk771531X/BfvrJttgPciseRZRorPhRj Jr6XHy665nG/bjrNVuQW4AxamdVL8jbl9+6uOoUQO8Z42lpuaR08ZAcc5L5yftfBfsDZ 6mliY8SirCzJdGlmvVs16ADuL0ryaE+910QoQSRCm/ciNg4TzgiY3m+hhBse+tU181xu ksKVoTqXAIdk0d8nKMrgbYPEhYxFyQJYyE8FCxRqh0s5EIp9qlWgNy3uNNdrRmRnWXUC u+1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ko3op72yDjypuNDAXu/dqSHTwKxocq7iTB74FMTlWNM=; b=nHOEPDD12HmrlSR3eMKSIjyDjBkRAzC4O/oCrY2IeEOE5fc3m3+p6NHnOqQVb4dQku B3DdT/OaLy/ObVQdrdqTHcjBtmATvCoYkQV91fBdAPFNQAeLkT9oT3IjvltwZ90sPaL+ +ZTd5msQxGShsgCcVwU72aWB/TzmtHsS6/D2oNdYM7VOFPY9xKoI+yYPnLGmq+JOS+ir ZMN6YTTEtAvcAbb0RTDm3uH2rUkFk6bp4fQXiibwPT+AcuAFDFACIVqWo6z3GZRwqzto xTXaRlcs4W1VARvIklFbpPR67YQubdVqFj0X2MiDBt4xfQ/aGm6dkQLh6F6xNBEAp0ru XZjg== X-Gm-Message-State: AJaThX53yXGthc8NrzLOgHAqrx1LXIblgycl6UV9Z2wjPTSpVOSirjzk ChO1BAcX94vnRJEqTsfgN/91+g== X-Google-Smtp-Source: AGs4zMZcyYx6CMQa6jGXx/kXgWzAD/xhcxRWKvb4uBP3oUydd0yVff4d6OGcVPSMsx86vkYsg7sFeg== X-Received: by 10.98.18.157 with SMTP id 29mr27307114pfs.84.1511532531659; Fri, 24 Nov 2017 06:08:51 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.08.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:08:50 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:11 +1000 Message-Id: <20171124140834.7099-3-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 02/25] fast-reboot: factor out direct control loops for sreset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This provides a simple API that is amenable to be implemented by the direct-controls subsystem in a future change. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 79 +++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 58 insertions(+), 21 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index f63a6454b..62c7216b2 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -226,13 +226,10 @@ static void set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) xscom_write(chip_id, xscom_addr, bits); } -static bool fast_reset_p8(void) +static int sreset_all_prepare(void) { struct cpu_thread *cpu; - /* Mark ourselves as last man standing in need of a reset */ - last_man_standing = this_cpu(); - prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); @@ -257,16 +254,28 @@ static bool fast_reset_p8(void) if (cpu != this_cpu()) set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); + } - /* Also make sure that saved_r1 is 0 ! That's what will - * make our reset vector jump to fast_reboot_entry - */ - cpu->save_r1 = 0; + return true; +} + +static void sreset_all_finish(void) +{ + struct cpu_thread *cpu; + + for_each_cpu(cpu) { + /* GARDed CPUs are marked unavailable. Skip them. */ + if (cpu->state == cpu_state_unavailable) + continue; + + if (cpu->primary == cpu) + clr_special_wakeup(cpu); } +} - /* Restore skiboot vectors */ - copy_exception_vectors(); - setup_reset_vector(); +static void sreset_all_others(void) +{ + struct cpu_thread *cpu; prlog(PR_DEBUG, "RESET: Pre-napping all threads but one...\n"); @@ -291,6 +300,42 @@ static bool fast_reset_p8(void) if (cpu != this_cpu()) set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); } +} + +static void sreset_cpu(struct cpu_thread *cpu) +{ + set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); + set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); +} + +static bool fast_reset_p8(void) +{ + struct cpu_thread *cpu; + + /* Mark ourselves as last man standing in need of a reset */ + last_man_standing = this_cpu(); + + if (!sreset_all_prepare()) + return false; + + /* Put everybody in stop except myself */ + for_each_cpu(cpu) { + /* GARDed CPUs are marked unavailable. Skip them. */ + if (cpu->state == cpu_state_unavailable) + continue; + + /* Also make sure that saved_r1 is 0 ! That's what will + * make our reset vector jump to fast_reboot_entry + */ + cpu->save_r1 = 0; + } + + /* Restore skiboot vectors */ + copy_exception_vectors(); + setup_reset_vector(); + + /* Send everyone else to 0x100 */ + sreset_all_others(); return true; } @@ -463,8 +508,7 @@ void __noreturn fast_reboot_entry(void) lock(&reset_lock); if (last_man_standing && next_cpu(first_cpu())) { prlog(PR_DEBUG, "RESET: last man standing fixup...\n"); - set_direct_ctl(last_man_standing, P8_DIRECT_CTL_PRENAP); - set_direct_ctl(last_man_standing, P8_DIRECT_CTL_SRESET); + sreset_cpu(last_man_standing); } last_man_standing = NULL; unlock(&reset_lock); @@ -540,14 +584,7 @@ void __noreturn fast_reboot_entry(void) prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - - if (cpu->primary == cpu) - clr_special_wakeup(cpu); - } + sreset_all_finish(); prlog(PR_INFO, "RESET: All done, cleaning up...\n"); From patchwork Fri Nov 24 14:08:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjykX6JM2z9s8J for ; Sat, 25 Nov 2017 01:09:56 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S46m0vKa"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjykX53lBzDrpC for ; Sat, 25 Nov 2017 01:09:56 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S46m0vKa"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::243; helo=mail-pg0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S46m0vKa"; dkim-atps=neutral Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjN5lLvzDrns for ; Sat, 25 Nov 2017 01:08:56 +1100 (AEDT) Received: by mail-pg0-x243.google.com with SMTP id 199so3754794pgg.3 for ; Fri, 24 Nov 2017 06:08:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pXotVBELEXp5eKiqEuKWtVqUXILqhblibFoVs8zVb4g=; b=S46m0vKapPOXlr8NVy0jQg5vPDwjIavRjDW3oU2nKpFh3VytrMtVQVRaMSEdF1sdmM 1hWQ47swPXJrXi2s+/a3K1x3+9o25myvbX8bsgXv1jaH+dEEOOwmbQnD41Xo526oqwqg WRzExhzmhGUOb9OZs5vKNq8y3EoAFcgUEdowhnXPA94wuJVN5gF8I4mrCGXMEzrZtM0E R2c+AUWpfC1AbkYHgq6k6iyrS6+dfIL1m4wjmgmOyfSl0DX5LmS/HE5+05A3VnU/skH+ 1qWCmcxJhFYH7jntfGR01gANM4q5y/b9prczdGrvXaOArGU1nBfKcWE4h48h1cPgPRFs gKjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pXotVBELEXp5eKiqEuKWtVqUXILqhblibFoVs8zVb4g=; b=HtKVRevAnFOR59qAumIENnnUjmKsdo3omH0Jdo99VOY/FHgg91iuFHHrk+45MopqHC fAiBteOimOe+eoDfm8bFxPXAJgD2TaCHhQe2RE3kU3u17++43PIt8k+1fN9TfUOImnOa P9QrAAsvCFMc7ty2ifyo/kn1SiW9/3+KlfShqbxQjRZLW2AUB8Cnf7NQ/Vz1Rhflf2uC zPpD5NKtVPgCrAC/+jKR8mKOMXqfHkIdmwIRRsGcT5+AQOT7VDGpeWkSII4tre/VXqN2 l058Kg8dot4Mb9kdzXxJc9SHRWkuVEeka0GAB/VViTILKiJB7TcnjnzeiQqZcTtQPbYH PbWw== X-Gm-Message-State: AJaThX5tWPRIi4LIxwPO5C3mY2rT3yRPUd9Gjh7r3qEU+YKx3sPqU/yN MCODRGk7mI4hQhRMC/yVNf+htg== X-Google-Smtp-Source: AGs4zMbUmppbtKJoF8fKJClpZbZm1xJ+DkRoFc65cc3mw3mf8aIIT9EaORVbcRckqOL8Kio26iBsRQ== X-Received: by 10.98.152.147 with SMTP id d19mr26812364pfk.95.1511532534517; Fri, 24 Nov 2017 06:08:54 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.08.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:08:53 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:12 +1000 Message-Id: <20171124140834.7099-4-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 03/25] fast-reboot: remove last man standing logic X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The "last man standing" logic has the initiator CPU sreset all others, then one of them sresets the initiator. This complicates the fast reboot process and increases potential for errors. The initiator can simply branch to 0x100 directly. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 62c7216b2..aad84adb4 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -37,7 +37,6 @@ /* Flag tested by the OPAL entry code */ uint8_t reboot_in_progress; static volatile bool fast_boot_release; -static struct cpu_thread *last_man_standing; static struct lock reset_lock = LOCK_UNLOCKED; static int set_special_wakeup(struct cpu_thread *cpu) @@ -302,19 +301,10 @@ static void sreset_all_others(void) } } -static void sreset_cpu(struct cpu_thread *cpu) -{ - set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); - set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); -} - static bool fast_reset_p8(void) { struct cpu_thread *cpu; - /* Mark ourselves as last man standing in need of a reset */ - last_man_standing = this_cpu(); - if (!sreset_all_prepare()) return false; @@ -402,10 +392,7 @@ void fast_reboot(void) unlock(&reset_lock); if (success) { - if (!next_cpu(first_cpu())) - /* Only 1 CPU, so fake reset ourselves */ - asm volatile("ba 0x100 " : : : ); - /* Don't return */ + asm volatile("ba 0x100\n\t" : : : "memory"); for (;;) ; } @@ -505,14 +492,6 @@ void __noreturn fast_reboot_entry(void) prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", this_cpu()->pir); time_wait_ms(100); - lock(&reset_lock); - if (last_man_standing && next_cpu(first_cpu())) { - prlog(PR_DEBUG, "RESET: last man standing fixup...\n"); - sreset_cpu(last_man_standing); - } - last_man_standing = NULL; - unlock(&reset_lock); - /* We reset our ICP first ! Otherwise we might get stray interrupts * when unsplitting */ From patchwork Fri Nov 24 14:08:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjykw1GYBz9s8J for ; Sat, 25 Nov 2017 01:10:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p8OZny9S"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjykv6rGWzDrcV for ; Sat, 25 Nov 2017 01:10:15 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p8OZny9S"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p8OZny9S"; dkim-atps=neutral Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjS0R0xzDrcT for ; Sat, 25 Nov 2017 01:08:59 +1100 (AEDT) Received: by mail-pf0-x244.google.com with SMTP id m88so14872454pfi.9 for ; Fri, 24 Nov 2017 06:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5qVd6mIlION6KMmNF6Yb9U91sknXIzcCtCJumAUlhp0=; b=p8OZny9S2OJUEo96Ex1h6b7S69U0OT+iWt0EOOSIcl66mJDauZiZyzwen/pjXMWciQ iNRg2jP0/7jniJ6jJUNNpomgmOKe/eotimfvhk0idHdldOGrPz3xM9rhMIRjoEQVw7Fh 5CED/PxBk7Sw+i1p0Y9BSgCVp3rIJHi9lYZcPiwaDtzxJWoPpuVEUH41xxxoAvMJqM1x 7AlYylVg5XhYRkB3J9RhfSWrk2uNxBVkoXKsnCr5g3u17t7PHbeMlTCghAgdnB2l89hI UB22FTATRVvhtifYWgmzfqWrQ8RawDjSBhnM4UC4spObJfORMP+KiJor5FB9VBG/aBcC nP3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5qVd6mIlION6KMmNF6Yb9U91sknXIzcCtCJumAUlhp0=; b=bFE7yB8TClAP44n07Kv8pAZ4TkD+5ezjbpQIqAT44CJJ7fFmG7zM8BI8WuIzKQAir8 g+DB7Il6RuKHwOHlfmGjr1oL4YnujoIfKgMZ8gvH8PDbXln4+x+tnYUKYNYTDPvX/fGl odkVCSrSQGLAYwLx0DOx/+PLkaZEsga0p+vvia4dnVQCu77IfWmy+yq7kVCwQtBnxEft Q5luTV50rraODTs7T9L/ZWcUMSdwJUVq8Fdw1pndgofgH1Y8xx/oAw8FlTuqVHPP/acx bFsqJZKX3cc9nHogjRLWYyXMLNAuAVHIaC+naX3c1zOZmrnK+4xxSXDKSdEnbfaT4IO0 St0g== X-Gm-Message-State: AJaThX4yOqI7OnpTI0UUKXZ5Bjb5mtmcLkQNGaJVLXNyJ7FcpiChNJOW I5ESitmZSDS5xRagCdC13Vwtcg== X-Google-Smtp-Source: AGs4zMbLxsc4wpgPCbSnGg4gAJoGSoSe/Ov2aLw5BA5tFog8GyIJLzJTfTNdNLJaQo/1KaG6Asveyg== X-Received: by 10.98.100.71 with SMTP id y68mr27295096pfb.178.1511532537480; Fri, 24 Nov 2017 06:08:57 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.08.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:08:56 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:13 +1000 Message-Id: <20171124140834.7099-5-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 04/25] fast-reboot: clean up some common cpu iteration processes with macros X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/cpu.c | 28 +++++++++++++++++++++++++++ core/fast-reboot.c | 57 +++++++++++------------------------------------------- include/cpu.h | 10 ++++++++++ 3 files changed, 49 insertions(+), 46 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index 27e0d6cf3..d07911031 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -709,6 +709,34 @@ struct cpu_thread *first_present_cpu(void) return next_present_cpu(NULL); } +struct cpu_thread *next_ungarded_cpu(struct cpu_thread *cpu) +{ + do { + cpu = next_cpu(cpu); + } while(cpu && cpu->state == cpu_state_unavailable); + + return cpu; +} + +struct cpu_thread *first_ungarded_cpu(void) +{ + return next_ungarded_cpu(NULL); +} + +struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu) +{ + do { + cpu = next_cpu(cpu); + } while(cpu && cpu->state == cpu_state_unavailable && cpu->primary != cpu); + + return cpu; +} + +struct cpu_thread *first_ungarded_primary(void) +{ + return next_ungarded_primary(NULL); +} + u8 get_available_nr_cores_in_chip(u32 chip_id) { struct cpu_thread *core; diff --git a/core/fast-reboot.c b/core/fast-reboot.c index aad84adb4..412639ad0 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -233,24 +233,15 @@ static int sreset_all_prepare(void) this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); /* Assert special wakup on all cores. Only on operational cores. */ - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - - if (cpu->primary == cpu) - if (set_special_wakeup(cpu) != OPAL_SUCCESS) - return false; + for_each_ungarded_primary(cpu) { + if (set_special_wakeup(cpu) != OPAL_SUCCESS) + return false; } prlog(PR_DEBUG, "RESET: Stopping the world...\n"); /* Put everybody in stop except myself */ - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - + for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); } @@ -262,14 +253,8 @@ static void sreset_all_finish(void) { struct cpu_thread *cpu; - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - - if (cpu->primary == cpu) - clr_special_wakeup(cpu); - } + for_each_ungarded_primary(cpu) + clr_special_wakeup(cpu); } static void sreset_all_others(void) @@ -279,11 +264,7 @@ static void sreset_all_others(void) prlog(PR_DEBUG, "RESET: Pre-napping all threads but one...\n"); /* Put everybody in pre-nap except myself */ - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - + for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); } @@ -291,11 +272,7 @@ static void sreset_all_others(void) prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); /* Reset everybody except my own core threads */ - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - + for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); } @@ -309,11 +286,7 @@ static bool fast_reset_p8(void) return false; /* Put everybody in stop except myself */ - for_each_cpu(cpu) { - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - + for_each_ungarded_cpu(cpu) { /* Also make sure that saved_r1 is 0 ! That's what will * make our reset vector jump to fast_reboot_entry */ @@ -522,14 +495,10 @@ void __noreturn fast_reboot_entry(void) /* We are the original boot CPU, wait for secondaries to * be captured. */ - for_each_cpu(cpu) { + for_each_ungarded_cpu(cpu) { if (cpu == this_cpu()) continue; - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - /* XXX Add a callin timeout ? */ while (cpu->state != cpu_state_present) { smt_lowest(); @@ -545,14 +514,10 @@ void __noreturn fast_reboot_entry(void) sync(); /* Wait for them to respond */ - for_each_cpu(cpu) { + for_each_ungarded_cpu(cpu) { if (cpu == this_cpu()) continue; - /* GARDed CPUs are marked unavailable. Skip them. */ - if (cpu->state == cpu_state_unavailable) - continue; - /* XXX Add a callin timeout ? */ while (cpu->state == cpu_state_present) { smt_lowest(); diff --git a/include/cpu.h b/include/cpu.h index 5db4ccbe6..3d5dbd40d 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -190,6 +190,10 @@ extern struct cpu_thread *first_available_cpu(void); extern struct cpu_thread *next_available_cpu(struct cpu_thread *cpu); extern struct cpu_thread *first_present_cpu(void); extern struct cpu_thread *next_present_cpu(struct cpu_thread *cpu); +extern struct cpu_thread *first_ungarded_cpu(void); +extern struct cpu_thread *next_ungarded_cpu(struct cpu_thread *cpu); +extern struct cpu_thread *first_ungarded_primary(void); +extern struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu); #define for_each_cpu(cpu) \ for (cpu = first_cpu(); cpu; cpu = next_cpu(cpu)) @@ -200,6 +204,12 @@ extern struct cpu_thread *next_present_cpu(struct cpu_thread *cpu); #define for_each_present_cpu(cpu) \ for (cpu = first_present_cpu(); cpu; cpu = next_present_cpu(cpu)) +#define for_each_ungarded_cpu(cpu) \ + for (cpu = first_ungarded_cpu(); cpu; cpu = next_ungarded_cpu(cpu)) + +#define for_each_ungarded_primary(cpu) \ + for (cpu = first_ungarded_primary(); cpu; cpu = next_ungarded_primary(cpu)) + extern struct cpu_thread *first_available_core_in_chip(u32 chip_id); extern struct cpu_thread *next_available_core_in_chip(struct cpu_thread *cpu, u32 chip_id); extern u8 get_available_nr_cores_in_chip(u32 chip_id); From patchwork Fri Nov 24 14:08:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjylB3Kfhz9s8J for ; Sat, 25 Nov 2017 01:10:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="llCwmwAR"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjylB1cvdzDrnp for ; Sat, 25 Nov 2017 01:10:30 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="llCwmwAR"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="llCwmwAR"; dkim-atps=neutral Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjW0nvrzDrpc for ; Sat, 25 Nov 2017 01:09:02 +1100 (AEDT) Received: by mail-pl0-x242.google.com with SMTP id b12so4525777plm.3 for ; Fri, 24 Nov 2017 06:09:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RoEK8i8ns5bb6KLUgQs+gpcnWswKPi+KcNxEuv07Fhg=; b=llCwmwARnB9aq+ErnGB7nuxMaI/nUmURmXmbj4ukGz1U03u87qy0ilFypYlzifkPDn eK932QboyH9fCdOml/KQUByGm/rFKG5Jk5YDz7s0BTQQH7yMXKHWRIhzrjRSLP4v965T fK1wRW2BpQ3w0pqHfrJrZ1IrCL6lfPZiCH6EJahGW4guT/KW0dQf4rClx3tfvkzi1O2X 4EVJW97oHvNdauTale2YyBTHFwjiAEDczOVUrX0e8CAz4k+Xgw5D7kyA6LIA9WxiDhXP OwMxXLmFrDNvk7rIxSsfN9b8fSVT53Vn//MqaMRvCT4hGe3gxtKpAYpMwkOrO13MfCrO jDzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RoEK8i8ns5bb6KLUgQs+gpcnWswKPi+KcNxEuv07Fhg=; b=HBfrA9BjNzXsY5AIxkarY3hmqx6etgsdSpt0a4hHM8hJTxEsgVS9vXCCkB1uZ85Ed/ 8JZKf4zen/x44xXAn4pHQOcHyAkfhndCd3Niucw4vVOAqyKuOOlKfWahQJTNFk4SU2KV Rlj6OhT3TSeHq3TGPYd8RtZ3fG7VN118TFNzKcVJg6364YA9r9nVohh79HgDoTRHcKsn 59tRQwSBDClHqPxZnBnY0ywUTyXkpAWrfGnb+MKhXEqbe4fLSRuJtm4rrkJYddz1CyT8 hlLUyxSY63hX3pJbM36VEtxIXimjN6aZJTnH1LRnjFEBHzs8ASF920+2NO3D3O7k1x9l N5cw== X-Gm-Message-State: AJaThX7crWIaH00mHHGItzQ1NUa3Y/681oTpjeS6Yd4OWGDdrXioiV+H nSbvy+yeQ3lwVA/p200OmuXhvQ== X-Google-Smtp-Source: AGs4zMbjJB5c2TwEqoPtuo5oJFZrzqAOpM0D7luTW7EomDgNG3CQ86NceLBNSeyDgnVfgoJxQtTEYQ== X-Received: by 10.84.168.226 with SMTP id f89mr29416811plb.176.1511532540213; Fri, 24 Nov 2017 06:09:00 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.08.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:08:59 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:14 +1000 Message-Id: <20171124140834.7099-6-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 05/25] fast-reboot: factor out the mambo sreset code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move the mambo sreset code out from the P8 implementation. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 85 +++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 59 insertions(+), 26 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 412639ad0..94ad660c9 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -39,7 +39,7 @@ uint8_t reboot_in_progress; static volatile bool fast_boot_release; static struct lock reset_lock = LOCK_UNLOCKED; -static int set_special_wakeup(struct cpu_thread *cpu) +static int p8_set_special_wakeup(struct cpu_thread *cpu) { uint64_t val, poll_target, stamp; uint32_t core_id; @@ -54,8 +54,6 @@ static int set_special_wakeup(struct cpu_thread *cpu) core_id = pir_to_core_id(cpu->pir); prlog(PR_DEBUG, "RESET Waking up core 0x%x\n", core_id); - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return OPAL_SUCCESS; /* * The original HWp reads the XSCOM first but ignores the result @@ -152,7 +150,7 @@ static int set_special_wakeup(struct cpu_thread *cpu) return OPAL_HARDWARE; } -static int clr_special_wakeup(struct cpu_thread *cpu) +static int p8_clr_special_wakeup(struct cpu_thread *cpu) { uint64_t val; uint32_t core_id; @@ -167,8 +165,6 @@ static int clr_special_wakeup(struct cpu_thread *cpu) core_id = pir_to_core_id(cpu->pir); prlog(PR_DEBUG, "RESET: Releasing core 0x%x wakeup\n", core_id); - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return OPAL_SUCCESS; /* * The original HWp reads the XSCOM first but ignores the result @@ -201,23 +197,12 @@ static int clr_special_wakeup(struct cpu_thread *cpu) return 0; } -extern unsigned long callthru_tcl(const char *str, int len); - -static void set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) +static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) { uint32_t core_id = pir_to_core_id(cpu->pir); uint32_t chip_id = pir_to_chip_id(cpu->pir); uint32_t thread_id = pir_to_thread_id(cpu->pir); uint32_t xscom_addr; - char tcl_cmd[50]; - - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { - if (bits != P8_DIRECT_CTL_SRESET) - return; - snprintf(tcl_cmd, sizeof(tcl_cmd), "mysim cpu %i:%i set spr pc 0x100", core_id, thread_id); - callthru_tcl(tcl_cmd, strlen(tcl_cmd)); - return; - } xscom_addr = XSCOM_ADDR_P8_EX(core_id, P8_EX_TCTL_DIRECT_CONTROLS(thread_id)); @@ -225,7 +210,7 @@ static void set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) xscom_write(chip_id, xscom_addr, bits); } -static int sreset_all_prepare(void) +static int p8_sreset_all_prepare(void) { struct cpu_thread *cpu; @@ -234,7 +219,7 @@ static int sreset_all_prepare(void) /* Assert special wakup on all cores. Only on operational cores. */ for_each_ungarded_primary(cpu) { - if (set_special_wakeup(cpu) != OPAL_SUCCESS) + if (p8_set_special_wakeup(cpu) != OPAL_SUCCESS) return false; } @@ -243,21 +228,21 @@ static int sreset_all_prepare(void) /* Put everybody in stop except myself */ for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) - set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); } return true; } -static void sreset_all_finish(void) +static void p8_sreset_all_finish(void) { struct cpu_thread *cpu; for_each_ungarded_primary(cpu) - clr_special_wakeup(cpu); + p8_clr_special_wakeup(cpu); } -static void sreset_all_others(void) +static void p8_sreset_all_others(void) { struct cpu_thread *cpu; @@ -266,7 +251,7 @@ static void sreset_all_others(void) /* Put everybody in pre-nap except myself */ for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) - set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); } prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); @@ -274,7 +259,55 @@ static void sreset_all_others(void) /* Reset everybody except my own core threads */ for_each_ungarded_cpu(cpu) { if (cpu != this_cpu()) - set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); + } +} + +extern unsigned long callthru_tcl(const char *str, int len); + +static void mambo_sreset_cpu(struct cpu_thread *cpu) +{ + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + char tcl_cmd[50]; + + snprintf(tcl_cmd, sizeof(tcl_cmd), "mysim cpu %i:%i set spr pc 0x100", core_id, thread_id); + callthru_tcl(tcl_cmd, strlen(tcl_cmd)); +} + +static int sreset_all_prepare(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return true; + + if (proc_gen == proc_gen_p8) + return p8_sreset_all_prepare(); + + return false; +} + +static void sreset_all_finish(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return; + + if (proc_gen == proc_gen_p8) + return p8_sreset_all_finish(); +} + +static void sreset_all_others(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { + struct cpu_thread *cpu; + + for_each_ungarded_cpu(cpu) + mambo_sreset_cpu(cpu); + return; + } + + if (proc_gen == proc_gen_p8) { + p8_sreset_all_others(); + return; } } From patchwork Fri Nov 24 14:08:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjylT1X36z9s8J for ; Sat, 25 Nov 2017 01:10:45 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QmD/U56Z"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjylT0J2nzDrcT for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:02 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:15 +1000 Message-Id: <20171124140834.7099-7-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 06/25] fast-reboot: add sreset_all_others error handling X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Pass back failures from sreset_all_others, also change return codes to OPAL_ form in sreset_all_prepare to match. Errors will revert to the IPL path, so it's not critical to completely clean up everything if that would complicate things. Detecting the error and failing is the important thing. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 94ad660c9..6203ff203 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -220,7 +220,7 @@ static int p8_sreset_all_prepare(void) /* Assert special wakup on all cores. Only on operational cores. */ for_each_ungarded_primary(cpu) { if (p8_set_special_wakeup(cpu) != OPAL_SUCCESS) - return false; + return OPAL_HARDWARE; } prlog(PR_DEBUG, "RESET: Stopping the world...\n"); @@ -231,7 +231,7 @@ static int p8_sreset_all_prepare(void) p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); } - return true; + return OPAL_SUCCESS; } static void p8_sreset_all_finish(void) @@ -278,12 +278,12 @@ static void mambo_sreset_cpu(struct cpu_thread *cpu) static int sreset_all_prepare(void) { if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return true; + return OPAL_SUCCESS; if (proc_gen == proc_gen_p8) return p8_sreset_all_prepare(); - return false; + return OPAL_UNSUPPORTED; } static void sreset_all_finish(void) @@ -295,27 +295,30 @@ static void sreset_all_finish(void) return p8_sreset_all_finish(); } -static void sreset_all_others(void) +static int sreset_all_others(void) { if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { struct cpu_thread *cpu; for_each_ungarded_cpu(cpu) mambo_sreset_cpu(cpu); - return; + + return OPAL_SUCCESS; } if (proc_gen == proc_gen_p8) { p8_sreset_all_others(); - return; + return OPAL_SUCCESS; } + + return OPAL_UNSUPPORTED; } static bool fast_reset_p8(void) { struct cpu_thread *cpu; - if (!sreset_all_prepare()) + if (sreset_all_prepare()) return false; /* Put everybody in stop except myself */ @@ -331,9 +334,10 @@ static bool fast_reset_p8(void) setup_reset_vector(); /* Send everyone else to 0x100 */ - sreset_all_others(); + if (sreset_all_others() == OPAL_SUCCESS) + return true; - return true; + return false; } extern void *fdt; From patchwork Fri Nov 24 14:08:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjylm5D66z9sBd for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:04 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:16 +1000 Message-Id: <20171124140834.7099-8-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 07/25] fast-reboot: make spin loops consistent and SMT friendly X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 6203ff203..c6ecd1cc6 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -518,11 +518,14 @@ void __noreturn fast_reboot_entry(void) */ if (this_cpu() != boot_cpu) { this_cpu()->state = cpu_state_present; - while (!fast_boot_release) { + sync(); + if (!fast_boot_release) { smt_lowest(); - sync(); + while (!fast_boot_release) + barrier(); + smt_medium(); } - smt_medium(); + sync(); cleanup_cpu_state(); __secondary_cpu_entry(); } @@ -537,11 +540,12 @@ void __noreturn fast_reboot_entry(void) continue; /* XXX Add a callin timeout ? */ - while (cpu->state != cpu_state_present) { + if (cpu->state != cpu_state_present) { smt_lowest(); - sync(); + while (cpu->state != cpu_state_present) + barrier(); + smt_medium(); } - smt_medium(); } prlog(PR_INFO, "RESET: Releasing secondaries...\n"); @@ -556,16 +560,18 @@ void __noreturn fast_reboot_entry(void) continue; /* XXX Add a callin timeout ? */ - while (cpu->state == cpu_state_present) { + if (cpu->state == cpu_state_present) { smt_lowest(); - sync(); + while (cpu->state == cpu_state_present) + barrier(); + smt_medium(); } - smt_medium(); } prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); sreset_all_finish(); + sync(); prlog(PR_INFO, "RESET: All done, cleaning up...\n"); From patchwork Fri Nov 24 14:08:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjym05XM2z9s8J for ; Sat, 25 Nov 2017 01:11:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aG5jldI/"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjym04L1SzDrpv for ; Sat, 25 Nov 2017 01:11:12 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aG5jldI/"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aG5jldI/"; dkim-atps=neutral Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjf6VJXzDrpS for ; Sat, 25 Nov 2017 01:09:10 +1100 (AEDT) Received: by mail-pf0-x244.google.com with SMTP id l24so14890747pfj.6 for ; Fri, 24 Nov 2017 06:09:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QdAiF6mx0gliR2IdV7tjWpprQOd1Kenj/FzEoR1yEHE=; b=aG5jldI/7svQx8+s9YbHJDXtZjvDsWov26O4o9GuRwY8FDTNvQOpgOGfqhHZUACPQc 1KgJUpPnIMTR4yk+g2qnLUFhZah85M+irLGvuWX9UXiJncWkLR+LHwesAKOvmcL97GBx 3xGQZzzQN+qYgNMaoCEN3wunbSWpWg7x0n4fWKkQAHgXBvpirm3ugPNthcBbXWKnP8Oi i1IIVsxY9CLxCTSgiCJA7035gXz0sMFpGjOkah+4kquM1PjkcCM74FnSvyiQGP192g1j 3X+8GT1GpSMhu0i41BV8vYMfjSiniPkb+uSjin+pyndWBzoBr9MpkdpMMKd/QHVaZUr0 Vgpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QdAiF6mx0gliR2IdV7tjWpprQOd1Kenj/FzEoR1yEHE=; b=XAppzq/ECI/FPEEh5G3bRVRv6F6A5w777d0cSdaB1TZbGl/iV7TfM3kh0S/6QgJqKY XIugA4n9OxpY7wx841Ec19jtp9LyZgnyXGpRF2hJwhGEx/ThY5Fmu+8olaffdx5YwjXO LanrqpyMLmTJda8/EhmhNOP6zfZMLDqsKY0SUvlACy8vKTpZVpD408+mzkqhAcMMX5cX 97mcOFkSNnd3KblpuUoDYcXxL+7gVXr36MKsnQ+zwSYnvliEZTdoxaV51GSWNcUS1hSB dsFnMNX8JBUyfaOK9D6TCf0N47XxQgllqYlOBfAb6/Gb6vwJ78oXfJePA+X/P7qBnIq8 aoPA== X-Gm-Message-State: AJaThX4FR0Sx3Xp5+GUaixICmH2KtXfTFH4pXLGqo3Uh/Mvy68on79wH n7bEKt5JdOW533doz++auXmbag== X-Google-Smtp-Source: AGs4zMZ7YTd1P2+u9rkeqCpsnN8XrMhJ5iDZpyRS4i0KNi3NAv3ZTycdAnDtb89Q0j68xqFEvsnnXw== X-Received: by 10.99.124.24 with SMTP id x24mr27896434pgc.196.1511532548783; Fri, 24 Nov 2017 06:09:08 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:07 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:17 +1000 Message-Id: <20171124140834.7099-9-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 08/25] fast-reboot: add sreset timeout detection and handling X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Have the initiator wait for all its sreset targets to call in, and time out after 200ms if they did not. Fail and revert to IPL reboot. Testing indicates that after successful sreset_all_others(), it takes less than 102ms (in hundreds of fast reboots) for secondaries to call in. 100 of that is due to an initial delay, but core un-splitting was not measured. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 78 +++++++++++++++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 33 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index c6ecd1cc6..70fb4eb9f 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -340,6 +340,35 @@ static bool fast_reset_p8(void) return false; } +static bool cpu_state_wait_all_others(enum cpu_thread_state state, + unsigned long timeout_tb) +{ + struct cpu_thread *cpu; + unsigned long end = mftb() + timeout_tb; + + sync(); + for_each_ungarded_cpu(cpu) { + if (cpu == this_cpu()) + continue; + + if (cpu->state != state) { + smt_lowest(); + while (cpu->state != state) { + barrier(); + + if (timeout_tb && (tb_compare(mftb(), end) == TB_AAFTERB)) { + smt_medium(); + return false; + } + } + smt_medium(); + } + } + sync(); + + return true; +} + extern void *fdt; extern struct lock capi_lock; @@ -401,11 +430,16 @@ void fast_reboot(void) /* Unlock, at this point we go away */ unlock(&reset_lock); - if (success) { - asm volatile("ba 0x100\n\t" : : : "memory"); - for (;;) - ; - } + if (!success) + return; + + /* Ensure all the sresets get through */ + if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(200))) + return; + + asm volatile("ba 0x100\n\t" : : : "memory"); + for (;;) + ; } static void cleanup_cpu_state(void) @@ -497,8 +531,6 @@ void __noreturn fast_reboot_entry(void); void __noreturn fast_reboot_entry(void) { - struct cpu_thread *cpu; - prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", this_cpu()->pir); time_wait_ms(100); @@ -512,13 +544,15 @@ void __noreturn fast_reboot_entry(void) */ check_split_core(); + sync(); + this_cpu()->state = cpu_state_present; + sync(); + /* Are we the original boot CPU ? If not, we spin waiting * for a relase signal from CPU 1, then we clean ourselves * up and go processing jobs. */ if (this_cpu() != boot_cpu) { - this_cpu()->state = cpu_state_present; - sync(); if (!fast_boot_release) { smt_lowest(); while (!fast_boot_release) @@ -535,18 +569,7 @@ void __noreturn fast_reboot_entry(void) /* We are the original boot CPU, wait for secondaries to * be captured. */ - for_each_ungarded_cpu(cpu) { - if (cpu == this_cpu()) - continue; - - /* XXX Add a callin timeout ? */ - if (cpu->state != cpu_state_present) { - smt_lowest(); - while (cpu->state != cpu_state_present) - barrier(); - smt_medium(); - } - } + cpu_state_wait_all_others(cpu_state_present, 0); prlog(PR_INFO, "RESET: Releasing secondaries...\n"); @@ -555,18 +578,7 @@ void __noreturn fast_reboot_entry(void) sync(); /* Wait for them to respond */ - for_each_ungarded_cpu(cpu) { - if (cpu == this_cpu()) - continue; - - /* XXX Add a callin timeout ? */ - if (cpu->state == cpu_state_present) { - smt_lowest(); - while (cpu->state == cpu_state_present) - barrier(); - smt_medium(); - } - } + cpu_state_wait_all_others(cpu_state_active, 0); prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); From patchwork Fri Nov 24 14:08:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjymG2SnHz9s8J for ; Sat, 25 Nov 2017 01:11:26 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z3XN8RSz"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjymG1HWPzDrpp for ; Sat, 25 Nov 2017 01:11:26 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z3XN8RSz"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z3XN8RSz"; dkim-atps=neutral Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjk3tSTzDrp6 for ; Sat, 25 Nov 2017 01:09:14 +1100 (AEDT) Received: by mail-pl0-x241.google.com with SMTP id u14so4516953plm.8 for ; Fri, 24 Nov 2017 06:09:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pn6lUSXgHqg7OhVML6mjq/+BnE/RfQ5tiMR6cBtbLz4=; b=Z3XN8RSzTZqDybqLvG8lawvgq3LcISNmziu/OSSw3WGHQpfDxwpy+zK4XCnj5bS5Hh B8ChPWYUy3oYl6SYPV/oQrrzs0Sr+R3u4jOGCwxdaZ/arkOfl0hD1lLrwjXmo0TEc48K 6FqpSG88smY/50Y8/tmiAXN7TdCB9cEFONTM4JPP95MxU48uxXuv/dyxZZ02WlNqRbTd oLw4YYXRQ3BYRgV52+V0SjA0cOMkATwdSg5fP4kw3FQOxFDgcN0ppt7Upso9hQ1PWSgV ZJElfRqf+TIE1rai/r51ZFQm6KyL3dl1dK+cT5R7v1tSFwN9vNRrlP+VfKndORYIC/hN jBXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pn6lUSXgHqg7OhVML6mjq/+BnE/RfQ5tiMR6cBtbLz4=; b=letjvikhFVDis3uMjc9tydiqV1ev7kKQlLk2hpdoBYbt27B2FJysGu7m+BiIh2Muky mqac3nUybr3dqn4pqKa4VYt38uMG9iIxxgubeBwPmkB01tWtH/smjypAYGiulVTfTb1b FFwNtoFd4ufe27fAXDm8hD3ChCfRxPGhoIZL3meUAA5DjBqsPFrnrEhCuUKTUTzxJxHL BiF+mlCpJb0eX3OdzmKpJqiqacnKRIte7jFyI+6pKhaZ9vW/Z5m7LBNk4UH6mlh031a4 eGFy0sx28hSLBwOQoh3jG+5xyt1H6J/OIo8cmcvXD/cihfyGPc2jxmchawvM6H0pgQgv eKyg== X-Gm-Message-State: AJaThX74DeAIDU7HJrXBJN7QbRwUzQaYu3g7r3bJYkznbqsBCq3KzOzd /6GCrwQiIkrVNBqfbJkqZe5S0w== X-Google-Smtp-Source: AGs4zMbpZ/Qx/5EKvY0+b+sa5N7qHCuzFxVN+sv3304c/uXaUL3bHoi+vMjzlYsag/vMUGM0A+ZKJQ== X-Received: by 10.159.204.145 with SMTP id t17mr22088160plo.215.1511532551893; Fri, 24 Nov 2017 06:09:11 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:10 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:18 +1000 Message-Id: <20171124140834.7099-10-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 09/25] fast-reboot: add more barriers around cpu state changes X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is a bit of paranoia, but when a CPU changes state to signal it has reached a particular point, all previous stores should be visible. Signed-off-by: Nicholas Piggin --- core/cpu.c | 3 +++ core/fast-reboot.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/core/cpu.c b/core/cpu.c index d07911031..2dba2f504 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1126,7 +1126,10 @@ void cpu_bringup(void) void cpu_callin(struct cpu_thread *cpu) { + sync(); cpu->state = cpu_state_active; + sync(); + cpu->job_has_no_return = false; init_hid(); diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 70fb4eb9f..8f9823e28 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -424,6 +424,7 @@ void fast_reboot(void) lock(&reset_lock); fast_boot_release = false; + sync(); success = fast_reset_p8(); @@ -574,8 +575,8 @@ void __noreturn fast_reboot_entry(void) prlog(PR_INFO, "RESET: Releasing secondaries...\n"); /* Release everybody */ - fast_boot_release = true; sync(); + fast_boot_release = true; /* Wait for them to respond */ cpu_state_wait_all_others(cpu_state_active, 0); @@ -595,7 +596,9 @@ void __noreturn fast_reboot_entry(void) cleanup_cpu_state(); /* Set our state to active */ + sync(); this_cpu()->state = cpu_state_active; + sync(); /* Let the CPU layer do some last minute global cleanups */ cpu_fast_reboot_complete(); From patchwork Fri Nov 24 14:08:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjymV2hRLz9s8J for ; Sat, 25 Nov 2017 01:11:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UvS9b71N"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjymV1W3xzDsFM for ; Sat, 25 Nov 2017 01:11:38 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UvS9b71N"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UvS9b71N"; dkim-atps=neutral Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjm5SKszDrnx for ; Sat, 25 Nov 2017 01:09:16 +1100 (AEDT) Received: by mail-pl0-x243.google.com with SMTP id 62so4520175plc.2 for ; Fri, 24 Nov 2017 06:09:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S4WC8Ar+73RqcsA6GMrxiEWlL2wvfCJZyOyysedQFa8=; b=UvS9b71N0N9cnJpCDBxsy8IGx+yfOLqjEw02s1acwNQEu9QFw6AyYUUMdcIj8/+Cr+ F6WaeLHyhCuMDcTzJRfD6ZaE0Iy9wH0CeZQRtW8Aj0h8IXcBmwY/vfvbFrSHvRwUtCI0 E9D0M3th0Fc5c3hKVopBiRX5IwAfyRnDNrRhJB+rNXKhw7UtARorJ4tr8/MHXv4cfBvC 6BjMcVZXoLvv79Ekd8xmDu1mRZO4inoPRgsFC5at7fIuBT4tiYnV9iVNqOCzzxjAll02 nYhbVxdJI/98rRiTPEu8+j0mi/s8Oj6MhDOXWrQQRM/8cwWR0ocLTQtvCP3xQVqKBJBR bKXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S4WC8Ar+73RqcsA6GMrxiEWlL2wvfCJZyOyysedQFa8=; b=PYj7GYU6WwiACH3A+51+Yz7Gn6+lOb6ZQgiJiPzxrUL5RodijqQE8q3lqmepxd2+yZ 1HIqpACecIbFCtLTK/vH+65MfPBN2sgOYLHJPZlBjOt71y1QcLWbxkN+kD79SO50Aux2 juKUdHFRtcC53KU/dSOYHY5xJdEuUkoHxJvnQpE3JQ4zqahbh6B8YDgaY2te79ZBvGz3 B0IF3lilDHCViWs3RWSLa6axQGZ8dmoWLPv2YQ8Cg/I7WmqrrX1QYh+8vGx8WY1TqU3Y 35RDKQOeIw466sKN0r49vD6IPT92WLJXxcGElXWTNzTZqW5oXFuKOm4Xkyn55W7lAGZ0 l/tQ== X-Gm-Message-State: AJaThX6QUBgj9tcnec3Ci4BwK3FMAATAX+phFnKMMoiu9memsAyUalFY xyhF/e/qjowcqHmUe/LWwWKIGg== X-Google-Smtp-Source: AGs4zMb2AcrEkQpqoY9dTF3b/59yS/8uvx3jJtuAiS8RIsPrE+gPZvZIFK6B1XLUeoeotDQV2i7ZdQ== X-Received: by 10.84.193.129 with SMTP id f1mr29608154pld.317.1511532554714; Fri, 24 Nov 2017 06:09:14 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:13 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:19 +1000 Message-Id: <20171124140834.7099-11-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 10/25] fast-reboot: remove delay after sreset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There is a 100ms delay when targets reach sreset which does not appear to have a good purpose. Remove it and therefore reduce the sreset timeout by the same amount. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 8f9823e28..278c288f5 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -435,7 +435,7 @@ void fast_reboot(void) return; /* Ensure all the sresets get through */ - if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(200))) + if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(100))) return; asm volatile("ba 0x100\n\t" : : : "memory"); @@ -533,7 +533,6 @@ void __noreturn fast_reboot_entry(void); void __noreturn fast_reboot_entry(void) { prlog(PR_DEBUG, "RESET: CPU 0x%04x reset in\n", this_cpu()->pir); - time_wait_ms(100); /* We reset our ICP first ! Otherwise we might get stray interrupts * when unsplitting From patchwork Fri Nov 24 14:08:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyml2Lnmz9sBd for ; Sat, 25 Nov 2017 01:11:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pUrZdeV1"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyml16CszDrqQ for ; Sat, 25 Nov 2017 01:11:51 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pUrZdeV1"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pUrZdeV1"; dkim-atps=neutral Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjq40fwzDrcP for ; Sat, 25 Nov 2017 01:09:19 +1100 (AEDT) Received: by mail-pl0-x241.google.com with SMTP id k7so4524199pln.13 for ; Fri, 24 Nov 2017 06:09:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N5UTq3LrinVwxGxSDHXKBaXd1fCYQfeqBcctu2USYvc=; b=pUrZdeV1KHcY/Q8tDA0uGJuxDiBzrRsqpVtmNCpHlD/oSDgneZEv/ik76pGt8E4IjR iuRn2wC3gT94WfV6zrSYOPitibRgz20lHqXmCASQ29lzC4WwXhDz+eaeV+HJx4Wb5YOg yirco7mqOIJ9nJh6FqQ5NQ4V9zQVLQG6pDeyiQ/01s8rwx3SETHq1Nu8OeS5zCgHJEx0 v6OZ0fxAYYtCyUY98BlhDNp0B+NM81oHfKr7riFhQ/6H7TeqNQXLvndfFNOfruNnAnzk la7Bj11KBy2+hzfEzswoKQ0ZeB3BGYTQB2HzA3y7FF7J2wDgTulF2nOpEctcR8uHqQiI lldg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N5UTq3LrinVwxGxSDHXKBaXd1fCYQfeqBcctu2USYvc=; b=ght+x7e6XzvkT5mLqm60MOU5WBEMNNNmO4TrCcWf2v+ms510qEEJXDwL83bZivl2xz 6a+8rFWK/biwG3lDdNVieSdhseSAh1UQMOVpwQ9CQ88WEn6ZojdfYvx7nW922KRciDcw gierwU5jEDcS2MqEca54u30oCw67dpG6TMiTptFocHII4VAjCVfaBb9+jXNjJqgw4qwk WBhdGRmvMh9+jl1IRcvwJ1QxWEOQljJ2qdAMVdIz66UqOpQfCOAAjcnlDam3o1WZ4CE2 Gb2MesvcAsoak09P2J4Ke4OASfIntgdKrFneScJbdLXmiWM1HGoaRWJ10Um4411fSHUB I2/Q== X-Gm-Message-State: AJaThX7AF7/A4Frx15nFt5CEyXVdktdWFabnJHY5xucVE4e5FE0ipE3N tVXThuAMdpaGMSucAdtFJZU36Q== X-Google-Smtp-Source: AGs4zMbJnInpdYK3Zibwi3MnRYlWCITUUJqH7NRrZvjIHa7cMbi1HZNBfIgA58VjHu8QXfOYr3CmHA== X-Received: by 10.159.198.148 with SMTP id g20mr28925466plo.89.1511532557614; Fri, 24 Nov 2017 06:09:17 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:16 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:20 +1000 Message-Id: <20171124140834.7099-12-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 11/25] fast-reboot: inline fast_reset_p8 into fast_reboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This function has shrunk to the point it's not so helpful to keep it, it's no longer power8 specific, and getting rid of it simplifies error handling a little in future changes. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 54 ++++++++++++++++++++++++------------------------------ 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 278c288f5..575894b75 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -314,32 +314,6 @@ static int sreset_all_others(void) return OPAL_UNSUPPORTED; } -static bool fast_reset_p8(void) -{ - struct cpu_thread *cpu; - - if (sreset_all_prepare()) - return false; - - /* Put everybody in stop except myself */ - for_each_ungarded_cpu(cpu) { - /* Also make sure that saved_r1 is 0 ! That's what will - * make our reset vector jump to fast_reboot_entry - */ - cpu->save_r1 = 0; - } - - /* Restore skiboot vectors */ - copy_exception_vectors(); - setup_reset_vector(); - - /* Send everyone else to 0x100 */ - if (sreset_all_others() == OPAL_SUCCESS) - return true; - - return false; -} - static bool cpu_state_wait_all_others(enum cpu_thread_state state, unsigned long timeout_tb) { @@ -384,7 +358,7 @@ void disable_fast_reboot(const char *reason) void fast_reboot(void) { - bool success; + struct cpu_thread *cpu; static int fast_reboot_count = 0; if (proc_gen != proc_gen_p8) { @@ -426,12 +400,32 @@ void fast_reboot(void) fast_boot_release = false; sync(); - success = fast_reset_p8(); + /* Put everybody in stop except myself */ + if (sreset_all_prepare()) + return; - /* Unlock, at this point we go away */ + /* Now everyone else is stopped */ unlock(&reset_lock); - if (!success) + /* + * There is no point clearing special wakeup due to failure after this + * point, because we will be going to full IPL. Less cleanup work means + * less opportunity to fail. + */ + + for_each_ungarded_cpu(cpu) { + /* Also make sure that saved_r1 is 0 ! That's what will + * make our reset vector jump to fast_reboot_entry + */ + cpu->save_r1 = 0; + } + + /* Restore skiboot vectors */ + copy_exception_vectors(); + setup_reset_vector(); + + /* Send everyone else to 0x100 */ + if (sreset_all_others() != OPAL_SUCCESS) return; /* Ensure all the sresets get through */ From patchwork Fri Nov 24 14:08:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyn03K7nz9s8J for ; Sat, 25 Nov 2017 01:12:04 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p3+MRIx/"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyn021FJzDrvF for ; Sat, 25 Nov 2017 01:12:04 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p3+MRIx/"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="p3+MRIx/"; dkim-atps=neutral Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjt6q8yzDrp2 for ; Sat, 25 Nov 2017 01:09:22 +1100 (AEDT) Received: by mail-pg0-x242.google.com with SMTP id 70so15392016pgf.6 for ; Fri, 24 Nov 2017 06:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0PrsdARtxFKkGnqWqLsHBTKe7P8Ps76fYgxJOHAEWAA=; b=p3+MRIx/ontjzEfcZBKWG7sqxKrWWgss7nkX72EEcKffw7Cyk6drqAPMl08h5W0oRM aTCuUROCHcjG65K44IEwNrrxYkW69lNzD52g5/264PMfOMhdrUaIZsMpaM1SxRUv2icG IYnArFXTFGJaSKsaDKOrrYuxBDDXEu6gHAOyb4Ums368EXYk4TAK/lR91yOnVg9Qq3ai Fl4yXLtHeJJnxlq18DyJG6fO3gxPpIhbzaUE3e+QcnMrZZaBmrZ0Zs1+vW+YyXzq+Olh leyN7WrJzToQuvPbc01KI1v/CJK5PHZFCc094w+orHNSQ5UOrq9ncEe7utKvzNErKT8c mTmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0PrsdARtxFKkGnqWqLsHBTKe7P8Ps76fYgxJOHAEWAA=; b=t7+kYPSzdnXxnjRo7mpiDPPdOA3DcVvVjhuV0AobGWtAJzE6/n8ynJNIhRDbgM3+qN fxokhwBL4ApD0o/aLiUCrtKHFHsy1zrEC3rNuspEVCETOT88qqd8zpHiQXJXmopm0xBk ij1mMbjyCu5WeAbYjfEwFEIeMA/aXNOuqOHpdJCt1dnrhc0mzrrKOU4n+SI2H7POoi4z 4EbcKqPFtjwLgBsB6AQpE49iJsbCm0KENxKAmqvjCuXRIlNb3CJ36IGrGEHfSQ5UdqG0 1Zwiek8uY+GtRYmtkxhiMbABOAprwKy4kVDs+5nyM8ajUe7d9p/YqLCWeSSridr8zXiw IdAQ== X-Gm-Message-State: AJaThX7JxXGkKUbnDVA3/ZCGZN4op9VYGXsP1UDXqhOqz8cQs8bV73wC beRUix6JlGqplbnd+vPax7lFYg== X-Google-Smtp-Source: AGs4zMaV3868MI9Gnz7W8QM+3uFe7GWFK5dC3DlXKpuFRTiDZRlHTe95KRr0YpL9w/RMomS3VJkUEw== X-Received: by 10.101.81.202 with SMTP id i10mr9692223pgq.23.1511532560327; Fri, 24 Nov 2017 06:09:20 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:19 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:21 +1000 Message-Id: <20171124140834.7099-13-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 12/25] fast-reboot: move de-asserting of special wakeups to the initiator X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently the boot CPU (not the initiator) clears special wakeups after all CPUs have called in. After the earlier change to have the initiator wait for secondaries before calling in, this is no longer necessary. Have the initiator finish the entire sreset sequence, clearing special wakeups after all others have called in. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 575894b75..8e0a394ad 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -432,6 +432,9 @@ void fast_reboot(void) if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(100))) return; + prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); + sreset_all_finish(); + asm volatile("ba 0x100\n\t" : : : "memory"); for (;;) ; @@ -574,9 +577,6 @@ void __noreturn fast_reboot_entry(void) /* Wait for them to respond */ cpu_state_wait_all_others(cpu_state_active, 0); - prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); - - sreset_all_finish(); sync(); prlog(PR_INFO, "RESET: All done, cleaning up...\n"); From patchwork Fri Nov 24 14:08:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjynD2hS3z9s8J for ; Sat, 25 Nov 2017 01:12:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NluVEOkF"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjynD1YHZzDsG7 for ; Sat, 25 Nov 2017 01:12:16 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NluVEOkF"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NluVEOkF"; dkim-atps=neutral Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyjx38DKzDrnw for ; Sat, 25 Nov 2017 01:09:25 +1100 (AEDT) Received: by mail-pf0-x242.google.com with SMTP id r14so8364370pfl.11 for ; Fri, 24 Nov 2017 06:09:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HE4Wj7QEHW4J1tY9+jw8eauMsqIIebrAJBAYPOG3hBM=; b=NluVEOkFEBSNCXhgGXCbHcUgFOwF9P+lHPVbMDFHjb1wegew0zBpX3YVQTemWC5ueO eaMes4XkA8VHXHgePZ+sCi9XAduV/duKbbudOpdn27UHMkGrzEACIKZQKjFD6AeoWIhz 7qznLFQNFnPg0cZeMbnE0yyKLHKDfEDmIpyDHWt3Q59oxHUgZTEbXp5Tv3Jf26+2uIwr 2gvevX0Eff4o8midwhd7bseXOS+0uPxFS77FcN10zfz/vMNSTHMxau6BNoBkOd+arwBg ONlLOHzfwdKlvpeZEnlgRtsXP6ujSZJynSU7h++lOBWCINHLWCCdn9ZET+zqJiem1WJY sYeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HE4Wj7QEHW4J1tY9+jw8eauMsqIIebrAJBAYPOG3hBM=; b=biJN0ToHWbL24rvYcIP+NiyUVXVOGURJxRRVQVTs0BPVe/IKGHDDRiuO9ZV8quu/5m 4Yi4WTMp4hbBftfjell72Pby7qQWFL5aH8ktsYBsAF6YdocQaqWgkrr4FEd1QG0O8R7b DNoJO+LZO40jj/vRlWIK1DDx+rL2JsLoRwe2X3chbom7524/IhQ9MA6lP5v9SvuAVWZY 8G+hcoulSYAZf4q/LmLkT/r/MRe9J2HxnacBwmeq+lARAwMbBoOMnVcto71n4N0hni0l 6E12IbGb/qCYuqVuSBGW8ekkPARMiUnXhpz1SufkBv25HedeiROvtfhMean5diib8xto e91A== X-Gm-Message-State: AJaThX4myqRYkboUx0dzTlqCOTQqDGTahQEFp2dYYjpaHrOD5FQIG4wK lAi3pmT00D8mIf9mvG9HFp+IrA== X-Google-Smtp-Source: AGs4zMZidNDeq/RbN9OsZAMEIKoQ59P1ZXxA+YqeZCIfmwCzd8WDP3fs4vu1BKm7iHGeLtrfDdy3Ow== X-Received: by 10.99.124.88 with SMTP id l24mr28933531pgn.355.1511532563349; Fri, 24 Nov 2017 06:09:23 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:22 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:22 +1000 Message-Id: <20171124140834.7099-14-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 13/25] fast-reboot: allow mambo fast reboot independent of CPU type X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Don't tie mambo fast reboot to POWER8 CPU type. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 8e0a394ad..fe9ab8e2a 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -361,7 +361,8 @@ void fast_reboot(void) struct cpu_thread *cpu; static int fast_reboot_count = 0; - if (proc_gen != proc_gen_p8) { + if (chip_quirk(QUIRK_MAMBO_CALLOUTS) || + proc_gen != proc_gen_p8) { prlog(PR_DEBUG, "RESET: Fast reboot not available on this CPU\n"); return; From patchwork Fri Nov 24 14:08:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjynT4HV3z9s8J for ; Sat, 25 Nov 2017 01:12:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nJCDYTrf"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjynT2q58zDrpK for ; Sat, 25 Nov 2017 01:12:29 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nJCDYTrf"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::22d; helo=mail-pl0-x22d.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nJCDYTrf"; dkim-atps=neutral Received: from mail-pl0-x22d.google.com (mail-pl0-x22d.google.com [IPv6:2607:f8b0:400e:c01::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyk10l6GzDrcP for ; Sat, 25 Nov 2017 01:09:28 +1100 (AEDT) Received: by mail-pl0-x22d.google.com with SMTP id l16so4519447pli.6 for ; Fri, 24 Nov 2017 06:09:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4sVcIjnQY0xLNOQZnojw4MSKizK1QnVZktVWepzZOzo=; b=nJCDYTrfVSwP6nTQeWEJi536RmfXXv/AIoLXQAX0bnYI1Zcbwyi6tcOgOW1Rclp4OW MYyhDtbcmzCwCfDHXPVf2dAL0B92i6O56tqgx6nwW+uI7i9fclgHFZ/aDgxUw7U0WQ6X g+2NDb8WazZK96goFN6lnjmG0m8ct73S+SFqi59gIApeXPjHGtRjfzVPU5EgdTVTwwHX YrzDRt5R1VKyG3OQW9zkSfM9CgPhyS15XEFkgz1bErKM2Op65BiJPgYVxwwT4wi32Xl8 ywmZobrhQaiX0NIFc8IXPtzhOgD+SLYeqp1RNFJtn3kzPI4ucPiH1Okbh9pRPoZvisjX Jscg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4sVcIjnQY0xLNOQZnojw4MSKizK1QnVZktVWepzZOzo=; b=foyYpoIenfRtMaNFqD3dd255yNQhjZsFU7k9DObF2F9q3sGSt/xquL/F863p+xov5K qamHJPA4MJR8APnEXxWZPdEHaG4fLuR1uTjICWOX18mdWr8LEALA5w08We+wWM9ZRdz3 iP/Wh0/m9Md7bXTZxaUzGQP+VZaf/C96ophdC7yPKUeMk+Yh0N8BoRCFVcXPpFUoGfVc 5gEUBHrq7bky1gJGWljjyEePBmZjzKEEF/xubIlWP0U0LnL9QatkPeHxo0SzAlCrD8mS k9bs/V2y0DXbckITmzjYcAHeaMqK25YYjWINqMqUP1lRBMN1yLN9kQaH5ZuVDhs9LfXR NqXw== X-Gm-Message-State: AJaThX6we6RzPpkNTTWTwuPN5wbinFl88TPsuNCuQRZfdQGFHJhpOedD kxTfUDlbZ0xxacJFO5hizDT6TA== X-Google-Smtp-Source: AGs4zMbXtUqPAL5Oy2hdQsY/F5eB7h8vaSbzQRoMyFGIol71n9jLdUkRc80Jt1lltwHjBWPVoC5hVw== X-Received: by 10.84.170.132 with SMTP id j4mr24661799plb.316.1511532566356; Fri, 24 Nov 2017 06:09:26 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:25 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:23 +1000 Message-Id: <20171124140834.7099-15-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 14/25] fast-reboot: move sreset direct controls to direct-controls.c X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/direct-controls.c | 289 ++++++++++++++++++++++++++++++++++++++++++++++ core/fast-reboot.c | 282 +------------------------------------------- include/direct-controls.h | 29 +++++ 3 files changed, 319 insertions(+), 281 deletions(-) create mode 100644 include/direct-controls.h diff --git a/core/direct-controls.c b/core/direct-controls.c index c5ba80e94..1be80c4bb 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -14,6 +14,7 @@ * limitations under the License. */ +#include #include #include #include @@ -21,6 +22,294 @@ #include #include + +/**************** mambo direct controls ****************/ + +extern unsigned long callthru_tcl(const char *str, int len); + +static void mambo_sreset_cpu(struct cpu_thread *cpu) +{ + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + char tcl_cmd[50]; + + snprintf(tcl_cmd, sizeof(tcl_cmd), "mysim cpu %i:%i set spr pc 0x100", core_id, thread_id); + callthru_tcl(tcl_cmd, strlen(tcl_cmd)); +} + +/**************** POWER8 direct controls ****************/ + +#define P8_EX_TCTL_DIRECT_CONTROLS(t) (0x10013000 + (t) * 0x10) +#define P8_DIRECT_CTL_STOP PPC_BIT(63) +#define P8_DIRECT_CTL_PRENAP PPC_BIT(47) +#define P8_DIRECT_CTL_SRESET PPC_BIT(60) + +static int p8_set_special_wakeup(struct cpu_thread *cpu) +{ + uint64_t val, poll_target, stamp; + uint32_t core_id; + int rc; + + /* + * Note: HWP checks for checkstops, but I assume we don't need to + * as we wouldn't be running if one was present + */ + + /* Grab core ID once */ + core_id = pir_to_core_id(cpu->pir); + + prlog(PR_DEBUG, "RESET Waking up core 0x%x\n", core_id); + + /* + * The original HWp reads the XSCOM first but ignores the result + * and error, let's do the same until I know for sure that is + * not necessary + */ + xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), + &val); + + /* Then we write special wakeup */ + rc = xscom_write(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, + EX_PM_SPECIAL_WAKEUP_PHYP), + PPC_BIT(0)); + if (rc) { + prerror("RESET: XSCOM error %d asserting special" + " wakeup on 0x%x\n", rc, cpu->pir); + return rc; + } + + /* + * HWP uses the history for Perf register here, dunno why it uses + * that one instead of the pHyp one, maybe to avoid clobbering it... + * + * In any case, it does that to check for run/nap vs.sleep/winkle/other + * to decide whether to poll on checkstop or not. Since we don't deal + * with checkstop conditions here, we ignore that part. + */ + + /* + * Now poll for completion of special wakeup. The HWP is nasty here, + * it will poll at 5ms intervals for up to 200ms. This is not quite + * acceptable for us at runtime, at least not until we have the + * ability to "context switch" HBRT. In practice, because we don't + * winkle, it will never take that long, so we increase the polling + * frequency to 1us per poll. However we do have to keep the same + * timeout. + * + * We don't use time_wait_ms() either for now as we don't want to + * poll the FSP here. + */ + stamp = mftb(); + poll_target = stamp + msecs_to_tb(200); + val = 0; + while (!(val & EX_PM_GP0_SPECIAL_WAKEUP_DONE)) { + /* Wait 1 us */ + time_wait_us(1); + + /* Read PM state */ + rc = xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_GP0), + &val); + if (rc) { + prerror("RESET: XSCOM error %d reading PM state on" + " 0x%x\n", rc, cpu->pir); + return rc; + } + /* Check timeout */ + if (mftb() > poll_target) + break; + } + + /* Success ? */ + if (val & EX_PM_GP0_SPECIAL_WAKEUP_DONE) { + uint64_t now = mftb(); + prlog(PR_TRACE, "RESET: Special wakeup complete after %ld us\n", + tb_to_usecs(now - stamp)); + return 0; + } + + /* + * We timed out ... + * + * HWP has a complex workaround for HW255321 which affects + * Murano DD1 and Venice DD1. Ignore that for now + * + * Instead we just dump some XSCOMs for error logging + */ + prerror("RESET: Timeout on special wakeup of 0x%0x\n", cpu->pir); + prerror("RESET: PM0 = 0x%016llx\n", val); + val = -1; + xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), + &val); + prerror("RESET: SPC_WKUP = 0x%016llx\n", val); + val = -1; + xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, + EX_PM_IDLE_STATE_HISTORY_PHYP), + &val); + prerror("RESET: HISTORY = 0x%016llx\n", val); + + return OPAL_HARDWARE; +} + +static int p8_clr_special_wakeup(struct cpu_thread *cpu) +{ + uint64_t val; + uint32_t core_id; + int rc; + + /* + * Note: HWP checks for checkstops, but I assume we don't need to + * as we wouldn't be running if one was present + */ + + /* Grab core ID once */ + core_id = pir_to_core_id(cpu->pir); + + prlog(PR_DEBUG, "RESET: Releasing core 0x%x wakeup\n", core_id); + + /* + * The original HWp reads the XSCOM first but ignores the result + * and error, let's do the same until I know for sure that is + * not necessary + */ + xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), + &val); + + /* Then we write special wakeup */ + rc = xscom_write(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, + EX_PM_SPECIAL_WAKEUP_PHYP), 0); + if (rc) { + prerror("RESET: XSCOM error %d deasserting" + " special wakeup on 0x%x\n", rc, cpu->pir); + return rc; + } + + /* + * The original HWp reads the XSCOM again with the comment + * "This puts an inherent delay in the propagation of the reset + * transition" + */ + xscom_read(cpu->chip_id, + XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), + &val); + + return 0; +} + +static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) +{ + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t xscom_addr; + + xscom_addr = XSCOM_ADDR_P8_EX(core_id, + P8_EX_TCTL_DIRECT_CONTROLS(thread_id)); + + xscom_write(chip_id, xscom_addr, bits); +} + +static int p8_sreset_all_prepare(void) +{ + struct cpu_thread *cpu; + + prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", + this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); + + /* Assert special wakup on all cores. Only on operational cores. */ + for_each_ungarded_primary(cpu) { + if (p8_set_special_wakeup(cpu) != OPAL_SUCCESS) + return OPAL_HARDWARE; + } + + prlog(PR_DEBUG, "RESET: Stopping the world...\n"); + + /* Put everybody in stop except myself */ + for_each_ungarded_cpu(cpu) { + if (cpu != this_cpu()) + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); + } + + return OPAL_SUCCESS; +} + +static void p8_sreset_all_finish(void) +{ + struct cpu_thread *cpu; + + for_each_ungarded_primary(cpu) + p8_clr_special_wakeup(cpu); +} + +static void p8_sreset_all_others(void) +{ + struct cpu_thread *cpu; + + prlog(PR_DEBUG, "RESET: Pre-napping all threads but one...\n"); + + /* Put everybody in pre-nap except myself */ + for_each_ungarded_cpu(cpu) { + if (cpu != this_cpu()) + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); + } + + prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); + + /* Reset everybody except my own core threads */ + for_each_ungarded_cpu(cpu) { + if (cpu != this_cpu()) + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); + } +} + +int sreset_all_prepare(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return OPAL_SUCCESS; + + if (proc_gen == proc_gen_p8) + return p8_sreset_all_prepare(); + + return OPAL_UNSUPPORTED; +} + +void sreset_all_finish(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return; + + if (proc_gen == proc_gen_p8) + return p8_sreset_all_finish(); +} + +int sreset_all_others(void) +{ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { + struct cpu_thread *cpu; + + for_each_ungarded_cpu(cpu) + mambo_sreset_cpu(cpu); + + return OPAL_SUCCESS; + } + + if (proc_gen == proc_gen_p8) { + p8_sreset_all_others(); + return OPAL_SUCCESS; + } + + return OPAL_UNSUPPORTED; +} + + +/**************** POWER9 direct controls ****************/ + #define P9_RAS_STATUS 0x10a02 #define P9_THREAD_QUIESCED(t) PPC_BITMASK(0 + 8*(t), 3 + 8*(t)) #define P9_QUIESCE_RETRIES 100 diff --git a/core/fast-reboot.c b/core/fast-reboot.c index fe9ab8e2a..f9ed697db 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -27,293 +27,13 @@ #include #include #include - -#define P8_EX_TCTL_DIRECT_CONTROLS(t) (0x10013000 + (t) * 0x10) -#define P8_DIRECT_CTL_STOP PPC_BIT(63) -#define P8_DIRECT_CTL_PRENAP PPC_BIT(47) -#define P8_DIRECT_CTL_SRESET PPC_BIT(60) - +#include /* Flag tested by the OPAL entry code */ uint8_t reboot_in_progress; static volatile bool fast_boot_release; static struct lock reset_lock = LOCK_UNLOCKED; -static int p8_set_special_wakeup(struct cpu_thread *cpu) -{ - uint64_t val, poll_target, stamp; - uint32_t core_id; - int rc; - - /* - * Note: HWP checks for checkstops, but I assume we don't need to - * as we wouldn't be running if one was present - */ - - /* Grab core ID once */ - core_id = pir_to_core_id(cpu->pir); - - prlog(PR_DEBUG, "RESET Waking up core 0x%x\n", core_id); - - /* - * The original HWp reads the XSCOM first but ignores the result - * and error, let's do the same until I know for sure that is - * not necessary - */ - xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), - &val); - - /* Then we write special wakeup */ - rc = xscom_write(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, - EX_PM_SPECIAL_WAKEUP_PHYP), - PPC_BIT(0)); - if (rc) { - prerror("RESET: XSCOM error %d asserting special" - " wakeup on 0x%x\n", rc, cpu->pir); - return rc; - } - - /* - * HWP uses the history for Perf register here, dunno why it uses - * that one instead of the pHyp one, maybe to avoid clobbering it... - * - * In any case, it does that to check for run/nap vs.sleep/winkle/other - * to decide whether to poll on checkstop or not. Since we don't deal - * with checkstop conditions here, we ignore that part. - */ - - /* - * Now poll for completion of special wakeup. The HWP is nasty here, - * it will poll at 5ms intervals for up to 200ms. This is not quite - * acceptable for us at runtime, at least not until we have the - * ability to "context switch" HBRT. In practice, because we don't - * winkle, it will never take that long, so we increase the polling - * frequency to 1us per poll. However we do have to keep the same - * timeout. - * - * We don't use time_wait_ms() either for now as we don't want to - * poll the FSP here. - */ - stamp = mftb(); - poll_target = stamp + msecs_to_tb(200); - val = 0; - while (!(val & EX_PM_GP0_SPECIAL_WAKEUP_DONE)) { - /* Wait 1 us */ - time_wait_us(1); - - /* Read PM state */ - rc = xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_GP0), - &val); - if (rc) { - prerror("RESET: XSCOM error %d reading PM state on" - " 0x%x\n", rc, cpu->pir); - return rc; - } - /* Check timeout */ - if (mftb() > poll_target) - break; - } - - /* Success ? */ - if (val & EX_PM_GP0_SPECIAL_WAKEUP_DONE) { - uint64_t now = mftb(); - prlog(PR_TRACE, "RESET: Special wakeup complete after %ld us\n", - tb_to_usecs(now - stamp)); - return 0; - } - - /* - * We timed out ... - * - * HWP has a complex workaround for HW255321 which affects - * Murano DD1 and Venice DD1. Ignore that for now - * - * Instead we just dump some XSCOMs for error logging - */ - prerror("RESET: Timeout on special wakeup of 0x%0x\n", cpu->pir); - prerror("RESET: PM0 = 0x%016llx\n", val); - val = -1; - xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), - &val); - prerror("RESET: SPC_WKUP = 0x%016llx\n", val); - val = -1; - xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, - EX_PM_IDLE_STATE_HISTORY_PHYP), - &val); - prerror("RESET: HISTORY = 0x%016llx\n", val); - - return OPAL_HARDWARE; -} - -static int p8_clr_special_wakeup(struct cpu_thread *cpu) -{ - uint64_t val; - uint32_t core_id; - int rc; - - /* - * Note: HWP checks for checkstops, but I assume we don't need to - * as we wouldn't be running if one was present - */ - - /* Grab core ID once */ - core_id = pir_to_core_id(cpu->pir); - - prlog(PR_DEBUG, "RESET: Releasing core 0x%x wakeup\n", core_id); - - /* - * The original HWp reads the XSCOM first but ignores the result - * and error, let's do the same until I know for sure that is - * not necessary - */ - xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), - &val); - - /* Then we write special wakeup */ - rc = xscom_write(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, - EX_PM_SPECIAL_WAKEUP_PHYP), 0); - if (rc) { - prerror("RESET: XSCOM error %d deasserting" - " special wakeup on 0x%x\n", rc, cpu->pir); - return rc; - } - - /* - * The original HWp reads the XSCOM again with the comment - * "This puts an inherent delay in the propagation of the reset - * transition" - */ - xscom_read(cpu->chip_id, - XSCOM_ADDR_P8_EX_SLAVE(core_id, EX_PM_SPECIAL_WAKEUP_PHYP), - &val); - - return 0; -} - -static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) -{ - uint32_t core_id = pir_to_core_id(cpu->pir); - uint32_t chip_id = pir_to_chip_id(cpu->pir); - uint32_t thread_id = pir_to_thread_id(cpu->pir); - uint32_t xscom_addr; - - xscom_addr = XSCOM_ADDR_P8_EX(core_id, - P8_EX_TCTL_DIRECT_CONTROLS(thread_id)); - - xscom_write(chip_id, xscom_addr, bits); -} - -static int p8_sreset_all_prepare(void) -{ - struct cpu_thread *cpu; - - prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", - this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); - - /* Assert special wakup on all cores. Only on operational cores. */ - for_each_ungarded_primary(cpu) { - if (p8_set_special_wakeup(cpu) != OPAL_SUCCESS) - return OPAL_HARDWARE; - } - - prlog(PR_DEBUG, "RESET: Stopping the world...\n"); - - /* Put everybody in stop except myself */ - for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); - } - - return OPAL_SUCCESS; -} - -static void p8_sreset_all_finish(void) -{ - struct cpu_thread *cpu; - - for_each_ungarded_primary(cpu) - p8_clr_special_wakeup(cpu); -} - -static void p8_sreset_all_others(void) -{ - struct cpu_thread *cpu; - - prlog(PR_DEBUG, "RESET: Pre-napping all threads but one...\n"); - - /* Put everybody in pre-nap except myself */ - for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); - } - - prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); - - /* Reset everybody except my own core threads */ - for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); - } -} - -extern unsigned long callthru_tcl(const char *str, int len); - -static void mambo_sreset_cpu(struct cpu_thread *cpu) -{ - uint32_t core_id = pir_to_core_id(cpu->pir); - uint32_t thread_id = pir_to_thread_id(cpu->pir); - char tcl_cmd[50]; - - snprintf(tcl_cmd, sizeof(tcl_cmd), "mysim cpu %i:%i set spr pc 0x100", core_id, thread_id); - callthru_tcl(tcl_cmd, strlen(tcl_cmd)); -} - -static int sreset_all_prepare(void) -{ - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return OPAL_SUCCESS; - - if (proc_gen == proc_gen_p8) - return p8_sreset_all_prepare(); - - return OPAL_UNSUPPORTED; -} - -static void sreset_all_finish(void) -{ - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return; - - if (proc_gen == proc_gen_p8) - return p8_sreset_all_finish(); -} - -static int sreset_all_others(void) -{ - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { - struct cpu_thread *cpu; - - for_each_ungarded_cpu(cpu) - mambo_sreset_cpu(cpu); - - return OPAL_SUCCESS; - } - - if (proc_gen == proc_gen_p8) { - p8_sreset_all_others(); - return OPAL_SUCCESS; - } - - return OPAL_UNSUPPORTED; -} - static bool cpu_state_wait_all_others(enum cpu_thread_state state, unsigned long timeout_tb) { diff --git a/include/direct-controls.h b/include/direct-controls.h new file mode 100644 index 000000000..9df154902 --- /dev/null +++ b/include/direct-controls.h @@ -0,0 +1,29 @@ +/* Copyright 2017 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DIRECT_CONTROLS_H +#define __DIRECT_CONTROLS_H + +#include +#include +#include + +/* fast reboot APIs */ +extern int sreset_all_prepare(void); +extern int sreset_all_others(void); +extern void sreset_all_finish(void); + +#endif /* __DIRECT_CONTROLS_H */ From patchwork Fri Nov 24 14:08:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjynj2GL8z9s8J for ; Sat, 25 Nov 2017 01:12:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="caDNXUd1"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjynj15dfzDsFf for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:28 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:24 +1000 Message-Id: <20171124140834.7099-16-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 15/25] direct-controls: change p8_sreset_all_others sequence X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Change the p8_sreset_all_others sequence from prenap all, sreset all; to prenap, sreset all. This makes it more suitable to fit the direct controls APIs, which does not expose "prenap". Signed-off-by: Nicholas Piggin --- core/direct-controls.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 1be80c4bb..f3f61fbd5 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -251,20 +251,15 @@ static void p8_sreset_all_others(void) { struct cpu_thread *cpu; - prlog(PR_DEBUG, "RESET: Pre-napping all threads but one...\n"); - - /* Put everybody in pre-nap except myself */ - for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); - } - prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); /* Reset everybody except my own core threads */ for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); + if (cpu == this_cpu()) + continue; + + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); } } From patchwork Fri Nov 24 14:08:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjynx2wP3z9s8J for ; Sat, 25 Nov 2017 01:12:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tNG4wg3e"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjynx1dhwzDsGL for ; Sat, 25 Nov 2017 01:12:53 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tNG4wg3e"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tNG4wg3e"; dkim-atps=neutral Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyk60YkGzDrnw for ; Sat, 25 Nov 2017 01:09:34 +1100 (AEDT) Received: by mail-pl0-x243.google.com with SMTP id u14so4517412plm.8 for ; Fri, 24 Nov 2017 06:09:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tUMtO0t6VnXpS+T3aZfLoC1Qh4U1ujS0KaHrqMW7C7A=; b=tNG4wg3ePQeJE2wGLwIV7ple4gttTv8XhrI9We+ivkpOW5wMXlyG4KPta8r5bcVabX R/HG1tqYSGgDeq1JnZ4iVRWyPd1HsVFUL+2i9lWLs+YH7yUQ4JseJapnI01k55RurMI3 6vJIQduIG4RP9OuHIv+aJUEEdbSyye7FGqjEiE/rTrSFSuYINAhnzzoTsD8ZPMrKbYBF KlObD2jHP7RdgR2nmFnaIYujBHxlSp3BECneOcrzxxJTrIY6aNW+q8BXi3+ifbZfgaNl rXnCxe5BoBpKgHZSQn2DzBZ+lc0nxrJ7YVSJYFsffuF9kp+L2cz7Fj4S4+J8UV5F+ie5 4O5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tUMtO0t6VnXpS+T3aZfLoC1Qh4U1ujS0KaHrqMW7C7A=; b=Fe6Z93k4cWiXQqnLvDjzjApG7G99zNgVrBdkSigtjZOn50IVIBXwA5n3NQ3xsLh370 zlwSru62d5ObHyRE8NSXOBCr3jafhtOgEQupffr1Qf76bCYMf09JmOFaQ3hKN3gVEbAP 5Kw1y2aZhzdxN0/g2UlfIDPpFx3UYTkeOAanqUJlakc8kie0h1yLzhqkXDg1q+ncc0W0 YAeA0xAzTtI2tW3gzISykjzBUHhD0DAqcx4SbguwzBCRYdrS5jcuOPUI7RpLj4FHQn3E kUze8ZZKY9VVcCGChv0aYXBl/rIOc56p/9BOZ1xmQFrjWg4hbdkaF5QfKBH8xscKmadi DM4g== X-Gm-Message-State: AJaThX7gaIft9Ggca5aILkmNKXAwZ6scz3UXi60PloVGtncAah5YTi1q 3SoMzWz/ki0TG+mzJ14lDRBkow== X-Google-Smtp-Source: AGs4zMaK+RciYs0BeU0+i9PmUrMboqe6FgTb16Fk0Y1U8B8L3bugpzjDLcTkU4lWVNbnMvHmYaN9GA== X-Received: by 10.159.198.70 with SMTP id y6mr12684891plt.334.1511532571971; Fri, 24 Nov 2017 06:09:31 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:31 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:25 +1000 Message-Id: <20171124140834.7099-17-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 16/25] direct-controls: p8 implementation of generic direct controls X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This reworks the sreset functionality that was brought over from fast-reboot, and fits it under the generic direct controls APIs. The fast reboot APIs are implemented using generic direct controls, which also makes them available on p9. Signed-off-by: Nicholas Piggin --- core/direct-controls.c | 207 ++++++++++++++++++++++++++++--------------------- 1 file changed, 117 insertions(+), 90 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index f3f61fbd5..464639921 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -44,7 +44,7 @@ static void mambo_sreset_cpu(struct cpu_thread *cpu) #define P8_DIRECT_CTL_PRENAP PPC_BIT(47) #define P8_DIRECT_CTL_SRESET PPC_BIT(60) -static int p8_set_special_wakeup(struct cpu_thread *cpu) +static int p8_core_set_special_wakeup(struct cpu_thread *cpu) { uint64_t val, poll_target, stamp; uint32_t core_id; @@ -155,7 +155,7 @@ static int p8_set_special_wakeup(struct cpu_thread *cpu) return OPAL_HARDWARE; } -static int p8_clr_special_wakeup(struct cpu_thread *cpu) +static int p8_core_clear_special_wakeup(struct cpu_thread *cpu) { uint64_t val; uint32_t core_id; @@ -215,91 +215,19 @@ static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) xscom_write(chip_id, xscom_addr, bits); } -static int p8_sreset_all_prepare(void) +static int p8_stop_thread(struct cpu_thread *cpu) { - struct cpu_thread *cpu; - - prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", - this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); - - /* Assert special wakup on all cores. Only on operational cores. */ - for_each_ungarded_primary(cpu) { - if (p8_set_special_wakeup(cpu) != OPAL_SUCCESS) - return OPAL_HARDWARE; - } - - prlog(PR_DEBUG, "RESET: Stopping the world...\n"); - - /* Put everybody in stop except myself */ - for_each_ungarded_cpu(cpu) { - if (cpu != this_cpu()) - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); - } + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); return OPAL_SUCCESS; } -static void p8_sreset_all_finish(void) -{ - struct cpu_thread *cpu; - - for_each_ungarded_primary(cpu) - p8_clr_special_wakeup(cpu); -} - -static void p8_sreset_all_others(void) -{ - struct cpu_thread *cpu; - - prlog(PR_DEBUG, "RESET: Resetting all threads but one...\n"); - - /* Reset everybody except my own core threads */ - for_each_ungarded_cpu(cpu) { - if (cpu == this_cpu()) - continue; - - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); - } -} - -int sreset_all_prepare(void) -{ - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return OPAL_SUCCESS; - - if (proc_gen == proc_gen_p8) - return p8_sreset_all_prepare(); - - return OPAL_UNSUPPORTED; -} - -void sreset_all_finish(void) +static int p8_sreset_thread(struct cpu_thread *cpu) { - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) - return; - - if (proc_gen == proc_gen_p8) - return p8_sreset_all_finish(); -} - -int sreset_all_others(void) -{ - if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { - struct cpu_thread *cpu; - - for_each_ungarded_cpu(cpu) - mambo_sreset_cpu(cpu); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); + p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); - return OPAL_SUCCESS; - } - - if (proc_gen == proc_gen_p8) { - p8_sreset_all_others(); - return OPAL_SUCCESS; - } - - return OPAL_UNSUPPORTED; + return OPAL_SUCCESS; } @@ -526,17 +454,23 @@ static int p9_sreset_thread(struct cpu_thread *cpu) return 0; } +/**************** generic direct controls ****************/ + int dctl_set_special_wakeup(struct cpu_thread *t) { struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); - if (c->special_wakeup_count == 0) - rc = p9_core_set_special_wakeup(c); + if (c->special_wakeup_count == 0) { + if (proc_gen == proc_gen_p9) + rc = p9_core_set_special_wakeup(c); + else /* (proc_gen == proc_gen_p8) */ + rc = p8_core_set_special_wakeup(c); + } if (!rc) c->special_wakeup_count++; unlock(&c->dctl_lock); @@ -549,14 +483,18 @@ int dctl_clear_special_wakeup(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); if (!c->special_wakeup_count) goto out; - if (c->special_wakeup_count == 1) - rc = p9_core_clear_special_wakeup(c); + if (c->special_wakeup_count == 1) { + if (proc_gen == proc_gen_p9) + rc = p9_core_clear_special_wakeup(c); + else /* (proc_gen == proc_gen_p8) */ + rc = p8_core_clear_special_wakeup(c); + } if (!rc) c->special_wakeup_count--; out: @@ -573,6 +511,9 @@ int dctl_core_is_gated(struct cpu_thread *t) uint32_t sshhyp_addr; uint64_t val; + if (proc_gen != proc_gen_p9) + return OPAL_UNSUPPORTED; + sshhyp_addr = XSCOM_ADDR_P9_EC_SLAVE(core_id, P9_EC_PPM_SSHHYP); if (xscom_read(chip_id, sshhyp_addr, &val)) { @@ -590,7 +531,7 @@ static int dctl_stop(struct cpu_thread *t) struct cpu_thread *c = t->primary; int rc; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); @@ -598,7 +539,10 @@ static int dctl_stop(struct cpu_thread *t) unlock(&c->dctl_lock); return OPAL_BUSY; } - rc = p9_stop_thread(t); + if (proc_gen == proc_gen_p9) + rc = p9_stop_thread(t); + else /* (proc_gen == proc_gen_p8) */ + rc = p8_stop_thread(t); if (!rc) t->dctl_stopped = true; unlock(&c->dctl_lock); @@ -627,12 +571,18 @@ static int dctl_cont(struct cpu_thread *t) return rc; } +/* + * NOTE: + * The POWER8 sreset does not provide SRR registers, so it can be used + * for fast reboot, but not OPAL_SIGNAL_SYSTEM_RESET or anywhere that is + * expected to return. For now, callers beware. + */ static int dctl_sreset(struct cpu_thread *t) { struct cpu_thread *c = t->primary; int rc; - if (proc_gen != proc_gen_p9) + if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) return OPAL_UNSUPPORTED; lock(&c->dctl_lock); @@ -640,7 +590,10 @@ static int dctl_sreset(struct cpu_thread *t) unlock(&c->dctl_lock); return OPAL_BUSY; } - rc = p9_sreset_thread(t); + if (proc_gen == proc_gen_p9) + rc = p9_sreset_thread(t); + else /* (proc_gen == proc_gen_p8) */ + rc = p8_sreset_thread(t); if (!rc) t->dctl_stopped = false; unlock(&c->dctl_lock); @@ -648,6 +601,80 @@ static int dctl_sreset(struct cpu_thread *t) return rc; } + +/**************** fast reboot API ****************/ + +int sreset_all_prepare(void) +{ + struct cpu_thread *cpu; + + prlog(PR_DEBUG, "RESET: Resetting from cpu: 0x%x (core 0x%x)\n", + this_cpu()->pir, pir_to_core_id(this_cpu()->pir)); + + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return OPAL_SUCCESS; + + /* Assert special wakup on all cores. Only on operational cores. */ + for_each_ungarded_primary(cpu) { + if (dctl_set_special_wakeup(cpu) != OPAL_SUCCESS) + return OPAL_HARDWARE; + } + + prlog(PR_DEBUG, "RESET: Stopping the world...\n"); + + /* Put everybody in stop except myself */ + for_each_ungarded_cpu(cpu) { + if (cpu == this_cpu()) + continue; + if (dctl_stop(cpu) != OPAL_SUCCESS) + return OPAL_HARDWARE; + + } + + return OPAL_SUCCESS; +} + +void sreset_all_finish(void) +{ + struct cpu_thread *cpu; + + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return; + + for_each_ungarded_primary(cpu) + dctl_clear_special_wakeup(cpu); +} + +int sreset_all_others(void) +{ + struct cpu_thread *cpu; + + prlog(PR_DEBUG, "RESET: Resetting all threads but self...\n"); + + /* + * mambo should actually implement stop as well, and implement + * the dctl_ helpers properly. Currently it's racy just sresetting. + */ + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) { + for_each_ungarded_cpu(cpu) + mambo_sreset_cpu(cpu); + + return OPAL_SUCCESS; + } + + for_each_ungarded_cpu(cpu) { + if (cpu == this_cpu()) + continue; + if (dctl_sreset(cpu) != OPAL_SUCCESS) + return OPAL_HARDWARE; + } + + return OPAL_SUCCESS; +} + + +/**************** OPAL_SIGNAL_SYSTEM_RESET API ****************/ + /* * This provides a way for the host to raise system reset exceptions * on other threads using direct control scoms on POWER9. From patchwork Fri Nov 24 14:08:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjypD0vCZz9s8J for ; Sat, 25 Nov 2017 01:13:08 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="feSo1jkF"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjypC6nfzzDsFT for ; Sat, 25 Nov 2017 01:13:07 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="feSo1jkF"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="feSo1jkF"; dkim-atps=neutral Received: from mail-pf0-x243.google.com (mail-pf0-x243.google.com [IPv6:2607:f8b0:400e:c00::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjyk971w7zDrbq for ; Sat, 25 Nov 2017 01:09:37 +1100 (AEDT) Received: by mail-pf0-x243.google.com with SMTP id m88so14873087pfi.9 for ; Fri, 24 Nov 2017 06:09:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZliKMUP0/0OZ/14z7+9q/1OKj8t0jyLnlMK/eOAJRtk=; b=feSo1jkFzBwzL434yPxcHc0hGVce9QRPi3Ae435iqY4xvtxVWd9mSqnmQyI5b8lVYe EnFwLy0nXpn+lnSFKd+zRx+Iy/dOfZJLBT8YzhdgChXbZPsbofsoBhLr1Lzs5TSowUdd Zks0O0nG1OHRGARNXX8LRJXHfLxhAL7/YXgIWx0ZcscE0c+arZYKcgEmHbhCoe8bgb28 OrQN/E7BtftdWH+H5JQJ78fxEKAMNNAHLFR8IQJI6xENA2xgCxVHmQ8P1J5ZWzX/6i47 +ou2j7LB6WsRPNAjTYFPGTFiYKUcD9jUi7/NeSvURaGAGDxOJUZdzfu7600zBvHjzasL omCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZliKMUP0/0OZ/14z7+9q/1OKj8t0jyLnlMK/eOAJRtk=; b=Vc/gwTVrFe2FDvyxznPj4Hy2a/wZoXEfH3lZOaPLS9Z0UyfkUp4zwu651hWDnVIfQo h2rfgA1Qroh6gf5gziNkBgV8792SJo3gkwIi8soZ2mMNyDmRZtPXmY4r7f3GO2ASs1B2 Xy1VYpb+MkCD78xN7ihZxkP4R9nLB83s8I/ZuwZV48hn4KcCKgISNzxUDRteuyrnKkDc oGPsnVJAQ3ArVtgjLryQocIMef5OnJlZHxjSopO4bKKMgyq0zivTcBKwBxqU4CMkEj0R iLdBahnClmxSII5lGLjteKTwLYDJ+dNiacVuUET2Yu90z8JifT+Kj5zjrF7YqxHGjjbB mf2g== X-Gm-Message-State: AJaThX6kUTZwUHM91pHpbk7W8ML527RQnoo3OpmX19NpJxM3VI8pHd5W EatbcWltVTzMvcM3hrCuZm9TtQ== X-Google-Smtp-Source: AGs4zMbZ+o29ARC6wt60AW6Bw5Tr5EcomPlE6NpBmIovbPaxNX/B6g8Zxh+XVJ4qAtV9gUV+xdFgMA== X-Received: by 10.98.34.85 with SMTP id i82mr4357758pfi.57.1511532574864; Fri, 24 Nov 2017 06:09:34 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:33 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:26 +1000 Message-Id: <20171124140834.7099-18-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 17/25] direct-controls: add xscom error handling for p8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add xscom checks which will print something useful and return error back to callers (which already have error handling plumbed in). Signed-off-by: Nicholas Piggin --- core/direct-controls.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 464639921..ed105b81c 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -202,7 +202,7 @@ static int p8_core_clear_special_wakeup(struct cpu_thread *cpu) return 0; } -static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) +static int p8_stop_thread(struct cpu_thread *cpu) { uint32_t core_id = pir_to_core_id(cpu->pir); uint32_t chip_id = pir_to_chip_id(cpu->pir); @@ -212,20 +212,38 @@ static void p8_set_direct_ctl(struct cpu_thread *cpu, uint64_t bits) xscom_addr = XSCOM_ADDR_P8_EX(core_id, P8_EX_TCTL_DIRECT_CONTROLS(thread_id)); - xscom_write(chip_id, xscom_addr, bits); -} - -static int p8_stop_thread(struct cpu_thread *cpu) -{ - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_STOP); + if (xscom_write(chip_id, xscom_addr, P8_DIRECT_CTL_STOP)) { + prlog(PR_ERR, "Could not stop thread %u:%u:%u:" + " Unable to write EX_TCTL_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } return OPAL_SUCCESS; } static int p8_sreset_thread(struct cpu_thread *cpu) { - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_PRENAP); - p8_set_direct_ctl(cpu, P8_DIRECT_CTL_SRESET); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t xscom_addr; + + xscom_addr = XSCOM_ADDR_P8_EX(core_id, + P8_EX_TCTL_DIRECT_CONTROLS(thread_id)); + + if (xscom_write(chip_id, xscom_addr, P8_DIRECT_CTL_PRENAP)) { + prlog(PR_ERR, "Could not prenap thread %u:%u:%u:" + " Unable to write EX_TCTL_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } + if (xscom_write(chip_id, xscom_addr, P8_DIRECT_CTL_SRESET)) { + prlog(PR_ERR, "Could not sreset thread %u:%u:%u:" + " Unable to write EX_TCTL_DIRECT_CONTROLS.\n", + chip_id, core_id, thread_id); + return OPAL_HARDWARE; + } return OPAL_SUCCESS; } From patchwork Fri Nov 24 14:08:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjypS2dSTz9s8J for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:36 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:27 +1000 Message-Id: <20171124140834.7099-19-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 18/25] core/lock: Introduce atomic cmpxchg and implement try_lock with it X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" cmpxchg will be used in a subsequent change, and this reduces the amount of asm code. Signed-off-by: Nicholas Piggin --- asm/Makefile.inc | 2 +- asm/lock.S | 43 ----------------------------------------- core/lock.c | 26 +++++++++++++++++++++---- include/lock.h | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 79 insertions(+), 50 deletions(-) delete mode 100644 asm/lock.S diff --git a/asm/Makefile.inc b/asm/Makefile.inc index 2e678fd86..34e2b2883 100644 --- a/asm/Makefile.inc +++ b/asm/Makefile.inc @@ -1,7 +1,7 @@ # -*-Makefile-*- SUBDIRS += asm -ASM_OBJS = head.o lock.o misc.o kernel-wrapper.o rom_entry.o +ASM_OBJS = head.o misc.o kernel-wrapper.o rom_entry.o ASM=asm/built-in.o # Add extra dependency to the kernel wrapper diff --git a/asm/lock.S b/asm/lock.S deleted file mode 100644 index ce28010fe..000000000 --- a/asm/lock.S +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2013-2014 IBM Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - * implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include - - .section ".text","ax" - .balign 0x10 - - /* bool try_lock(struct lock *lock) */ -.global __try_lock -__try_lock: - ld %r0,0(%r3) - andi. %r10,%r0,1 - bne 2f - lwz %r9,CPUTHREAD_PIR(%r13) -1: ldarx %r0,0,%r3 - andi. %r10,%r0,1 - bne- 2f - ori %r0,%r0,1 - rldimi %r0,%r9,32,0 - stdcx. %r0,0,%r3 - bne 1b - sync - li %r3,-1 - blr -2: li %r3,0 - blr - diff --git a/core/lock.c b/core/lock.c index 0868f2ba2..916a02412 100644 --- a/core/lock.c +++ b/core/lock.c @@ -33,7 +33,7 @@ static void lock_error(struct lock *l, const char *reason, uint16_t err) { bust_locks = true; - fprintf(stderr, "LOCK ERROR: %s @%p (state: 0x%016lx)\n", + fprintf(stderr, "LOCK ERROR: %s @%p (state: 0x%016llx)\n", reason, l, l->lock_val); op_display(OP_FATAL, OP_MOD_LOCK, err); @@ -73,12 +73,30 @@ bool lock_held_by_me(struct lock *l) return l->lock_val == ((pir64 << 32) | 1); } +static inline bool __try_lock(struct cpu_thread *cpu, struct lock *l) +{ + uint64_t val; + + val = cpu->pir; + val <<= 32; + val |= 1; + + barrier(); + if (__cmpxchg64(&l->lock_val, 0, val) == 0) { + sync(); + return true; + } + return false; +} + bool try_lock(struct lock *l) { - if (__try_lock(l)) { + struct cpu_thread *cpu = this_cpu(); + + if (__try_lock(cpu, l)) { if (l->in_con_path) - this_cpu()->con_suspend++; - this_cpu()->lock_depth++; + cpu->con_suspend++; + cpu->lock_depth++; return true; } return false; diff --git a/include/lock.h b/include/lock.h index 0ac943dc9..1597f4224 100644 --- a/include/lock.h +++ b/include/lock.h @@ -18,12 +18,13 @@ #define __LOCK_H #include +#include struct lock { /* Lock value has bit 63 as lock bit and the PIR of the owner * in the top 32-bit */ - unsigned long lock_val; + uint64_t lock_val; /* * Set to true if lock is involved in the console flush path @@ -63,7 +64,60 @@ static inline void init_lock(struct lock *l) *l = (struct lock)LOCK_UNLOCKED; } -extern bool __try_lock(struct lock *l); +/* + * Bare cmpxchg, no barriers. + */ +static inline uint32_t __cmpxchg32(uint32_t *mem, uint32_t old, uint32_t new) +{ + uint32_t prev; + + asm volatile( + "# __cmpxchg32 \n" + "1: lwarx %0,0,%2 \n" + " cmpw %0,%3 \n" + " bne- 2f \n" + " stwcx. %4,0,%2 \n" + " bne- 1b \n" + "2: \n" + + : "=&r"(prev), "+m"(*mem) + : "r"(mem), "r"(old), "r"(new) + : "cr0"); + + return prev; +} + +static inline uint64_t __cmpxchg64(uint64_t *mem, uint64_t old, uint64_t new) +{ + uint64_t prev; + + asm volatile( + "# __cmpxchg64 \n" + "1: ldarx %0,0,%2 \n" + " cmpd %0,%3 \n" + " bne- 2f \n" + " stdcx. %4,0,%2 \n" + " bne- 1b \n" + "2: \n" + + : "=&r"(prev), "+m"(*mem) + : "r"(mem), "r"(old), "r"(new) + : "cr0"); + + return prev; +} + +static inline uint32_t cmpxchg32(uint32_t *mem, uint32_t old, uint32_t new) +{ + uint32_t prev; + + sync(); + prev = __cmpxchg32(mem, old,new); + sync(); + + return prev; +} + extern bool try_lock(struct lock *l); extern void lock(struct lock *l); extern void unlock(struct lock *l); From patchwork Fri Nov 24 14:08:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjypj01M4z9s8J for ; Sat, 25 Nov 2017 01:13:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KbtSfW/t"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyph5vn3zDsMB for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:39 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:28 +1000 Message-Id: <20171124140834.7099-20-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 19/25] core/lock: improve bust_locks X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Prevent try_lock from modifying the lock state when bust_locks is set. unlock will not unlock it in that case, so locks will get taken and never released while bust_locks is set. Signed-off-by: Nicholas Piggin --- core/lock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/core/lock.c b/core/lock.c index 916a02412..b5e3323f2 100644 --- a/core/lock.c +++ b/core/lock.c @@ -93,6 +93,9 @@ bool try_lock(struct lock *l) { struct cpu_thread *cpu = this_cpu(); + if (bust_locks) + return true; + if (__try_lock(cpu, l)) { if (l->in_con_path) cpu->con_suspend++; From patchwork Fri Nov 24 14:08:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjypx0M8Mz9s8J for ; Sat, 25 Nov 2017 01:13:45 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SfHuXWKI"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjypw69f3zDrp7 for ; Sat, 25 Nov 2017 01:13:44 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SfHuXWKI"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::243; helo=mail-pg0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SfHuXWKI"; dkim-atps=neutral Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjykK3WbCzDrnp for ; Sat, 25 Nov 2017 01:09:45 +1100 (AEDT) Received: by mail-pg0-x243.google.com with SMTP id s75so15409206pgs.0 for ; Fri, 24 Nov 2017 06:09:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T2vU+y1TBIqHpYvwRqHkFIyrmEQqOmw2W9i83DHGkjc=; b=SfHuXWKI6+kYFr5dt+Al9+FQVYElt56cVmSzHDJfjdey1Vsg48fIlprRawFM3JgZHF Vc1mWrWu4t2kXi4hgqvDMtpNrTFziV+rPCmNypbcdBYFGlekFNZHTPLmq8BQ2R7qL0Kk US2On29gV/Hq0vXTiOHvn87dile/Dfdm7rFFpvSKDSeYA2sFUtGSIjyRQzerSbM+dgtp K9Q++mrG8EEQYnAJW81Kabj8ocdfpvhLPzsJF9atXyki+2RZOAz+0/FHK1qlhRy0iZIg HOX6PcvjanPBda9RfBrNst0hb7YahPKcdPaTlV3WMf3EKHjdI1a5gbWVVtl8INLaJCCh QmEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T2vU+y1TBIqHpYvwRqHkFIyrmEQqOmw2W9i83DHGkjc=; b=iQotigKD2a/Fw8w1AVJ+vte8ugYa8N5UTPgyrmPxgM9U3PM87L5XFrwz90GSkAFD95 b/NWGdHeitJ1IQ9GL7rhQxAsPoW6bOwOktST56V1u4TFAltfZa2j6+6McN9jBuMZSeIl yfvCdSadnYJ1ppay01d3gX+JwDUV7HDAwyflFxz377T0VSbIzQhi57jX87lSUBJBtnbo 4VkWT9B2KriH416FN04VPlWZ02wKFCVXyyUwePAbGquI1drmxa7qbZ0BKdjGweNYKBG4 MTLyPPEMGUvlPdmASQr10KYR4/jFC09BeF3u/zeGVLQToOQYRA0IPtIYBfbt2HsBBpEn prdg== X-Gm-Message-State: AJaThX7g15siwMqlxZr1n0ODU8KBe24ahrY/UNU4zakEIR1OU1+zhARW 6PxXazWLC7s5DE0y06kXawfZiw== X-Google-Smtp-Source: AGs4zMbbMAdU4gEy0M5VMQRJAJe8KLHpMW6R4h1HyN8Llmw1N3NqWgkE/IZbTfn9AsWefyqE4MBm6A== X-Received: by 10.99.144.68 with SMTP id a65mr29089113pge.429.1511532583416; Fri, 24 Nov 2017 06:09:43 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:42 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:29 +1000 Message-Id: <20171124140834.7099-21-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 20/25] asm/head: add entry/exit calls X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add entry and exit C functions that can do some more complex checks before the opal proper call. This requires saving off volatile registers that have arguments in them. Signed-off-by: Nicholas Piggin --- asm/head.S | 16 ++++++++++------ core/opal.c | 27 +++++++++++++++++++++++---- 2 files changed, 33 insertions(+), 10 deletions(-) diff --git a/asm/head.S b/asm/head.S index ccf094827..a786ba126 100644 --- a/asm/head.S +++ b/asm/head.S @@ -930,8 +930,7 @@ opal_entry: std %r1,STACK_GPR1(%r12) mr %r1,%r12 - /* May save arguments for tracing */ -#ifdef OPAL_TRACE_ENTRY + /* Save arguments because we call C */ std %r3,STACK_GPR3(%r1) std %r4,STACK_GPR4(%r1) std %r5,STACK_GPR5(%r1) @@ -940,7 +939,7 @@ opal_entry: std %r8,STACK_GPR8(%r1) std %r9,STACK_GPR9(%r1) std %r10,STACK_GPR10(%r1) -#endif + /* Save Token (r0), LR and r13 */ mflr %r12 std %r0,STACK_GPR0(%r1) @@ -967,9 +966,12 @@ opal_entry: cmpwi %r12,0 bne 3f -#ifdef OPAL_TRACE_ENTRY + /* Check entry */ mr %r3,%r1 - bl opal_trace_entry + bl opal_entry_check + cmpdi %r3,0 + bne 1f + ld %r0,STACK_GPR0(%r1) ld %r3,STACK_GPR3(%r1) ld %r4,STACK_GPR4(%r1) @@ -979,7 +981,6 @@ opal_entry: ld %r8,STACK_GPR8(%r1) ld %r9,STACK_GPR9(%r1) ld %r10,STACK_GPR10(%r1) -#endif /* OPAL_TRACE_ENTRY */ /* Convert our token into a table entry and get the * function pointer. Also check the token. @@ -997,6 +998,9 @@ opal_entry: /* Jump ! */ bctrl + mr %r4,%r1 + bl opal_exit_check + 1: ld %r12,STACK_LR(%r1) mtlr %r12 ld %r13,STACK_GPR13(%r1) diff --git a/core/opal.c b/core/opal.c index 8095f7312..5143692d8 100644 --- a/core/opal.c +++ b/core/opal.c @@ -92,11 +92,9 @@ long opal_bad_token(uint64_t token) return OPAL_PARAMETER; } -/* Called from head.S, thus no prototype */ -void opal_trace_entry(struct stack_frame *eframe); - -void opal_trace_entry(struct stack_frame *eframe) +static void opal_trace_entry(struct stack_frame *eframe __unused) { +#ifdef OPAL_TRACE_ENTRY union trace t; unsigned nargs, i; @@ -117,6 +115,27 @@ void opal_trace_entry(struct stack_frame *eframe) t.opal.r3_to_11[i] = cpu_to_be64(eframe->gpr[3+i]); trace_add(&t, TRACE_OPAL, offsetof(struct trace_opal, r3_to_11[nargs])); +#endif +} + +/* Called from head.S, thus no prototype */ +int64_t opal_entry_check(struct stack_frame *eframe); + +int64_t __attrconst opal_entry_check(struct stack_frame *eframe) +{ + uint64_t token = eframe->gpr[0]; + + opal_trace_entry(eframe); + + return OPAL_SUCCESS; +} + +void opal_exit_check(int64_t retval, struct stack_frame *eframe); + +void __attrconst opal_exit_check(int64_t retval, struct stack_frame *eframe) +{ + (void)retval; + (void)eframe; } void __opal_register(uint64_t token, void *func, unsigned int nargs) From patchwork Fri Nov 24 14:08:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841064 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyqB145wz9s8J for ; Sat, 25 Nov 2017 01:13:58 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FFlhfN6S"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyq971zJzDrpF for ; Sat, 25 Nov 2017 01:13:57 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FFlhfN6S"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FFlhfN6S"; dkim-atps=neutral Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjykN20NjzDrp2 for ; Sat, 25 Nov 2017 01:09:48 +1100 (AEDT) Received: by mail-pl0-x243.google.com with SMTP id a12so4534185pll.0 for ; Fri, 24 Nov 2017 06:09:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mBCG1+uKyfp0rrpk2ZGlwbqIyvLPPn+adJ8JICNDHHA=; b=FFlhfN6SbZeYYtS6ED8BeoiW6WMhXnsOIilljTyUJ+xHZblb1msKPMCEzkLnD+Ny/3 4vLbNoF3BtTjRmOOsy09rB966K5YoQ57/t7j8EwiN+DNGPpbJX1RrZGM/bSy/EjB5pbt yxJOpLgNAxQK/gvxJ3NXKER5vQp3J95ANcwF25rfcrD5r3ybdl737MFKXVhg4ZVl8eIA JUzOdjkdWazvH+f1i8gz3em95cf28mfIes1HdhEASL3GbBfKK2e8m84X6SnKZomdoXAD GAc6afSa6SZVBLBJL3m2C8qc5C897A+ze/yjFIqfOasJEcMbHTqnbbAx0U34eAODvhKL j+jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mBCG1+uKyfp0rrpk2ZGlwbqIyvLPPn+adJ8JICNDHHA=; b=heW1ettRKttj0tXQijeS3hs90h6Ji3tge9IX1WL4/jMPvi5C/OQ8Zq/aM9Fe2UITHA /shAyDmD+owQLsuM9muvKcDgahEjnBDqdFJb/zLqZw1fkNdPA5C3Lgk/vymOtfnjwpA9 YmKWvaPNXI2z8j+6IhZhGeCaEaW0XkionbF9yf7Rpw2cPHAlirT+zmncjkok6rAcOAnk Dx1xjGdRHRPGdZtR04slJHZANrZLndR2NxBIcmbIyO0bEiKvqF/97Hj7wHUOdwQRxSWP aSKqyBkVy/Bp8ln/KDnrMvioVQvU2U0CUu0bp/fKnU+c6CUZFEy6gj6tDOQX93qrKJkx QB/g== X-Gm-Message-State: AJaThX5EKkWF+3QlbcAsFMWj50IIoOlvwzieR+N2VD1Z/co2lcHJMZnv SAMIcGZxnHa4vCvwPjvN19zE9Q== X-Google-Smtp-Source: AGs4zMbjTRk+QLOpILfiXpRejPjGU9mypzz47aopCE5yp/62wjctuGfbWn+DLhM/DEuxsjrOsOBxOQ== X-Received: by 10.84.229.5 with SMTP id b5mr29724790plk.405.1511532586217; Fri, 24 Nov 2017 06:09:46 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:45 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:30 +1000 Message-Id: <20171124140834.7099-22-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 21/25] asm/head: move opal entry token check into C X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move opal_check_token from asm to C. Signed-off-by: Nicholas Piggin --- asm/head.S | 13 ++----------- core/opal.c | 7 ++++++- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/asm/head.S b/asm/head.S index a786ba126..68a4e7b87 100644 --- a/asm/head.S +++ b/asm/head.S @@ -964,7 +964,7 @@ opal_entry: LOAD_ADDR_FROM_TOC(%r12, reboot_in_progress) lbz %r12,0(%r12) cmpwi %r12,0 - bne 3f + bne 2f /* Check entry */ mr %r3,%r1 @@ -986,13 +986,9 @@ opal_entry: * function pointer. Also check the token. * For ELFv2 ABI, the local entry point is used so no need for r12. */ - cmpldi %r0,OPAL_LAST - bgt- 2f sldi %r0,%r0,3 LOAD_ADDR_FROM_TOC(%r12, opal_branch_table) ldx %r0,%r12,%r0 - cmpldi %r0,0 - beq- 2f mtctr %r0 /* Jump ! */ @@ -1007,12 +1003,7 @@ opal_entry: ld %r1,STACK_GPR1(%r1) blr -2: /* Bad token */ - ld %r3,STACK_GPR0(%r1) - bl opal_bad_token - b 1b - -3: /* Reboot in progress, reject all calls */ +2: /* Reboot in progress, reject all calls */ li %r3,OPAL_BUSY b 1b diff --git a/core/opal.c b/core/opal.c index 5143692d8..4d5282791 100644 --- a/core/opal.c +++ b/core/opal.c @@ -118,15 +118,20 @@ static void opal_trace_entry(struct stack_frame *eframe __unused) #endif } +static int64_t opal_check_token(uint64_t token); + /* Called from head.S, thus no prototype */ int64_t opal_entry_check(struct stack_frame *eframe); -int64_t __attrconst opal_entry_check(struct stack_frame *eframe) +int64_t opal_entry_check(struct stack_frame *eframe) { uint64_t token = eframe->gpr[0]; opal_trace_entry(eframe); + if (!opal_check_token(token)) + return opal_bad_token(token); + return OPAL_SUCCESS; } From patchwork Fri Nov 24 14:08:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyqT51mnz9s8J for ; Sat, 25 Nov 2017 01:14:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LaULrl3D"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyqT3mhKzDsW7 for ; Sat, 25 Nov 2017 01:14:13 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LaULrl3D"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LaULrl3D"; dkim-atps=neutral Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjykR1RphzDrcV for ; Sat, 25 Nov 2017 01:09:50 +1100 (AEDT) Received: by mail-pl0-x243.google.com with SMTP id k7so4524863pln.13 for ; Fri, 24 Nov 2017 06:09:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jUDo/GGmFO9IbQ2RLeQIN7Wvsr11GScECw52L5zGpKA=; b=LaULrl3DtaNkMDrqIXA/9K+e0UpQuj6KdaB8sQyBk6EaXPF/SOWGxV5yHtYOdrMV2f JBFSfY9EXTftodRm3ev3uRDixN9tnu2wvJbkIouch2BKhJmfUyqPqMpevH9+kCWfGtfx tZRjPu26Re6nPKjO34cUjc2q8ElYWbhZ6RRTFbuazecUJcB4JMfCDJ69Vxi/wu8r2IzK rfZKXpc4PKdlsis9TtT24wYhdhPCB3QidF+j7gYZkQFxI00ITxRcYok7PX9jmooxHGFP qnV2rif1OUrZa9XZeo+as3/eIc97CXPjocv7t5IC0tMflGOohlKvdZZc+ha3PvQke6e8 AxwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jUDo/GGmFO9IbQ2RLeQIN7Wvsr11GScECw52L5zGpKA=; b=T/VBWWrFzSMygl2ok/9PP1yj2Fm45PQb6/hYNVA2lDoJheIGz3pVKZChLrQY5HWzVE V5gk60taTvuEn/VSunl+8lstHq3WH2un64ZaNrrbtNihne/wD191R/q6ANHGlqp+P583 eQOczJiF+xo1eVB7JJFO5K74g2kaEaz3uS6LzI8dpgSmOCxsglksM9imLwID2yUk8zln EXWWbacZS4rkCnZ+Au+raxcxRH98dhZsjpYDJ4lvsPJD7z9eiCesZpLxYfY3u1Ulxkvu WtTrgsDipDnITfVIT/Tp5SRXXmi4yRuVL1gAF7cSmdyPCX12VSq3hs2FYZNblEbDKP1A pvCw== X-Gm-Message-State: AJaThX68V5WVBhrdt8GU5Nm8AF2GQMev7RjmTJPR9/IvEHNz5qJH71N0 nLyyyOY349gdNf476aLhZVcX4A== X-Google-Smtp-Source: AGs4zMbQiiZkq+pJCEJJ2Jj5ypUyca8aIQ05j+2hya3rdI6vCWpvD97biCVPNBS0YpbajPpGh7iB0g== X-Received: by 10.84.178.129 with SMTP id z1mr18774612plb.365.1511532588893; Fri, 24 Nov 2017 06:09:48 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:48 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:31 +1000 Message-Id: <20171124140834.7099-23-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 22/25] core/opal: always verify cpu->pir on entry X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/opal.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/core/opal.c b/core/opal.c index 4d5282791..752dd3023 100644 --- a/core/opal.c +++ b/core/opal.c @@ -98,11 +98,6 @@ static void opal_trace_entry(struct stack_frame *eframe __unused) union trace t; unsigned nargs, i; - if (this_cpu()->pir != mfspr(SPR_PIR)) { - printf("CPU MISMATCH ! PIR=%04lx cpu @%p -> pir=%04x\n", - mfspr(SPR_PIR), this_cpu(), this_cpu()->pir); - abort(); - } if (eframe->gpr[0] > OPAL_LAST) nargs = 0; else @@ -125,8 +120,15 @@ int64_t opal_entry_check(struct stack_frame *eframe); int64_t opal_entry_check(struct stack_frame *eframe) { + struct cpu_thread *cpu = this_cpu(); uint64_t token = eframe->gpr[0]; + if (cpu->pir != mfspr(SPR_PIR)) { + printf("CPU MISMATCH ! PIR=%04lx cpu @%p -> pir=%04x token=%llu\n", + mfspr(SPR_PIR), cpu, cpu->pir, token); + abort(); + } + opal_trace_entry(eframe); if (!opal_check_token(token)) From patchwork Fri Nov 24 14:08:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841066 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyqh2WdBz9s8J for ; Sat, 25 Nov 2017 01:14:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q/abqy4r"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yjyqh1BKvzDsF3 for ; Sat, 25 Nov 2017 01:14:24 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q/abqy4r"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Q/abqy4r"; dkim-atps=neutral Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yjykV0zpTzDrbq for ; Sat, 25 Nov 2017 01:09:54 +1100 (AEDT) Received: by mail-pl0-x242.google.com with SMTP id a12so4534322pll.0 for ; Fri, 24 Nov 2017 06:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J+GbB0ZiK/rA7vr8ZFrt3ciLPo6cO39Coq2LCFUGWaI=; b=Q/abqy4r5Uv1F6k8E/I4bmtse25oPUHj1jw6pJHrZeQFi7GuzKfidMNTLl2kFPhYhA awbnKTYkHn1Dwz784A11Fw5ceJFxrsncYfpHwNEeGcq/d8ZZwyhbFO6GGQcKHiDAdXs7 MuWvVESbAu4hHq9QWf6p67i9ae2sH2TpWR+V9RapWn0yEgKrRa38MSXvFQzCSkF+ZNgl jnomciYC7wB4dhvw3M7MQzs2ndlUrkDSAXmFSdc5HXt7UaZtwsAE6dhKIGfSr4Iem/+3 QdcJRtxQDrVfJLPHmqJUUWJrZzGNrUYs7WPwWwvjIavPJe6Bpw3+2gJkPoS+d5aF9v2C zuJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J+GbB0ZiK/rA7vr8ZFrt3ciLPo6cO39Coq2LCFUGWaI=; b=ALntMNapYdE0+3dojrJPg1uKG2x6kAjvDwpZroFDyMX5l8q0FdekGSyBcs/YFqsvEE vopNSuSSxCoPMsPAwBRBXdNl/0tjDjYpUGX1czPUql4JC9kotmRkg2A5QTZclGrWDBxh iIMCzD1yqgu5ofBD7tyUeNM2JRgUKIU3kx7aOREqquyIpA+xa+j+5lUkvjTIyIJCa0bv uRQ22A4KRscR2pmqvXa2i+UQ9aHkEj/lkSB5MmmeJYubPhZTkwtqZsZGhsubg+jwOl6x VtROsm13eGWbiR8I9v3WVvMrYdwTI6i33qtcv0b1qsTZn7e0/XNOtS3uqrfmuB4OO/nj 4zXg== X-Gm-Message-State: AJaThX6yqmYtNyCBftA7glL3ZtFAvWSOz2j9sHo0WF/wdYtes6ln2ATF APr0+FjgBpQSfb4nMSESmY3YdA== X-Google-Smtp-Source: AGs4zMYrUNpCVQCLqcyb+NFMma6kFW89MvZD/UtDhI+rny0qCQfPclzp/wxSHk7irWTJ6Pru9fd7tw== X-Received: by 10.84.239.1 with SMTP id w1mr23736152plk.227.1511532591921; Fri, 24 Nov 2017 06:09:51 -0800 (PST) Received: from roar.au.ibm.com (27-33-241-2.tpgi.com.au. [27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:50 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:32 +1000 Message-Id: <20171124140834.7099-24-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 23/25] core: Add support for quiescing OPAL X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Quiescing is ensuring all host controlled CPUs (except the current one) are out of OPAL and prevented from entering. This can be use in debug and shutdown paths, particularly with system reset sequences. This patch adds per-CPU entry and exit tracking for OPAL calls, and adds logic to "hold" or "reject" at entry time, if OPAL is quiesced. An OPAL call is added, to expose the functionality to Linux, where it can be used for shutdown, kexec, and before generating sreset IPIs for debugging (so the debug code does not recurse into OPAL). Signed-off-by: Nicholas Piggin --- core/cpu.c | 5 + core/opal.c | 166 +++++++++++++++++++++++++- doc/opal-api/opal-quiesce-158.rst | 59 +++++++++ doc/opal-api/opal-signal-system-reset-145.rst | 7 ++ include/cpu.h | 2 + include/opal-api.h | 9 +- include/opal-internal.h | 2 + 7 files changed, 246 insertions(+), 4 deletions(-) create mode 100644 doc/opal-api/opal-quiesce-158.rst diff --git a/core/cpu.c b/core/cpu.c index 2dba2f504..b94e04ef2 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1220,6 +1220,11 @@ static int64_t opal_return_cpu(void) { prlog(PR_DEBUG, "OPAL: Returning CPU 0x%04x\n", this_cpu()->pir); + this_cpu()->in_opal_call--; + if (this_cpu()->in_opal_call != 0) { + printf("OPAL in_opal_call=%u\n", this_cpu()->in_opal_call); + } + __secondary_cpu_entry(); return OPAL_HARDWARE; /* Should not happen */ diff --git a/core/opal.c b/core/opal.c index 752dd3023..dab5b78ac 100644 --- a/core/opal.c +++ b/core/opal.c @@ -113,6 +113,14 @@ static void opal_trace_entry(struct stack_frame *eframe __unused) #endif } +/* + * opal_quiesce_state is used as a lock. Don't use an actual lock to avoid + * lock busting. + */ +static uint32_t opal_quiesce_state; /* 0 or QUIESCE_HOLD/QUIESCE_REJECT */ +static int32_t opal_quiesce_owner; /* PIR */ +static int32_t opal_quiesce_target; /* -1 or PIR */ + static int64_t opal_check_token(uint64_t token); /* Called from head.S, thus no prototype */ @@ -134,16 +142,168 @@ int64_t opal_entry_check(struct stack_frame *eframe) if (!opal_check_token(token)) return opal_bad_token(token); + if (!opal_quiesce_state && cpu->in_opal_call) { + printf("CPU ATTEMPT TO RE-ENTER FIRMWARE! PIR=%04lx cpu @%p -> pir=%04x token=%llu\n", + mfspr(SPR_PIR), cpu, cpu->pir, token); + return OPAL_BUSY; + } + +again: + cpu->in_opal_call++; + /* + * Order the store in_opal_call vs load quiesce_opal_call. + * This also provides an acquire barrier for opal entry vs + * another thread quiescing opal. In this way, quiescing + * can behave as mutual exclusion. + */ + sync(); + if (cpu->quiesce_opal_call) { + cpu->in_opal_call--; + if (opal_quiesce_state == QUIESCE_REJECT) + return OPAL_BUSY; + smt_lowest(); + while (cpu->quiesce_opal_call) + barrier(); + smt_medium(); + goto again; + } + return OPAL_SUCCESS; } void opal_exit_check(int64_t retval, struct stack_frame *eframe); -void __attrconst opal_exit_check(int64_t retval, struct stack_frame *eframe) +void opal_exit_check(int64_t retval, struct stack_frame *eframe) { - (void)retval; - (void)eframe; + struct cpu_thread *cpu = this_cpu(); + uint64_t token = eframe->gpr[0]; + + if (!cpu->in_opal_call) { + printf("CPU UN-ACCOUNTED FIRMWARE ENTRY! PIR=%04lx cpu @%p -> pir=%04x token=%llu retval=%lld\n", + mfspr(SPR_PIR), cpu, cpu->pir, token, retval); + } else { + sync(); /* release barrier vs quiescing */ + cpu->in_opal_call--; + } +} + +int64_t opal_quiesce(uint32_t quiesce_type, int32_t cpu_target) +{ + struct cpu_thread *cpu = this_cpu(); + struct cpu_thread *c = NULL; + uint64_t end; + bool stuck = false; + + if (cpu_target >= 0) { + c = find_cpu_by_server(cpu_target); + if (!c) + return OPAL_PARAMETER; + } else if (cpu_target != -1) { + return OPAL_PARAMETER; + } + + if (quiesce_type == QUIESCE_HOLD || quiesce_type == QUIESCE_REJECT) { + if (cmpxchg32(&opal_quiesce_state, 0, quiesce_type) != 0) { + if (opal_quiesce_owner != cpu->pir) { + /* + * Nested is allowed for now just for + * internal uses, so an error is returned + * for OS callers, but no error message + * printed if we are nested. + */ + printf("opal_quiesce already quiescing\n"); + } + return OPAL_BUSY; + } + opal_quiesce_owner = cpu->pir; + opal_quiesce_target = cpu_target; + } + + if (opal_quiesce_owner != cpu->pir) { + printf("opal_quiesce CPU does not own quiesce state (must call QUIESCE_HOLD or QUIESCE_REJECT)\n"); + return OPAL_BUSY; + } + + /* Okay now we own the quiesce state */ + + if (quiesce_type == QUIESCE_RESUME || quiesce_type == QUIESCE_RESUME_FAST_REBOOT) { + bust_locks = false; + sync(); /* release barrier vs opal entry */ + if (c) { + c->quiesce_opal_call = false; + } else { + for_each_cpu(c) { + if (quiesce_type == QUIESCE_RESUME_FAST_REBOOT) + cpu->in_opal_call = 0; + + if (c == cpu) + continue; + c->quiesce_opal_call = false; + } + } + sync(); + opal_quiesce_state = 0; + return OPAL_SUCCESS; + } + + if (quiesce_type == QUIESCE_LOCK_BREAK) { + if (opal_quiesce_target != -1) { + printf("opal_quiesce has not quiesced all CPUs (must target -1)\n"); + return OPAL_BUSY; + } + bust_locks = true; + return OPAL_SUCCESS; + } + + if (c) { + c->quiesce_opal_call = true; + } else { + for_each_cpu(c) { + if (c == cpu) + continue; + c->quiesce_opal_call = true; + } + } + + sync(); /* Order stores to quiesce_opal_call vs loads of in_opal_call */ + + end = mftb() + msecs_to_tb(1000); + + smt_lowest(); + if (c) { + while (c->in_opal_call) { + if (tb_compare(mftb(), end) == TB_AAFTERB) { + printf("OPAL quiesce CPU:%04x stuck in OPAL\n", c->pir); + stuck = true; + break; + } + barrier(); + } + } else { + for_each_cpu(c) { + if (c == cpu) + continue; + while (c->in_opal_call) { + if (tb_compare(mftb(), end) == TB_AAFTERB) { + printf("OPAL quiesce CPU:%04x stuck in OPAL\n", c->pir); + stuck = true; + break; + } + barrier(); + } + } + } + smt_medium(); + sync(); /* acquire barrier vs opal entry */ + + if (stuck) { + printf("OPAL quiesce could not kick all CPUs out of OPAL\n"); + return OPAL_PARTIAL; + } + + return OPAL_SUCCESS; } +opal_call(OPAL_QUIESCE, opal_quiesce, 2); void __opal_register(uint64_t token, void *func, unsigned int nargs) { diff --git a/doc/opal-api/opal-quiesce-158.rst b/doc/opal-api/opal-quiesce-158.rst new file mode 100644 index 000000000..19604396b --- /dev/null +++ b/doc/opal-api/opal-quiesce-158.rst @@ -0,0 +1,59 @@ +.. _opal-quiesce: + +OPAL_QUIESCE +============ + +The host OS can use OPAL_QUIESCE to ensure CPUs under host control are not +executing OPAL. This is useful in crash or shutdown scenarios to try to +ensure that CPUs are not holding locks, and is intended to be used with +OPAL_SIGNAL_SYSTEM_RESET, for example. + +Arguments +--------- +:: + + uint32_t quiesce_type + QUIESCE_HOLD Wait for all target(s) currently executing OPAL to + return to the host. Any new OPAL call that is made + will be held off until QUIESCE_RESUME. + QUIESCE_REJECT Wait for all target(s) currently executing OPAL to + return to the host. Any new OPAL call that is made + will fail with OPAL_BUSY until QUIESCE_RESUME. + QUIESCE_LOCK_BREAK After QUIESCE_HOLD or QUIESCE_REJECT is successful, + the CPU can call QUIESCE_LOCK_BREAK to skip all + locking in OPAL to give the best chance of making + progress in the crash/debug paths. The host should + ensure all other CPUs are stopped (e.g., with + OPAL_SIGNAL_SYSTEM_RESET) before this call is made, to + avoid concurrency. + QUIESCE_RESUME Undo the effects of QUIESCE_HOLD/QUIESCE_REJECT and + QUIESCE_LOCK_BREAK calls. + QUIESCE_RESUME_FAST_REBOOT + As above, but also reset the tracking of OS calls + into firmware as part of fast reboot (secondaries + will never return to OS, but instead be released + into a new OS boot). + + int32_t target_cpu + cpu_nr >= 0 The cpu server number of the target cpu to reset. + -1 All cpus except the current one should be quiesced. + +Returns +------- +OPAL_SUCCESS + The quiesce call was successful. + +OPAL_PARTIAL + Some or all of the CPUs executing OPAL when the call was made did not + return to the host after a timeout of 1 second. This is a best effort + at quiescing OPAL, and QUIESCE_RESUME must be called to resume normal + firmware operation. + +OPAL_PARAMETER + A parameter was incorrect. + +OPAL_BUSY + This CPU was not able to complete the operation, either because another + has concurrently started quiescing the system, or because it has not + successfully called QUIESCE_HOLD or QUIESCE_REJECT before attempting + QUIESCE_LOCK_BREAK or QUIESCE_RESUME. diff --git a/doc/opal-api/opal-signal-system-reset-145.rst b/doc/opal-api/opal-signal-system-reset-145.rst index 28e5e2f41..98baef72a 100644 --- a/doc/opal-api/opal-signal-system-reset-145.rst +++ b/doc/opal-api/opal-signal-system-reset-145.rst @@ -17,6 +17,13 @@ raised when the target has MSR[RI]=0), so it should not be used in normal operation, but only for crashing, debugging, and similar exceptional cases. +OPAL_SIGNAL_SYSTEM_RESET can pull CPUs out of OPAL, which may be +undesirable in a crash or shutdown situation (e.g., because they may +hold locks which are required to access the console, or may be halfway +through setting hardware registers), so OPAL_QUIESCE can be used +before OPAL_SIGNAL_SYSTEM_RESET to (attempt to) ensure all CPUs are +out of OPAL before being interrupted. + Arguments --------- :: diff --git a/include/cpu.h b/include/cpu.h index 3d5dbd40d..28041057d 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -55,9 +55,11 @@ struct cpu_thread { struct trace_info *trace; uint64_t save_r1; void *icp_regs; + uint32_t in_opal_call; uint32_t lock_depth; uint32_t con_suspend; bool con_need_flush; + bool quiesce_opal_call; bool in_mcount; bool in_poller; bool in_reinit; diff --git a/include/opal-api.h b/include/opal-api.h index 0bc036ed7..5013b71b5 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -214,7 +214,14 @@ #define OPAL_SET_POWER_SHIFT_RATIO 155 #define OPAL_SENSOR_GROUP_CLEAR 156 #define OPAL_PCI_SET_P2P 157 -#define OPAL_LAST 157 +#define OPAL_QUIESCE 158 +#define OPAL_LAST 158 + +#define QUIESCE_HOLD 1 /* Spin all calls at entry */ +#define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ +#define QUIESCE_LOCK_BREAK 3 /* Set to ignore locks. */ +#define QUIESCE_RESUME 4 /* Un-quiesce */ +#define QUIESCE_RESUME_FAST_REBOOT 5 /* Un-quiesce, fast reboot */ /* Device tree flags */ diff --git a/include/opal-internal.h b/include/opal-internal.h index 583e99948..8d3d0a177 100644 --- a/include/opal-internal.h +++ b/include/opal-internal.h @@ -61,6 +61,8 @@ extern void add_opal_node(void); (func), (nargs)) extern void __opal_register(uint64_t token, void *func, unsigned num_args); +int64_t opal_quiesce(uint32_t shutdown_type, int32_t cpu); + /* Warning: no locking at the moment, do at init time only * * XXX TODO: Add the big RCU-ish "opal API lock" to protect us here From patchwork Fri Nov 24 14:08:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyqy4ntXz9sBd for ; Sat, 25 Nov 2017 01:14:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aZ9RKi79"; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:53 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:33 +1000 Message-Id: <20171124140834.7099-25-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 24/25] fast-reboot: quiesce opal before initiating a fast reboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Switch fast reboot to use quiescing rather than "wait for a while". If firmware can not be quiesced, then fast reboot is skipped. This significantly improves the robustness of fast reboot in the face of bugs or unexpected latencies. Complexity of synchronization in fast-reboot is reduced, because we are guaranteed to be single-threaded when quiesce succeeds, so locks can be removed. In the case that firmware can be quiesced, then it will generally reduce fast reboot times by nearly 200ms, because quiescing usually takes very little time. Signed-off-by: Nicholas Piggin --- asm/head.S | 10 ---------- core/fast-reboot.c | 47 ++++++++++++++++++----------------------------- core/platform.c | 6 ++++++ 3 files changed, 24 insertions(+), 39 deletions(-) diff --git a/asm/head.S b/asm/head.S index 68a4e7b87..eccf0702c 100644 --- a/asm/head.S +++ b/asm/head.S @@ -960,12 +960,6 @@ opal_entry: addis %r2,%r2,(__toc_start - __head)@ha addi %r2,%r2,(__toc_start - __head)@l - /* Check for a reboot in progress */ - LOAD_ADDR_FROM_TOC(%r12, reboot_in_progress) - lbz %r12,0(%r12) - cmpwi %r12,0 - bne 2f - /* Check entry */ mr %r3,%r1 bl opal_entry_check @@ -1003,10 +997,6 @@ opal_entry: ld %r1,STACK_GPR1(%r1) blr -2: /* Reboot in progress, reject all calls */ - li %r3,OPAL_BUSY - b 1b - .global start_kernel start_kernel: sync diff --git a/core/fast-reboot.c b/core/fast-reboot.c index f9ed697db..d51017ac8 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -30,9 +30,7 @@ #include /* Flag tested by the OPAL entry code */ -uint8_t reboot_in_progress; static volatile bool fast_boot_release; -static struct lock reset_lock = LOCK_UNLOCKED; static bool cpu_state_wait_all_others(enum cpu_thread_state state, unsigned long timeout_tb) @@ -67,13 +65,10 @@ extern void *fdt; extern struct lock capi_lock; static const char *fast_reboot_disabled = NULL; -static struct lock fast_reboot_disabled_lock = LOCK_UNLOCKED; void disable_fast_reboot(const char *reason) { - lock(&fast_reboot_disabled_lock); fast_reboot_disabled = reason; - unlock(&fast_reboot_disabled_lock); } void fast_reboot(void) @@ -93,45 +88,37 @@ void fast_reboot(void) return; } - lock(&fast_reboot_disabled_lock); + /* + * Ensure all other CPUs have left OPAL calls. + */ + if (!opal_quiesce(QUIESCE_HOLD, -1)) { + prlog(PR_DEBUG, "RESET: Fast reboot disabled because OPAL quiesce timed out\n"); + return; + } + if (fast_reboot_disabled) { prlog(PR_DEBUG, "RESET: Fast reboot disabled because %s\n", fast_reboot_disabled); - unlock(&fast_reboot_disabled_lock); + opal_quiesce(QUIESCE_RESUME, -1); return; } - unlock(&fast_reboot_disabled_lock); prlog(PR_NOTICE, "RESET: Initiating fast reboot %d...\n", ++fast_reboot_count); free(fdt); - /* XXX We need a way to ensure that no other CPU is in skiboot - * holding locks (via the OPAL APIs) and if they are, we need - * for them to get out. Hopefully that isn't happening, but... - * - * To fix this properly, we want to keep track of OPAL entry/exit - * on all CPUs. - */ - reboot_in_progress = 1; - time_wait_ms(200); - - /* Lock so the new guys coming don't reset us */ - lock(&reset_lock); - fast_boot_release = false; sync(); /* Put everybody in stop except myself */ - if (sreset_all_prepare()) + if (sreset_all_prepare()) { + opal_quiesce(QUIESCE_RESUME, -1); return; - - /* Now everyone else is stopped */ - unlock(&reset_lock); + } /* - * There is no point clearing special wakeup due to failure after this - * point, because we will be going to full IPL. Less cleanup work means - * less opportunity to fail. + * There is no point clearing special wakeup or un-quiesce due to + * failure after this point, because we will be going to full IPL. + * Less cleanup work means less opportunity to fail. */ for_each_ungarded_cpu(cpu) { @@ -156,6 +143,9 @@ void fast_reboot(void) prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); sreset_all_finish(); + /* This resets our quiesce state ready to enter the new kernel. */ + opal_quiesce(QUIESCE_RESUME_FAST_REBOOT, -1); + asm volatile("ba 0x100\n\t" : : : "memory"); for (;;) ; @@ -304,7 +294,6 @@ void __noreturn fast_reboot_entry(void) /* Clear release flag for next time */ fast_boot_release = false; - reboot_in_progress = 0; /* Cleanup ourselves */ cleanup_cpu_state(); diff --git a/core/platform.c b/core/platform.c index 732f67e50..6816fe58a 100644 --- a/core/platform.c +++ b/core/platform.c @@ -41,6 +41,8 @@ static int64_t opal_cec_power_down(uint64_t request) { prlog(PR_NOTICE, "OPAL: Shutdown request type 0x%llx...\n", request); + opal_quiesce(QUIESCE_HOLD, -1); + console_complete_flush(); if (platform.cec_power_down) @@ -54,6 +56,8 @@ static int64_t opal_cec_reboot(void) { prlog(PR_NOTICE, "OPAL: Reboot request...\n"); + opal_quiesce(QUIESCE_HOLD, -1); + console_complete_flush(); /* Try fast-reset unless explicitly disabled */ @@ -71,6 +75,8 @@ static int64_t opal_cec_reboot2(uint32_t reboot_type, char *diag) { struct errorlog *buf; + opal_quiesce(QUIESCE_HOLD, -1); + switch (reboot_type) { case OPAL_REBOOT_NORMAL: return opal_cec_reboot(); From patchwork Fri Nov 24 14:08:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 841068 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yjyrF0ps0z9s8J for ; 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[27.33.241.2]) by smtp.gmail.com with ESMTPSA id z23sm32945712pgc.2.2017.11.24.06.09.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Nov 2017 06:09:56 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 25 Nov 2017 00:08:34 +1000 Message-Id: <20171124140834.7099-26-npiggin@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171124140834.7099-1-npiggin@gmail.com> References: <20171124140834.7099-1-npiggin@gmail.com> Subject: [Skiboot] [PATCH v2 25/25] fast-reboot: improve failure error messages X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Change existing failure error messages to PR_NOTICE so they get printed to the console, and add some new ones. It's not a more severe class because it falls back to IPL on failure. Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index d51017ac8..350ccd375 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -92,7 +92,8 @@ void fast_reboot(void) * Ensure all other CPUs have left OPAL calls. */ if (!opal_quiesce(QUIESCE_HOLD, -1)) { - prlog(PR_DEBUG, "RESET: Fast reboot disabled because OPAL quiesce timed out\n"); + prlog(PR_NOTICE, "RESET: Fast reboot disabled because OPAL " + "quiesce timed out\n"); return; } @@ -104,6 +105,7 @@ void fast_reboot(void) } prlog(PR_NOTICE, "RESET: Initiating fast reboot %d...\n", ++fast_reboot_count); + free(fdt); fast_boot_release = false; @@ -111,6 +113,8 @@ void fast_reboot(void) /* Put everybody in stop except myself */ if (sreset_all_prepare()) { + prlog(PR_NOTICE, "RESET: Fast reboot failed to prepare " + "secondaries for system reset\n"); opal_quiesce(QUIESCE_RESUME, -1); return; } @@ -133,12 +137,18 @@ void fast_reboot(void) setup_reset_vector(); /* Send everyone else to 0x100 */ - if (sreset_all_others() != OPAL_SUCCESS) + if (sreset_all_others() != OPAL_SUCCESS) { + prlog(PR_NOTICE, "RESET: Fast reboot failed to system reset " + "secondaries\n"); return; + } /* Ensure all the sresets get through */ - if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(100))) + if (!cpu_state_wait_all_others(cpu_state_present, msecs_to_tb(100))) { + prlog(PR_NOTICE, "RESET: Fast reboot timed out waiting for " + "secondaries to call in\n"); return; + } prlog(PR_DEBUG, "RESET: Releasing special wakeups...\n"); sreset_all_finish();