From patchwork Sun Dec 22 14:10:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rnl7ok3k"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksZ0C5nz9sP6 for ; Mon, 23 Dec 2019 01:10:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725932AbfLVOKl (ORCPT ); Sun, 22 Dec 2019 09:10:41 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52778 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725840AbfLVOKl (ORCPT ); Sun, 22 Dec 2019 09:10:41 -0500 Received: by mail-wm1-f67.google.com with SMTP id p9so13385769wmc.2; Sun, 22 Dec 2019 06:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/VDBOK2IJqgukN9tSgWPXP9FuHvsRdT8O5ST1j5LKEI=; b=rnl7ok3k3yjSKvrZzu7/K3jfanSdQylXdtfY/RoXQpe+JzH8lTjtrV5oWs0XohTMJP nPfrMz9rKWA2kLADIV4PliiG0IS+oWJC5kZNEPaW+I8m+PSfv/9HD78grLlzoEYJUNgh 6XhbHzwIgPpu8BtTdVmkoKyYB6P5NZ8rjcDLKnkuOgrBegB5rm3qg0NRtixyQnCJ5Zyx m7pWENICuUdxl3Mrgv93EuLvdkr+HwNz8sWpRUj9JCQymTcndTgvjxabLYsA6E+54WBc BkHb6R5ZTuLRsMJcpYS1E1jYGVJeCS37KXuHw0BiCJYxnE5N9BoehShBbytL3/ezI8rF 2Fcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/VDBOK2IJqgukN9tSgWPXP9FuHvsRdT8O5ST1j5LKEI=; b=tokdpnQQV+Nfto3RcHaoYqHiuWH9EAMgDEg59onomIsvv0iS7V+Pe6j5ZQu0uvS1Gk weWFRqVVvkOFw7AU5pU+A/Bxr0ZA0rS2o9hFCOCp6y5197MGwQkCycBBwc8/uqv7Ynx8 JtMCHblb+zmvq+1pju9KMo0A1Lx/8MXqW/K/OA4sNyYinzFCElZZYhHz8Z3KT2epWMof DKSAYW1sEzJulOCGXX2WknN5SgMldrIE2z5E4J4/MhQ5bPtxNh62RkCbhReAKvT2abKe HlvuZXnBbRj96I3HPBKl7MB0smRfzNHRQa7yFdpIEpf1yYsf5xfBzeC3GM6jQRxfPlw1 mYqw== X-Gm-Message-State: APjAAAWj0UpjjzoGIKlrOVoaR/vlq8VPmKeff7LltXm+Uz+y6nTPhUuC byLOS6tcrwfmvNE+Y0vKtE4= X-Google-Smtp-Source: APXvYqxznfu5OShpVsrN3qzpIHEnzPpf0Bh5ApTGjy7QwGouyzgUUr2uDphv4ytkG04CXs9mfuA43A== X-Received: by 2002:a1c:66d6:: with SMTP id a205mr8411887wmc.171.1577023838861; Sun, 22 Dec 2019 06:10:38 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id s128sm16794353wme.39.2019.12.22.06.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:37 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/13] dt-bindings: memory: Add Tegra186 memory client IDs Date: Sun, 22 Dec 2019 15:10:23 +0100 Message-Id: <20191222141035.1649937-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add IDs for the memory clients found on NVIDIA Tegra186 SoCs. This will be used to describe interconnect paths from devices to system memory. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- include/dt-bindings/memory/tegra186-mc.h | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/include/dt-bindings/memory/tegra186-mc.h b/include/dt-bindings/memory/tegra186-mc.h index 64813536aec9..82a1e27f7357 100644 --- a/include/dt-bindings/memory/tegra186-mc.h +++ b/include/dt-bindings/memory/tegra186-mc.h @@ -108,4 +108,143 @@ #define TEGRA186_SID_SE_VM6 0x4e #define TEGRA186_SID_SE_VM7 0x4f +/* + * memory client IDs + */ + +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA186_MEMORY_CLIENT_PTCR 0x00 +/* PCIE reads */ +#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e +/* High-definition audio (HDA) reads */ +#define TEGRA186_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data reads */ +#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c +/* SATA reads */ +#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f +/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 +#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b +/* PCIE writes */ +#define TEGRA186_MEMORY_CLIENT_AFIW 0x31 +/* High-definition audio (HDA) writes */ +#define TEGRA186_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 +/* SATA writes */ +#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d +/* ISP Read client for Crossbar A */ +#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 +/* ISP Write client for Crossbar A */ +#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 +/* XUSB reads */ +#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST writes */ +#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB reads */ +#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV writes */ +#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* TSEC Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 +/* TSEC Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 +/* 3D, ltcx reads instance 0 */ +#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 +/* 3D, ltcx writes instance 0 */ +#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 +/* sdmmca memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 +/* sdmmcbmemory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 +/* sdmmc memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 +/* sdmmcd memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 +/* sdmmcb memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 +/* sdmmc memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 +/* sdmmcd memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d +/* VI Write client */ +#define TEGRA186_MEMORY_CLIENT_VIW 0x72 +#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine reads */ +#define TEGRA186_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine writes */ +#define TEGRA186_MEMORY_CLIENT_APEW 0x7b +#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f +/* SE Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_SESRD 0x80 +/* SE Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_SESWR 0x81 +/* ETR reads */ +#define TEGRA186_MEMORY_CLIENT_ETRR 0x84 +/* ETR writes */ +#define TEGRA186_MEMORY_CLIENT_ETRW 0x85 +/* TSECB Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 +/* TSECB Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 +/* 3D, ltcx reads instance 1 */ +#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 +/* 3D, ltcx writes instance 1 */ +#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 +/* AXI Switch read client */ +#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 +/* BPMP read client */ +#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA186_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA186_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA186_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e +/* APEDMA read client */ +#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 +#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 + #endif From patchwork Sun Dec 22 14:10:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="q6AF1fNf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksd36Rmz9sPh for ; Mon, 23 Dec 2019 01:10:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725997AbfLVOKp (ORCPT ); Sun, 22 Dec 2019 09:10:45 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:39807 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725922AbfLVOKo (ORCPT ); Sun, 22 Dec 2019 09:10:44 -0500 Received: by mail-wr1-f67.google.com with SMTP id y11so13939338wrt.6; Sun, 22 Dec 2019 06:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IM3/+6wY0RhsLaRbP0KEDdMrdNqKpo+DUDIDTMR9vZo=; b=q6AF1fNfWEsxrntENK+ju5rtZYEsExqYgqRhNM8JXexorq/XIOJtOfMBPAW7xyTYHe kLiUyJ6Sz7INU8yhPwp2EgSZSvGFn4FGhH4gBPTKzDsQ7/ofAcCxQ5uQa2/Ica0vm/+G 6gqOtX+IHOXOqC8dJLN4npr/cCIDmBGT4XTyaLWQZ1ZVY47MZcQUf9RaygP77uJGcL69 wt+f4EVfkPvwtvfQ4B3bk5pppX3kVrdPHzpxGK4lqkm67f89TBFB33cKBN++gW8aULnX MBu67vX8ou0g1zCqRT3Xk4sgnOuz6bk650UHfGR3r8PzpTmr3xDaZSPk+RKw0fEhv7Nr jRrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IM3/+6wY0RhsLaRbP0KEDdMrdNqKpo+DUDIDTMR9vZo=; b=Ht+W1KXS+DxVEglxtNxRdIuU/E69G82usEFetq6BPJKWkpRhzEbh29/QSHFnhDAUKr pCX/n3y/YcjxlTHcAXPUTi8/XWIQIw9NxWZv+FOsmThqU8WtiRVY0uN2ovD3fJCsYYNi P9AjMHeoWwWGlztTo/b/+xK2LI3NbVRXSlwVR29RhEyK/NETwmkvMxFdoalqzw71+Ejz xCTcsOzWA2PprHomP9yhvza0gcZBY1nqzhPT2cTTjFQ7eC7UV11jCN4nmUk1xObRfRD2 +rUnqNWc2P+DX/CtVJDhsrNLLhpSin16RkRgjcQ1zhISnwkIcBerdurO1wGRSsSw+x5p Gdjg== X-Gm-Message-State: APjAAAWYlE5AqqpoyfMae73BSha2QyqcykFl88UylHbEHohCnTnZ5NUb 8Usba6398pIj3rDsw2DHaNu3s9PW X-Google-Smtp-Source: APXvYqy/coUS2BxeDXnhsxPcxPsGOPaccEkpRvnEsKyz6vNQr38rNjRAjrka5SaRMRxE7DuMsocnkg== X-Received: by 2002:adf:cd03:: with SMTP id w3mr24776398wrm.191.1577023840729; Sun, 22 Dec 2019 06:10:40 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id a1sm16966867wrr.80.2019.12.22.06.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:39 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/13] dt-bindings: memory: Add Tegra194 memory controller header Date: Sun, 22 Dec 2019 15:10:24 +0100 Message-Id: <20191222141035.1649937-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This header contains definitions for the memory controller found on NVIDIA Tegra194 SoCs, such as the stream IDs used for the ARM SMMU and the IDs used to identify the various memory clients. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- include/dt-bindings/memory/tegra194-mc.h | 410 +++++++++++++++++++++++ 1 file changed, 410 insertions(+) create mode 100644 include/dt-bindings/memory/tegra194-mc.h diff --git a/include/dt-bindings/memory/tegra194-mc.h b/include/dt-bindings/memory/tegra194-mc.h new file mode 100644 index 000000000000..eed48b746bc9 --- /dev/null +++ b/include/dt-bindings/memory/tegra194-mc.h @@ -0,0 +1,410 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H +#define DT_BINDINGS_MEMORY_TEGRA194_MC_H + +/* special clients */ +#define TEGRA194_SID_INVALID 0x00 +#define TEGRA194_SID_PASSTHROUGH 0x7f + +/* host1x clients */ +#define TEGRA194_SID_HOST1X 0x01 +#define TEGRA194_SID_CSI 0x02 +#define TEGRA194_SID_VIC 0x03 +#define TEGRA194_SID_VI 0x04 +#define TEGRA194_SID_ISP 0x05 +#define TEGRA194_SID_NVDEC 0x06 +#define TEGRA194_SID_NVENC 0x07 +#define TEGRA194_SID_NVJPG 0x08 +#define TEGRA194_SID_NVDISPLAY 0x09 +#define TEGRA194_SID_TSEC 0x0a +#define TEGRA194_SID_TSECB 0x0b +#define TEGRA194_SID_SE 0x0c +#define TEGRA194_SID_SE1 0x0d +#define TEGRA194_SID_SE2 0x0e +#define TEGRA194_SID_SE3 0x0f + +/* GPU clients */ +#define TEGRA194_SID_GPU 0x10 + +/* other SoC clients */ +#define TEGRA194_SID_AFI 0x11 +#define TEGRA194_SID_HDA 0x12 +#define TEGRA194_SID_ETR 0x13 +#define TEGRA194_SID_EQOS 0x14 +#define TEGRA194_SID_UFSHC 0x15 +#define TEGRA194_SID_AON 0x16 +#define TEGRA194_SID_SDMMC4 0x17 +#define TEGRA194_SID_SDMMC3 0x18 +#define TEGRA194_SID_SDMMC2 0x19 +#define TEGRA194_SID_SDMMC1 0x1a +#define TEGRA194_SID_XUSB_HOST 0x1b +#define TEGRA194_SID_XUSB_DEV 0x1c +#define TEGRA194_SID_SATA 0x1d +#define TEGRA194_SID_APE 0x1e +#define TEGRA194_SID_SCE 0x1f + +/* GPC DMA clients */ +#define TEGRA194_SID_GPCDMA_0 0x20 +#define TEGRA194_SID_GPCDMA_1 0x21 +#define TEGRA194_SID_GPCDMA_2 0x22 +#define TEGRA194_SID_GPCDMA_3 0x23 +#define TEGRA194_SID_GPCDMA_4 0x24 +#define TEGRA194_SID_GPCDMA_5 0x25 +#define TEGRA194_SID_GPCDMA_6 0x26 +#define TEGRA194_SID_GPCDMA_7 0x27 + +/* APE DMA clients */ +#define TEGRA194_SID_APE_1 0x28 +#define TEGRA194_SID_APE_2 0x29 + +/* camera RTCPU */ +#define TEGRA194_SID_RCE 0x2a + +/* camera RTCPU on host1x address space */ +#define TEGRA194_SID_RCE_1X 0x2b + +/* APE DMA clients */ +#define TEGRA194_SID_APE_3 0x2c + +/* camera RTCPU running on APE */ +#define TEGRA194_SID_APE_CAM 0x2d +#define TEGRA194_SID_APE_CAM_1X 0x2e + +#define TEGRA194_SID_RCE_RM 0x2f +#define TEGRA194_SID_VI_FALCON 0x30 +#define TEGRA194_SID_ISP_FALCON 0x31 + +/* + * The BPMP has its SID value hardcoded in the firmware. Changing it requires + * considerable effort. + */ +#define TEGRA194_SID_BPMP 0x32 + +/* for SMMU tests */ +#define TEGRA194_SID_SMMU_TEST 0x33 + +/* host1x virtualization channels */ +#define TEGRA194_SID_HOST1X_CTX0 0x38 +#define TEGRA194_SID_HOST1X_CTX1 0x39 +#define TEGRA194_SID_HOST1X_CTX2 0x3a +#define TEGRA194_SID_HOST1X_CTX3 0x3b +#define TEGRA194_SID_HOST1X_CTX4 0x3c +#define TEGRA194_SID_HOST1X_CTX5 0x3d +#define TEGRA194_SID_HOST1X_CTX6 0x3e +#define TEGRA194_SID_HOST1X_CTX7 0x3f + +/* host1x command buffers */ +#define TEGRA194_SID_HOST1X_VM0 0x40 +#define TEGRA194_SID_HOST1X_VM1 0x41 +#define TEGRA194_SID_HOST1X_VM2 0x42 +#define TEGRA194_SID_HOST1X_VM3 0x43 +#define TEGRA194_SID_HOST1X_VM4 0x44 +#define TEGRA194_SID_HOST1X_VM5 0x45 +#define TEGRA194_SID_HOST1X_VM6 0x46 +#define TEGRA194_SID_HOST1X_VM7 0x47 + +/* SE data buffers */ +#define TEGRA194_SID_SE_VM0 0x48 +#define TEGRA194_SID_SE_VM1 0x49 +#define TEGRA194_SID_SE_VM2 0x4a +#define TEGRA194_SID_SE_VM3 0x4b +#define TEGRA194_SID_SE_VM4 0x4c +#define TEGRA194_SID_SE_VM5 0x4d +#define TEGRA194_SID_SE_VM6 0x4e +#define TEGRA194_SID_SE_VM7 0x4f + +#define TEGRA194_SID_MIU 0x50 + +#define TEGRA194_SID_NVDLA0 0x51 +#define TEGRA194_SID_NVDLA1 0x52 + +#define TEGRA194_SID_PVA0 0x53 +#define TEGRA194_SID_PVA1 0x54 +#define TEGRA194_SID_NVENC1 0x55 +#define TEGRA194_SID_PCIE0 0x56 +#define TEGRA194_SID_PCIE1 0x57 +#define TEGRA194_SID_PCIE2 0x58 +#define TEGRA194_SID_PCIE3 0x59 +#define TEGRA194_SID_PCIE4 0x5a +#define TEGRA194_SID_PCIE5 0x5b +#define TEGRA194_SID_NVDEC1 0x5c + +#define TEGRA194_SID_XUSB_VF0 0x5d +#define TEGRA194_SID_XUSB_VF1 0x5e +#define TEGRA194_SID_XUSB_VF2 0x5f +#define TEGRA194_SID_XUSB_VF3 0x60 + +#define TEGRA194_SID_RCE_VM3 0x61 +#define TEGRA194_SID_VI_VM2 0x62 +#define TEGRA194_SID_VI_VM3 0x63 +#define TEGRA194_SID_RCE_SERVER 0x64 + +/* + * memory client IDs + */ + +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 +/* MSS internal memqual MIU7 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 +/* MSS internal memqual MIU7 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 +/* High-definition audio (HDA) read clients */ +#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data read clients */ +#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c +/* SATA read clients */ +#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f +/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 +#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b +/* High-definition audio (HDA) write clients */ +#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 +/* SATA write clients */ +#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d +/* ISP read client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 +/* ISP read client 1 for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 +/* ISP Write client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 +/* XUSB_HOST read clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST write clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB read clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV write clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* sdmmca memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 +/* sdmmc memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 +/* sdmmcd memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 +/* sdmmc memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 +/* sdmmcd memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d +/* VI Write client */ +#define TEGRA194_MEMORY_CLIENT_VIW 0x72 +#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine read clients */ +#define TEGRA194_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine write clients */ +#define TEGRA194_MEMORY_CLIENT_APEW 0x7b +#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f +/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ +#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 +/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ +#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 +/* ETR read clients */ +#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 +/* ETR write clients */ +#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 +/* AXI Switch read client */ +#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 +/* BPMP read client */ +#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA194_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA194_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA194_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e +/* APEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 +#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 +/* MSS internal memqual MIU0 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 +/* MSS internal memqual MIU0 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 +/* MSS internal memqual MIU1 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 +/* MSS internal memqual MIU1 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 +/* MSS internal memqual MIU2 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae +/* MSS internal memqual MIU2 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf +/* MSS internal memqual MIU3 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 +/* MSS internal memqual MIU3 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 +/* MSS internal memqual MIU4 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 +/* MSS internal memqual MIU4 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 +#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 +#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 +#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 +#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 +#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 +#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 +#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba +#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb +/* VI FLACON read clients */ +#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc +/* VIFAL write clients */ +#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd +/* DLA0ARDA read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe +/* DLA0 Falcon read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf +/* DLA0 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 +/* DLA0 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 +/* DLA1ARDA read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 +/* DLA1 Falcon read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 +/* DLA1 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 +/* DLA1 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 +/* PVA0RDA read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 +/* PVA0RDB read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 +/* PVA0RDC read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 +/* PVA0WRA write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 +/* PVA0WRB write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca +/* PVA0WRC write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb +/* PVA1RDA read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc +/* PVA1RDB read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd +/* PVA1RDC read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce +/* PVA1WRA write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf +/* PVA1WRB write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 +/* PVA1WRC write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 +/* RCE read client */ +#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 +/* RCE write client */ +#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 +/* RCEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 +/* RCEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 +#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 +#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 +/* PCIE0 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 +/* PCIE0 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 +/* ISP read client 1 for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 +#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 +#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 +#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 +#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 +/* DLA0ARDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 +/* DLA1ARDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea +/* PVA0RDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb +/* PVA0RDB1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec +/* PVA1RDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed +/* PVA1RDB1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee +/* PCIE5r1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef +#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 +#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 +/* ISP read client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 +/* PCIE0 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 +#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 +#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 +#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 +#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 +#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 +#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 +#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa +#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb +/* MSS internal memqual MIU5 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc +/* MSS internal memqual MIU5 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd +/* MSS internal memqual MIU6 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe +/* MSS internal memqual MIU6 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff + +#endif From patchwork Sun Dec 22 14:10:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FVClek6m"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksf61yXz9sQp for ; Mon, 23 Dec 2019 01:10:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725922AbfLVOKp (ORCPT ); Sun, 22 Dec 2019 09:10:45 -0500 Received: from mail-wr1-f53.google.com ([209.85.221.53]:32780 "EHLO mail-wr1-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725840AbfLVOKp (ORCPT ); Sun, 22 Dec 2019 09:10:45 -0500 Received: by mail-wr1-f53.google.com with SMTP id b6so13983577wrq.0; Sun, 22 Dec 2019 06:10:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8j9eOWE07q09JFeaj2clIPgNgVmP6iqPKn1MuSSo7Oc=; b=FVClek6mKaJOjogEQLFMQAkMI/BdjhvFdPu+anfn54WLHMlADjW0cR/H0YPZczqs7n rC344yXpt8uBNgeAG1cSvhWn8IAYvqtUwGQVl5y1YMfFG4TI0RRBj+9wmakWMoBVzQdM 57qumlvrliy/fxkSSDUZmKAbV6//QUmYTkWb3ZYSVj1B8Ey+yx7rO99HCb+LCZxNC3eF PK1L4I6IJSVB5Z8iQYusGvY80EK3vj7i60yJ8095KgI8b+RSLdzIqEx9jxKQkz1/khW6 Pn043pgRI39oelRIStes3s/0YLavBij2Njm/IKfS8qP0HwrWbsBzf8R1v4tRsLtb4RMJ fLSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8j9eOWE07q09JFeaj2clIPgNgVmP6iqPKn1MuSSo7Oc=; b=avdquuZwNE0hMOBnXwmhKMmdtOAfYNegIqglfJq0ZlyF77RCrhQQLFd3DfmNBwvGq/ f7+FBV15kg47Mkl656eYxAVXaNpatMw3OvDgyMBYEl+YiUtYMMlzrQwTqfQ1T3KbxSBv qGtTkaVbGgBjAHKdX9pCrO2SpEmUIO2rrw23gSoe1/p2WrnzNEcZMQS46sKtaJPG6NFQ RohYslVSYpIJKVqblB2WZ/O8BR0qFEUXilwQfcovv/X8F5vb9jMXTk0dk2qFM1tPEBU1 eeTTwvXmWxzjBBAMKsJrxp9yLgBlDGeryAYbWb9kH690vqb0vXyHdnjBKabwhLAQDNpb 0giQ== X-Gm-Message-State: APjAAAWIQG7Jv2ZIHbkel0tstWJrerfFC8o7h5wPkwpa++Q5oDIrdgxD XBi2nvOrbolKDKt1+c+zYjY= X-Google-Smtp-Source: APXvYqwSAMiWX4D5ZDFDftFWr1MP4Lsx68aGKsyiaWVVVuw3+AJXMCYq9rsZp5L5tgh0Vbs6O7Y39w== X-Received: by 2002:a05:6000:f:: with SMTP id h15mr24397770wrx.90.1577023842589; Sun, 22 Dec 2019 06:10:42 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id c4sm16570068wml.7.2019.12.22.06.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:41 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/13] dt-bindings: memory: Add Tegra186 memory subsystem Date: Sun, 22 Dec 2019 15:10:25 +0100 Message-Id: <20191222141035.1649937-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The NVIDIA Tegra186 SoC contains a memory subsystem composed of the memory controller and the external memory controller. The memory controller provides interfaces for the memory clients to access the memory. Accesses can be either bounced through the SMMU for IOVA translation or directly to the EMC. The bulk of the programming of the external memory controller happens through interfaces exposed by the BPMP. Describe this relationship by adding a phandle reference to the BPMP to the EMC node. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../nvidia,tegra186-mc.yaml | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml new file mode 100644 index 000000000000..b98a1d03410b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) SoC Memory Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split + into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC + handles memory requests for 40-bit virtual addresses from internal clients + and arbitrates among them to allocate memory bandwidth. + + Up to 15 GiB of physical memory can be supported. Security features such as + encryption of traffic to and from DRAM via general security apertures are + available for video and other secure applications, as well as DRAM ECC for + automotive safety applications (single bit error correction and double bit + error detection). + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + items: + - enum: + - nvidia,tegra186-mc + - nvidia,tegra194-mc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + dma-ranges: true + +patternProperties: + "^external-memory-controller@[0-9a-f]+$": + description: + The bulk of the work involved in controlling the external memory + controller on NVIDIA Tegra186 and later is performed on the BPMP. This + coprocessor exposes the EMC clock that is used to set the frequency at + which the external memory is clocked and a remote procedure call that + can be used to obtain the set of available frequencies. + type: object + properties: + compatible: + items: + - enum: + - nvidia,tegra186-emc + - nvidia,tegra194-emc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: external memory clock + + clock-names: + items: + - const: emc + + nvidia,bpmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the node representing the BPMP + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + memory-controller@2c00000 { + compatible = "nvidia,tegra186-mc"; + reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = ; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>; + + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + #clock-cells = <1>; + }; From patchwork Sun Dec 22 14:10:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fPtWVoeZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksh01Ttz9sP6 for ; Mon, 23 Dec 2019 01:10:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726057AbfLVOKq (ORCPT ); Sun, 22 Dec 2019 09:10:46 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:39849 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725971AbfLVOKq (ORCPT ); Sun, 22 Dec 2019 09:10:46 -0500 Received: by mail-wm1-f65.google.com with SMTP id 20so13565686wmj.4; Sun, 22 Dec 2019 06:10:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gypWLRrVcyfmXsR2Lq/xNfZI590shTJoNFs/LRxFM9k=; b=fPtWVoeZOG+Jis11ejJC365MxwVBPDZ7g+QyhTF8O+IdzM8l2PadMus/O68hVIW7dS kExO0Sd95JI9dUPUMBZ4o2D/rgVdqaks9iXncDetUxmKh3aLr49iOb7pdIDGKNswqNdb dTv+eGmE4da/N8WeZaSeM7bnVJpuCmzju1lAFJxNysMvBFhI8tPArJ7fYy5VLHvOHRBl GJ7PL5V3b6XI604zjQ7H6S/px+QwhtWSl727uzuTeViD9fRXOx7QnwJWfcYuOILyhUBe AJu+FXRo/72xSql53PnOc6CxSfphtgYSFrDd5JdIXj0uzGc5X8uY9X9OPC3FIX67Ldbv 6Tsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gypWLRrVcyfmXsR2Lq/xNfZI590shTJoNFs/LRxFM9k=; b=FJEZX8yK3OwQREg11xrUv8Gp2m4Sxa6xGF1dNOxrn+LjFZXEfPYo+S+/DMMTpdf0W3 /obIKAU+n8wUAsFERYT0QDEgdyRXpU7NZNaUSlfDXshCB3LL8Kf/m/qQXfXuYgBtkgkz vu9Q6BYCdEnbaT0+/9Hfh4bs4BOmhCkhCxIVUG5ftiL3Bv4F494l69UUPNxM/bcOdmMY 3GWSHBHdfUDaVf2f5au+gKvErt/NCF3xP+/eu6Q618MMDy44zCPH0aDLi7sJB5IOTX1k yXcMiwF7C7cT84mvXKhdcz4RoA3anKyGStVlVzYbIxPXU0JTDyozbf6n9ei09dwcAheQ owDw== X-Gm-Message-State: APjAAAXmVRKDPHzhR1gf0BLWJ7VxNxeBzY1kTCRW4XRud97+1Q/fNWF6 OLTTWRrHg/8qaQlo3GEh1MQ= X-Google-Smtp-Source: APXvYqwfQQ/i9Xw8UCOw53luspQWYcwLDoCCJmQaYEcZnycgiR6FaeP9pkigflvubw3L7Ds34KO/fg== X-Received: by 2002:a1c:7901:: with SMTP id l1mr26455323wme.67.1577023844301; Sun, 22 Dec 2019 06:10:44 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id c4sm16570126wml.7.2019.12.22.06.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:43 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/13] memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 Date: Sun, 22 Dec 2019 15:10:26 +0100 Message-Id: <20191222141035.1649937-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This is just for consistency with the rest of the driver. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 441213a35930..f72e89877295 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -15,7 +15,7 @@ struct tegra_mc { void __iomem *regs; }; -struct tegra_mc_client { +struct tegra186_mc_client { const char *name; unsigned int sid; struct { @@ -24,7 +24,13 @@ struct tegra_mc_client { } regs; }; -static const struct tegra_mc_client tegra186_mc_clients[] = { +struct tegra186_mc { + struct memory_controller base; + struct device *dev; + void __iomem *regs; +}; + +static const struct tegra186_mc_client tegra186_mc_clients[] = { { .name = "ptcr", .sid = TEGRA186_SID_PASSTHROUGH, @@ -534,8 +540,8 @@ static const struct tegra_mc_client tegra186_mc_clients[] = { static int tegra186_mc_probe(struct platform_device *pdev) { + struct tegra186_mc *mc; struct resource *res; - struct tegra_mc *mc; unsigned int i; int err = 0; @@ -551,7 +557,7 @@ static int tegra186_mc_probe(struct platform_device *pdev) mc->dev = &pdev->dev; for (i = 0; i < ARRAY_SIZE(tegra186_mc_clients); i++) { - const struct tegra_mc_client *client = &tegra186_mc_clients[i]; + const struct tegra186_mc_client *client = &tegra186_mc_clients[i]; u32 override, security; override = readl(mc->regs + client->regs.override); From patchwork Sun Dec 22 14:10:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jwAlx0mO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksj4RLnz9sP6 for ; Mon, 23 Dec 2019 01:10:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726162AbfLVOKs (ORCPT ); Sun, 22 Dec 2019 09:10:48 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:35581 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725840AbfLVOKr (ORCPT ); Sun, 22 Dec 2019 09:10:47 -0500 Received: by mail-wm1-f66.google.com with SMTP id p17so13708576wmb.0; Sun, 22 Dec 2019 06:10:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1/mOro4NgYwnpZevvzpvIEMzpkoj/ksBreNeBpDTYAo=; b=jwAlx0mOsatYHy659lNHs1JqYLJfwOW7+lDE/v1+aWLfc/ysrbCmdr3v9o/hLAjxKP 2hUvC3lm6hWE2fyKnK61Rq36WqdvgiLx3i7w0wVik41w/8yfHrRf6/xOV7UETxhgVffA 7L2oKnsmbRGH71Tn0A61uLqXa7JDv5deudZZViRbpaWD7zBxraKtzafK91lMTiOTbMBk hgeT4eB/PY/AoFD7YodB+vafhDj8oi/TnyiqAcXakHJjxs1UATYmWNUIDbOu4YgDQKAi +OF+mCJOnzxM5lSzlouewcTgKnXMMy7U3jus6qZjZwFUQ4vRyiCNShJad+uuu5Toiu7i 850Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1/mOro4NgYwnpZevvzpvIEMzpkoj/ksBreNeBpDTYAo=; b=HYBWlUhuipVJTEZvKIB+F7fieFkMEecq1kl2OBGw+yrH75bzg1yik5c6gt1328Iqo0 di+BVIXiIgtqjBAq59NIQ2ZzFmWzm5F7B6ETcdOFXjyvXiOUXrliKBfmVZxq3pkUy2KY 2j0YTjCyHqqnmwC9jJ21s14m63KNwiqQzx23W5p3PgRoCtDyW4aG7L196qyqzrjvluuR uEDzIE1+GJiLyRVwveKpTg50GWF3cDDEXrjuLbUaAvJsLRIYmdvSvsAkBNTBNr96sGws +x4xOQz9GK7yAvb4bOCAehlMwr0jG4MeURKCiGAssC9WVR580PUHMmy9idArPbBkA7xo xZ1Q== X-Gm-Message-State: APjAAAUQq5dGGi/mkeOfHlpDM/ndkCHDHWOgczahlybh2dA7CjcU9bqt DHuERbN+X3UO5vB1kEAbf1U= X-Google-Smtp-Source: APXvYqziLMOLPfZ2htSrLwZmXGW0Pd0oOIxjqj2jMcn+NCV3zxFx4bNvvnbirf3o0UrmwIrgXs4a2Q== X-Received: by 2002:a1c:a745:: with SMTP id q66mr25711997wme.167.1577023845756; Sun, 22 Dec 2019 06:10:45 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id p18sm17057478wmb.8.2019.12.22.06.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:45 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/13] memory: tegra: Add per-SoC data for Tegra186 Date: Sun, 22 Dec 2019 15:10:27 +0100 Message-Id: <20191222141035.1649937-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Instead of hard-coding the memory client table, use per-SoC data in preparation for adding support for other SoCs. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index f72e89877295..ad5c353dba6e 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -6,15 +6,11 @@ #include #include #include +#include #include #include -struct tegra_mc { - struct device *dev; - void __iomem *regs; -}; - struct tegra186_mc_client { const char *name; unsigned int sid; @@ -24,10 +20,16 @@ struct tegra186_mc_client { } regs; }; +struct tegra186_mc_soc { + const struct tegra186_mc_client *clients; + unsigned int num_clients; +}; + struct tegra186_mc { - struct memory_controller base; struct device *dev; void __iomem *regs; + + const struct tegra186_mc_soc *soc; }; static const struct tegra186_mc_client tegra186_mc_clients[] = { @@ -538,17 +540,24 @@ static const struct tegra186_mc_client tegra186_mc_clients[] = { }, }; +static const struct tegra186_mc_soc tegra186_mc_soc = { + .num_clients = ARRAY_SIZE(tegra186_mc_clients), + .clients = tegra186_mc_clients, +}; + static int tegra186_mc_probe(struct platform_device *pdev) { struct tegra186_mc *mc; struct resource *res; unsigned int i; - int err = 0; + int err; mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); if (!mc) return -ENOMEM; + mc->soc = of_device_get_match_data(&pdev->dev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); mc->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(mc->regs)) @@ -556,8 +565,8 @@ static int tegra186_mc_probe(struct platform_device *pdev) mc->dev = &pdev->dev; - for (i = 0; i < ARRAY_SIZE(tegra186_mc_clients); i++) { - const struct tegra186_mc_client *client = &tegra186_mc_clients[i]; + for (i = 0; i < mc->soc->num_clients; i++) { + const struct tegra186_mc_client *client = &mc->soc->clients[i]; u32 override, security; override = readl(mc->regs + client->regs.override); @@ -583,7 +592,7 @@ static int tegra186_mc_probe(struct platform_device *pdev) } static const struct of_device_id tegra186_mc_of_match[] = { - { .compatible = "nvidia,tegra186-mc", }, + { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); From patchwork Sun Dec 22 14:10:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aNPLaEpg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksl01Sfz9sP6 for ; Mon, 23 Dec 2019 01:10:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725840AbfLVOKt (ORCPT ); Sun, 22 Dec 2019 09:10:49 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:35091 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725971AbfLVOKs (ORCPT ); Sun, 22 Dec 2019 09:10:48 -0500 Received: by mail-wr1-f66.google.com with SMTP id g17so13943045wro.2; Sun, 22 Dec 2019 06:10:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FvfcScGOqGCyba7I+4/EUJ/GDOw2ve0f7wiG+UB+Yk=; b=aNPLaEpgXfe75PXfHkh/q2rblg7LM/KyqESWRqdYRdmuOLmibo6GmhKl+N+OoX5chn FaN+qnTy/PFcd7Nx8kgqN2T5wCGx7ppknWZiyNaT2uMPNVp+tofRAaERrvOre/lVID3h VcDHh1pFqVuy8dVACycHeD9f5j5WFsIE7fqJzuSB+4m18d/2gHuAeCtIHYj+9H8FY8ap 6ns05TefErVRgvQl/HUuXcg+BHcnPb4kblTVwM2cmbIBtTeGbawO0GXnyKNsnxemNtoi cSggQXQHgbV8YsQ8YmrdugrpGbxnOknFh3KMr7B8GwpbvugR+z9g3/B1dc7w3hQTq28O LkFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FvfcScGOqGCyba7I+4/EUJ/GDOw2ve0f7wiG+UB+Yk=; b=BWH7txtvOWFmkoKGndjvCLi8KENR7oy6WDaf5f/KptfUCNccg/L1VDl+DP3MD4yACH 2Ooxmbg6iXjlmSn5UBhlcfNlZQ06vYOdxK+gSdWmhuQro68TQgE/KeJB8OKFloUr3wqj odYNOKi5YOobRMqeawIBwWH/6HdHC++H82eiPtVx5FDTYRsBen9SnZpW3KNJSJLg+VIY /kc97TKCo40IUyg0eux1rV3A8r2QH9CcD9FdIhGjre+3K4OTLrgb78XZjyKEF6jfBjsV q0CGH0TdaZubIGAIxZImFL092zyBADhwYAmwFHucG3A3952nVSpz95+8GHNCK6U/hbEi MXcA== X-Gm-Message-State: APjAAAWbW4wHIroUn5H6vJr6+9zkH6fp1ThNLSge58IJSOYS62IvYe6/ MmS+4i8JljNRUfI/l7CzvAU= X-Google-Smtp-Source: APXvYqwsyfdpXYdEEVQFXEvp0IDzKMoJPOqO6It1AhrUeq0ndIPicJ1AmEY9lzhoj3jt/FLdu3bitg== X-Received: by 2002:a5d:690e:: with SMTP id t14mr25345611wru.65.1577023847368; Sun, 22 Dec 2019 06:10:47 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id l17sm16860427wro.77.2019.12.22.06.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:46 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/13] memory: tegra: Extract memory client SID programming Date: Sun, 22 Dec 2019 15:10:28 +0100 Message-Id: <20191222141035.1649937-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Move programming of the memory client to SID mapping into a separate function so that it can be reused from multiple call sites. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 49 ++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index ad5c353dba6e..57895116c8e5 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -32,6 +32,32 @@ struct tegra186_mc { const struct tegra186_mc_soc *soc; }; +static void tegra186_mc_program_sid(struct tegra186_mc *mc) +{ + unsigned int i; + + for (i = 0; i < mc->soc->num_clients; i++) { + const struct tegra186_mc_client *client = &mc->soc->clients[i]; + u32 override, security; + + override = readl(mc->regs + client->regs.override); + security = readl(mc->regs + client->regs.security); + + dev_dbg(mc->dev, "client %s: override: %x security: %x\n", + client->name, override, security); + + dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid, + client->name); + writel(client->sid, mc->regs + client->regs.override); + + override = readl(mc->regs + client->regs.override); + security = readl(mc->regs + client->regs.security); + + dev_dbg(mc->dev, "client %s: override: %x security: %x\n", + client->name, override, security); + } +} + static const struct tegra186_mc_client tegra186_mc_clients[] = { { .name = "ptcr", @@ -549,7 +575,6 @@ static int tegra186_mc_probe(struct platform_device *pdev) { struct tegra186_mc *mc; struct resource *res; - unsigned int i; int err; mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); @@ -565,28 +590,8 @@ static int tegra186_mc_probe(struct platform_device *pdev) mc->dev = &pdev->dev; - for (i = 0; i < mc->soc->num_clients; i++) { - const struct tegra186_mc_client *client = &mc->soc->clients[i]; - u32 override, security; - - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); - - dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n", - client->name, override, security); - - dev_dbg(&pdev->dev, "setting SID %u for %s\n", client->sid, - client->name); - writel(client->sid, mc->regs + client->regs.override); - - override = readl(mc->regs + client->regs.override); - security = readl(mc->regs + client->regs.security); - - dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n", - client->name, override, security); - } - platform_set_drvdata(pdev, mc); + tegra186_mc_program_sid(mc); return err; } From patchwork Sun Dec 22 14:10:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214725 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gzLNJJ0Q"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksm2Zq5z9sPh for ; Mon, 23 Dec 2019 01:10:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726215AbfLVOKv (ORCPT ); Sun, 22 Dec 2019 09:10:51 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:52784 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725971AbfLVOKv (ORCPT ); Sun, 22 Dec 2019 09:10:51 -0500 Received: by mail-wm1-f65.google.com with SMTP id p9so13385947wmc.2; Sun, 22 Dec 2019 06:10:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ikfJiDpjg9QYCtJ3tEmCYkHOmVUTASh0OD5MpVkjVLU=; b=gzLNJJ0Q+KkYDQw5mVCzdY39juEHI8921wIgvSOjZnq1UQYZGK9ioW6xbd1w/pZyOc 0FTklasvkROuH4jJvbWbnzv/l8jlw/ytE9LaNk0ms+B0WE4SVnpersTg5bb6c6prdwu/ 7qhUoU6YDXcQ9GaiNxFL2uVuy5/6zbiwjfXR+AyIcmWKaqxG87IIPFDfhMZt7Sp65zzr Ac3OLh/kvNmUAMfD13U1nVS3q0GT+in7M7LFeQjeY0F6wkGiRokwV2TGK21hDkLIgLUh xM02vCWaEXRAUPHS17wOr4APBbYGsdv+rHwPImkyemBUhN+aarFT2XQlCST7n0FP3ceE WGXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ikfJiDpjg9QYCtJ3tEmCYkHOmVUTASh0OD5MpVkjVLU=; b=jXIiuUw+hiNenOsP+hEIebElzirdiuooQjo4Z9iM+arF2Q7LmIuqlwsLBh3Ii0/IWX GybJYsWsd8KkiTdaA2AMjZXxWVD+YXKDYo16FAfxW+2LtF6t3dkAfaAGKlCER5NjRIFU UOf25ku+tb8tHCcUGjaJY12/ryg3MrRJNFln9MPfOHCEOk2MqOAM4XIQQ7YIWVtlU0pR a3ygz+/gRCCcFVDP6L/unCGrlAjcHPMzxcmO47K6Ybr4K9XYnO11ciyfb/W1ai/N3mVX gQvB+85Wk9jN36AbH9A4s8z3f5JyslaiVP5+0urkVISfN7VTpzk5QvcMvGEjlnoHTAUh KuIA== X-Gm-Message-State: APjAAAWCQwJgTbNe1hjL3k1xfd2TPWF4Yoz2ZMsMbd0YgNskYz6D29rE zOjBeaSc9+5NhDcqVq5AVR0= X-Google-Smtp-Source: APXvYqxH/UjRNAHzS217dwm1H2UKxNF5l3vyB9FvGUpFv1KPJJBP0SrEThecMZsb/8psOPk7oPR+eg== X-Received: by 2002:a1c:9d8b:: with SMTP id g133mr25936600wme.27.1577023849320; Sun, 22 Dec 2019 06:10:49 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id t190sm16546496wmt.44.2019.12.22.06.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:48 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/13] memory: tegra: Add system sleep support Date: Sun, 22 Dec 2019 15:10:29 +0100 Message-Id: <20191222141035.1649937-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 57895116c8e5..77a313f1bf0e 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -602,10 +602,29 @@ static const struct of_device_id tegra186_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); +static int tegra186_mc_suspend(struct device *dev) +{ + return 0; +} + +static int tegra186_mc_resume(struct device *dev) +{ + struct tegra186_mc *mc = dev_get_drvdata(dev); + + tegra186_mc_program_sid(mc); + + return 0; +} + +static const struct dev_pm_ops tegra186_mc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume) +}; + static struct platform_driver tegra186_mc_driver = { .driver = { .name = "tegra186-mc", .of_match_table = tegra186_mc_of_match, + .pm = &tegra186_mc_pm_ops, .suppress_bind_attrs = true, }, .prevent_deferred_probe = true, From patchwork Sun Dec 22 14:10:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kKqQD1zO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksr1trBz9sPh for ; Mon, 23 Dec 2019 01:10:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726449AbfLVOKy (ORCPT ); Sun, 22 Dec 2019 09:10:54 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:35587 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725971AbfLVOKy (ORCPT ); Sun, 22 Dec 2019 09:10:54 -0500 Received: by mail-wm1-f68.google.com with SMTP id p17so13708694wmb.0; Sun, 22 Dec 2019 06:10:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JLC9lrfgfa+2fElLPLarspKF7TQ1WkQucfGmNyEr9Uk=; b=kKqQD1zOEreP5iquZSfmgcIFiBhPielW5AH6uYfDjnIG7eYduLjCL6pGSReVyXQa8a nw5IWl0HyBfVC6jweaFYqE+pL+kltVdjd6bTi7pvAEv8UCImL5Op/8yZvm4L4kSU0A4l HBoYZ7B3vYhn76pNj+fXICXKY0jn3HJtnoA7stRI6JZJeCbbswSeUgWqodTHZji9fCpU 2JCVLb6lRCq5tD6f3p+LSWNPuR3jl6w5svw4txOIZ9wsL3FPFLryR5bZUSQlkEluPmvU LXWKsfktvwqHpIRd9Y4AOwIldBq6zTOf9bnUEmqDV5KOaq4M9tRfC8VXAupTCLz9pDd+ rZBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JLC9lrfgfa+2fElLPLarspKF7TQ1WkQucfGmNyEr9Uk=; b=RPo1r6XnwmSXOM24Htbf15xk+MmvidT2F7xmnsC85yAxfCpmG0gdH6VYwHM8FlUD5l zTLF2jfdEzA2YgJi70eHxkoNRaEfHdJa2C4nUXG953p+V609Mh80PvIXfYHNHert5ydv 0Sx4KQtf31ORy7VoujY5YAyk1KQ8v0seR3iewAoaadu7ZecefWScuDMX4VQpL6cWE2Vu 7xdTVE4el0x3/wRqtmFoEod3PgSg6lT5dv/299I1CXqCOw7kEFzMSOwrMthLqQ5zcXNz c/If2W4MhtkKyEWYguOei9Na19r5fzmaVzR/XrNdkhk0eedDFfRFX0x3HFwKuPfTSUsd rR5Q== X-Gm-Message-State: APjAAAXaO+nXPgu6sbAcOj0gWnEmMlOERB1FkfFRciKlsFjq2oYTZRiR s4glo46KqEkqxZ9boCZX1HM= X-Google-Smtp-Source: APXvYqwBRmwTbjUnDp5jtx10uNYp9R4cN72PPj6UG0lyFTQkx+UpBscLGA+TYgYRqdeEVHFaI31wxQ== X-Received: by 2002:a1c:f210:: with SMTP id s16mr3482950wmc.57.1577023850885; Sun, 22 Dec 2019 06:10:50 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id p7sm16356242wmp.31.2019.12.22.06.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:50 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/13] memory: tegra: Support DVFS on Tegra186 and later Date: Sun, 22 Dec 2019 15:10:30 +0100 Message-Id: <20191222141035.1649937-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding --- drivers/memory/tegra/Makefile | 2 +- drivers/memory/tegra/tegra186-emc.c | 288 ++++++++++++++++++++++++++++ drivers/memory/tegra/tegra186.c | 20 +- 3 files changed, 308 insertions(+), 2 deletions(-) create mode 100644 drivers/memory/tegra/tegra186-emc.c diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 3d23c4261104..1a5e112f6196 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -13,4 +13,4 @@ obj-$(CONFIG_TEGRA_MC) += tegra-mc.o obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o -obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o +obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c new file mode 100644 index 000000000000..a3f275a7b4d6 --- /dev/null +++ b/drivers/memory/tegra/tegra186-emc.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +struct tegra186_emc_dvfs { + unsigned long latency; + unsigned long rate; +}; + +struct tegra186_emc { + struct tegra_bpmp *bpmp; + struct device *dev; + struct clk *clk; + + struct tegra186_emc_dvfs *dvfs; + unsigned int num_dvfs; + + struct { + struct dentry *root; + unsigned long min_rate; + unsigned long max_rate; + } debugfs; +}; + +/* + * debugfs interface + * + * The memory controller driver exposes some files in debugfs that can be used + * to control the EMC frequency. The top-level directory can be found here: + * + * /sys/kernel/debug/emc + * + * It contains the following files: + * + * - available_rates: This file contains a list of valid, space-separated + * EMC frequencies. + * + * - min_rate: Writing a value to this file sets the given frequency as the + * floor of the permitted range. If this is higher than the currently + * configured EMC frequency, this will cause the frequency to be + * increased so that it stays within the valid range. + * + * - max_rate: Similarily to the min_rate file, writing a value to this file + * sets the given frequency as the ceiling of the permitted range. If + * the value is lower than the currently configured EMC frequency, this + * will cause the frequency to be decreased so that it stays within the + * valid range. + */ + +static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, + unsigned long rate) +{ + unsigned int i; + + for (i = 0; i < emc->num_dvfs; i++) + if (rate == emc->dvfs[i].rate) + return true; + + return false; +} + +static int tegra186_emc_debug_available_rates_show(struct seq_file *s, + void *data) +{ + struct tegra186_emc *emc = s->private; + const char *prefix = ""; + unsigned int i; + + for (i = 0; i < emc->num_dvfs; i++) { + seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate); + prefix = " "; + } + + seq_puts(s, "\n"); + + return 0; +} + +static int tegra186_emc_debug_available_rates_open(struct inode *inode, + struct file *file) +{ + return single_open(file, tegra186_emc_debug_available_rates_show, + inode->i_private); +} + +static const struct file_operations tegra186_emc_debug_available_rates_fops = { + .open = tegra186_emc_debug_available_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate) +{ + struct tegra186_emc *emc = data; + + *rate = emc->debugfs.min_rate; + + return 0; +} + +static int tegra186_emc_debug_min_rate_set(void *data, u64 rate) +{ + struct tegra186_emc *emc = data; + int err; + + if (!tegra186_emc_validate_rate(emc, rate)) + return -EINVAL; + + err = clk_set_min_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.min_rate = rate; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_min_rate_fops, + tegra186_emc_debug_min_rate_get, + tegra186_emc_debug_min_rate_set, "%llu\n"); + +static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate) +{ + struct tegra186_emc *emc = data; + + *rate = emc->debugfs.max_rate; + + return 0; +} + +static int tegra186_emc_debug_max_rate_set(void *data, u64 rate) +{ + struct tegra186_emc *emc = data; + int err; + + if (!tegra186_emc_validate_rate(emc, rate)) + return -EINVAL; + + err = clk_set_max_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.max_rate = rate; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, + tegra186_emc_debug_max_rate_get, + tegra186_emc_debug_max_rate_set, "%llu\n"); + +static int tegra186_emc_probe(struct platform_device *pdev) +{ + struct mrq_emc_dvfs_latency_response response; + struct tegra_bpmp_message msg; + struct tegra186_emc *emc; + unsigned int i; + int err; + + emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); + if (!emc) + return -ENOMEM; + + emc->bpmp = tegra_bpmp_get(&pdev->dev); + if (IS_ERR(emc->bpmp)) { + err = PTR_ERR(emc->bpmp); + + if (err != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get BPMP: %d\n", err); + + return err; + } + + emc->clk = devm_clk_get(&pdev->dev, "emc"); + if (IS_ERR(emc->clk)) { + err = PTR_ERR(emc->clk); + dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err); + return err; + } + + platform_set_drvdata(pdev, emc); + emc->dev = &pdev->dev; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_EMC_DVFS_LATENCY; + msg.tx.data = NULL; + msg.tx.size = 0; + msg.rx.data = &response; + msg.rx.size = sizeof(response); + + err = tegra_bpmp_transfer(emc->bpmp, &msg); + if (err < 0) { + dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); + return err; + } + + emc->debugfs.min_rate = ULONG_MAX; + emc->debugfs.max_rate = 0; + + emc->num_dvfs = response.num_pairs; + + emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, + sizeof(*emc->dvfs), GFP_KERNEL); + if (!emc->dvfs) + return -ENOMEM; + + dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); + + for (i = 0; i < emc->num_dvfs; i++) { + emc->dvfs[i].rate = response.pairs[i].freq * 1000; + emc->dvfs[i].latency = response.pairs[i].latency; + + if (emc->dvfs[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->dvfs[i].rate; + + if (emc->dvfs[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->dvfs[i].rate; + + dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, + emc->dvfs[i].rate, emc->dvfs[i].latency); + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, + emc->debugfs.max_rate); + if (err < 0) { + dev_err(&pdev->dev, + "failed to set rate range [%lu-%lu] for %pC\n", + emc->debugfs.min_rate, emc->debugfs.max_rate, + emc->clk); + return err; + } + + emc->debugfs.root = debugfs_create_dir("emc", NULL); + if (!emc->debugfs.root) { + dev_err(&pdev->dev, "failed to create debugfs directory\n"); + return 0; + } + + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, + emc, &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_max_rate_fops); + + return 0; +} + +static int tegra186_emc_remove(struct platform_device *pdev) +{ + struct tegra186_emc *emc = platform_get_drvdata(pdev); + + debugfs_remove_recursive(emc->debugfs.root); + tegra_bpmp_put(emc->bpmp); + + return 0; +} + +static const struct of_device_id tegra186_emc_of_match[] = { + { .compatible = "nvidia,tegra186-emc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra186_emc_of_match); + +static struct platform_driver tegra186_emc_driver = { + .driver = { + .name = "tegra186-emc", + .of_match_table = tegra186_emc_of_match, + .suppress_bind_attrs = true, + }, + .probe = tegra186_emc_probe, + .remove = tegra186_emc_remove, +}; +module_platform_driver(tegra186_emc_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 77a313f1bf0e..a727f0925276 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -590,12 +590,30 @@ static int tegra186_mc_probe(struct platform_device *pdev) mc->dev = &pdev->dev; + err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (err < 0) + goto unregister; + platform_set_drvdata(pdev, mc); tegra186_mc_program_sid(mc); + return 0; + +unregister: + memory_controller_unregister(&mc->base); return err; } +static int tegra186_mc_remove(struct platform_device *pdev) +{ + struct tegra186_mc *mc = platform_get_drvdata(pdev); + + of_platform_depopulate(mc->dev); + memory_controller_unregister(&mc->base); + + return 0; +} + static const struct of_device_id tegra186_mc_of_match[] = { { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, { /* sentinel */ } @@ -627,8 +645,8 @@ static struct platform_driver tegra186_mc_driver = { .pm = &tegra186_mc_pm_ops, .suppress_bind_attrs = true, }, - .prevent_deferred_probe = true, .probe = tegra186_mc_probe, + .remove = tegra186_mc_remove, }; module_platform_driver(tegra186_mc_driver); From patchwork Sun Dec 22 14:10:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pqkswmr4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksq0hqhz9sP6 for ; Mon, 23 Dec 2019 01:10:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726393AbfLVOKy (ORCPT ); Sun, 22 Dec 2019 09:10:54 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43316 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726449AbfLVOKy (ORCPT ); Sun, 22 Dec 2019 09:10:54 -0500 Received: by mail-wr1-f66.google.com with SMTP id d16so13911461wre.10; Sun, 22 Dec 2019 06:10:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aNNkzdmoZGfEvwyeSAAoGpupKiOvMsZG3DgnjeluIjA=; b=pqkswmr4T9zR4ih6X3amPK5UcPQzY1rWkOC5jnAbU9sVpVWynAHpbQ1ewIfagmeqtW Rkvth87jP3v48uXh0B1Upbytpykih/0pw4aRSF9LMET8zIc0sLSQ6BLdMOejF4qHPQoE 2n6a+LDLDEEkxCNv93qlxuv+kvn70e9RkMaRQlQCZmzjrzZslKCIazIustcGAaxxaBJE fliRE9Y2cN3e9AAFyZq8EcrHbY9X8so4gCRS21okAC8PCg6dmifWg15nHHrRAfvsilGN gH8ER+JB522Mp2nHOeZQPMYdFG/7YdzsWoroCAtAkkAnka7BnAntOwX0JxgcUHaDfG8m tkmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aNNkzdmoZGfEvwyeSAAoGpupKiOvMsZG3DgnjeluIjA=; b=TqfP/iZnzuJwGnmVTx9nrbKe7Bqk7KVbyikDXyb4egdwOT3QsmzTs7FjQRbaX+Z7KK p3SjJ4GxOQXBAdyz2yEE73g5nQsM4YtmA9sQr4cX2rrr9mdmBluUjvrLQls5n8wiKAiv WqAjsh9r9Wn5tQq19Gvj30o5IZvHdrlZIsodNsymmeZKSphm85wEBreyye6UNqjCN2v7 NEk9fcLnloRS3S5B8B9Gn+0htUZLwWijcFNkuWQnCsroxscnUf/Padmrbq3f4ySMke5D eAbQr6n/Tu+ip2vNg3+rwym/gnE97TcrYtrNrzWLwuSvpa3GCObtTMeFbPqIRe8hq7b6 dZcw== X-Gm-Message-State: APjAAAWCjdTAdYFUPx2vlqxfSyI1TCUB+OFameBA2nW7u2GqiWvznacE so1LEsImwNPTD1vnUqEGEmk= X-Google-Smtp-Source: APXvYqxEiakSXD9oiQQ5Wrwmum38SiaGapo+YQu1G840m6nf9h0khaL2V8wnzpS5mqPdFDdSmemqTw== X-Received: by 2002:a5d:5403:: with SMTP id g3mr25727058wrv.302.1577023852472; Sun, 22 Dec 2019 06:10:52 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id q11sm17308214wrp.24.2019.12.22.06.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:51 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/13] memory: tegra: Only include support for enabled SoCs Date: Sun, 22 Dec 2019 15:10:31 +0100 Message-Id: <20191222141035.1649937-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186-emc.c | 2 ++ drivers/memory/tegra/tegra186.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index a3f275a7b4d6..812a4e152dcb 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -267,7 +267,9 @@ static int tegra186_emc_remove(struct platform_device *pdev) } static const struct of_device_id tegra186_emc_of_match[] = { +#if defined(CONFIG_ARCH_TEGRA186_SOC) { .compatible = "nvidia,tegra186-emc" }, +#endif { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, tegra186_emc_of_match); diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index a727f0925276..9c9a2f54b6fc 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -9,7 +9,9 @@ #include #include +#if defined(CONFIG_ARCH_TEGRA_186_SOC) #include +#endif struct tegra186_mc_client { const char *name; @@ -58,6 +60,7 @@ static void tegra186_mc_program_sid(struct tegra186_mc *mc) } } +#if defined(CONFIG_ARCH_TEGRA_186_SOC) static const struct tegra186_mc_client tegra186_mc_clients[] = { { .name = "ptcr", @@ -570,6 +573,7 @@ static const struct tegra186_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, }; +#endif static int tegra186_mc_probe(struct platform_device *pdev) { @@ -615,7 +619,9 @@ static int tegra186_mc_remove(struct platform_device *pdev) } static const struct of_device_id tegra186_mc_of_match[] = { +#if defined(CONFIG_ARCH_TEGRA_186_SOC) { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#endif { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); From patchwork Sun Dec 22 14:10:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214730 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="el3gY7ht"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksv5SNwz9sPh for ; Mon, 23 Dec 2019 01:10:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726632AbfLVOK6 (ORCPT ); Sun, 22 Dec 2019 09:10:58 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:44474 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725971AbfLVOK6 (ORCPT ); Sun, 22 Dec 2019 09:10:58 -0500 Received: by mail-wr1-f65.google.com with SMTP id q10so13923826wrm.11; Sun, 22 Dec 2019 06:10:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QsHmATglC+CsY8GxIs0+y5YwYExVek8iDDm6BClbEA8=; b=el3gY7htjRq3cf6LrN/Oq/0Vribt57alob1/UlIki9EPc0sjYdqDGKd8O/0YZdCR1G mo1/Cv7EqSWL7SBzO7h/2CB8lDbr0oI3iI32Wj+kRbNHO/EjpskZBbj3xMZC+HIdI/iu PPLe+DRnaqFQaE/T67jF9Ssl5z9v2NVuOVQBK+EvdfbHHAUR+a25nXuN8eWXetTOMV/r H2v/PJZMxvXS3J/FhTi17oLyXquHn3XZVvQP8Rny2tuvEH16yjnR7SlCIsAm3Fv2Gmt3 cjYKNoZvjY29R2pe+xTASHsFtMfS1dsxMDmJhIpqBr5NTTrk+MSiPXT/uJgJ0ipP1CHV 51jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QsHmATglC+CsY8GxIs0+y5YwYExVek8iDDm6BClbEA8=; b=ghw4Z5h1zwlV/YyHkL5HVM20JWpbLDP7tvclgSAARgtsUgC7tBhSBhMvV15qQe6/gv TabJA4ryyRIa1meQgtrPq4s0i7xHD9CbdqGf7jrvEtEFIJe5PLjlJ5G6I7X8gsoQ2wvu fXZUZ1oHXDTjATcEQ7Js78pi0pilMXVIBn/PiteEg9h1HqQObwOgmQcS+dL2HPVZrBV8 sWhYxxHs/H1oLGIRYVrGHIr/f90ZhY5hoAkm8cupFqqcUF4L7GYSnWhTGkUjLD03u04b ovgNAtG9lbiStLQDIlLdElXAw6jPsvSss/DtVRjgjXTTVJBKyncgXoVgIJXlJutuz/nR TypA== X-Gm-Message-State: APjAAAVIcaFZ5qp+JmAETAZBrzvDmi3zJOh4siqMXEmAndxAFmuQtuyW r5fiKvDsSA3IVGuIIqk04Sk= X-Google-Smtp-Source: APXvYqzwQ+tlxPrFejM68zbOHLrKEKY7xk0X055GDBFpHDmC4+sSv3EQ/0bPe4nZr6MLlSMhqJ1AgA== X-Received: by 2002:a5d:6802:: with SMTP id w2mr25052941wru.353.1577023854205; Sun, 22 Dec 2019 06:10:54 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id z11sm16993394wrt.82.2019.12.22.06.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:53 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/13] memory: tegra: Add support for the Tegra194 memory controller Date: Sun, 22 Dec 2019 15:10:32 +0100 Message-Id: <20191222141035.1649937-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding --- drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra186-emc.c | 3 + drivers/memory/tegra/tegra186.c | 1041 +++++++++++++++++++++++++-- 3 files changed, 999 insertions(+), 46 deletions(-) diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 1a5e112f6196..529d10bc5650 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 812a4e152dcb..97f26bc77ad4 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -269,6 +269,9 @@ static int tegra186_emc_remove(struct platform_device *pdev) static const struct of_device_id tegra186_emc_of_match[] = { #if defined(CONFIG_ARCH_TEGRA186_SOC) { .compatible = "nvidia,tegra186-emc" }, +#endif +#if defined(CONFIG_ARCH_TEGRA194_SOC) + { .compatible = "nvidia,tegra194-emc" }, #endif { /* sentinel */ } }; diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 9c9a2f54b6fc..8b4dcc3d02ae 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -13,6 +13,10 @@ #include #endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC) +#include +#endif + struct tegra186_mc_client { const char *name; unsigned int sid; @@ -575,52 +579,997 @@ static const struct tegra186_mc_soc tegra186_mc_soc = { }; #endif -static int tegra186_mc_probe(struct platform_device *pdev) -{ - struct tegra186_mc *mc; - struct resource *res; - int err; - - mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); - if (!mc) - return -ENOMEM; - - mc->soc = of_device_get_match_data(&pdev->dev); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mc->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mc->regs)) - return PTR_ERR(mc->regs); - - mc->dev = &pdev->dev; - - err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); - if (err < 0) - goto unregister; - - platform_set_drvdata(pdev, mc); - tegra186_mc_program_sid(mc); - - return 0; - -unregister: - memory_controller_unregister(&mc->base); - return err; -} - -static int tegra186_mc_remove(struct platform_device *pdev) -{ - struct tegra186_mc *mc = platform_get_drvdata(pdev); - - of_platform_depopulate(mc->dev); - memory_controller_unregister(&mc->base); - - return 0; -} - -static const struct of_device_id tegra186_mc_of_match[] = { -#if defined(CONFIG_ARCH_TEGRA_186_SOC) - { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#if defined(CONFIG_ARCH_TEGRA_194_SOC) +static const struct tegra186_mc_client tegra194_mc_clients[] = { + { + .name = "ptcr", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x000, + .security = 0x004, + }, + }, { + .name = "miu7r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x008, + .security = 0x00c, + }, + }, { + .name = "miu7w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x010, + .security = 0x014, + }, + }, { + .name = "hdar", + .sid = TEGRA194_SID_HDA, + .regs = { + .override = 0x0a8, + .security = 0x0ac, + }, + }, { + .name = "host1xdmar", + .sid = TEGRA194_SID_HOST1X, + .regs = { + .override = 0x0b0, + .security = 0x0b4, + }, + }, { + .name = "nvencsrd", + .sid = TEGRA194_SID_NVENC, + .regs = { + .override = 0x0e0, + .security = 0x0e4, + }, + }, { + .name = "satar", + .sid = TEGRA194_SID_SATA, + .regs = { + .override = 0x0f8, + .security = 0x0fc, + }, + }, { + .name = "mpcorer", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x138, + .security = 0x13c, + }, + }, { + .name = "nvencswr", + .sid = TEGRA194_SID_NVENC, + .regs = { + .override = 0x158, + .security = 0x15c, + }, + }, { + .name = "hdaw", + .sid = TEGRA194_SID_HDA, + .regs = { + .override = 0x1a8, + .security = 0x1ac, + }, + }, { + .name = "mpcorew", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x1c8, + .security = 0x1cc, + }, + }, { + .name = "sataw", + .sid = TEGRA194_SID_SATA, + .regs = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, { + .name = "ispra", + .sid = TEGRA194_SID_ISP, + .regs = { + .override = 0x220, + .security = 0x224, + }, + }, { + .name = "ispfalr", + .sid = TEGRA194_SID_ISP_FALCON, + .regs = { + .override = 0x228, + .security = 0x22c, + }, + }, { + .name = "ispwa", + .sid = TEGRA194_SID_ISP, + .regs = { + .override = 0x230, + .security = 0x234, + }, + }, { + .name = "ispwb", + .sid = TEGRA194_SID_ISP, + .regs = { + .override = 0x238, + .security = 0x23c, + }, + }, { + .name = "xusb_hostr", + .sid = TEGRA194_SID_XUSB_HOST, + .regs = { + .override = 0x250, + .security = 0x254, + }, + }, { + .name = "xusb_hostw", + .sid = TEGRA194_SID_XUSB_HOST, + .regs = { + .override = 0x258, + .security = 0x25c, + }, + }, { + .name = "xusb_devr", + .sid = TEGRA194_SID_XUSB_DEV, + .regs = { + .override = 0x260, + .security = 0x264, + }, + }, { + .name = "xusb_devw", + .sid = TEGRA194_SID_XUSB_DEV, + .regs = { + .override = 0x268, + .security = 0x26c, + }, + }, { + .name = "sdmmcra", + .sid = TEGRA194_SID_SDMMC1, + .regs = { + .override = 0x300, + .security = 0x304, + }, + }, { + .name = "sdmmcr", + .sid = TEGRA194_SID_SDMMC3, + .regs = { + .override = 0x310, + .security = 0x314, + }, + }, { + .name = "sdmmcrab", + .sid = TEGRA194_SID_SDMMC4, + .regs = { + .override = 0x318, + .security = 0x31c, + }, + }, { + .name = "sdmmcwa", + .sid = TEGRA194_SID_SDMMC1, + .regs = { + .override = 0x320, + .security = 0x324, + }, + }, { + .name = "sdmmcw", + .sid = TEGRA194_SID_SDMMC3, + .regs = { + .override = 0x330, + .security = 0x334, + }, + }, { + .name = "sdmmcwab", + .sid = TEGRA194_SID_SDMMC4, + .regs = { + .override = 0x338, + .security = 0x33c, + }, + }, { + .name = "vicsrd", + .sid = TEGRA194_SID_VIC, + .regs = { + .override = 0x360, + .security = 0x364, + }, + }, { + .name = "vicswr", + .sid = TEGRA194_SID_VIC, + .regs = { + .override = 0x368, + .security = 0x36c, + }, + }, { + .name = "viw", + .sid = TEGRA194_SID_VI, + .regs = { + .override = 0x390, + .security = 0x394, + }, + }, { + .name = "nvdecsrd", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, { + .name = "nvdecswr", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, { + .name = "aper", + .sid = TEGRA194_SID_APE, + .regs = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, { + .name = "apew", + .sid = TEGRA194_SID_APE, + .regs = { + .override = 0x3d0, + .security = 0x3d4, + }, + }, { + .name = "nvjpgsrd", + .sid = TEGRA194_SID_NVJPG, + .regs = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, { + .name = "nvjpgswr", + .sid = TEGRA194_SID_NVJPG, + .regs = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, { + .name = "axiapr", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x410, + .security = 0x414, + }, + }, { + .name = "axiapw", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x418, + .security = 0x41c, + }, + }, { + .name = "etrr", + .sid = TEGRA194_SID_ETR, + .regs = { + .override = 0x420, + .security = 0x424, + }, + }, { + .name = "etrw", + .sid = TEGRA194_SID_ETR, + .regs = { + .override = 0x428, + .security = 0x42c, + }, + }, { + .name = "axisr", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x460, + .security = 0x464, + }, + }, { + .name = "axisw", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x468, + .security = 0x46c, + }, + }, { + .name = "eqosr", + .sid = TEGRA194_SID_EQOS, + .regs = { + .override = 0x470, + .security = 0x474, + }, + }, { + .name = "eqosw", + .sid = TEGRA194_SID_EQOS, + .regs = { + .override = 0x478, + .security = 0x47c, + }, + }, { + .name = "ufshcr", + .sid = TEGRA194_SID_UFSHC, + .regs = { + .override = 0x480, + .security = 0x484, + }, + }, { + .name = "ufshcw", + .sid = TEGRA194_SID_UFSHC, + .regs = { + .override = 0x488, + .security = 0x48c, + }, + }, { + .name = "nvdisplayr", + .sid = TEGRA194_SID_NVDISPLAY, + .regs = { + .override = 0x490, + .security = 0x494, + }, + }, { + .name = "bpmpr", + .sid = TEGRA194_SID_BPMP, + .regs = { + .override = 0x498, + .security = 0x49c, + }, + }, { + .name = "bpmpw", + .sid = TEGRA194_SID_BPMP, + .regs = { + .override = 0x4a0, + .security = 0x4a4, + }, + }, { + .name = "bpmpdmar", + .sid = TEGRA194_SID_BPMP, + .regs = { + .override = 0x4a8, + .security = 0x4ac, + }, + }, { + .name = "bpmpdmaw", + .sid = TEGRA194_SID_BPMP, + .regs = { + .override = 0x4b0, + .security = 0x4b4, + }, + }, { + .name = "aonr", + .sid = TEGRA194_SID_AON, + .regs = { + .override = 0x4b8, + .security = 0x4bc, + }, + }, { + .name = "aonw", + .sid = TEGRA194_SID_AON, + .regs = { + .override = 0x4c0, + .security = 0x4c4, + }, + }, { + .name = "aondmar", + .sid = TEGRA194_SID_AON, + .regs = { + .override = 0x4c8, + .security = 0x4cc, + }, + }, { + .name = "aondmaw", + .sid = TEGRA194_SID_AON, + .regs = { + .override = 0x4d0, + .security = 0x4d4, + }, + }, { + .name = "scer", + .sid = TEGRA194_SID_SCE, + .regs = { + .override = 0x4d8, + .security = 0x4dc, + }, + }, { + .name = "scew", + .sid = TEGRA194_SID_SCE, + .regs = { + .override = 0x4e0, + .security = 0x4e4, + }, + }, { + .name = "scedmar", + .sid = TEGRA194_SID_SCE, + .regs = { + .override = 0x4e8, + .security = 0x4ec, + }, + }, { + .name = "scedmaw", + .sid = TEGRA194_SID_SCE, + .regs = { + .override = 0x4f0, + .security = 0x4f4, + }, + }, { + .name = "apedmar", + .sid = TEGRA194_SID_APE, + .regs = { + .override = 0x4f8, + .security = 0x4fc, + }, + }, { + .name = "apedmaw", + .sid = TEGRA194_SID_APE, + .regs = { + .override = 0x500, + .security = 0x504, + }, + }, { + .name = "nvdisplayr1", + .sid = TEGRA194_SID_NVDISPLAY, + .regs = { + .override = 0x508, + .security = 0x50c, + }, + }, { + .name = "vicsrd1", + .sid = TEGRA194_SID_VIC, + .regs = { + .override = 0x510, + .security = 0x514, + }, + }, { + .name = "nvdecsrd1", + .sid = TEGRA194_SID_NVDEC, + .regs = { + .override = 0x518, + .security = 0x51c, + }, + }, { + .name = "miu0r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x530, + .security = 0x534, + }, + }, { + .name = "miu0w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x538, + .security = 0x53c, + }, + }, { + .name = "miu1r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x540, + .security = 0x544, + }, + }, { + .name = "miu1w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x548, + .security = 0x54c, + }, + }, { + .name = "miu2r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x570, + .security = 0x574, + }, + }, { + .name = "miu2w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x578, + .security = 0x57c, + }, + }, { + .name = "miu3r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x580, + .security = 0x584, + }, + }, { + .name = "miu3w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x588, + .security = 0x58c, + }, + }, { + .name = "miu4r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x590, + .security = 0x594, + }, + }, { + .name = "miu4w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x598, + .security = 0x59c, + }, + }, { + .name = "dpmur", + .sid = TEGRA194_SID_PASSTHROUGH, + .regs = { + .override = 0x598, + .security = 0x59c, + }, + }, { + .name = "vifalr", + .sid = TEGRA194_SID_VI_FALCON, + .regs = { + .override = 0x5e0, + .security = 0x5e4, + }, + }, { + .name = "vifalw", + .sid = TEGRA194_SID_VI_FALCON, + .regs = { + .override = 0x5e8, + .security = 0x5ec, + }, + }, { + .name = "dla0rda", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .override = 0x5f0, + .security = 0x5f4, + }, + }, { + .name = "dla0falrdb", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .override = 0x5f8, + .security = 0x5fc, + }, + }, { + .name = "dla0wra", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .override = 0x600, + .security = 0x604, + }, + }, { + .name = "dla0falwrb", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .override = 0x608, + .security = 0x60c, + }, + }, { + .name = "dla1rda", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .override = 0x610, + .security = 0x614, + }, + }, { + .name = "dla1falrdb", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .override = 0x618, + .security = 0x61c, + }, + }, { + .name = "dla1wra", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .override = 0x620, + .security = 0x624, + }, + }, { + .name = "dla1falwrb", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .override = 0x628, + .security = 0x62c, + }, + }, { + .name = "pva0rda", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x630, + .security = 0x634, + }, + }, { + .name = "pva0rdb", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x638, + .security = 0x63c, + }, + }, { + .name = "pva0rdc", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x640, + .security = 0x644, + }, + }, { + .name = "pva0wra", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x648, + .security = 0x64c, + }, + }, { + .name = "pva0wrb", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x650, + .security = 0x654, + }, + }, { + .name = "pva0wrc", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x658, + .security = 0x65c, + }, + }, { + .name = "pva1rda", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x660, + .security = 0x664, + }, + }, { + .name = "pva1rdb", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x668, + .security = 0x66c, + }, + }, { + .name = "pva1rdc", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x670, + .security = 0x674, + }, + }, { + .name = "pva1wra", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x678, + .security = 0x67c, + }, + }, { + .name = "pva1wrb", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x680, + .security = 0x684, + }, + }, { + .name = "pva1wrc", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x688, + .security = 0x68c, + }, + }, { + .name = "rcer", + .sid = TEGRA194_SID_RCE, + .regs = { + .override = 0x690, + .security = 0x694, + }, + }, { + .name = "rcew", + .sid = TEGRA194_SID_RCE, + .regs = { + .override = 0x698, + .security = 0x69c, + }, + }, { + .name = "rcedmar", + .sid = TEGRA194_SID_RCE, + .regs = { + .override = 0x6a0, + .security = 0x6a4, + }, + }, { + .name = "rcedmaw", + .sid = TEGRA194_SID_RCE, + .regs = { + .override = 0x6a8, + .security = 0x6ac, + }, + }, { + .name = "nvenc1srd", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .override = 0x6b0, + .security = 0x6b4, + }, + }, { + .name = "nvenc1swr", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .override = 0x6b8, + .security = 0x6bc, + }, + }, { + .name = "pcie0r", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .override = 0x6c0, + .security = 0x6c4, + }, + }, { + .name = "pcie0w", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .override = 0x6c8, + .security = 0x6cc, + }, + }, { + .name = "pcie1r", + .sid = TEGRA194_SID_PCIE1, + .regs = { + .override = 0x6d0, + .security = 0x6d4, + }, + }, { + .name = "pcie1w", + .sid = TEGRA194_SID_PCIE1, + .regs = { + .override = 0x6d8, + .security = 0x6dc, + }, + }, { + .name = "pcie2ar", + .sid = TEGRA194_SID_PCIE2, + .regs = { + .override = 0x6e0, + .security = 0x6e4, + }, + }, { + .name = "pcie2aw", + .sid = TEGRA194_SID_PCIE2, + .regs = { + .override = 0x6e8, + .security = 0x6ec, + }, + }, { + .name = "pcie3r", + .sid = TEGRA194_SID_PCIE3, + .regs = { + .override = 0x6f0, + .security = 0x6f4, + }, + }, { + .name = "pcie3w", + .sid = TEGRA194_SID_PCIE3, + .regs = { + .override = 0x6f8, + .security = 0x6fc, + }, + }, { + .name = "pcie4r", + .sid = TEGRA194_SID_PCIE4, + .regs = { + .override = 0x700, + .security = 0x704, + }, + }, { + .name = "pcie4w", + .sid = TEGRA194_SID_PCIE4, + .regs = { + .override = 0x708, + .security = 0x70c, + }, + }, { + .name = "pcie5r", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .override = 0x710, + .security = 0x714, + }, + }, { + .name = "pcie5w", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .override = 0x718, + .security = 0x71c, + }, + }, { + .name = "ispfalw", + .sid = TEGRA194_SID_ISP_FALCON, + .regs = { + .override = 0x720, + .security = 0x724, + }, + }, { + .name = "dla0rda1", + .sid = TEGRA194_SID_NVDLA0, + .regs = { + .override = 0x748, + .security = 0x74c, + }, + }, { + .name = "dla1rda1", + .sid = TEGRA194_SID_NVDLA1, + .regs = { + .override = 0x750, + .security = 0x754, + }, + }, { + .name = "pva0rda1", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x758, + .security = 0x75c, + }, + }, { + .name = "pva0rdb1", + .sid = TEGRA194_SID_PVA0, + .regs = { + .override = 0x760, + .security = 0x764, + }, + }, { + .name = "pva1rda1", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x768, + .security = 0x76c, + }, + }, { + .name = "pva1rdb1", + .sid = TEGRA194_SID_PVA1, + .regs = { + .override = 0x770, + .security = 0x774, + }, + }, { + .name = "pcie5r1", + .sid = TEGRA194_SID_PCIE5, + .regs = { + .override = 0x778, + .security = 0x77c, + }, + }, { + .name = "nvencsrd1", + .sid = TEGRA194_SID_NVENC, + .regs = { + .override = 0x780, + .security = 0x784, + }, + }, { + .name = "nvenc1srd1", + .sid = TEGRA194_SID_NVENC1, + .regs = { + .override = 0x788, + .security = 0x78c, + }, + }, { + .name = "ispra1", + .sid = TEGRA194_SID_ISP, + .regs = { + .override = 0x790, + .security = 0x794, + }, + }, { + .name = "pcie0r1", + .sid = TEGRA194_SID_PCIE0, + .regs = { + .override = 0x798, + .security = 0x79c, + }, + }, { + .name = "nvdec1srd", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .override = 0x7c8, + .security = 0x7cc, + }, + }, { + .name = "nvdec1srd1", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .override = 0x7d0, + .security = 0x7d4, + }, + }, { + .name = "nvdec1swr", + .sid = TEGRA194_SID_NVDEC1, + .regs = { + .override = 0x7d8, + .security = 0x7dc, + }, + }, { + .name = "miu5r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x7e0, + .security = 0x7e4, + }, + }, { + .name = "miu5w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x7e8, + .security = 0x7ec, + }, + }, { + .name = "miu6r", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x7f0, + .security = 0x7f4, + }, + }, { + .name = "miu6w", + .sid = TEGRA194_SID_MIU, + .regs = { + .override = 0x7f8, + .security = 0x7fc, + }, + }, +}; + +static const struct tegra186_mc_soc tegra194_mc_soc = { + .num_clients = ARRAY_SIZE(tegra194_mc_clients), + .clients = tegra194_mc_clients, +}; +#endif + +static int tegra186_mc_probe(struct platform_device *pdev) +{ + struct tegra186_mc *mc; + struct resource *res; + int err; + + mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); + if (!mc) + return -ENOMEM; + + mc->soc = of_device_get_match_data(&pdev->dev); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mc->regs)) + return PTR_ERR(mc->regs); + + mc->dev = &pdev->dev; + + err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (err < 0) + goto unregister; + + platform_set_drvdata(pdev, mc); + tegra186_mc_program_sid(mc); + + return 0; + +unregister: + memory_controller_unregister(&mc->base); + return err; +} + +static int tegra186_mc_remove(struct platform_device *pdev) +{ + struct tegra186_mc *mc = platform_get_drvdata(pdev); + + of_platform_depopulate(mc->dev); + memory_controller_unregister(&mc->base); + + return 0; +} + +static const struct of_device_id tegra186_mc_of_match[] = { +#if defined(CONFIG_ARCH_TEGRA_186_SOC) + { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC) + { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, #endif { /* sentinel */ } }; From patchwork Sun Dec 22 14:10:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214729 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uLUP93BW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gkst4C74z9sP6 for ; Mon, 23 Dec 2019 01:10:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726616AbfLVOK6 (ORCPT ); Sun, 22 Dec 2019 09:10:58 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:41371 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726603AbfLVOK6 (ORCPT ); Sun, 22 Dec 2019 09:10:58 -0500 Received: by mail-wr1-f67.google.com with SMTP id c9so13944582wrw.8; Sun, 22 Dec 2019 06:10:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vzFYuc95AWY6svq+EBkTgwMguKL8GySeZ2TwbGI8OIM=; b=uLUP93BWw0o+JzGgvJbHS+JQq2j1+NBwmhp+m4Ik109/D6oaX5YQAmSL97SKYfWENj 9U3hX5wRhynx3P/ymFwsgDAiQlvfSSoAoSyyoULEMnlaqPsc64jHQQLDlfRc7hGKjZ8m RkEUeiqYjQW+OG7JZROkofNpcYfASzs8CLN6WRihBpRh7zNO6hm8KKmnKFceUkx5f3DX 4XeySBgPFwdUYAaOPuVgwj0oblL5rCXAvU14LkZTn76fQfE7x4jqAh45YvYgleyxNqAc EV2DBP5T4M48S/NnnqlZHiNveDd0i5hN8ZycFqoBb309C0x8tk6HfTnJyxnGOVU4oG5D USJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vzFYuc95AWY6svq+EBkTgwMguKL8GySeZ2TwbGI8OIM=; b=dKn2w8PTYYw6yuypmf36K5KMoxiqXoGzFzbLgNdfCPcezLF9NlDd/mypEOgus+4/Kl OfsXIx7vsu3d7Y9PE5kMwaKVTsQ7VGy0/Zv1AHli0UGqxliODCFAuo++AUJUK0eKoYVb mNWSDGG4nCv0/wDB0xzNt7kgkpmpDCEaEzsjd9VO22VNCYhl5XwTMbxDebF600weK5jt 1QuiZTzz28VRcw9Dp91ZimtzIeBxCUI83aluCcQ//e44JQrM7RQXkXbpABnkMFnPLIzT MAzFjH/H4P+gr7e3V/sMf7ReE/LDMyoOGPmFOIlQPbVj3WRYxdkCJ4Z5Ktb6IMtYVrfY zg8A== X-Gm-Message-State: APjAAAW287UnOhru1pAubnDisq9CNIpkseF1PozNpc0ybo2Q9feYv2Ot VdeT+sT04nwptAw5iyN4K1Y= X-Google-Smtp-Source: APXvYqzAiT+VAg4ExN9JaDt0Y33c1cY7telDW1fwAubpR0qMOkVKKO0fuJ7ozhYjeykY1C+d8exOHg== X-Received: by 2002:adf:ee45:: with SMTP id w5mr24860066wro.352.1577023855885; Sun, 22 Dec 2019 06:10:55 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id c5sm16640151wmb.9.2019.12.22.06.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:54 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/13] arm64: tegra: Add interrupt for memory controller on Tegra186 Date: Sun, 22 Dec 2019 15:10:33 +0100 Message-Id: <20191222141035.1649937-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory controller can be interrupted by certain conditions. Add the interrupt to the device tree node to allow drivers to trap these conditions. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 7dc7fa8bcc39..584498a999d4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -142,6 +142,7 @@ agic: interrupt-controller@2a40000 { memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = ; status = "disabled"; }; From patchwork Sun Dec 22 14:10:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214731 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pHezw3Kg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksy4yrQz9sP6 for ; Mon, 23 Dec 2019 01:11:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726650AbfLVOK7 (ORCPT ); Sun, 22 Dec 2019 09:10:59 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46652 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726564AbfLVOK7 (ORCPT ); Sun, 22 Dec 2019 09:10:59 -0500 Received: by mail-wr1-f68.google.com with SMTP id z7so13883742wrl.13; Sun, 22 Dec 2019 06:10:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9NLd2mHZgSanSF4J79TwmNol8PZQ1XjUStKYPMmwtKY=; b=pHezw3KgOalhagOA8ELZM/hrh4fQ8lAGOKSnJXcC1LfySeZAeMTRvGB02qX6RwTjIi LgPx2hiGAxsNdsvD52YPPI50k3Q2OO0xrZRSpZgDqHN61SkaI94lyaMh3r0dQiylmSmn /XS47KLgP83xghibqMP0a0ASi3mWcjeRvpvBCK4LVemxShy+qYSafIiALVnaDj6rXJBv 1CErmlegu57ZvPDSY9A4e9eY47urKn2fM7mgHnfUAJEar7/qCPpfBQ892bkbYTSeCa0L YckvpvcqKpqeiX9fY/4OSOOCRne4KZobZRnrvmuEojjGsys7LF3KE9+2l3jYEeOY9/Z3 1LfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9NLd2mHZgSanSF4J79TwmNol8PZQ1XjUStKYPMmwtKY=; b=hPifkMtsxe6RHlSLD8y7e3r0umObV1imnLTOVWDp4Ud+Ss53WGe749DI5vBqrEG8PT JNmgejFQKzyX8xaWhvA3Q8h4ZxNhMWAg9CqoYQkJrK9lldiYsnUsIV/wEcAAEJkqQL3u MiexNh76tLdKemGX8ipJh/DnDqnEg2wVG55LJakk6Wy6I1enxGkKYyQP7j+HL2LSXjyQ SEB94tSuXb5IKbfiNu5gj6d+GHA3n3kJ/b19j+c3wn/mpwc8oWfsB4fR5CIsG+V87qat ZoNjx8iudHNDo9XiLnT9u1hOOqZ4R7CxXok0KYarjbcuAyjlExygST+JYrQWMOnh6JFq HDaQ== X-Gm-Message-State: APjAAAW+Ubr44ClDsE9NrR/UJYsgtQYLtBKECUKbr7Jan3SVxZA9H62d UhhYRrBH1O1HGyTg6qZUvKA= X-Google-Smtp-Source: APXvYqxRYGHgLZemcl/o8PPZd4p2Lzq1fSAv3l9MR1in32eLNeV1VqBcGboJgv2+yaSFlVoDnWG8vA== X-Received: by 2002:adf:f70b:: with SMTP id r11mr27216079wrp.388.1577023857414; Sun, 22 Dec 2019 06:10:57 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id f16sm17271848wrm.65.2019.12.22.06.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:56 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/13] arm64: tegra: Add external memory controller on Tegra186 Date: Sun, 22 Dec 2019 15:10:34 +0100 Message-Id: <20191222141035.1649937-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add the external memory controller as a child device of the memory controller on Tegra186. The memory controller really represents the memory subsystem that encompasses both the memory and external memory controllers. The external memory controller uses the BPMP to obtain the list of supported EMC frequencies and set the EMC frequency. Also set up the dma-ranges property to describe that all memory clients can address up to 40 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 584498a999d4..dba7f57469c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -144,6 +144,27 @@ memory-controller@2c00000 { reg = <0x0 0x02c00000 0x0 0xb0000>; interrupts = ; status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; + + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; }; timer@3010000 { From patchwork Sun Dec 22 14:10:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1214733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aIuz0c3D"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47gksz4J8Xz9sQp for ; Mon, 23 Dec 2019 01:11:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725971AbfLVOLB (ORCPT ); Sun, 22 Dec 2019 09:11:01 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39828 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726633AbfLVOLB (ORCPT ); Sun, 22 Dec 2019 09:11:01 -0500 Received: by mail-wr1-f65.google.com with SMTP id y11so13939802wrt.6; Sun, 22 Dec 2019 06:10:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZ2ifsUJ0JDecwnLRVKVryT2ldTM9sS1JLZapFRyFbA=; b=aIuz0c3DIOIV/V+RoJaNOt6Nn5j607gJYUni3sEgec5lT2zUWSZPU+Yj6XQ0G7MofH /DUytOuJemu6cW+YXcGa9hLeNq/rqhKyp7/fPTej2dWEtKuJHSp9hY+IOlChisFnR4dD ugg2D1RyA3GjfZrXmxU5Sf9qTZqo8OmsCDUe39MsJgpKkQnUKWoXAVHU4gkl/+jt9bu8 GUqNf/XVUC0UEmw2nZlY8uMmCd/3Wivkx9pshLdC6AZAtJHXT0nXHZ++W8mWhRl1q5V0 3ZGlxCbqtbfRXj1F8PJoUcoXHEbVnLoRRVTKVMfc/TCxe09p9CFAZpCp26SVekLHVgAK Sb7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZ2ifsUJ0JDecwnLRVKVryT2ldTM9sS1JLZapFRyFbA=; b=epKAm9cxbAJgWNjGvQjjIUbY65+MYbCS/dx8Pd6jMutEpzJlFL5YFqh5xkJJ+fYgG0 jHcoKgSr4KCxIiIZg6lnHgEbl6Xl7QoItIweV2uGv6p2I8T69miqz9APV9zFgDCTsCwR yCC0PyFvy2isrpYfMC05pEuHNMApA4wW5zHAJGleqIy0neBeHYOm9laGBtPktTzNPnU0 e7xUJnxax13YvE6GWeL+rRnB9WZsHuEqluZ2JOcLSnWNpxW31GMOD3BcpLTLMHfmfutY OKAMzMM0rJT5kq0BYCXHUtjlT0bCF4w0ZxYcFMBtkxHohbZesD/Sac6a1fj/t0SNi1P5 A1yg== X-Gm-Message-State: APjAAAUndr9uEmB9nQCvVIFo7GPKpNAxmHZPaiscA4N5i0L9nqJnvVts WvTzTrgge5WIyorGkuzNpVI= X-Google-Smtp-Source: APXvYqzIPId95QD1p9h5yyQqJIuAkR5ecaXNbnqV/zOLqeN67IxeDaDqVDQUlrB6cCQ/CY+ZiuuuVw== X-Received: by 2002:a5d:4c85:: with SMTP id z5mr24874687wrs.42.1577023859107; Sun, 22 Dec 2019 06:10:59 -0800 (PST) Received: from localhost (p2E5BEF3F.dip0.t-ipconnect.de. [46.91.239.63]) by smtp.gmail.com with ESMTPSA id e6sm16834831wru.44.2019.12.22.06.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:58 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/13] arm64: tegra: Add the memory subsystem on Tegra194 Date: Sun, 22 Dec 2019 15:10:35 +0100 Message-Id: <20191222141035.1649937-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges. A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 ++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 43 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index b6ffd5dde20d..cc23d59240ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -48,6 +48,10 @@ phy: phy@0 { }; }; + memory-controller@2c00000 { + status = "okay"; + }; + serial@3110000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9f000bb7fca7..73e23ca158dc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra194"; @@ -166,6 +167,48 @@ clkreq { }; }; + mc: memory-controller@2c00000 { + compatible = "nvidia,tegra194-mc"; + reg = <0x02c00000 0x100000>, + <0x02b80000 0x040000>, + <0x01700000 0x100000>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + + /* + * Bit 39 of addresses passing through the memory + * controller selects the XBAR format used when memory + * is accessed. This is used to transparently access + * memory in the XBAR format used by the discrete GPU + * (bit 39 set) or Tegra (bit 39 clear). + * + * As a consequence, the operating system must ensure + * that bit 39 is never used implicitly, for example + * via an I/O virtual address mapping of an IOMMU. If + * devices require access to the XBAR switch, their + * drivers must set this bit explicitly. + * + * Limit the DMA range for memory clients to [38:0]. + */ + dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra194-emc"; + reg = <0x0 0x02c60000 0x0 0x90000>, + <0x0 0x01780000 0x0 0x80000>; + clocks = <&bpmp TEGRA194_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>;