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x-microsoft-antispam-message-info: Spa6nkHf/KH0jnVwl9Q68XwPsJyVpK1AUpF1RiFMypQly6wvwIQxqlHUrbGUoh2mqgSf8KEIibnoU+I2Ll6YSq9vmk4ZhgsTQ09UP+BpSg+N4H0WMoz890HulNTk1EWRvOJ3uYVXW504rydxOhIu/hQkTuakI1nXl7xWw8ddA717c6TykBJvugbh/LumGzIcToNdsq7tRx8LVtBib+MiEN91QfcRbQaEdSI66XaBKb4z7504xmnWNZu4mDlkS/75syNehWWfsa4nnKoCs6qAwrcGXxg74acaZq9F6NeI8PE0LzhfysViSPBb++yqkUQo7zQ3D2HHx4XSIbFPocSPE+qzrH8DqWnraELvVlcVF10PMhWVWzT6V1tKlnEHCmnsoj1eB+dRqTcsgJB630YbJkWgVj0GivQInkxVDCgrTe1InmrMAaeicuxbGrRafk13 MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: fcebe143-55c7-4fdb-9a86-08d7846845b9 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Dec 2019 09:46:08.0420 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3m8hgw+iHArVXYiYlIv/vmYxz/4Ig1ROEdBjyQPZRlr2ns1spAreiexUUm0Ki4KRMk1uRF8EnNs5SURrd7lhNbac1VUkeN2ZQOm1CPAkDT4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR1001MB1176 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean The current mpc83xx_clk driver is broken for any board for which mpc83xx_has_pci() is true, i.e. anything not MPC8308: When is_clk_valid() reports that MPC83XX_CLK_PCI is valid, init_all_clks() proceeds to call init_single_clk(), but that doesn't know about either MPC83XX_CLK_PCI or has any handling of the TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence init_single_clk() ends up returning -EINVAL, and the whole board hangs in serial_init(). The quickest fix is to simply pretend that clock is invalid for all, since nobody can have been relying on it. Adding proper support seems to be a bit more involved than just handling TYPE_SCCR_ONOFF: - The power-on-reset value of SCCR[PCICM] is 0, so mpc83xx_clk_enable() would probably need to be tought to enable the clock. - The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2 depending on the CFG_CLKIN_DIV configuration input, but that can't be read from software, so to properly fill out ->speed[MPC83XX_CLK_PCI] I think one would need guidance from Kconfig or dtb. Partially fixes: 07d538d281 clk: Add MPC83xx clock driver Signed-off-by: Rasmus Villemoes Reviewed-by: Mario Six --- drivers/clk/mpc83xx_clk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 32d2db9eda..1b2b216596 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -65,7 +65,10 @@ static inline bool is_clk_valid(struct udevice *clk, int id) case MPC83XX_CLK_DMAC: return (type == SOC_MPC8308) || (type == SOC_MPC8309); case MPC83XX_CLK_PCI: - return mpc83xx_has_pci(type); + /* + * FIXME: implement proper support for this. + */ + return 0 && mpc83xx_has_pci(type); case MPC83XX_CLK_CSB: return true; case MPC83XX_CLK_I2C2: