From patchwork Wed Dec 18 15:09:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212523 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJRC0wtkz9sSS for ; Thu, 19 Dec 2019 02:12:55 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJRB5Z4KzDqf3 for ; Thu, 19 Dec 2019 02:12:54 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=eajames@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47dJNw3DV4zDqgP for ; Thu, 19 Dec 2019 02:09:59 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBIErHHx015890; Wed, 18 Dec 2019 10:09:44 -0500 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wyjf8hpb9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:43 -0500 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF4nNw006295; Wed, 18 Dec 2019 15:09:42 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma04wdc.us.ibm.com with ESMTP id 2wvqc6p71t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:42 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9fOg61538592 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:41 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2864013604F; Wed, 18 Dec 2019 15:09:41 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 14989136059; Wed, 18 Dec 2019 15:09:40 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:39 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 01/12] dt-bindings: interrupt-controller: Add Aspeed SCU interrupt controller Date: Wed, 18 Dec 2019 09:09:27 -0600 Message-Id: <1576681778-18737-2-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=780 lowpriorityscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 suspectscore=1 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Document the Aspeed SCU interrupt controller and add an include file for the interrupts it provides. Signed-off-by: Eddie James Reviewed-by: Rob Herring Acked-by: Andrew Jeffery --- .../aspeed,ast2xxx-scu-ic.txt | 23 +++++++++++++++++++ MAINTAINERS | 7 ++++++ .../interrupt-controller/aspeed-scu-ic.h | 23 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt create mode 100644 include/dt-bindings/interrupt-controller/aspeed-scu-ic.h diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt new file mode 100644 index 000000000000..251ed44171db --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt @@ -0,0 +1,23 @@ +Aspeed AST25XX and AST26XX SCU Interrupt Controller + +Required Properties: + - #interrupt-cells : must be 1 + - compatible : must be "aspeed,ast2500-scu-ic", + "aspeed,ast2600-scu-ic0" or + "aspeed,ast2600-scu-ic1" + - interrupts : interrupt from the parent controller + - interrupt-controller : indicates that the controller receives and + fires new interrupts for child busses + +Example: + + syscon@1e6e2000 { + ranges = <0 0x1e6e2000 0x1a8>; + + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + interrupts = <21>; + interrupt-controller; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 39a8c6a49b81..219cd69d871b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2692,6 +2692,13 @@ S: Maintained F: drivers/pinctrl/aspeed/ F: Documentation/devicetree/bindings/pinctrl/aspeed,* +ASPEED SCU INTERRUPT CONTROLLER DRIVER +M: Eddie James +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt +F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h + ASPEED VIDEO ENGINE DRIVER M: Eddie James L: linux-media@vger.kernel.org diff --git a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h new file mode 100644 index 000000000000..f315d5a7f5ee --- /dev/null +++ b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ + +#define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 +#define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 + +#define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 +#define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 +#define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 +#define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 +#define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 + +#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 +#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 +#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 +#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 + +#define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 +#define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ From patchwork Wed Dec 18 15:09:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQM5JnGz9sSL for ; Thu, 19 Dec 2019 02:12:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJQM4FLKzDqh3 for ; Thu, 19 Dec 2019 02:12:11 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=eajames@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47dJNw3BtszDqgD for ; Thu, 19 Dec 2019 02:09:58 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBIErdr0027552; Wed, 18 Dec 2019 10:09:45 -0500 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wykb6ypcs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:44 -0500 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIEt5Ix016038; Wed, 18 Dec 2019 15:09:43 GMT Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by ppma05wdc.us.ibm.com with ESMTP id 2wvqc6e8ru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:43 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9gnT55509394 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:42 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 59177136060; Wed, 18 Dec 2019 15:09:42 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 70AE0136053; Wed, 18 Dec 2019 15:09:41 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:41 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 02/12] irqchip: Add Aspeed SCU interrupt controller Date: Wed, 18 Dec 2019 09:09:28 -0600 Message-Id: <1576681778-18737-3-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=1 clxscore=1015 lowpriorityscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" The Aspeed SOCs provide some interrupts through the System Control Unit registers. Add an interrupt controller that provides these interrupts to the system. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery --- MAINTAINERS | 1 + drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-aspeed-scu-ic.c | 239 ++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-aspeed-scu-ic.c diff --git a/MAINTAINERS b/MAINTAINERS index 219cd69d871b..ac9c120d192b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2697,6 +2697,7 @@ M: Eddie James L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt +F: drivers/irqchip/irq-aspeed-scu-ic.c F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h ASPEED VIDEO ENGINE DRIVER diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..6c9262c673bf 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -87,7 +87,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o -obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o +obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c new file mode 100644 index 000000000000..c90a3346b985 --- /dev/null +++ b/drivers/irqchip/irq-aspeed-scu-ic.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller + * Copyright 2019 IBM Corporation + * + * Eddie James + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ASPEED_SCU_IC_REG 0x018 +#define ASPEED_SCU_IC_SHIFT 0 +#define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT) +#define ASPEED_SCU_IC_NUM_IRQS 7 +#define ASPEED_SCU_IC_STATUS_SHIFT 16 + +#define ASPEED_AST2600_SCU_IC0_REG 0x560 +#define ASPEED_AST2600_SCU_IC0_SHIFT 0 +#define ASPEED_AST2600_SCU_IC0_ENABLE \ + GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT) +#define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6 + +#define ASPEED_AST2600_SCU_IC1_REG 0x570 +#define ASPEED_AST2600_SCU_IC1_SHIFT 4 +#define ASPEED_AST2600_SCU_IC1_ENABLE \ + GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT) +#define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2 + +struct aspeed_scu_ic { + unsigned long irq_enable; + unsigned long irq_shift; + unsigned int num_irqs; + unsigned int reg; + struct regmap *scu; + struct irq_domain *irq_domain; +}; + +static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) +{ + unsigned int irq; + unsigned int sts; + unsigned long bit; + unsigned long enabled; + unsigned long max; + unsigned long status; + struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; + + chained_irq_enter(chip, desc); + + /* + * The SCU IC has just one register to control its operation and read + * status. The interrupt enable bits occupy the lower 16 bits of the + * register, while the interrupt status bits occupy the upper 16 bits. + * The status bit for a given interrupt is always 16 bits shifted from + * the enable bit for the same interrupt. + * Therefore, perform the IRQ operations in the enable bit space by + * shifting the status down to get the mapping and then back up to + * clear the bit. + */ + regmap_read(scu_ic->scu, scu_ic->reg, &sts); + enabled = sts & scu_ic->irq_enable; + status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled; + + bit = scu_ic->irq_shift; + max = scu_ic->num_irqs + bit; + + for_each_set_bit_from(bit, &status, max) { + irq = irq_find_mapping(scu_ic->irq_domain, + bit - scu_ic->irq_shift); + generic_handle_irq(irq); + + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, + BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT)); + } + + chained_irq_exit(chip, desc); +} + +static void aspeed_scu_ic_irq_mask(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); + unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) | + (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT); + + /* + * Status bits are cleared by writing 1. In order to prevent the mask + * operation from clearing the status bits, they should be under the + * mask and written with 0. + */ + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0); +} + +static void aspeed_scu_ic_irq_unmask(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); + unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift); + unsigned int mask = bit | + (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT); + + /* + * Status bits are cleared by writing 1. In order to prevent the unmask + * operation from clearing the status bits, they should be under the + * mask and written with 0. + */ + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit); +} + +static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + return -EINVAL; +} + +static struct irq_chip aspeed_scu_ic_chip = { + .name = "aspeed-scu-ic", + .irq_mask = aspeed_scu_ic_irq_mask, + .irq_unmask = aspeed_scu_ic_irq_unmask, + .irq_set_affinity = aspeed_scu_ic_irq_set_affinity, +}; + +static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops aspeed_scu_ic_domain_ops = { + .map = aspeed_scu_ic_map, +}; + +static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic, + struct device_node *node) +{ + int irq; + int rc = 0; + + if (!node->parent) { + rc = -ENODEV; + goto err; + } + + scu_ic->scu = syscon_node_to_regmap(node->parent); + if (IS_ERR(scu_ic->scu)) { + rc = PTR_ERR(scu_ic->scu); + goto err; + } + + irq = irq_of_parse_and_map(node, 0); + if (irq < 0) { + rc = irq; + goto err; + } + + scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs, + &aspeed_scu_ic_domain_ops, + scu_ic); + if (!scu_ic->irq_domain) { + rc = -ENOMEM; + goto err; + } + + irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler, + scu_ic); + + return 0; + +err: + kfree(scu_ic); + + return rc; +} + +static int __init aspeed_scu_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); + + if (!scu_ic) + return -ENOMEM; + + scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE; + scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT; + scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS; + scu_ic->reg = ASPEED_SCU_IC_REG; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); + + if (!scu_ic) + return -ENOMEM; + + scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE; + scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT; + scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS; + scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); + + if (!scu_ic) + return -ENOMEM; + + scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE; + scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT; + scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS; + scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init); +IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init); +IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", + aspeed_ast2600_scu_ic0_of_init); +IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", + aspeed_ast2600_scu_ic1_of_init); From patchwork Wed Dec 18 15:09:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212513 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJPr6Yk9z9sSY for ; Thu, 19 Dec 2019 02:11:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJPr4fm0zDqh3 for ; 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Wed, 18 Dec 2019 15:09:42 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:42 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 03/12] ARM: dts: aspeed: ast2500: Add SCU interrupt controller Date: Wed, 18 Dec 2019 09:09:29 -0600 Message-Id: <1576681778-18737-4-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=616 lowpriorityscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 suspectscore=1 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery --- Changes since v2: - Remove the addition of ranges in the SCU arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index a259c63fff06..4791a50e37ee 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -231,6 +231,13 @@ p2a: p2a-control { compatible = "aspeed,ast2500-p2a-ctrl"; status = "disabled"; }; + + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + interrupts = <21>; + interrupt-controller; + }; }; rng: hwrng@1e6e2078 { From patchwork Wed Dec 18 15:09:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQ46sz4z9sSl for ; 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Wed, 18 Dec 2019 10:09:46 -0500 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0b-001b2d01.pphosted.com with ESMTP id 2wyp9kgjgm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:46 -0500 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF5Rk9028206; Wed, 18 Dec 2019 15:09:45 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma05wdc.us.ibm.com with ESMTP id 2wvqc6e8s2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:45 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9iEi57147740 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:44 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B127A13604F; Wed, 18 Dec 2019 15:09:44 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C98D4136053; Wed, 18 Dec 2019 15:09:43 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:43 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 04/12] ARM: dts: aspeed: ast2600: Add SCU interrupt controllers Date: Wed, 18 Dec 2019 09:09:30 -0600 Message-Id: <1576681778-18737-5-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 suspectscore=1 adultscore=0 mlxlogscore=666 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add nodes for the interrupt controllers provided by the SCU. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-g6.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 5f6142d99eeb..ead336e93a12 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -288,6 +288,20 @@ smp-memram@180 { compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; }; + + scu_ic0: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic0"; + interrupts = ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@1 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic1"; + interrupts = ; + interrupt-controller; + }; }; rng: hwrng@1e6e2524 { From patchwork Wed Dec 18 15:09:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJRZ0T6Lz9sSP for ; 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Wed, 18 Dec 2019 10:09:48 -0500 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0b-001b2d01.pphosted.com with ESMTP id 2wyp9kgjhp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:48 -0500 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF50lx008928; Wed, 18 Dec 2019 15:09:47 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma03dal.us.ibm.com with ESMTP id 2wvqc6yxgf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:47 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9j3m47514066 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:46 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DBE2213605E; Wed, 18 Dec 2019 15:09:45 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E862913604F; Wed, 18 Dec 2019 15:09:44 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:44 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 05/12] dt-bindings: soc: Add Aspeed XDMA Engine Date: Wed, 18 Dec 2019 09:09:31 -0600 Message-Id: <1576681778-18737-6-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 suspectscore=1 adultscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine. Signed-off-by: Eddie James Reviewed-by: Rob Herring --- Changes since v2: - Remove 'sdmc', rename 'vga-mem' to 'memory' .../devicetree/bindings/soc/aspeed/xdma.txt | 40 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/xdma.txt diff --git a/Documentation/devicetree/bindings/soc/aspeed/xdma.txt b/Documentation/devicetree/bindings/soc/aspeed/xdma.txt new file mode 100644 index 000000000000..58253ea1587b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/xdma.txt @@ -0,0 +1,40 @@ +Aspeed AST25XX and AST26XX XDMA Engine + +The XDMA Engine embedded in the AST2500 and AST2600 SOCs can perform automatic +DMA operations over PCI between the SOC (acting as a BMC) and a host processor. + +Required properties: + - compatible : must be "aspeed,ast2500-xdma" or + "aspeed,ast2600-xdma" + - reg : contains the address and size of the memory region + associated with the XDMA engine registers + - clocks : clock specifier for the clock associated with the + XDMA engine + - resets : reset specifier for the syscon reset associated with + the XDMA engine + - interrupts-extended : two interrupt cells; the first specifies the global + interrupt for the XDMA engine and the second + specifies the PCI-E reset or PERST interrupt. + - scu : a phandle to the syscon node for the system control + unit of the SOC + - memory : contains the address and size of the memory area to + be used by the XDMA engine for DMA operations + +Optional properties: + - pcie-device : should be either "bmc" or "vga", corresponding to + which device should be used by the XDMA engine for + DMA operations. If this property is not set, the XDMA + engine will use the BMC PCI-E device. + +Example: + + xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; + scu = <&syscon>; + pcie-device = "bmc"; + memory = <0x9f000000 0x01000000>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index ac9c120d192b..8a14d4268bdc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2708,6 +2708,12 @@ S: Maintained F: drivers/media/platform/aspeed-video.c F: Documentation/devicetree/bindings/media/aspeed-video.txt +ASPEED XDMA ENGINE DRIVER +M: Eddie James +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/soc/aspeed/xdma.txt + ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS M: Corentin Chary L: acpi4asus-user@lists.sourceforge.net From patchwork Wed Dec 18 15:09:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQq3tklz9sRv for ; Thu, 19 Dec 2019 02:12:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJQp6g2hzDqkG for ; Thu, 19 Dec 2019 02:12:34 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=eajames@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47dJNw3GYLzDqgX for ; Thu, 19 Dec 2019 02:10:03 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBIErOmN134910; Wed, 18 Dec 2019 10:09:49 -0500 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wyhcbv1s0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:49 -0500 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF3cZm031890; Wed, 18 Dec 2019 15:09:48 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma03wdc.us.ibm.com with ESMTP id 2wvqc6pcf8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:48 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9ljR47186228 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:47 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1BC04136061; Wed, 18 Dec 2019 15:09:47 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 12ECD136053; Wed, 18 Dec 2019 15:09:46 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:45 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 06/12] soc: aspeed: Add XDMA Engine Driver Date: Wed, 18 Dec 2019 09:09:32 -0600 Message-Id: <1576681778-18737-7-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=3 phishscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. This commit adds a driver to control the XDMA engine and adds functions to initialize the hardware and memory and start DMA operations. Signed-off-by: Eddie James --- Changes since v2: - Remove SDRAM memory controller configuration - Add client_lock to protect client state - Rename things away from "vga" - Refactor set_cmd and aspeed_xdma_start a bit - Did various suggested cleanup items MAINTAINERS | 2 + drivers/soc/aspeed/Kconfig | 8 + drivers/soc/aspeed/Makefile | 1 + drivers/soc/aspeed/aspeed-xdma.c | 777 +++++++++++++++++++++++++++++++ include/uapi/linux/aspeed-xdma.h | 38 ++ 5 files changed, 826 insertions(+) create mode 100644 drivers/soc/aspeed/aspeed-xdma.c create mode 100644 include/uapi/linux/aspeed-xdma.h diff --git a/MAINTAINERS b/MAINTAINERS index 8a14d4268bdc..b72cc581c7a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2713,6 +2713,8 @@ M: Eddie James L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/soc/aspeed/xdma.txt +F: drivers/soc/aspeed/aspeed-xdma.c +F: include/uapi/linux/aspeed-xdma.h ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS M: Corentin Chary diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 323e177aa74d..2a6c16f9e50b 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -29,4 +29,12 @@ config ASPEED_P2A_CTRL ioctl()s, the driver also provides an interface for userspace mappings to a pre-defined region. +config ASPEED_XDMA + tristate "Aspeed XDMA Engine Driver" + depends on SOC_ASPEED && REGMAP && MFD_SYSCON && HAS_DMA + help + Enable support for the Aspeed XDMA Engine found on the Aspeed AST2XXX + SOCs. The XDMA engine can perform automatic PCI DMA operations + between the AST2XXX (acting as a BMC) and a host processor. + endmenu diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index b64be47f2b1f..977b046dfb73 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o +obj-$(CONFIG_ASPEED_XDMA) += aspeed-xdma.o diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c new file mode 100644 index 000000000000..cb94adf798b1 --- /dev/null +++ b/drivers/soc/aspeed/aspeed-xdma.c @@ -0,0 +1,777 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright IBM Corp 2019 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_NAME "aspeed-xdma" + +#define SCU_AST2500_PCIE_CONF 0x180 +#define SCU_AST2600_PCIE_CONF 0xc20 +#define SCU_PCIE_CONF_VGA_EN BIT(0) +#define SCU_PCIE_CONF_VGA_EN_MMIO BIT(1) +#define SCU_PCIE_CONF_VGA_EN_LPC BIT(2) +#define SCU_PCIE_CONF_VGA_EN_MSI BIT(3) +#define SCU_PCIE_CONF_VGA_EN_MCTP BIT(4) +#define SCU_PCIE_CONF_VGA_EN_IRQ BIT(5) +#define SCU_PCIE_CONF_VGA_EN_DMA BIT(6) +#define SCU_PCIE_CONF_BMC_EN BIT(8) +#define SCU_PCIE_CONF_BMC_EN_MMIO BIT(9) +#define SCU_PCIE_CONF_BMC_EN_MSI BIT(11) +#define SCU_PCIE_CONF_BMC_EN_MCTP BIT(12) +#define SCU_PCIE_CONF_BMC_EN_IRQ BIT(13) +#define SCU_PCIE_CONF_BMC_EN_DMA BIT(14) + +#define SCU_AST2500_BMC_CLASS_REV 0x19c +#define SCU_AST2600_BMC_CLASS_REV 0xc4c +#define SCU_BMC_CLASS_REV_XDMA 0xff000001 + +#define XDMA_CMDQ_SIZE PAGE_SIZE +#define XDMA_NUM_CMDS \ + (XDMA_CMDQ_SIZE / sizeof(struct aspeed_xdma_cmd)) + +/* Aspeed specification requires 10ms after switching the reset line */ +#define XDMA_RESET_TIME_MS 10 + +#define XDMA_CMD_AST2500_PITCH_SHIFT 3 +#define XDMA_CMD_AST2500_PITCH_BMC GENMASK_ULL(62, 51) +#define XDMA_CMD_AST2500_PITCH_HOST GENMASK_ULL(46, 35) +#define XDMA_CMD_AST2500_PITCH_UPSTREAM BIT_ULL(31) +#define XDMA_CMD_AST2500_PITCH_ADDR GENMASK_ULL(29, 4) +#define XDMA_CMD_AST2500_PITCH_ID BIT_ULL(0) +#define XDMA_CMD_AST2500_CMD_IRQ_EN BIT_ULL(31) +#define XDMA_CMD_AST2500_CMD_LINE_NO GENMASK_ULL(27, 16) +#define XDMA_CMD_AST2500_CMD_IRQ_BMC BIT_ULL(15) +#define XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT 4 +#define XDMA_CMD_AST2500_CMD_LINE_SIZE \ + GENMASK_ULL(14, XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT) +#define XDMA_CMD_AST2500_CMD_ID BIT_ULL(1) + +#define XDMA_CMD_AST2600_PITCH_BMC GENMASK_ULL(62, 48) +#define XDMA_CMD_AST2600_PITCH_HOST GENMASK_ULL(46, 32) +#define XDMA_CMD_AST2600_PITCH_ADDR GENMASK_ULL(30, 0) +#define XDMA_CMD_AST2600_CMD_64_EN BIT_ULL(40) +#define XDMA_CMD_AST2600_CMD_IRQ_BMC BIT_ULL(37) +#define XDMA_CMD_AST2600_CMD_IRQ_HOST BIT_ULL(36) +#define XDMA_CMD_AST2600_CMD_UPSTREAM BIT_ULL(32) +#define XDMA_CMD_AST2600_CMD_LINE_NO GENMASK_ULL(27, 16) +#define XDMA_CMD_AST2600_CMD_LINE_SIZE GENMASK_ULL(14, 0) +#define XDMA_CMD_AST2600_CMD_MULTILINE_SIZE GENMASK_ULL(14, 12) + +#define XDMA_AST2500_QUEUE_ENTRY_SIZE 4 +#define XDMA_AST2500_HOST_CMDQ_ADDR0 0x00 +#define XDMA_AST2500_HOST_CMDQ_ENDP 0x04 +#define XDMA_AST2500_HOST_CMDQ_WRITEP 0x08 +#define XDMA_AST2500_HOST_CMDQ_READP 0x0c +#define XDMA_AST2500_BMC_CMDQ_ADDR 0x10 +#define XDMA_AST2500_BMC_CMDQ_ENDP 0x14 +#define XDMA_AST2500_BMC_CMDQ_WRITEP 0x18 +#define XDMA_AST2500_BMC_CMDQ_READP 0x1c +#define XDMA_BMC_CMDQ_READP_RESET 0xee882266 +#define XDMA_AST2500_CTRL 0x20 +#define XDMA_AST2500_CTRL_US_COMP BIT(4) +#define XDMA_AST2500_CTRL_DS_COMP BIT(5) +#define XDMA_AST2500_CTRL_DS_DIRTY BIT(6) +#define XDMA_AST2500_CTRL_DS_SIZE_256 BIT(17) +#define XDMA_AST2500_CTRL_DS_TIMEOUT BIT(28) +#define XDMA_AST2500_CTRL_DS_CHECK_ID BIT(29) +#define XDMA_AST2500_STATUS 0x24 +#define XDMA_AST2500_STATUS_US_COMP BIT(4) +#define XDMA_AST2500_STATUS_DS_COMP BIT(5) +#define XDMA_AST2500_STATUS_DS_DIRTY BIT(6) +#define XDMA_AST2500_INPRG_DS_CMD1 0x38 +#define XDMA_AST2500_INPRG_DS_CMD2 0x3c +#define XDMA_AST2500_INPRG_US_CMD00 0x40 +#define XDMA_AST2500_INPRG_US_CMD01 0x44 +#define XDMA_AST2500_INPRG_US_CMD10 0x48 +#define XDMA_AST2500_INPRG_US_CMD11 0x4c +#define XDMA_AST2500_INPRG_US_CMD20 0x50 +#define XDMA_AST2500_INPRG_US_CMD21 0x54 +#define XDMA_AST2500_HOST_CMDQ_ADDR1 0x60 +#define XDMA_AST2500_VGA_CMDQ_ADDR0 0x64 +#define XDMA_AST2500_VGA_CMDQ_ENDP 0x68 +#define XDMA_AST2500_VGA_CMDQ_WRITEP 0x6c +#define XDMA_AST2500_VGA_CMDQ_READP 0x70 +#define XDMA_AST2500_VGA_CMD_STATUS 0x74 +#define XDMA_AST2500_VGA_CMDQ_ADDR1 0x78 + +#define XDMA_AST2600_QUEUE_ENTRY_SIZE 2 +#define XDMA_AST2600_HOST_CMDQ_ADDR0 0x00 +#define XDMA_AST2600_HOST_CMDQ_ADDR1 0x04 +#define XDMA_AST2600_HOST_CMDQ_ENDP 0x08 +#define XDMA_AST2600_HOST_CMDQ_WRITEP 0x0c +#define XDMA_AST2600_HOST_CMDQ_READP 0x10 +#define XDMA_AST2600_BMC_CMDQ_ADDR 0x14 +#define XDMA_AST2600_BMC_CMDQ_ENDP 0x18 +#define XDMA_AST2600_BMC_CMDQ_WRITEP 0x1c +#define XDMA_AST2600_BMC_CMDQ_READP 0x20 +#define XDMA_AST2600_VGA_CMDQ_ADDR0 0x24 +#define XDMA_AST2600_VGA_CMDQ_ADDR1 0x28 +#define XDMA_AST2600_VGA_CMDQ_ENDP 0x2c +#define XDMA_AST2600_VGA_CMDQ_WRITEP 0x30 +#define XDMA_AST2600_VGA_CMDQ_READP 0x34 +#define XDMA_AST2600_CTRL 0x38 +#define XDMA_AST2600_CTRL_US_COMP BIT(16) +#define XDMA_AST2600_CTRL_DS_COMP BIT(17) +#define XDMA_AST2600_CTRL_DS_DIRTY BIT(18) +#define XDMA_AST2600_CTRL_DS_SIZE_256 BIT(20) +#define XDMA_AST2600_STATUS 0x3c +#define XDMA_AST2600_STATUS_US_COMP BIT(16) +#define XDMA_AST2600_STATUS_DS_COMP BIT(17) +#define XDMA_AST2600_STATUS_DS_DIRTY BIT(18) +#define XDMA_AST2600_INPRG_DS_CMD00 0x40 +#define XDMA_AST2600_INPRG_DS_CMD01 0x44 +#define XDMA_AST2600_INPRG_DS_CMD10 0x48 +#define XDMA_AST2600_INPRG_DS_CMD11 0x4c +#define XDMA_AST2600_INPRG_DS_CMD20 0x50 +#define XDMA_AST2600_INPRG_DS_CMD21 0x54 +#define XDMA_AST2600_INPRG_US_CMD00 0x60 +#define XDMA_AST2600_INPRG_US_CMD01 0x64 +#define XDMA_AST2600_INPRG_US_CMD10 0x68 +#define XDMA_AST2600_INPRG_US_CMD11 0x6c +#define XDMA_AST2600_INPRG_US_CMD20 0x70 +#define XDMA_AST2600_INPRG_US_CMD21 0x74 + +struct aspeed_xdma_cmd { + u64 host_addr; + u64 pitch; + u64 cmd; + u64 reserved; +}; + +struct aspeed_xdma_regs { + u8 bmc_cmdq_addr; + u8 bmc_cmdq_endp; + u8 bmc_cmdq_writep; + u8 bmc_cmdq_readp; + u8 control; + u8 status; +}; + +struct aspeed_xdma_status_bits { + u32 us_comp; + u32 ds_comp; + u32 ds_dirty; +}; + +struct aspeed_xdma; + +struct aspeed_xdma_chip { + u32 control; + u32 scu_bmc_class; + u32 scu_pcie_conf; + unsigned int queue_entry_size; + struct aspeed_xdma_regs regs; + struct aspeed_xdma_status_bits status_bits; + unsigned int (*set_cmd)(struct aspeed_xdma *ctx, + struct aspeed_xdma_cmd *cmds, + struct aspeed_xdma_op *op, u32 bmc_addr); +}; + +struct aspeed_xdma_client; + +struct aspeed_xdma { + const struct aspeed_xdma_chip *chip; + + struct device *dev; + void __iomem *base; + struct clk *clock; + struct reset_control *reset; + + /* client_lock protects error and in_progress of the client */ + spinlock_t client_lock; + struct aspeed_xdma_client *current_client; + + /* start_lock protects cmd_idx, cmdq, and the state of the engine */ + struct mutex start_lock; + struct aspeed_xdma_cmd *cmdq; + bool upstream; + unsigned int cmd_idx; + + /* reset_lock protects in_reset and the reset state of the engine */ + spinlock_t reset_lock; + bool in_reset; + + wait_queue_head_t wait; + struct work_struct reset_work; + + u32 mem_phys; + u32 mem_size; + void __iomem *mem_virt; + dma_addr_t cmdq_phys; + struct gen_pool *pool; +}; + +struct aspeed_xdma_client { + struct aspeed_xdma *ctx; + + bool error; + bool in_progress; + void *virt; + dma_addr_t phys; + u32 size; +}; + +static u32 aspeed_xdma_readl(struct aspeed_xdma *ctx, u8 reg) +{ + u32 v = readl(ctx->base + reg); + + dev_dbg(ctx->dev, "read %02x[%08x]\n", reg, v); + return v; +} + +static void aspeed_xdma_writel(struct aspeed_xdma *ctx, u8 reg, u32 val) +{ + writel(val, ctx->base + reg); + dev_dbg(ctx->dev, "write %02x[%08x]\n", reg, val); +} + +static void aspeed_xdma_init_eng(struct aspeed_xdma *ctx) +{ + aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_endp, + ctx->chip->queue_entry_size * XDMA_NUM_CMDS); + aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_readp, + XDMA_BMC_CMDQ_READP_RESET); + aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_writep, 0); + aspeed_xdma_writel(ctx, ctx->chip->regs.control, ctx->chip->control); + aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_addr, ctx->cmdq_phys); + + ctx->cmd_idx = 0; + ctx->current_client = NULL; +} + +static unsigned int aspeed_xdma_ast2500_set_cmd(struct aspeed_xdma *ctx, + struct aspeed_xdma_cmd *cmds, + struct aspeed_xdma_op *op, + u32 bmc_addr) +{ + unsigned int rc = 1; + unsigned int pitch = 1; + unsigned int line_no = 1; + unsigned int line_size = op->len >> + XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT; + u64 cmd = XDMA_CMD_AST2500_CMD_IRQ_EN | XDMA_CMD_AST2500_CMD_IRQ_BMC | + XDMA_CMD_AST2500_CMD_ID; + u64 cmd_pitch = (op->direction ? XDMA_CMD_AST2500_PITCH_UPSTREAM : 0) | + XDMA_CMD_AST2500_PITCH_ID; + + dev_dbg(ctx->dev, "xdma %s ast2500: bmc[%08x] len[%08x] host[%08x]\n", + op->direction ? "upstream" : "downstream", bmc_addr, op->len, + (u32)op->host_addr); + + if (op->len > XDMA_CMD_AST2500_CMD_LINE_SIZE) { + unsigned int rem; + unsigned int total; + + line_no = op->len / XDMA_CMD_AST2500_CMD_LINE_SIZE; + total = XDMA_CMD_AST2500_CMD_LINE_SIZE * line_no; + rem = (op->len - total) >> + XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT; + line_size = XDMA_CMD_AST2500_CMD_LINE_SIZE; + pitch = line_size >> XDMA_CMD_AST2500_PITCH_SHIFT; + line_size >>= XDMA_CMD_AST2500_CMD_LINE_SIZE_SHIFT; + + if (rem) { + u32 rbmc = bmc_addr + total; + + cmds[1].host_addr = op->host_addr + (u64)total; + cmds[1].pitch = cmd_pitch | + ((u64)rbmc & XDMA_CMD_AST2500_PITCH_ADDR) | + FIELD_PREP(XDMA_CMD_AST2500_PITCH_HOST, 1) | + FIELD_PREP(XDMA_CMD_AST2500_PITCH_BMC, 1); + cmds[1].cmd = cmd | + FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_NO, 1) | + FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_SIZE, + rem); + cmds[1].reserved = 0ULL; + + print_hex_dump_debug("xdma rem ", DUMP_PREFIX_OFFSET, + 16, 1, &cmds[1], sizeof(*cmds), + true); + + cmd &= ~(XDMA_CMD_AST2500_CMD_IRQ_EN | + XDMA_CMD_AST2500_CMD_IRQ_BMC); + + rc++; + } + } + + cmds[0].host_addr = op->host_addr; + cmds[0].pitch = cmd_pitch | + ((u64)bmc_addr & XDMA_CMD_AST2500_PITCH_ADDR) | + FIELD_PREP(XDMA_CMD_AST2500_PITCH_HOST, pitch) | + FIELD_PREP(XDMA_CMD_AST2500_PITCH_BMC, pitch); + cmds[0].cmd = cmd | FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_NO, line_no) | + FIELD_PREP(XDMA_CMD_AST2500_CMD_LINE_SIZE, line_size); + cmds[0].reserved = 0ULL; + + print_hex_dump_debug("xdma cmd ", DUMP_PREFIX_OFFSET, 16, 1, cmds, + sizeof(*cmds), true); + + return rc; +} + +static unsigned int aspeed_xdma_ast2600_set_cmd(struct aspeed_xdma *ctx, + struct aspeed_xdma_cmd *cmds, + struct aspeed_xdma_op *op, + u32 bmc_addr) +{ + unsigned int rc = 1; + unsigned int pitch = 1; + unsigned int line_no = 1; + unsigned int line_size = op->len; + u64 cmd = XDMA_CMD_AST2600_CMD_IRQ_BMC | + (op->direction ? XDMA_CMD_AST2600_CMD_UPSTREAM : 0); + + if (op->host_addr & 0xffffffff00000000ULL || + (op->host_addr + (u64)op->len) & 0xffffffff00000000ULL) + cmd |= XDMA_CMD_AST2600_CMD_64_EN; + + dev_dbg(ctx->dev, "xdma %s ast2600: bmc[%08x] len[%08x] " + "host[%016llx]\n", op->direction ? "upstream" : "downstream", + bmc_addr, op->len, op->host_addr); + + if (op->len > XDMA_CMD_AST2600_CMD_LINE_SIZE) { + unsigned int rem; + unsigned int total; + + line_no = op->len / XDMA_CMD_AST2600_CMD_MULTILINE_SIZE; + total = XDMA_CMD_AST2600_CMD_MULTILINE_SIZE * line_no; + rem = op->len - total; + line_size = XDMA_CMD_AST2600_CMD_MULTILINE_SIZE; + pitch = line_size; + + if (rem) { + u32 rbmc = bmc_addr + total; + + cmds[1].host_addr = op->host_addr + (u64)total; + cmds[1].pitch = + ((u64)rbmc & XDMA_CMD_AST2600_PITCH_ADDR) | + FIELD_PREP(XDMA_CMD_AST2600_PITCH_HOST, 1) | + FIELD_PREP(XDMA_CMD_AST2600_PITCH_BMC, 1); + cmds[1].cmd = cmd | + FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_NO, 1) | + FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_SIZE, + rem); + cmds[1].reserved = 0ULL; + + print_hex_dump_debug("xdma rem ", DUMP_PREFIX_OFFSET, + 16, 1, &cmds[1], sizeof(*cmds), + true); + + cmd &= ~XDMA_CMD_AST2600_CMD_IRQ_BMC; + + rc++; + } + } + + cmds[0].host_addr = op->host_addr; + cmds[0].pitch = ((u64)bmc_addr & XDMA_CMD_AST2600_PITCH_ADDR) | + FIELD_PREP(XDMA_CMD_AST2600_PITCH_HOST, pitch) | + FIELD_PREP(XDMA_CMD_AST2600_PITCH_BMC, pitch); + cmds[0].cmd = cmd | FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_NO, line_no) | + FIELD_PREP(XDMA_CMD_AST2600_CMD_LINE_SIZE, line_size); + cmds[0].reserved = 0ULL; + + print_hex_dump_debug("xdma cmd ", DUMP_PREFIX_OFFSET, 16, 1, cmds, + sizeof(*cmds), true); + + return rc; +} + +static void aspeed_xdma_start(struct aspeed_xdma *ctx, + struct aspeed_xdma_op *op, u32 bmc_addr, + struct aspeed_xdma_client *client) +{ + unsigned long flags; + struct aspeed_xdma_cmd cmds[2]; + unsigned int rc = ctx->chip->set_cmd(ctx, cmds, op, bmc_addr); + + mutex_lock(&ctx->start_lock); + + memcpy(&ctx->cmdq[ctx->cmd_idx], cmds, + rc * sizeof(struct aspeed_xdma_cmd)); + ctx->cmd_idx = (ctx->cmd_idx + rc) % XDMA_NUM_CMDS; + ctx->upstream = !!op->direction; + + spin_lock_irqsave(&ctx->client_lock, flags); + + client->error = false; + client->in_progress = true; + ctx->current_client = client; + + spin_unlock_irqrestore(&ctx->client_lock, flags); + + aspeed_xdma_writel(ctx, ctx->chip->regs.bmc_cmdq_writep, + ctx->cmd_idx * ctx->chip->queue_entry_size); + + mutex_unlock(&ctx->start_lock); +} + +static void aspeed_xdma_done(struct aspeed_xdma *ctx, bool error) +{ + unsigned long flags; + + spin_lock_irqsave(&ctx->client_lock, flags); + + if (ctx->current_client) { + ctx->current_client->error = error; + ctx->current_client->in_progress = false; + ctx->current_client = NULL; + } + + spin_unlock_irqrestore(&ctx->client_lock, flags); + + wake_up_interruptible_all(&ctx->wait); +} + +static irqreturn_t aspeed_xdma_irq(int irq, void *arg) +{ + struct aspeed_xdma *ctx = arg; + u32 status = aspeed_xdma_readl(ctx, ctx->chip->regs.status); + + if (status & ctx->chip->status_bits.ds_dirty) { + aspeed_xdma_done(ctx, true); + } else { + if (status & ctx->chip->status_bits.us_comp) { + if (ctx->upstream) + aspeed_xdma_done(ctx, false); + } + + if (status & ctx->chip->status_bits.ds_comp) { + if (!ctx->upstream) + aspeed_xdma_done(ctx, false); + } + } + + aspeed_xdma_writel(ctx, ctx->chip->regs.status, status); + + return IRQ_HANDLED; +} + +static void aspeed_xdma_reset(struct aspeed_xdma *ctx) +{ + reset_control_assert(ctx->reset); + msleep(XDMA_RESET_TIME_MS); + + reset_control_deassert(ctx->reset); + msleep(XDMA_RESET_TIME_MS); + + aspeed_xdma_init_eng(ctx); + + ctx->in_reset = false; + aspeed_xdma_done(ctx, true); +} + +static void aspeed_xdma_reset_work(struct work_struct *work) +{ + struct aspeed_xdma *ctx = container_of(work, struct aspeed_xdma, + reset_work); + + /* + * Lock to make sure operations aren't started while the engine is + * in reset. + */ + mutex_lock(&ctx->start_lock); + + aspeed_xdma_reset(ctx); + + mutex_unlock(&ctx->start_lock); +} + +static irqreturn_t aspeed_xdma_pcie_irq(int irq, void *arg) +{ + unsigned long flags; + struct aspeed_xdma *ctx = arg; + + dev_dbg(ctx->dev, "pcie reset\n"); + + spin_lock_irqsave(&ctx->reset_lock, flags); + if (ctx->in_reset) { + spin_unlock_irqrestore(&ctx->reset_lock, flags); + return IRQ_HANDLED; + } + + ctx->in_reset = true; + spin_unlock_irqrestore(&ctx->reset_lock, flags); + + schedule_work(&ctx->reset_work); + return IRQ_HANDLED; +} + +static int aspeed_xdma_probe(struct platform_device *pdev) +{ + int rc; + int irq; + int pcie_irq; + u32 memory[2]; + struct regmap *scu; + struct aspeed_xdma *ctx; + struct device *dev = &pdev->dev; + const void *md = of_device_get_match_data(dev); + + if (!md) + return -ENODEV; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->chip = md; + ctx->dev = dev; + platform_set_drvdata(pdev, ctx); + mutex_init(&ctx->start_lock); + INIT_WORK(&ctx->reset_work, aspeed_xdma_reset_work); + spin_lock_init(&ctx->client_lock); + spin_lock_init(&ctx->reset_lock); + init_waitqueue_head(&ctx->wait); + + ctx->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ctx->base)) { + dev_err(dev, "Failed to map registers.\n"); + return PTR_ERR(ctx->base); + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "Unable to find IRQ.\n"); + return irq; + } + + rc = devm_request_irq(dev, irq, aspeed_xdma_irq, IRQF_SHARED, + DEVICE_NAME, ctx); + if (rc < 0) { + dev_err(dev, "Failed to request IRQ %d.\n", irq); + return rc; + } + + ctx->clock = devm_clk_get(dev, NULL); + if (IS_ERR(ctx->clock)) { + dev_err(dev, "Failed to request clock.\n"); + return PTR_ERR(ctx->clock); + } + + ctx->reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(ctx->reset)) { + dev_err(dev, "Failed to request reset control.\n"); + return PTR_ERR(ctx->reset); + } + + ctx->pool = devm_gen_pool_create(dev, ilog2(PAGE_SIZE), -1, NULL); + if (!ctx->pool) { + dev_err(dev, "Failed to setup genalloc pool.\n"); + return -ENOMEM; + } + + rc = of_property_read_u32_array(dev->of_node, "memory", memory, 2); + if (rc) { + dev_err(dev, "Unable to get memory space.\n"); + return rc; + } + + ctx->mem_phys = memory[0]; + ctx->mem_size = memory[1]; + + ctx->mem_virt = devm_ioremap(dev, ctx->mem_phys, ctx->mem_size); + if (IS_ERR(ctx->mem_virt)) { + dev_err(dev, "Failed to map memory space.\n"); + return PTR_ERR(ctx->mem_virt); + } + + rc = gen_pool_add_virt(ctx->pool, (unsigned long)ctx->mem_virt, + ctx->mem_phys, ctx->mem_size, -1); + if (rc) { + dev_err(ctx->dev, "Failed to add memory to genalloc pool.\n"); + return rc; + } + + scu = syscon_regmap_lookup_by_phandle(dev->of_node, "scu"); + if (!IS_ERR(scu)) { + u32 selection; + bool pcie_device_bmc = true; + const u32 bmc = SCU_PCIE_CONF_BMC_EN | + SCU_PCIE_CONF_BMC_EN_MSI | SCU_PCIE_CONF_BMC_EN_IRQ | + SCU_PCIE_CONF_BMC_EN_DMA; + const u32 vga = SCU_PCIE_CONF_VGA_EN | + SCU_PCIE_CONF_VGA_EN_MSI | SCU_PCIE_CONF_VGA_EN_IRQ | + SCU_PCIE_CONF_VGA_EN_DMA; + const char *pcie = NULL; + + if (!of_property_read_string(dev->of_node, "pcie-device", + &pcie)) { + if (!strcmp(pcie, "vga")) { + pcie_device_bmc = false; + } else if (strcmp(pcie, "bmc")) { + dev_err(ctx->dev, + "Invalid pcie-device property %s.\n", + pcie); + return -EINVAL; + } + } + + if (pcie_device_bmc) { + selection = bmc; + regmap_write(scu, ctx->chip->scu_bmc_class, + SCU_BMC_CLASS_REV_XDMA); + } else { + selection = vga; + } + + regmap_update_bits(scu, ctx->chip->scu_pcie_conf, bmc | vga, + selection); + } else { + dev_warn(dev, "Unable to configure PCIe; continuing.\n"); + } + + rc = clk_prepare_enable(ctx->clock); + if (rc) { + dev_err(dev, "Failed to enable the clock.\n"); + return rc; + } + msleep(XDMA_RESET_TIME_MS); + + rc = reset_control_deassert(ctx->reset); + if (rc) { + clk_disable_unprepare(ctx->clock); + + dev_err(dev, "Failed to clear the reset.\n"); + return rc; + } + msleep(XDMA_RESET_TIME_MS); + + ctx->cmdq = gen_pool_dma_alloc(ctx->pool, XDMA_CMDQ_SIZE, + &ctx->cmdq_phys); + if (!ctx->cmdq) { + dev_err(ctx->dev, "Failed to genalloc cmdq.\n"); + + reset_control_assert(ctx->reset); + clk_disable_unprepare(ctx->clock); + return -ENOMEM; + } + + aspeed_xdma_init_eng(ctx); + + /* + * This interrupt could fire immediately so only request it once the + * engine and driver are initialized. + */ + pcie_irq = platform_get_irq(pdev, 1); + if (pcie_irq < 0) { + dev_warn(dev, "Unable to find PCI-E IRQ.\n"); + } else { + rc = devm_request_irq(dev, pcie_irq, aspeed_xdma_pcie_irq, + IRQF_SHARED, DEVICE_NAME, ctx); + if (rc < 0) + dev_warn(dev, "Failed to request PCI-E IRQ %d.\n", rc); + } + + return 0; +} + +static int aspeed_xdma_remove(struct platform_device *pdev) +{ + struct aspeed_xdma *ctx = platform_get_drvdata(pdev); + + gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq_virt, + XDMA_CMDQ_SIZE); + + reset_control_assert(ctx->reset); + clk_disable_unprepare(ctx->clock); + + return 0; +} + +static const struct aspeed_xdma_chip aspeed_ast2500_xdma_chip = { + .control = XDMA_AST2500_CTRL_US_COMP | XDMA_AST2500_CTRL_DS_COMP | + XDMA_AST2500_CTRL_DS_DIRTY | XDMA_AST2500_CTRL_DS_SIZE_256 | + XDMA_AST2500_CTRL_DS_TIMEOUT | XDMA_AST2500_CTRL_DS_CHECK_ID, + .scu_bmc_class = SCU_AST2500_BMC_CLASS_REV, + .scu_pcie_conf = SCU_AST2500_PCIE_CONF, + .queue_entry_size = XDMA_AST2500_QUEUE_ENTRY_SIZE, + .regs = { + .bmc_cmdq_addr = XDMA_AST2500_BMC_CMDQ_ADDR, + .bmc_cmdq_endp = XDMA_AST2500_BMC_CMDQ_ENDP, + .bmc_cmdq_writep = XDMA_AST2500_BMC_CMDQ_WRITEP, + .bmc_cmdq_readp = XDMA_AST2500_BMC_CMDQ_READP, + .control = XDMA_AST2500_CTRL, + .status = XDMA_AST2500_STATUS, + }, + .status_bits = { + .us_comp = XDMA_AST2500_STATUS_US_COMP, + .ds_comp = XDMA_AST2500_STATUS_DS_COMP, + .ds_dirty = XDMA_AST2500_STATUS_DS_DIRTY, + }, + .set_cmd = aspeed_xdma_ast2500_set_cmd, +}; + +static const struct aspeed_xdma_chip aspeed_ast2600_xdma_chip = { + .control = XDMA_AST2600_CTRL_US_COMP | XDMA_AST2600_CTRL_DS_COMP | + XDMA_AST2600_CTRL_DS_DIRTY | XDMA_AST2600_CTRL_DS_SIZE_256, + .scu_bmc_class = SCU_AST2600_BMC_CLASS_REV, + .scu_pcie_conf = SCU_AST2600_PCIE_CONF, + .queue_entry_size = XDMA_AST2600_QUEUE_ENTRY_SIZE, + .regs = { + .bmc_cmdq_addr = XDMA_AST2600_BMC_CMDQ_ADDR, + .bmc_cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP, + .bmc_cmdq_writep = XDMA_AST2600_BMC_CMDQ_WRITEP, + .bmc_cmdq_readp = XDMA_AST2600_BMC_CMDQ_READP, + .control = XDMA_AST2600_CTRL, + .status = XDMA_AST2600_STATUS, + }, + .status_bits = { + .us_comp = XDMA_AST2600_STATUS_US_COMP, + .ds_comp = XDMA_AST2600_STATUS_DS_COMP, + .ds_dirty = XDMA_AST2600_STATUS_DS_DIRTY, + }, + .set_cmd = aspeed_xdma_ast2600_set_cmd, +}; + +static const struct of_device_id aspeed_xdma_match[] = { + { + .compatible = "aspeed,ast2500-xdma", + .data = &aspeed_ast2500_xdma_chip, + }, + { + .compatible = "aspeed,ast2600-xdma", + .data = &aspeed_ast2600_xdma_chip, + }, + { }, +}; + +static struct platform_driver aspeed_xdma_driver = { + .probe = aspeed_xdma_probe, + .remove = aspeed_xdma_remove, + .driver = { + .name = DEVICE_NAME, + .of_match_table = aspeed_xdma_match, + }, +}; + +module_platform_driver(aspeed_xdma_driver); + +MODULE_AUTHOR("Eddie James"); +MODULE_DESCRIPTION("Aspeed XDMA Engine Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/uapi/linux/aspeed-xdma.h b/include/uapi/linux/aspeed-xdma.h new file mode 100644 index 000000000000..2efaa6067c39 --- /dev/null +++ b/include/uapi/linux/aspeed-xdma.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* Copyright IBM Corp 2019 */ + +#ifndef _UAPI_LINUX_ASPEED_XDMA_H_ +#define _UAPI_LINUX_ASPEED_XDMA_H_ + +#include + +/* + * aspeed_xdma_direction + * + * ASPEED_XDMA_DIRECTION_DOWNSTREAM: transfers data from the host to the BMC + * + * ASPEED_XDMA_DIRECTION_UPSTREAM: transfers data from the BMC to the host + */ +enum aspeed_xdma_direction { + ASPEED_XDMA_DIRECTION_DOWNSTREAM = 0, + ASPEED_XDMA_DIRECTION_UPSTREAM, +}; + +/* + * aspeed_xdma_op + * + * host_addr: the DMA address on the host side, typically configured by PCI + * subsystem + * + * len: the size of the transfer in bytes + * + * direction: an enumerator indicating the direction of the DMA operation; see + * enum aspeed_xdma_direction + */ +struct aspeed_xdma_op { + __u64 host_addr; + __u32 len; + __u32 direction; +}; + +#endif /* _UAPI_LINUX_ASPEED_XDMA_H_ */ From patchwork Wed Dec 18 15:09:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQk0BYmz9sRv for ; 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Wed, 18 Dec 2019 10:09:51 -0500 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wyjf8hpf3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:50 -0500 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF8bpB015102; Wed, 18 Dec 2019 15:09:49 GMT Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by ppma02wdc.us.ibm.com with ESMTP id 2wvqc6pd5n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:49 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9muO49742110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:48 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5410C136053; Wed, 18 Dec 2019 15:09:48 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4AC2613604F; Wed, 18 Dec 2019 15:09:47 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:47 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 07/12] soc: aspeed: xdma: Add user interface Date: Wed, 18 Dec 2019 09:09:33 -0600 Message-Id: <1576681778-18737-8-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 suspectscore=4 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" This commits adds a miscdevice to provide a user interface to the XDMA engine. The interface provides the write operation to start DMA operations. The DMA parameters are passed as the data to the write call. The actual data to transfer is NOT passed through write. Note that both directions of DMA operation are accomplished through the write command; BMC to host and host to BMC. The XDMA driver reserves an area of physical memory for DMA operations, as the XDMA engine is restricted to accessing certain physical memory areas on some platforms. This memory forms a pool from which users can allocate pages for their usage with calls to mmap. The space allocated by a client will be the space used in the DMA operation. For an "upstream" (BMC to host) operation, the data in the client's area will be transferred to the host. For a "downstream" (host to BMC) operation, the host data will be placed in the client's memory area. Poll is also provided in order to determine when the DMA operation is complete for non-blocking IO. Signed-off-by: Eddie James --- Changes since v2: - Rework commit message to talk about VGA memory less - Remove user reset functionality - Clean up sanity checks in aspeed_xdma_write() - Wait for transfer complete in the vm area close function drivers/soc/aspeed/aspeed-xdma.c | 205 ++++++++++++++++++++++++++++++- 1 file changed, 203 insertions(+), 2 deletions(-) diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c index cb94adf798b1..e844937dc925 100644 --- a/drivers/soc/aspeed/aspeed-xdma.c +++ b/drivers/soc/aspeed/aspeed-xdma.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -201,6 +202,8 @@ struct aspeed_xdma { struct clk *clock; struct reset_control *reset; + /* file_lock serializes reads of current_client */ + struct mutex file_lock; /* client_lock protects error and in_progress of the client */ spinlock_t client_lock; struct aspeed_xdma_client *current_client; @@ -223,6 +226,8 @@ struct aspeed_xdma { void __iomem *mem_virt; dma_addr_t cmdq_phys; struct gen_pool *pool; + + struct miscdevice misc; }; struct aspeed_xdma_client { @@ -522,6 +527,185 @@ static irqreturn_t aspeed_xdma_pcie_irq(int irq, void *arg) return IRQ_HANDLED; } +static ssize_t aspeed_xdma_write(struct file *file, const char __user *buf, + size_t len, loff_t *offset) +{ + int rc; + struct aspeed_xdma_op op; + struct aspeed_xdma_client *client = file->private_data; + struct aspeed_xdma *ctx = client->ctx; + + if (len != sizeof(op)) + return -EINVAL; + + rc = copy_from_user(&op, buf, len); + if (rc) + return rc; + + if (!op.len || op.len > client->size || + op.direction > ASPEED_XDMA_DIRECTION_UPSTREAM) + return -EINVAL; + + if (file->f_flags & O_NONBLOCK) { + if (!mutex_trylock(&ctx->file_lock)) + return -EAGAIN; + + if (ctx->current_client) { + mutex_unlock(&ctx->file_lock); + return -EBUSY; + } + } else { + mutex_lock(&ctx->file_lock); + + rc = wait_event_interruptible(ctx->wait, !ctx->current_client); + if (rc) { + mutex_unlock(&ctx->file_lock); + return -EINTR; + } + } + + aspeed_xdma_start(ctx, &op, client->phys, client); + + mutex_unlock(&ctx->file_lock); + + if (!(file->f_flags & O_NONBLOCK)) { + rc = wait_event_interruptible(ctx->wait, !client->in_progress); + if (rc) + return -EINTR; + + if (client->error) + return -EIO; + } + + return len; +} + +static __poll_t aspeed_xdma_poll(struct file *file, + struct poll_table_struct *wait) +{ + __poll_t mask = 0; + __poll_t req = poll_requested_events(wait); + struct aspeed_xdma_client *client = file->private_data; + struct aspeed_xdma *ctx = client->ctx; + + if (req & (EPOLLIN | EPOLLRDNORM)) { + if (client->in_progress) + poll_wait(file, &ctx->wait, wait); + + if (!client->in_progress) { + if (client->error) + mask |= EPOLLERR; + else + mask |= EPOLLIN | EPOLLRDNORM; + } + } + + if (req & (EPOLLOUT | EPOLLWRNORM)) { + if (ctx->current_client) + poll_wait(file, &ctx->wait, wait); + + if (!ctx->current_client) + mask |= EPOLLOUT | EPOLLWRNORM; + } + + return mask; +} + +static void aspeed_xdma_vma_close(struct vm_area_struct *vma) +{ + int rc; + struct aspeed_xdma_client *client = vma->vm_private_data; + + rc = wait_event_interruptible(client->ctx->wait, !client->in_progress); + if (rc) + return; + + gen_pool_free(client->ctx->pool, (unsigned long)client->virt, + client->size); + + client->virt = NULL; + client->phys = 0; + client->size = 0; +} + +static const struct vm_operations_struct aspeed_xdma_vm_ops = { + .close = aspeed_xdma_vma_close, +}; + +static int aspeed_xdma_mmap(struct file *file, struct vm_area_struct *vma) +{ + int rc; + struct aspeed_xdma_client *client = file->private_data; + struct aspeed_xdma *ctx = client->ctx; + + /* restrict file to one mapping */ + if (client->size) + return -EBUSY; + + client->size = vma->vm_end - vma->vm_start; + client->virt = gen_pool_dma_alloc(ctx->pool, client->size, + &client->phys); + if (!client->virt) { + client->phys = 0; + client->size = 0; + return -ENOMEM; + } + + vma->vm_pgoff = (client->phys - ctx->mem_phys) >> PAGE_SHIFT; + vma->vm_ops = &aspeed_xdma_vm_ops; + vma->vm_private_data = client; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + rc = io_remap_pfn_range(vma, vma->vm_start, client->phys >> PAGE_SHIFT, + client->size, vma->vm_page_prot); + if (rc) { + gen_pool_free(ctx->pool, (unsigned long)client->virt, + client->size); + + client->virt = NULL; + client->phys = 0; + client->size = 0; + return rc; + } + + dev_dbg(ctx->dev, "mmap: v[%08lx] to p[%08x], s[%08x]\n", + vma->vm_start, (u32)client->phys, client->size); + + return 0; +} + +static int aspeed_xdma_open(struct inode *inode, struct file *file) +{ + struct miscdevice *misc = file->private_data; + struct aspeed_xdma *ctx = container_of(misc, struct aspeed_xdma, misc); + struct aspeed_xdma_client *client = kzalloc(sizeof(*client), + GFP_KERNEL); + + if (!client) + return -ENOMEM; + + client->ctx = ctx; + file->private_data = client; + return 0; +} + +static int aspeed_xdma_release(struct inode *inode, struct file *file) +{ + struct aspeed_xdma_client *client = file->private_data; + + kfree(client); + return 0; +} + +static const struct file_operations aspeed_xdma_fops = { + .owner = THIS_MODULE, + .write = aspeed_xdma_write, + .poll = aspeed_xdma_poll, + .mmap = aspeed_xdma_mmap, + .open = aspeed_xdma_open, + .release = aspeed_xdma_release, +}; + static int aspeed_xdma_probe(struct platform_device *pdev) { int rc; @@ -543,6 +727,7 @@ static int aspeed_xdma_probe(struct platform_device *pdev) ctx->chip = md; ctx->dev = dev; platform_set_drvdata(pdev, ctx); + mutex_init(&ctx->file_lock); mutex_init(&ctx->start_lock); INIT_WORK(&ctx->reset_work, aspeed_xdma_reset_work); spin_lock_init(&ctx->client_lock); @@ -674,6 +859,22 @@ static int aspeed_xdma_probe(struct platform_device *pdev) aspeed_xdma_init_eng(ctx); + ctx->misc.minor = MISC_DYNAMIC_MINOR; + ctx->misc.fops = &aspeed_xdma_fops; + ctx->misc.name = "aspeed-xdma"; + ctx->misc.parent = dev; + rc = misc_register(&ctx->misc); + if (rc) { + dev_err(dev, "Failed to register xdma miscdevice.\n"); + + gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq, + XDMA_CMDQ_SIZE); + + reset_control_assert(ctx->reset); + clk_disable_unprepare(ctx->clock); + return rc; + } + /* * This interrupt could fire immediately so only request it once the * engine and driver are initialized. @@ -695,8 +896,8 @@ static int aspeed_xdma_remove(struct platform_device *pdev) { struct aspeed_xdma *ctx = platform_get_drvdata(pdev); - gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq_virt, - XDMA_CMDQ_SIZE); + misc_deregister(&ctx->misc); + gen_pool_free(ctx->pool, (unsigned long)ctx->cmdq, XDMA_CMDQ_SIZE); reset_control_assert(ctx->reset); clk_disable_unprepare(ctx->clock); From patchwork Wed Dec 18 15:09:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJRR1wNSz9sSL for ; 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Wed, 18 Dec 2019 10:09:53 -0500 Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wyjb58061-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:51 -0500 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIEt5J5016038; Wed, 18 Dec 2019 15:09:50 GMT Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by ppma05wdc.us.ibm.com with ESMTP id 2wvqc6e8sh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:50 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9n4t41419236 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:49 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 73CF2136053; Wed, 18 Dec 2019 15:09:49 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 82500136051; Wed, 18 Dec 2019 15:09:48 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:48 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 08/12] soc: aspeed: xdma: Add reset ioctl Date: Wed, 18 Dec 2019 09:09:34 -0600 Message-Id: <1576681778-18737-9-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 spamscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 priorityscore=1501 adultscore=0 suspectscore=1 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Users of the XDMA engine need a way to reset it if something goes wrong. Problems on the host side, or user error, such as incorrect host address, may result in the DMA operation never completing and no way to determine what went wrong. Therefore, add an ioctl to reset the engine so that users can recover in this situation. Signed-off-by: Eddie James --- drivers/soc/aspeed/aspeed-xdma.c | 36 ++++++++++++++++++++++++++++++++ include/uapi/linux/aspeed-xdma.h | 4 ++++ 2 files changed, 40 insertions(+) diff --git a/drivers/soc/aspeed/aspeed-xdma.c b/drivers/soc/aspeed/aspeed-xdma.c index e844937dc925..21a36b59e718 100644 --- a/drivers/soc/aspeed/aspeed-xdma.c +++ b/drivers/soc/aspeed/aspeed-xdma.c @@ -611,6 +611,41 @@ static __poll_t aspeed_xdma_poll(struct file *file, return mask; } +static long aspeed_xdma_ioctl(struct file *file, unsigned int cmd, + unsigned long param) +{ + unsigned long flags; + struct aspeed_xdma_client *client = file->private_data; + struct aspeed_xdma *ctx = client->ctx; + + switch (cmd) { + case ASPEED_XDMA_IOCTL_RESET: + spin_lock_irqsave(&ctx->reset_lock, flags); + if (ctx->in_reset) { + spin_unlock_irqrestore(&ctx->reset_lock, flags); + return 0; + } + + ctx->in_reset = true; + spin_unlock_irqrestore(&ctx->reset_lock, flags); + + if (ctx->current_client) + dev_warn(ctx->dev, + "User reset with transfer in progress.\n"); + + mutex_lock(&ctx->start_lock); + + aspeed_xdma_reset(ctx); + + mutex_unlock(&ctx->start_lock); + break; + default: + return -EINVAL; + } + + return 0; +} + static void aspeed_xdma_vma_close(struct vm_area_struct *vma) { int rc; @@ -701,6 +736,7 @@ static const struct file_operations aspeed_xdma_fops = { .owner = THIS_MODULE, .write = aspeed_xdma_write, .poll = aspeed_xdma_poll, + .unlocked_ioctl = aspeed_xdma_ioctl, .mmap = aspeed_xdma_mmap, .open = aspeed_xdma_open, .release = aspeed_xdma_release, diff --git a/include/uapi/linux/aspeed-xdma.h b/include/uapi/linux/aspeed-xdma.h index 2efaa6067c39..3a3646fd1e9e 100644 --- a/include/uapi/linux/aspeed-xdma.h +++ b/include/uapi/linux/aspeed-xdma.h @@ -4,8 +4,12 @@ #ifndef _UAPI_LINUX_ASPEED_XDMA_H_ #define _UAPI_LINUX_ASPEED_XDMA_H_ +#include #include +#define __ASPEED_XDMA_IOCTL_MAGIC 0xb7 +#define ASPEED_XDMA_IOCTL_RESET _IO(__ASPEED_XDMA_IOCTL_MAGIC, 0) + /* * aspeed_xdma_direction * From patchwork Wed Dec 18 15:09:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJPb3ZSPz9sSP for ; Thu, 19 Dec 2019 02:11:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJPb2BCXzDqj1 for ; Thu, 19 Dec 2019 02:11:31 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; 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Wed, 18 Dec 2019 15:09:52 GMT Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by ppma04dal.us.ibm.com with ESMTP id 2wvqc6yxkw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:51 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9osV58196282 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:50 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 877F5136053; Wed, 18 Dec 2019 15:09:50 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A175513604F; Wed, 18 Dec 2019 15:09:49 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:49 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 09/12] ARM: dts: aspeed: ast2500: Add XDMA Engine Date: Wed, 18 Dec 2019 09:09:35 -0600 Message-Id: <1576681778-18737-10-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 spamscore=0 mlxscore=0 adultscore=0 mlxlogscore=914 phishscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James --- Changes since v2: - Remove addition of sdmc stuff arch/arm/boot/dts/aspeed-g5.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 4791a50e37ee..777eeca9c550 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include +#include / { model = "Aspeed BMC"; @@ -257,6 +258,17 @@ gfx: display@1e6e6000 { interrupts = <0x19>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; + pcie-device = "bmc"; + scu = <&syscon>; + status = "disabled"; + }; + adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; From patchwork Wed Dec 18 15:09:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212510 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJPJ00TZz9sRv for ; Thu, 19 Dec 2019 02:11:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47dJPH2Dr7zDqjN for ; Thu, 19 Dec 2019 02:11:15 +1100 (AEDT) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=eajames@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47dJNw3X1nzDqht for ; Thu, 19 Dec 2019 02:10:05 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBIEsGdl033776; Wed, 18 Dec 2019 10:09:54 -0500 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wyp9erkua-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:53 -0500 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF4nO7006295; Wed, 18 Dec 2019 15:09:52 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma04wdc.us.ibm.com with ESMTP id 2wvqc6p72v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:52 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9pd156754674 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:51 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C4B7136059; Wed, 18 Dec 2019 15:09:51 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BD5A7136055; Wed, 18 Dec 2019 15:09:50 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:50 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 10/12] ARM: dts: aspeed: ast2600: Add XDMA Engine Date: Wed, 18 Dec 2019 09:09:36 -0600 Message-Id: <1576681778-18737-11-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=1 clxscore=1015 impostorscore=0 mlxlogscore=871 priorityscore=1501 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James --- Changes since v2: - Remove addition of sdmc stuff arch/arm/boot/dts/aspeed-g6.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index ead336e93a12..d5ee235790f5 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { model = "Aspeed BMC"; @@ -311,6 +312,18 @@ rng: hwrng@1e6e2524 { quality = <100>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2600-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>; + interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; + pcie-device = "bmc"; + scu = <&syscon>; + status = "disabled"; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; From patchwork Wed Dec 18 15:09:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQF1kQLz9sSX for ; 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Wed, 18 Dec 2019 10:09:55 -0500 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0b-001b2d01.pphosted.com with ESMTP id 2wykb7fw6m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 10:09:55 -0500 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBIF8bSZ002226; Wed, 18 Dec 2019 15:09:54 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma04dal.us.ibm.com with ESMTP id 2wvqc6yxmc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2019 15:09:54 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBIF9qpG42271034 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Dec 2019 15:09:53 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ABD64136059; Wed, 18 Dec 2019 15:09:52 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9008136063; Wed, 18 Dec 2019 15:09:51 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:51 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 11/12] ARM: dts: aspeed: witherspoon: Enable XDMA Engine Date: Wed, 18 Dec 2019 09:09:37 -0600 Message-Id: <1576681778-18737-12-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 spamscore=0 mlxscore=0 adultscore=0 mlxlogscore=723 phishscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Enable the XDMA engine node. Signed-off-by: Eddie James --- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 569dad93e162..1a28b86f00ea 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -658,4 +658,9 @@ &video { memory-region = <&video_engine_memory>; }; +&xdma { + status = "okay"; + memory = <0x9f000000 0x01000000>; +}; + #include "ibm-power9-dual.dtsi" From patchwork Wed Dec 18 15:09:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 1212522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47dJQz3tfvz9sRv for ; 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Wed, 18 Dec 2019 15:09:53 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CEEE0136053; Wed, 18 Dec 2019 15:09:52 +0000 (GMT) Received: from talon7.ibm.com (unknown [9.41.103.158]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 18 Dec 2019 15:09:52 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 12/12] ARM: dts: aspeed: tacoma: Enable XDMA engine Date: Wed, 18 Dec 2019 09:09:38 -0600 Message-Id: <1576681778-18737-13-git-send-email-eajames@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> References: <1576681778-18737-1-git-send-email-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-12-18_04:2019-12-17, 2019-12-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 suspectscore=1 mlxlogscore=655 malwarescore=0 mlxscore=0 phishscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912180124 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Enable the XDMA engine node. Signed-off-by: Eddie James --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index f02de4ab058c..2e5cd51db7c2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -1193,3 +1193,8 @@ &pinctrl { pinctrl-0 = <&pinctrl_lpc_default>, <&pinctrl_lsirq_default>; }; + +&xdma { + status = "okay"; + memory = <0xbf800000 0x00800000>; +};