From patchwork Thu Dec 12 01:53:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 1208090 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47YGzf3KL8z9sP6 for ; Thu, 12 Dec 2019 12:53:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727473AbfLLBxd (ORCPT ); Wed, 11 Dec 2019 20:53:33 -0500 Received: from mga04.intel.com ([192.55.52.120]:34634 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727504AbfLLBxd (ORCPT ); Wed, 11 Dec 2019 20:53:33 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2019 17:53:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,303,1571727600"; d="scan'208";a="225744491" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga002.jf.intel.com with ESMTP; 11 Dec 2019 17:53:30 -0800 From: "Ramuthevar,Vadivel MuruganX" To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kishon@ti.com Cc: andriy.shevchenko@intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, peter.harliman.liem@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v8 1/2] dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY Date: Thu, 12 Dec 2019 09:53:19 +0800 Message-Id: <20191212015320.20969-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191212015320.20969-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20191212015320.20969-1-vadivel.muruganx.ramuthevar@linux.intel.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Add a YAML schema to use the host controller driver with the eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- .../bindings/phy/intel,lgm-emmc-phy.yaml | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml new file mode 100644 index 000000000000..aed11258d96d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings + +maintainers: + - Ramuthevar Vadivel Murugan + +description: |+ + Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon + node is used to reference the base address of eMMC phy registers. + + The eMMC PHY node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "intel,lgm-syscon", "syscon" + - reg: + maxItems: 1 + +properties: + compatible: + contains: + const: intel,lgm-emmc-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + +examples: + - | + sysconf: chiptop@e0200000 { + compatible = "intel,lgm-syscon", "syscon"; + reg = <0xe0200000 0x100>; + + emmc-phy: emmc-phy@a8 { + compatible = "intel,lgm-emmc-phy"; + reg = <0x00a8 0x10>; + clocks = <&emmc>; + clock-names = "emmcclk"; + #phy-cells = <0>; + }; + }; +...