From patchwork Tue Dec 3 07:45:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFtZXMgVGFpIFvmiLTlv5fls7Bd?= X-Patchwork-Id: 1203551 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47RvD53v5dz9sNx for ; Tue, 3 Dec 2019 18:45:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727562AbfLCHpl (ORCPT ); Tue, 3 Dec 2019 02:45:41 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:39391 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727517AbfLCHpk (ORCPT ); Tue, 3 Dec 2019 02:45:40 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID xB37jKtg016012, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (RTITCASV01.realtek.com.tw[172.21.6.18]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTPS id xB37jKtg016012 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 3 Dec 2019 15:45:21 +0800 Received: from james-BS01.localdomain (172.21.190.33) by RTITCASV01.realtek.com.tw (172.21.6.18) with Microsoft SMTP Server id 14.3.468.0; Tue, 3 Dec 2019 15:45:19 +0800 From: James Tai To: =?utf-8?q?Andreas_F=C3=A4rber?= CC: Palmer Dabbelt , Paul Walmsley , Matthias Brugger , , , , , , cylee12 , "Rob Herring" , Mark Rutland , Subject: [PATCH 1/6] dt-bindings: clock: add bindings for RTD1619 clocks Date: Tue, 3 Dec 2019 15:45:08 +0800 Message-ID: <20191203074513.9416-2-james.tai@realtek.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191203074513.9416-1-james.tai@realtek.com> References: <20191203074513.9416-1-james.tai@realtek.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: cylee12 Add devicetree binding for Realtek RTD1619 clocks. Signed-off-by: Cheng-Yu Lee Signed-off-by: James Tai --- include/dt-bindings/clock/rtk,clock-rtd1619.h | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 include/dt-bindings/clock/rtk,clock-rtd1619.h diff --git a/include/dt-bindings/clock/rtk,clock-rtd1619.h b/include/dt-bindings/clock/rtk,clock-rtd1619.h new file mode 100644 index 000000000000..497f9b914857 --- /dev/null +++ b/include/dt-bindings/clock/rtk,clock-rtd1619.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DT_BINDINGS_RTK_CLOCK_RTD1619_H +#define __DT_BINDINGS_RTK_CLOCK_RTD1619_H + +#define CC_PLL_SCPU 0 +#define CC_PLL_BUS 2 +#define CC_CLK_SYS 3 +#define CC_CLK_SYS_SB2 4 +#define CC_PLL_DCSB 5 +#define CC_CLK_SYSH 6 +#define CC_PLL_DDSA 7 +#define CC_PLL_DDSB 8 +#define CC_PLL_GPU 9 +#define CC_CLK_GPU 10 +#define CC_PLL_VE1 11 +#define CC_PLL_VE2 12 +#define CC_CLK_VE1 13 +#define CC_CLK_VE2 14 +#define CC_CLK_VE3 15 +#define CC_CLK_VE2_BPU 16 +#define CC_PLL_DIF 17 +#define CC_PLL_PSAUD1A 18 +#define CC_PLL_PSAUD2A 19 + +#define CC_CKE_MISC 33 +#define CC_CKE_PCIE0 34 +#define CC_CKE_GSPI 35 +#define CC_CKE_SDS 36 +#define CC_CKE_HDMI 37 +#define CC_CKE_LSADC 38 +#define CC_CKE_SE 39 +#define CC_CKE_CP 40 +#define CC_CKE_MD 41 +#define CC_CKE_TP 42 +#define CC_CKE_RSA 43 +#define CC_CKE_NF 44 +#define CC_CKE_EMMC 45 +#define CC_CKE_SD 46 +#define CC_CKE_SDIO_IP 47 +#define CC_CKE_MIPI 48 +#define CC_CKE_EMMC_IP 49 +#define CC_CKE_SDIO 50 +#define CC_CKE_SD_IP 51 +#define CC_CKE_CABLERX 52 +#define CC_CKE_TPB 53 +#define CC_CKE_SC1 54 +#define CC_CKE_I2C3 55 +#define CC_CKE_JPEG 56 +#define CC_CKE_SC0 57 +#define CC_CKE_HDMIRX 58 +#define CC_CKE_HSE 59 +#define CC_CKE_UR2 60 +#define CC_CKE_UR1 61 +#define CC_CKE_FAN 62 +#define CC_CKE_SATA_WRAP_SYS 63 +#define CC_CKE_SATA_WRAP_SYSH 64 +#define CC_CKE_SATA_MAC_SYSH 65 +#define CC_CKE_R2RDSC 66 +#define CC_CKE_PCIE1 67 +#define CC_CKE_I2C4 68 +#define CC_CKE_I2C5 69 +#define CC_CKE_EDP 70 +#define CC_CKE_TSIO_TRX 71 +#define CC_CKE_TVE 72 +#define CC_CKE_VO 73 + +#define CC_CLK_MAX 74 + + +#define IC_CKE_CEC0 2 +#define IC_CKE_CBUSRX_SYS 3 +#define IC_CKE_CBUSTX_SYS 4 +#define IC_CKE_CBUS_SYS 5 +#define IC_CKE_CBUS_OSC 6 +#define IC_CKE_IR 7 +#define IC_CKE_UR0 8 +#define IC_CKE_I2C0 9 +#define IC_CKE_I2C1 10 +#define IC_CKE_ETN_250M 11 +#define IC_CKE_ETN_SYS 12 +#define IC_CKE_USB_DRD 13 +#define IC_CKE_USB_HOST 14 +#define IC_CKE_USB_U3_HOST 15 +#define IC_CKE_USB 16 +#define IC_CLK_MAX 17 + +#endif /* __DT_BINDINGS_RTK_CLOCK_RTD1619_H */ + From patchwork Tue Dec 3 07:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFtZXMgVGFpIFvmiLTlv5fls7Bd?= X-Patchwork-Id: 1203553 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47RvDW1T86z9sRK for ; Tue, 3 Dec 2019 18:46:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727602AbfLCHpr (ORCPT ); Tue, 3 Dec 2019 02:45:47 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:39406 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727517AbfLCHpr (ORCPT ); Tue, 3 Dec 2019 02:45:47 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID xB37jMhk016017, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (RTITCASV01.realtek.com.tw[172.21.6.18]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTPS id xB37jMhk016017 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 3 Dec 2019 15:45:22 +0800 Received: from james-BS01.localdomain (172.21.190.33) by RTITCASV01.realtek.com.tw (172.21.6.18) with Microsoft SMTP Server id 14.3.468.0; Tue, 3 Dec 2019 15:45:21 +0800 From: James Tai To: =?utf-8?q?Andreas_F=C3=A4rber?= CC: Palmer Dabbelt , Paul Walmsley , Matthias Brugger , , , , , , cylee12 , Philipp Zabel , Rob Herring , Mark Rutland , Subject: [PATCH 2/6] dt-bindings: reset: add bindings for rtd1619 reset controls Date: Tue, 3 Dec 2019 15:45:09 +0800 Message-ID: <20191203074513.9416-3-james.tai@realtek.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191203074513.9416-1-james.tai@realtek.com> References: <20191203074513.9416-1-james.tai@realtek.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: cylee12 Add devicetree binding for Realtek RTD1619 SoC reset controls. Signed-off-by: Cheng-Yu Lee Signed-off-by: James Tai --- include/dt-bindings/reset/rtk,reset-rtd1619.h | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 include/dt-bindings/reset/rtk,reset-rtd1619.h diff --git a/include/dt-bindings/reset/rtk,reset-rtd1619.h b/include/dt-bindings/reset/rtk,reset-rtd1619.h new file mode 100644 index 000000000000..f6fa6359ec1c --- /dev/null +++ b/include/dt-bindings/reset/rtk,reset-rtd1619.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DT_BINDINGS_RTK_RESET_RTD1619_H +#define __DT_BINDINGS_RTK_RESET_RTD1619_H + +#define CC_RSTN_REG_BANK_1 (0x0000) +#define CC_RSTN_REG_BANK_2 (0x0100) +#define CC_RSTN_REG_BANK_3 (0x0200) +#define CC_RSTN_REG_BANK_4 (0x0300) +#define CC_RSTN_REG_BANK_6 (0x0400) +#define CC_RSTN_REG_BANK_7 (0x0500) + +#define CC_RSTN_MISC (CC_RSTN_REG_BANK_1 | 0x00) +#define CC_RSTN_DIP (CC_RSTN_REG_BANK_1 | 0x02) +#define CC_RSTN_GSPI (CC_RSTN_REG_BANK_1 | 0x04) +#define CC_RSTN_SDS (CC_RSTN_REG_BANK_1 | 0x06) +#define CC_RSTN_SDS_REG (CC_RSTN_REG_BANK_1 | 0x08) +#define CC_RSTN_SDS_PHY (CC_RSTN_REG_BANK_1 | 0x0a) +#define CC_RSTN_VE1 (CC_RSTN_REG_BANK_1 | 0x0c) +#define CC_RSTN_VE2 (CC_RSTN_REG_BANK_1 | 0x0e) +#define CC_RSTN_R2RDSC_A00 (CC_RSTN_REG_BANK_1 | 0x10) +#define CC_RSTN_RSA (CC_RSTN_REG_BANK_1 | 0x12) +#define CC_RSTN_GPU (CC_RSTN_REG_BANK_1 | 0x14) +#define CC_RSTN_DC_PHY (CC_RSTN_REG_BANK_1 | 0x16) +#define CC_RSTN_DCPHY_CRT (CC_RSTN_REG_BANK_1 | 0x18) +#define CC_RSTN_LSADC (CC_RSTN_REG_BANK_1 | 0x1a) +#define CC_RSTN_SE (CC_RSTN_REG_BANK_1 | 0x1c) +#define CC_RSTN_HSE_A00 (CC_RSTN_REG_BANK_1 | 0x1e) + +#define CC_RSTN_JPEG (CC_RSTN_REG_BANK_2 | 0x00) +#define CC_RSTN_SD (CC_RSTN_REG_BANK_2 | 0x02) +#define CC_RSTN_EMMC_A00 (CC_RSTN_REG_BANK_2 | 0x04) +#define CC_RSTN_SDIO (CC_RSTN_REG_BANK_2 | 0x06) +#define CC_RSTN_PCR_CNT (CC_RSTN_REG_BANK_2 | 0x08) +#define CC_RSTN_PCIE0_STITCH (CC_RSTN_REG_BANK_2 | 0x0a) +#define CC_RSTN_PCIE0_PHY (CC_RSTN_REG_BANK_2 | 0x0c) +#define CC_RSTN_PCIE0 (CC_RSTN_REG_BANK_2 | 0x0e) +#define CC_RSTN_PCIE0_CORE (CC_RSTN_REG_BANK_2 | 0x10) +#define CC_RSTN_PCIE0_POWER (CC_RSTN_REG_BANK_2 | 0x12) +#define CC_RSTN_PCIE0_NONSTITCH (CC_RSTN_REG_BANK_2 | 0x14) +#define CC_RSTN_PCIE0_PHY_MDIO (CC_RSTN_REG_BANK_2 | 0x16) +#define CC_RSTN_PCIE0_SGMII_MDIO (CC_RSTN_REG_BANK_2 | 0x18) +#define CC_RSTN_UR2 (CC_RSTN_REG_BANK_2 | 0x1a) +#define CC_RSTN_UR1 (CC_RSTN_REG_BANK_2 | 0x1c) +#define CC_RSTN_MISC_SC0 (CC_RSTN_REG_BANK_2 | 0x1e) + +#define CC_RSTN_AE (CC_RSTN_REG_BANK_3 | 0x00) +#define CC_RSTN_CABLERX (CC_RSTN_REG_BANK_3 | 0x02) +#define CC_RSTN_MD_A00 (CC_RSTN_REG_BANK_3 | 0x04) +#define CC_RSTN_TP_A00 (CC_RSTN_REG_BANK_3 | 0x06) +#define CC_RSTN_NF_A00 (CC_RSTN_REG_BANK_3 | 0x08) +#define CC_RSTN_MISC_SC1 (CC_RSTN_REG_BANK_3 | 0x0a) +#define CC_RSTN_I2C_3 (CC_RSTN_REG_BANK_3 | 0x0c) +#define CC_RSTN_FAN (CC_RSTN_REG_BANK_3 | 0x0e) +#define CC_RSTN_TVE (CC_RSTN_REG_BANK_3 | 0x10) +#define CC_RSTN_AIO (CC_RSTN_REG_BANK_3 | 0x12) +#define CC_RSTN_VO (CC_RSTN_REG_BANK_3 | 0x14) +#define CC_RSTN_MIPI_A00 (CC_RSTN_REG_BANK_3 | 0x16) +#define CC_RSTN_HDMIRX (CC_RSTN_REG_BANK_3 | 0x18) +#define CC_RSTN_HDMIRX_WRAP (CC_RSTN_REG_BANK_3 | 0x1a) +#define CC_RSTN_HDMI (CC_RSTN_REG_BANK_3 | 0x1c) +#define CC_RSTN_DISP (CC_RSTN_REG_BANK_3 | 0x1e) + +#define CC_RSTN_SATA_PHY_POW1 (CC_RSTN_REG_BANK_4 | 0x00) +#define CC_RSTN_SATA_PHY_POW0 (CC_RSTN_REG_BANK_4 | 0x02) +#define CC_RSTN_SATA_MDIO1 (CC_RSTN_REG_BANK_4 | 0x04) +#define CC_RSTN_SATA_MDIO0 (CC_RSTN_REG_BANK_4 | 0x06) +#define CC_RSTN_SATA_WRAP (CC_RSTN_REG_BANK_4 | 0x08) +#define CC_RSTN_SATA_MAC_P1 (CC_RSTN_REG_BANK_4 | 0x0a) +#define CC_RSTN_SATA_MAC_P0 (CC_RSTN_REG_BANK_4 | 0x0c) +#define CC_RSTN_SATA_MAC_COM (CC_RSTN_REG_BANK_4 | 0x0e) +#define CC_RSTN_PCIE1_STITCH (CC_RSTN_REG_BANK_4 | 0x10) +#define CC_RSTN_PCIE1_PHY (CC_RSTN_REG_BANK_4 | 0x12) +#define CC_RSTN_PCIE1 (CC_RSTN_REG_BANK_4 | 0x14) +#define CC_RSTN_PCIE1_CORE (CC_RSTN_REG_BANK_4 | 0x16) +#define CC_RSTN_PCIE1_POWER (CC_RSTN_REG_BANK_4 | 0x18) +#define CC_RSTN_PCIE1_NONSTITCH (CC_RSTN_REG_BANK_4 | 0x1a) +#define CC_RSTN_PCIE1_PHY_MDIO (CC_RSTN_REG_BANK_4 | 0x1c) +#define CC_RSTN_HDMITOP (CC_RSTN_REG_BANK_4 | 0x1e) + +#define CC_RSTN_HSE (CC_RSTN_REG_BANK_6 | 0x06) +#define CC_RSTN_R2RDSC (CC_RSTN_REG_BANK_6 | 0x08) +#define CC_RSTN_EMMC (CC_RSTN_REG_BANK_6 | 0x0a) +#define CC_RSTN_NF (CC_RSTN_REG_BANK_6 | 0x0c) +#define CC_RSTN_MD (CC_RSTN_REG_BANK_6 | 0x0e) +#define CC_RSTN_TPB (CC_RSTN_REG_BANK_6 | 0x18) +#define CC_RSTN_TP (CC_RSTN_REG_BANK_6 | 0x1a) +#define CC_RSTN_MIPI (CC_RSTN_REG_BANK_6 | 0x1c) + +#define CC_RSTN_TPB_A00 (CC_RSTN_REG_BANK_7 | 0x00) +#define CC_RSTN_I2C_4 (CC_RSTN_REG_BANK_7 | 0x02) +#define CC_RSTN_I2C_5 (CC_RSTN_REG_BANK_7 | 0x04) +#define CC_RSTN_TSIO (CC_RSTN_REG_BANK_7 | 0x06) +#define CC_RSTN_VE3 (CC_RSTN_REG_BANK_7 | 0x08) +#define CC_RSTN_EDP (CC_RSTN_REG_BANK_7 | 0x0a) + +/* 0x98007088 */ +#define IC_RSTN_VFD 0x0000 +#define IC_RSTN_IR 0x0001 +#define IC_RSTN_CEC0 0x0002 +#define IC_RSTN_CEC1 0x0003 +#define IC_RSTN_DP 0x0004 +#define IC_RSTN_CBUSTX 0x0005 +#define IC_RSTN_CBUSRX 0x0006 +#define IC_RSTN_EFUSE 0x0007 +#define IC_RSTN_UR0 0x0008 +#define IC_RSTN_GMAC 0x0009 +#define IC_RSTN_GPHY 0x000a +#define IC_RSTN_I2C_0 0x000b +#define IC_RSTN_I2C_1 0x000c +#define IC_RSTN_CBUS 0x000d +#define IC_RSTN_USB_DRD 0x000e +#define IC_RSTN_USB_HOST 0x000f +#define IC_RSTN_USB_PHY_0 0x0010 +#define IC_RSTN_USB_PHY_1 0x0011 +#define IC_RSTN_USB_PHY_2 0x0012 +#define IC_RSTN_USB 0x0013 +#define IC_RSTN_TYPE_C 0x0014 +#define IC_RSTN_USB_U3_HOST 0x0015 +#define IC_RSTN_USB3_PHY0_POW 0x0016 +#define IC_RSTN_USB3_P0_MDIO 0x0017 +#define IC_RSTN_USB3_PHY1_POW 0x0018 +#define IC_RSTN_USB3_P1_MDIO 0x0019 + +#endif From patchwork Tue Dec 3 07:45:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFtZXMgVGFpIFvmiLTlv5fls7Bd?= X-Patchwork-Id: 1203552 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=realtek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47RvDS3cNlz9sR7 for ; Tue, 3 Dec 2019 18:46:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727542AbfLCHpz (ORCPT ); Tue, 3 Dec 2019 02:45:55 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:39410 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727517AbfLCHpv (ORCPT ); Tue, 3 Dec 2019 02:45:51 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID xB37jTZl016051, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (RTITCASV01.realtek.com.tw[172.21.6.18]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTPS id xB37jTZl016051 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 3 Dec 2019 15:45:29 +0800 Received: from james-BS01.localdomain (172.21.190.33) by RTITCASV01.realtek.com.tw (172.21.6.18) with Microsoft SMTP Server id 14.3.468.0; Tue, 3 Dec 2019 15:45:28 +0800 From: James Tai To: =?utf-8?q?Andreas_F=C3=A4rber?= CC: Palmer Dabbelt , Paul Walmsley , Matthias Brugger , , , , , , cylee12 , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , , Subject: [PATCH 6/6] dt-bindings: clk: realtek: add rtd1619 clock controller bindings Date: Tue, 3 Dec 2019 15:45:13 +0800 Message-ID: <20191203074513.9416-7-james.tai@realtek.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191203074513.9416-1-james.tai@realtek.com> References: <20191203074513.9416-1-james.tai@realtek.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: cylee12 Signed-off-by: Cheng-Yu Lee Signed-off-by: James Tai --- .../bindings/clock/realtek,clocks.txt | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,clocks.txt diff --git a/Documentation/devicetree/bindings/clock/realtek,clocks.txt b/Documentation/devicetree/bindings/clock/realtek,clocks.txt new file mode 100644 index 000000000000..db101508ac6a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/realtek,clocks.txt @@ -0,0 +1,38 @@ +Realtek Clock/Reset Controller +============================== + +Realtek CRT/ISO controller device-tree binding for Realtek Platforms. + +This binding uses the common clock binding[1]. + +The controller node should be the child of a syscon node with the required +propertise: + +- compatible : + should contain only one of the following: + "realtek,rtd1619-cc" for RTD1619 CRT clock controller, + "realtek,rtd1619-ic" for RTD1619 ISO clock controller, + +- #clock-cells : should be 1. + +- #reset-cells : should be 1. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Example: + + crt@98000000 { + compatible = "realtek,rtd1619-crt", "simple-mfd", "syscon"; + reg = <0x98000000 0x1000>; + + cc: cc@98000000 { + compatible = "realtek,rtd1619-cc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + consumer { + clocks = <&cc CC_CKE_GSPI>; + }; +