From patchwork Tue Dec 3 05:46:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1203528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47RrZy0Wr4z9sPV for ; Tue, 3 Dec 2019 16:46:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ajRl1Ukc"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47RrZx1lxVzDqTG for ; Tue, 3 Dec 2019 16:46:49 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ajRl1Ukc"; dkim-atps=neutral Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47RrZl24jrzDqN1 for ; Tue, 3 Dec 2019 16:46:39 +1100 (AEDT) Received: by mail-pg1-x544.google.com with SMTP id k25so1139119pgt.7 for ; Mon, 02 Dec 2019 21:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2oKqNhmL9Vi0jWnj+kwAIfJTGV7t8TPc4HeId3gKtxU=; b=ajRl1Ukc0e1s7ZaaxAvMlZ8gRoZAX959uqpHaMqcTtAK9nZEzx3wF4RXHoHRqFUoTB hNSwZ6diTjnkBcf0KJC9/23MBIsLBmVmUWyNm1hbdWMoKOFkPfVDQJxquNFdxScL0qY5 d/5mGXxZLJOgHl0FLLBhJyhUK193mIRhZ4jrxLfsGZXj3DUBs8UHqIqvhBnV1x5STBZV Y7PMdms1T04kyO9XHT4aFN3Y2Tw/QsRthnQIOU6OZ94NUgR2wSS837MCg5/9cKqonsyY y7YHzIIzKhhuZyyZtcg/vr3eEpuuiNY4yP50EW7IUoLXp/Ku8PqXo9/hZwrkj87AyyEg hPKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2oKqNhmL9Vi0jWnj+kwAIfJTGV7t8TPc4HeId3gKtxU=; b=oijU302dfL3zM/AXjtNG2GbcbqeYGHs8Xhy9o3IEHF0sXMm/GriWvyJyS9tFPv0O9e acKiUip7y7COcfWYiuJmKfq4Igj1lQPt/FRZO50XJczMirG+dXI3R5/hwASc+LuiQQ/r xzLe1bhlRCg4kHqTc0Cee9WC99EqvCcN26g9lC84VXEvINK/6fmpXYPYNG2fiN9uCYCv ipMzPQyymBiqseQ1ftQQK8/M3i1/aTloeSP9ATVIV6w2R4fAerbAO8jKdX1CPgNO8sLT yX0A1Ck6s/Qzh5qypxzv72k12nx7E3ekFW0hQkd1voEBfZ1mVFHwqPbgRxJVTFHgTpNf 38TA== X-Gm-Message-State: APjAAAUuJK+ThpPQAGxV2MD6+G2mnZH6sSaR9vgvSyTbwjDgsVA0waSc IXETJPZVDFOwLh0QOkmPnmg+BbRf X-Google-Smtp-Source: APXvYqzz10h8WRCLBVFlAyf7rJRVWSsNyFwXAKT+0wIa7e1tHRAwAdvGmsWeCY+3ZnZYttKAKuwCkg== X-Received: by 2002:aa7:8007:: with SMTP id j7mr2987560pfi.73.1575351996370; Mon, 02 Dec 2019 21:46:36 -0800 (PST) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id i9sm1602365pfk.24.2019.12.02.21.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 21:46:35 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 3 Dec 2019 16:46:17 +1100 Message-Id: <20191203054619.20068-1-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Skiboot] [PATCH 1/3] hw/p8-i2c: Don't print warnings when dumping registers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There's not much point complaining if we can't collect debug data. Log a obviously-wrong value and continue. Also convert to using i2cm_read_reg() rather than xscom_read() directly while we're here. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 52 ++++++++++------------------------------------------ 1 file changed, 10 insertions(+), 42 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 1b2806208613..990dfca7a154 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -237,7 +237,6 @@ static void p8_i2c_print_debug_info(struct p8_i2c_master_port *port, { struct p8_i2c_master *master = port->master; uint64_t cmd, mode, stat, estat, intm, intc; - int rc; /* Print master and request structure bits */ log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER), @@ -255,48 +254,17 @@ static void p8_i2c_print_debug_info(struct p8_i2c_master_port *port, " start_time=%016llx end_time=%016llx (duration=%016llx)\n", master->start_time, end_time, end_time - master->start_time); - /* Dump the current state of i2c registers */ - rc = xscom_read(master->chip_id, master->xscom_base + I2C_CMD_REG, - &cmd); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read CMD_REG\n"); - cmd = 0ull; - } - - rc = xscom_read(master->chip_id, master->xscom_base + I2C_MODE_REG, - &mode); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read MODE_REG\n"); - mode = 0ull; - } - - rc = xscom_read(master->chip_id, master->xscom_base + I2C_STAT_REG, - &stat); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read STAT_REG\n"); - stat = 0ull; - } + /* initialise to some fake value in case of read errors */ + cmd = mode = stat = estat = intm = intc = 0xDEAD; - rc = xscom_read(master->chip_id, master->xscom_base + I2C_EXTD_STAT_REG, - &estat); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read EXTD_STAT_REG\n"); - estat = 0ull; - } - - rc = xscom_read(master->chip_id, master->xscom_base + I2C_INTR_MASK_REG, - &intm); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read INTR_MASK_REG\n"); - intm = 0ull; - } - - rc = xscom_read(master->chip_id, master->xscom_base + I2C_INTR_COND_REG, - &intc); - if (rc) { - prlog(PR_DEBUG, "I2C: Failed to read INTR_COND_REG\n"); - intc = 0ull; - } + /* Dump the current state of i2c registers */ + i2cm_read_reg(master, I2C_CMD_REG, &cmd); + i2cm_read_reg(master, I2C_MODE_REG, &mode); + i2cm_read_reg(master, I2C_MODE_REG, &mode); + i2cm_read_reg(master, I2C_STAT_REG, &stat); + i2cm_read_reg(master, I2C_EXTD_STAT_REG, &estat); + i2cm_read_reg(master, I2C_INTR_MASK_REG, &intm); + i2cm_read_reg(master, I2C_INTR_COND_REG, &intc); log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER), "I2C: Register dump--\n" " cmd:0x%016llx\tmode:0x%016llx\tstat:0x%016llx\n" From patchwork Tue Dec 3 05:46:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1203529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47RrbM2HhYz9sPJ for ; Tue, 3 Dec 2019 16:47:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kthgsY/0"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47RrbL6nmCzDqTK for ; Tue, 3 Dec 2019 16:47:10 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::1041; helo=mail-pj1-x1041.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kthgsY/0"; dkim-atps=neutral Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47RrZn2PR4zDqN1 for ; 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Mon, 02 Dec 2019 21:46:38 -0800 (PST) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id i9sm1602365pfk.24.2019.12.02.21.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 21:46:37 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 3 Dec 2019 16:46:18 +1100 Message-Id: <20191203054619.20068-2-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191203054619.20068-1-oohall@gmail.com> References: <20191203054619.20068-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/3] hw/p8-i2c: Clean up interrupt masking X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There's three interrupt registers defined for the I2C master: 1. Interrupt mask 2. Raw interrupt condition bits 3. Masked interrupt condition bits All the I2C master interrupts are LSIs so the raw condition bits will only go to zero if the interrupt condition is dealt with. As a result the latter two registers are read only. For writes their addresses are re-used as atomic OR and atomic AND update registers for the mask register. When unmasking interrupts we currently do that via the atomic OR register and mask via the atomic AND, but we use the interrupt condition register macro names. This is a bit confusing and the documentation isn't super clear about the behaviour so fix the macro names in favour of something saner. Signed-off-by: Oliver O'Halloran --- We should probably just write to the mask register directly since we aren't doing any read-modify-write cycles. --- hw/p8-i2c.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 990dfca7a154..cb134423b8d5 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -92,10 +92,23 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, #define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19) #define I2C_WATERMARK_LOW PPC_BITMASK(24, 27) -/* I2C interrupt mask, condition and interrupt registers */ +/* + * I2C interrupt mask and condition registers + * + * NB: The function of 0x9 and 0xa changes depending on whether you're reading + * or writing to them. When read they return the interrupt condition bits + * and on writes they update the interrupt mask register. + * + * The bit definitions are the same for all the interrupt registers. + */ #define I2C_INTR_MASK_REG 0x8 -#define I2C_INTR_COND_REG 0x9 -#define I2C_INTR_REG 0xa + +#define I2C_INTR_RAW_COND_REG 0x9 /* read */ +#define I2C_INTR_MASK_OR_REG 0x9 /* write*/ + +#define I2C_INTR_COND_REG 0xa /* read */ +#define I2C_INTR_MASK_AND_REG 0xa /* write */ + #define I2C_INTR_ALL PPC_BITMASK(16, 31) #define I2C_INTR_INVALID_CMD PPC_BIT(16) #define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17) @@ -140,6 +153,10 @@ DEFINE_LOG_ENTRY(OPAL_RC_I2C_RESET, OPAL_INPUT_OUTPUT_ERR_EVT, OPAL_I2C, I2C_STAT_BKEND_ACCESS_ERR | I2C_STAT_ARBT_LOST_ERR | \ I2C_STAT_NACK_RCVD_ERR | I2C_STAT_STOP_ERR) + +#define I2C_INTR_ACTIVE \ + ((I2C_STAT_ANY_ERR >> 16) | I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ) + /* Pseudo-status used for timeouts */ #define I2C_STAT_PSEUDO_TIMEOUT PPC_BIT(63) @@ -264,7 +281,7 @@ static void p8_i2c_print_debug_info(struct p8_i2c_master_port *port, i2cm_read_reg(master, I2C_STAT_REG, &stat); i2cm_read_reg(master, I2C_EXTD_STAT_REG, &estat); i2cm_read_reg(master, I2C_INTR_MASK_REG, &intm); - i2cm_read_reg(master, I2C_INTR_COND_REG, &intc); + i2cm_read_reg(master, I2C_INTR_RAW_COND_REG, &intc); log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER), "I2C: Register dump--\n" " cmd:0x%016llx\tmode:0x%016llx\tstat:0x%016llx\n" @@ -317,10 +334,8 @@ static int p8_i2c_enable_irqs(struct p8_i2c_master *master) { int rc; - /* Enable the interrupts */ - rc = xscom_write(master->chip_id, master->xscom_base + - I2C_INTR_COND_REG, I2C_STAT_ANY_ERR >> 16 | - I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ); + /* enable interrupts we're interested in */ + rc = i2cm_write_reg(master, I2C_INTR_MASK_OR_REG, I2C_INTR_ACTIVE); if (rc) prlog(PR_ERR, "I2C: Failed to enable the interrupts\n"); @@ -802,8 +817,8 @@ static void p8_i2c_check_status(struct p8_i2c_master *master) return; } - /* Mask the interrupts for this engine */ - rc = i2cm_write_reg(master, I2C_INTR_REG, ~I2C_INTR_ALL); + /* mask interrupts while we're mucking with the master */ + rc = i2cm_write_reg(master, I2C_INTR_MASK_AND_REG, ~I2C_INTR_ALL); if (rc) { log_simple_error(&e_info(OPAL_RC_I2C_TRANSFER), "I2C: Failed to disable the interrupts\n"); From patchwork Tue Dec 3 05:46:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1203530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47Rrbh057lz9sPJ for ; Tue, 3 Dec 2019 16:47:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Cs8zdpy0"; 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Mon, 02 Dec 2019 21:46:39 -0800 (PST) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id i9sm1602365pfk.24.2019.12.02.21.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 21:46:39 -0800 (PST) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Tue, 3 Dec 2019 16:46:19 +1100 Message-Id: <20191203054619.20068-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191203054619.20068-1-oohall@gmail.com> References: <20191203054619.20068-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/3] libstb/tpm: block access to unknown i2c devs on the tpm bus X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Our favourite TPM is capable of listening on multiple I2C bus addresses and although this feature is supposed to be disabled by default we have some systems in the wild where the TPM appears to be listening on these secondary addresses. The secondary addresses are also susceptible to the bus-lockup problem that we see with certain traffic patterns to the "main" TPM address. We don't know what addresses the TPM might be listening on it's best to take a conservitve approach and only allow traffic to I2C bus addresses that we are explicitly told about by firmware. This is only required on the TPM bus, so this patch extends the existing TPM workaround to also check that a DT node exists for any I2C bus address the OS wants to talk to. If there isn't one, we don't forward the I2C request to the bus and return an I2C timeout error to the OS. Signed-off-by: Oliver O'Halloran Acked-by: Stewart Smith --- libstb/drivers/tpm_i2c_nuvoton.c | 47 +++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/libstb/drivers/tpm_i2c_nuvoton.c b/libstb/drivers/tpm_i2c_nuvoton.c index ef32b79fd6f7..83ec1c81e485 100644 --- a/libstb/drivers/tpm_i2c_nuvoton.c +++ b/libstb/drivers/tpm_i2c_nuvoton.c @@ -493,12 +493,46 @@ static struct tpm_driver tpm_i2c_nuvoton_driver = { static int nuvoton_tpm_quirk(void *data, struct i2c_request *req, int *rc) { struct tpm_dev *tpm_device = data; + struct dt_node *dev; + uint16_t addr; + bool found; - /* If we're doing i2cdetect on the TPM, pretent we just NACKed - * it due to errata in nuvoton firmware where if we let this - * request go through, it would steal the bus and you'd end up - * in a nice world of pain. + /* + * The nuvoton TPM firmware has a problem where a single byte read or + * zero byte write to one of its I2C addresses causes the TPM to lock + * up the bus. Once locked up the bus can only be recovered by power + * cycling the TPM. Unfortunately, we don't have the ability to + * power cycle the TPM because allowing it to be reset at runtime + * would undermine the TPM's security model (we can reset it and + * send it whatever measurements we like to unlock it's secrets). + * So the best we can do here is try avoid triggering the problem + * in the first place. + * + * For a bit of added fun the TPM also appears to check for traffic + * on a few different I2C bus addresses. It does this even when not + * configured to respond on those addresses so you can trigger the + * bug by sending traffic... somwhere. To work around this we block + * sending I2C requests on the TPM's bus unless the DT explicitly + * tells us there is a device there. */ + + /* first, check if this a known address */ + addr = req->dev_addr; + found = false; + + dt_for_each_child(req->bus->dt_node, dev) { + if (dt_prop_get_u32(dev, "reg") == addr) { + found = true; + break; + } + } + + if (!found) { + *rc = OPAL_I2C_TIMEOUT; + return 1; + } + + /* second, check if it's a bad transaction to the TPM */ if (tpm_device->bus_id == req->bus->opal_id && tpm_device->i2c_addr == req->dev_addr && ((req->op == I2C_READ && req->rw_len == 1) || @@ -517,6 +551,7 @@ void tpm_i2c_nuvoton_probe(void) struct tpm_dev *tpm_device = NULL; struct dt_node *node = NULL; struct i2c_bus *bus; + const char *name; dt_for_each_compatible(dt_root, node, "nuvoton,npct650") { if (!dt_node_is_enabled(node)) @@ -562,6 +597,10 @@ void tpm_i2c_nuvoton_probe(void) assert(bus->check_quirk == NULL); bus->check_quirk = nuvoton_tpm_quirk; bus->check_quirk_data = tpm_device; + name = dt_prop_get(node, "ibm,port-name"); + + prlog(PR_NOTICE, "NUVOTON: TPM I2C workaround applied to %s\n", + name); /* * Tweak for linux. It doesn't have a driver compatible