From patchwork Mon Dec 2 07:43:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1202979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47RHH84xPjz9sP6 for ; Mon, 2 Dec 2019 18:46:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QcISmEJ7"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47RHH83NhXzDqRg for ; Mon, 2 Dec 2019 18:46:12 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::1042; helo=mail-pj1-x1042.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QcISmEJ7"; dkim-atps=neutral Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47RHGQ5QMGzDqMG for ; Mon, 2 Dec 2019 18:45:32 +1100 (AEDT) Received: by mail-pj1-x1042.google.com with SMTP id s35so3201558pjb.7 for ; Sun, 01 Dec 2019 23:45:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=irHxEojgCywJNi4MEXqJtP2p23323RUQ2rwHgyIzDxc=; b=QcISmEJ7QaBfiNLBBWOX98Y/q8a1GVk2jOgZ469D1nkezZOkbeNVWlnaG/lxuNCBoG CwDT4p5Nu1X3DWXiGLKcFFxeZ+GSSvVdfnFETAflR9PSsBIBVZJsfWm8YGretRH2yxf3 IfN9tqmzpEb++Oy9jt9zgGSp3eEZ5pgK42X7qk6/6DspYm28q2YpcgezPi0Z1Uo+t7v+ 2AoDCsdwAT75ENEc9HhwXcDTfvLUblP+JCOQKP7wh+2CNa+k5pf+J1NelyR2Cg/A8ruK YY6Lqkdhq9+3CccRec1NGEiJ8QdIeOpiD9gkFGxc9V8I0Z5vEgff/FW6F8+Hv80rpoco QnIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=irHxEojgCywJNi4MEXqJtP2p23323RUQ2rwHgyIzDxc=; b=eQfb4TpdmDjy85oXW+ps/WKu0QLhPotsGGTQz/D6X3nO+hapquaXBtCDE3XWYQEWft J+QiDdHY2yDc6UZb2N8IroTsUN76zYFM1T+Y4ROkqPcsnyUmsp9Q+G6tTpbmleGeYt0r RC4hPCONOOJpbMc95dUiJVpih7lC7IkmZ5BFcKzhhuQk3zDXE6guWVA/wvsy4fFsqoJr EM+zItY1kg2PSrI+dt/yx0MIBQEZ/aGrXJJvBCPw46ktIcI08gqiNTxwdJuVmJTJ6OcN omAdBG3w00Fs6leefrBccs5qFciU4DsHO3pqqDxon8LW1ihPNFTc8gyAPo8sKSHsGbSQ cMHg== X-Gm-Message-State: APjAAAUdFD1CO58sM7gBrw9FVx7pDI4I+t282uhvOaNswGt5mRJTWGb0 XZOec27amT2oDzcMuAfd6GtGSveq X-Google-Smtp-Source: APXvYqxBn8hJVf/h4UCJYEzwSTCkbD9vI6i00s1aC3VXC0cAzzILm/P62Dte9RDwb2xMpRS/HC6rVQ== X-Received: by 2002:a17:90a:8401:: with SMTP id j1mr33056880pjn.39.1575272728262; Sun, 01 Dec 2019 23:45:28 -0800 (PST) Received: from bobo.local0.net (123-243-13-215.tpgi.com.au. [123.243.13.215]) by smtp.gmail.com with ESMTPSA id r20sm33048601pgu.89.2019.12.01.23.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2019 23:45:27 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 2 Dec 2019 17:43:15 +1000 Message-Id: <20191202074316.23772-1-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 1/2] move the __this_cpu register to r16, reserve r13-r15 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There have been several bugs between Linux and OPAL caused by both using r13 for their primary per-CPU data address. This patch moves OPAL to use r16 for this, and prevents the compiler from touching r13-r15. This helps things to be a little more robust, and also makes crashes in OPAL easier to debug. Later, if we allow interrupts (other than non-maskable) to be taken when running in skiboot, Linux's interrupt return handler does not restore r13 if the interrupt was taken in PR=0 state, which would corrupt the skiboot r13 register. Signed-off-by: Nicholas Piggin --- Makefile.main | 7 +++++-- asm/head.S | 28 ++++++++++++++-------------- asm/misc.S | 8 ++++---- include/cpu.h | 2 +- 4 files changed, 24 insertions(+), 21 deletions(-) diff --git a/Makefile.main b/Makefile.main index e26a9ab17..527cd8ae9 100644 --- a/Makefile.main +++ b/Makefile.main @@ -87,7 +87,10 @@ endif CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables CFLAGS += -mcpu=power8 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb -CFLAGS += $(call try-cflag,$(CC),-ffixed-r13) +CFLAGS += -ffixed-r13 +CFLAGS += -ffixed-r14 +CFLAGS += -ffixed-r15 +CFLAGS += -ffixed-r16 CFLAGS += $(call try-cflag,$(CC),-std=gnu11) ifeq ($(LITTLE_ENDIAN),1) @@ -118,7 +121,7 @@ endif # Check if the new parametrized stack protector option is supported # by gcc, otherwise disable stack protector -STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r13 +STACK_PROT_CFLAGS := -mstack-protector-guard=tls -mstack-protector-guard-reg=r16 STACK_PROT_CFLAGS += -mstack-protector-guard-offset=0 HAS_STACK_PROT := $(call test_cflag,$(CC),$(STACK_PROT_CFLAGS)) diff --git a/asm/head.S b/asm/head.S index 0b4b1a5f0..825f4e74a 100644 --- a/asm/head.S +++ b/asm/head.S @@ -25,7 +25,7 @@ addi stack_reg,stack_reg,EMERGENCY_CPU_STACKS_OFFSET@l; #define GET_CPU() \ - clrrdi %r13,%r1,STACK_SHIFT + clrrdi %r16,%r1,STACK_SHIFT #define SAVE_GPR(reg,sp) std %r##reg,STACK_GPR##reg(sp) #define REST_GPR(reg,sp) ld %r##reg,STACK_GPR##reg(sp) @@ -464,18 +464,18 @@ boot_entry: addi %r3,%r3,8 bdnz 1b - /* Get our per-cpu pointer into r13 */ + /* Get our per-cpu pointer into r16 */ GET_CPU() #ifdef STACK_CHECK_ENABLED /* Initialize stack bottom mark to 0, it will be updated in C code */ li %r0,0 - std %r0,CPUTHREAD_STACK_BOT_MARK(%r13) + std %r0,CPUTHREAD_STACK_BOT_MARK(%r16) #endif /* Initialize the stack guard */ LOAD_IMM64(%r3,STACK_CHECK_GUARD_BASE); xor %r3,%r3,%r31 - std %r3,0(%r13) + std %r3,0(%r16) /* Jump to C */ mr %r3,%r27 @@ -592,12 +592,12 @@ reset_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() /* Restore original stack pointer */ - ld %r1,CPUTHREAD_SAVE_R1(%r13) + ld %r1,CPUTHREAD_SAVE_R1(%r16) /* Restore more stuff */ lwz %r4,STACK_CR(%r1) @@ -655,7 +655,7 @@ reset_fast_reboot_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR - /* Get that CPU stack base and use it to restore r13 */ + /* Get that CPU stack base and use it to restore r16 */ GET_STACK(%r1,%r31) GET_CPU() @@ -923,17 +923,17 @@ opal_entry: std %r9,STACK_GPR9(%r1) std %r10,STACK_GPR10(%r1) - /* Save Token (r0), LR and r13 */ + /* Save Token (r0), LR and r16 */ mflr %r12 std %r0,STACK_GPR0(%r1) - std %r13,STACK_GPR13(%r1) + std %r16,STACK_GPR16(%r1) std %r12,STACK_LR(%r1) /* Get the CPU thread */ GET_CPU() /* Store token in CPU thread */ - std %r0,CPUTHREAD_CUR_TOKEN(%r13) + std %r0,CPUTHREAD_CUR_TOKEN(%r16) /* Mark the stack frame */ li %r12,STACK_ENTRY_OPAL_API @@ -975,14 +975,14 @@ opal_entry: bl opal_exit_check /* r3 is preserved */ /* - * Restore r1 and r13 before decrementing in_opal_call. - * Move per-cpu pointer to volatile r12, restore lr, r1, r13. + * Restore r1 and r16 before decrementing in_opal_call. + * Move per-cpu pointer to volatile r12, restore lr, r1, r16. */ .Lreturn: ld %r12,STACK_LR(%r1) mtlr %r12 - mr %r12,%r13 - ld %r13,STACK_GPR13(%r1) + mr %r12,%r16 + ld %r16,STACK_GPR16(%r1) ld %r1,STACK_GPR1(%r1) .Lreject: sync /* release barrier vs quiescing */ diff --git a/asm/misc.S b/asm/misc.S index 647f60b26..9904b806f 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -213,7 +213,7 @@ enter_p8_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) /* Winkle or nap ? */ cmpli %cr0,0,%r3,0 @@ -221,7 +221,7 @@ enter_p8_pm_state: /* nap sequence */ ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_NAP @@ -229,7 +229,7 @@ enter_p8_pm_state: /* rvwinkle sequence */ 1: ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) +0: ld %r0,CPUTHREAD_SAVE_R1(%r16) cmpd cr0,%r0,%r0 bne 0b PPC_INST_RVWINKLE @@ -250,7 +250,7 @@ enter_p9_pm_state: bl pm_save_regs /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) + std %r1,CPUTHREAD_SAVE_R1(%r16) mtspr SPR_PSSCR,%r3 PPC_INST_STOP diff --git a/include/cpu.h b/include/cpu.h index 686310d71..9b7f41dfb 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -212,7 +212,7 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id); core = next_available_core_in_chip(core, chip_id)) /* Return the caller CPU (only after init_cpu_threads) */ -register struct cpu_thread *__this_cpu asm("r13"); +register struct cpu_thread *__this_cpu asm("r16"); static inline __nomcount struct cpu_thread *this_cpu(void) { return __this_cpu; From patchwork Mon Dec 2 07:43:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1202978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47RHGp1Yg2z9sP6 for ; Mon, 2 Dec 2019 18:45:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QkARzbKO"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47RHGp04lqzDqRD for ; Mon, 2 Dec 2019 18:45:54 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::1042; helo=mail-pj1-x1042.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QkARzbKO"; dkim-atps=neutral Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47RHGQ5NhTzDqM3 for ; Mon, 2 Dec 2019 18:45:32 +1100 (AEDT) Received: by mail-pj1-x1042.google.com with SMTP id ep17so2060935pjb.4 for ; Sun, 01 Dec 2019 23:45:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8PlDj0MWtE4cqzNAHUffzJ55eJ352vWdH7d/F2RJNPo=; b=QkARzbKOeD5a6+QK8LIosZUTT47Atp6gJqne14RxRNpYn+GpbH2YPDK+xM7cfAyzRW q6EAwgW4wnJJF8vaUIbHQp7JZLSUU+1D8i/Epd/5fKq3TTFPxeOkiLrf4ulQkF3S6NmJ ypU6CN7m4Diy/Z22gH3JYIkcN7B6hrkGe1PXe3hQnWwSYvvuKuzb2XGZUVOlT0N5Ss1d ghjj0eeBpEBhAdu+JJwSQm1AysButNoznwIRMmoTY6ZEwQ65M0b4jc644F9tAr/K5DNI WtvL1XHFiUW27ciYNIFF9k/BdXUTNbwxltkB3p6FkC4USqXKENbsRONlDzqS6xyxXkHd ZS2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8PlDj0MWtE4cqzNAHUffzJ55eJ352vWdH7d/F2RJNPo=; b=sANwwuVtmzM8tXk5ZBPRLxRD/3/tbUiBdYY0ufTO1Rttf+cRqtKs9hVy97CKYK+eYM +FjisWNoNhZy3uoSAadW3+jQYPGrGGU7PlzS147EkxmWexUhKM2rCOJUAGB5PVJJWaKK nKMFuzJMHuagHH8llwWMH6cmDMiC4iNn2r65Z6QZv0ZZCGgrsAAxeK8vkPFeVEPtbRPj 4RY/Dh90OR0/RweNahhFTcwQj05kAozHUdpQ8c7GsrMUHQwl2aMC9ptE6whfBZgmYm6m 3boA4xFFM3IjmrowACrKsBVbEyhCT4apQRvi+xcIMUiD6gVGHmCGzlMuW1D9H1NBCQOb NfKQ== X-Gm-Message-State: APjAAAXs9Cbvp5KxQlg3oIT0s1Y6f2iKpGP7Y5QPU8RY/LNztCC4Jx+f leHNK7TPpZVEcrFBVumkqKuGX+H4 X-Google-Smtp-Source: APXvYqzYrLOwNGGjx3xj5QtPFlraDhta0zeDSTApHM8aeOcJyqyhGoYxowRa+sg95DV6qrAIkdemiw== X-Received: by 2002:a17:90a:2e05:: with SMTP id q5mr14405026pjd.136.1575272730461; Sun, 01 Dec 2019 23:45:30 -0800 (PST) Received: from bobo.local0.net (123-243-13-215.tpgi.com.au. [123.243.13.215]) by smtp.gmail.com with ESMTPSA id r20sm33048601pgu.89.2019.12.01.23.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2019 23:45:30 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 2 Dec 2019 17:43:16 +1000 Message-Id: <20191202074316.23772-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191202074316.23772-1-npiggin@gmail.com> References: <20191202074316.23772-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH 2/2] New LE OPAL calling convention X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is a new LE calling convention for LE skiboot builds. It is simply called as an indirect function, with the first argument selecting the opal call token, and the subsequent arguments are the opal call args. The caller's stack is used by OPAL. Linux tries very hard to ensure the stack is re-entrant across interrupts including non-maskable ones. We've currently hacked around this in skiboot by using a different part of the skiboot stack if OPAL is re-entered, but this is fragile and error prone. Currently relocation must be disabled before calling OPAL, this convention can support relocation-on, provided that the kernel is providing virtual memory mappings to OPAL (which comes later). All together that would bring the cost of an OPAL call down to similar to that of a kernel module function call. --- core/cpu.c | 9 +-------- core/opal.c | 39 +++++++++++++++++++++++++++++++++++++-- include/cpu.h | 9 +++++++++ 3 files changed, 47 insertions(+), 10 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index d5b7d623b..0c13f29de 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -23,14 +23,7 @@ /* The cpu_threads array is static and indexed by PIR in * order to speed up lookup from asm entry points */ -struct cpu_stack { - union { - uint8_t stack[STACK_SIZE]; - struct cpu_thread cpu; - }; -} __align(STACK_SIZE); - -static struct cpu_stack * const cpu_stacks = (struct cpu_stack *)CPU_STACKS_BASE; +struct cpu_stack * const cpu_stacks = (struct cpu_stack *)CPU_STACKS_BASE; unsigned int cpu_thread_count; unsigned int cpu_max_pir; struct cpu_thread *boot_cpu; diff --git a/core/opal.c b/core/opal.c index da746e805..2d2ecab7b 100644 --- a/core/opal.c +++ b/core/opal.c @@ -371,6 +371,33 @@ static void add_opal_firmware_node(void) add_opal_firmware_exports_node(firmware); } +typedef int64_t (*opal_call_fn)(uint64_t r3, uint64_t r4, uint64_t r5, + uint64_t r6, uint64_t r7, uint64_t r8, + uint64_t r9); + +static int64_t opal_v4_le_entry(uint64_t r3, uint64_t r4, uint64_t r5, + uint64_t r6, uint64_t r7, uint64_t r8, + uint64_t r9, uint64_t r10) +{ + opal_call_fn *fn; + uint64_t pir; + uint64_t r16; + + pir = mfspr(SPR_PIR); + r16 = (uint64_t)__this_cpu; + __this_cpu = &cpu_stacks[pir].cpu; + + assert(!(mfmsr() & (MSR_IR|MSR_DR|MSR_EE))); + + fn = (opal_call_fn *)(&opal_branch_table[r3]); + + r3 = (*fn)(r4, r5, r6, r7, r8, r9, r10); + + __this_cpu = (struct cpu_thread *)r16; + + return r3; +} + void add_opal_node(void) { uint64_t base, entry, size; @@ -395,16 +422,24 @@ void add_opal_node(void) dt_add_property_cells(opal_node, "#address-cells", 0); dt_add_property_cells(opal_node, "#size-cells", 0); - if (proc_gen < proc_gen_p9) + if (proc_gen < proc_gen_p9) { dt_add_property_strings(opal_node, "compatible", "ibm,opal-v2", "ibm,opal-v3"); - else + } else if (HAVE_LITTLE_ENDIAN) { + dt_add_property_strings(opal_node, "compatible", "ibm,opal-v3", + "ibm,opal-v4"); + } else { dt_add_property_strings(opal_node, "compatible", "ibm,opal-v3"); + } dt_add_property_cells(opal_node, "opal-msg-async-num", OPAL_MAX_ASYNC_COMP); dt_add_property_cells(opal_node, "opal-msg-size", OPAL_MSG_SIZE); dt_add_property_u64(opal_node, "opal-base-address", base); dt_add_property_u64(opal_node, "opal-entry-address", entry); + if (HAVE_LITTLE_ENDIAN) { + dt_add_property_u64(opal_node, "opal-v4-le-entry-address", + (uint64_t)&opal_v4_le_entry); + } dt_add_property_u64(opal_node, "opal-boot-address", (uint64_t)&boot_entry); dt_add_property_u64(opal_node, "opal-runtime-size", size); diff --git a/include/cpu.h b/include/cpu.h index 9b7f41dfb..0ccbb2674 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -211,6 +211,15 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id); for (core = first_available_core_in_chip(chip_id); core; \ core = next_available_core_in_chip(core, chip_id)) +struct cpu_stack { + union { + uint8_t stack[STACK_SIZE]; + struct cpu_thread cpu; + }; +} __align(STACK_SIZE); + +struct cpu_stack * const cpu_stacks; + /* Return the caller CPU (only after init_cpu_threads) */ register struct cpu_thread *__this_cpu asm("r16"); static inline __nomcount struct cpu_thread *this_cpu(void)