From patchwork Tue Nov 21 07:17:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Bur X-Patchwork-Id: 839914 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygxlc74S7z9s7B for ; Tue, 21 Nov 2017 18:18:52 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ygxlc6HgHzDqr8 for ; Tue, 21 Nov 2017 18:18:52 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=softfail (mailfrom) smtp.mailfrom=gmail.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=cyrilbur@gmail.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ygxkJ4CyHzDrM8 for ; Tue, 21 Nov 2017 18:17:43 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAL7HfV1134457 for ; Tue, 21 Nov 2017 02:17:41 -0500 Received: from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ece8dmf73-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 21 Nov 2017 02:17:41 -0500 Received: from localhost by e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 21 Nov 2017 07:17:36 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAL7HaO140894490; Tue, 21 Nov 2017 07:17:36 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5DB8AAE051; Tue, 21 Nov 2017 07:10:53 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0B709AE055; Tue, 21 Nov 2017 07:10:53 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 21 Nov 2017 07:10:53 +0000 (GMT) Received: from camb691.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id A05BFA018E; Tue, 21 Nov 2017 18:17:34 +1100 (AEDT) From: Cyril Bur To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 1/2] selftests/powerpc: Check for pthread errors in tm-unavailable Date: Tue, 21 Nov 2017 18:17:19 +1100 X-Mailer: git-send-email 2.15.0 X-TM-AS-GCONF: 00 x-cbid: 17112107-0012-0000-0000-0000058FC419 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17112107-0013-0000-0000-0000190A9293 Message-Id: <20171121071720.24619-1-cyrilbur@gmail.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-21_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711210099 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leitao@debian.org, gromero@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Signed-off-by: Cyril Bur Signed-off-by: Gustavo Romero --- .../testing/selftests/powerpc/tm/tm-unavailable.c | 43 +++++++++++++++++----- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/powerpc/tm/tm-unavailable.c b/tools/testing/selftests/powerpc/tm/tm-unavailable.c index 96c37f84ce54..e6a0fad2bfd0 100644 --- a/tools/testing/selftests/powerpc/tm/tm-unavailable.c +++ b/tools/testing/selftests/powerpc/tm/tm-unavailable.c @@ -15,6 +15,7 @@ */ #define _GNU_SOURCE +#include #include #include #include @@ -33,6 +34,11 @@ #define VSX_UNA_EXCEPTION 2 #define NUM_EXCEPTIONS 3 +#define err_at_line(status, errnum, format, ...) \ + error_at_line(status, errnum, __FILE__, __LINE__, format ##__VA_ARGS__) + +#define pr_warn(code, format, ...) err_at_line(0, code, format, ##__VA_ARGS__) +#define pr_err(code, format, ...) err_at_line(1, code, format, ##__VA_ARGS__) struct Flags { int touch_fp; @@ -303,10 +309,19 @@ void test_fp_vec(int fp, int vec, pthread_attr_t *attr) * checking if the failure cause is the one we expect. */ do { + int rc; + /* Bind 'ping' to CPU 0, as specified in 'attr'. */ - pthread_create(&t0, attr, ping, (void *) &flags); - pthread_setname_np(t0, "ping"); - pthread_join(t0, &ret_value); + rc = pthread_create(&t0, attr, ping, (void *) &flags); + if (rc) + pr_err(rc, "pthread_create()"); + rc = pthread_setname_np(t0, "ping"); + if (rc) + pr_warn(rc, "pthread_setname_np"); + rc = pthread_join(t0, &ret_value); + if (rc) + pr_err(rc, "pthread_join"); + retries--; } while (ret_value != NULL && retries); @@ -320,7 +335,7 @@ void test_fp_vec(int fp, int vec, pthread_attr_t *attr) int main(int argc, char **argv) { - int exception; /* FP = 0, VEC = 1, VSX = 2 */ + int rc, exception; /* FP = 0, VEC = 1, VSX = 2 */ pthread_t t1; pthread_attr_t attr; cpu_set_t cpuset; @@ -330,13 +345,23 @@ int main(int argc, char **argv) CPU_SET(0, &cpuset); /* Init pthread attribute. */ - pthread_attr_init(&attr); + rc = pthread_attr_init(&attr); + if (rc) + pr_err(rc, "pthread_attr_init()"); /* Set CPU 0 mask into the pthread attribute. */ - pthread_attr_setaffinity_np(&attr, sizeof(cpu_set_t), &cpuset); - - pthread_create(&t1, &attr /* Bind 'pong' to CPU 0 */, pong, NULL); - pthread_setname_np(t1, "pong"); /* Name it for systemtap convenience */ + rc = pthread_attr_setaffinity_np(&attr, sizeof(cpu_set_t), &cpuset); + if (rc) + pr_err(rc, "pthread_attr_setaffinity_np()"); + + rc = pthread_create(&t1, &attr /* Bind 'pong' to CPU 0 */, pong, NULL); + if (rc) + pr_err(rc, "pthread_create()"); + + /* Name it for systemtap convenience */ + rc = pthread_setname_np(t1, "pong"); + if (rc) + pr_warn(rc, "pthread_create()"); flags.result = 0; From patchwork Tue Nov 21 07:17:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Bur X-Patchwork-Id: 839915 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygxnQ3fwhz9s71 for ; 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Violators will be prosecuted; Tue, 21 Nov 2017 07:17:38 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAL7Hbbe42598552; Tue, 21 Nov 2017 07:17:37 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E804D4C04E; Tue, 21 Nov 2017 07:12:43 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E7C94C046; Tue, 21 Nov 2017 07:12:43 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 21 Nov 2017 07:12:43 +0000 (GMT) Received: from camb691.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id ED342A01D8; Tue, 21 Nov 2017 18:17:35 +1100 (AEDT) From: Cyril Bur To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 2/2] selftests/powerpc: Calculate spin time in tm-unavailable Date: Tue, 21 Nov 2017 18:17:20 +1100 X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171121071720.24619-1-cyrilbur@gmail.com> References: <20171121071720.24619-1-cyrilbur@gmail.com> X-TM-AS-GCONF: 00 x-cbid: 17112107-0040-0000-0000-000003F0C270 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17112107-0041-0000-0000-000025F3883E Message-Id: <20171121071720.24619-2-cyrilbur@gmail.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-21_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711210099 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leitao@debian.org, gromero@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Currently the tm-unavailable test spins for a fixed amount of time in an attempt to ensure the FPU/VMX/VSX facilities are off. This value was experimentally tested to be long enough. Problems may arise if kernel heuristics were to change. This patch should future proof this test. Signed-off-by: Cyril Bur --- Because the test no longer needs to use such a conservative time for the busy wait, it actually runs much faster. .../testing/selftests/powerpc/tm/tm-unavailable.c | 92 ++++++++++++++++++++-- 1 file changed, 84 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/powerpc/tm/tm-unavailable.c b/tools/testing/selftests/powerpc/tm/tm-unavailable.c index e6a0fad2bfd0..54aeb7a7fbb1 100644 --- a/tools/testing/selftests/powerpc/tm/tm-unavailable.c +++ b/tools/testing/selftests/powerpc/tm/tm-unavailable.c @@ -33,6 +33,11 @@ #define VEC_UNA_EXCEPTION 1 #define VSX_UNA_EXCEPTION 2 +#define ERR_RETRY 1 +#define ERR_ADJUST 2 + +#define COUNTER_INCREMENT (0x1000000) + #define NUM_EXCEPTIONS 3 #define err_at_line(status, errnum, format, ...) \ error_at_line(status, errnum, __FILE__, __LINE__, format ##__VA_ARGS__) @@ -45,6 +50,7 @@ struct Flags { int touch_vec; int result; int exception; + uint64_t counter; } flags; bool expecting_failure(void) @@ -87,14 +93,12 @@ void *ping(void *input) * Expected values for vs0 and vs32 after a TM failure. They must never * change, otherwise they got corrupted. */ + long rc = 0; uint64_t high_vs0 = 0x5555555555555555; uint64_t low_vs0 = 0xffffffffffffffff; uint64_t high_vs32 = 0x5555555555555555; uint64_t low_vs32 = 0xffffffffffffffff; - /* Counter for busy wait */ - uint64_t counter = 0x1ff000000; - /* * Variable to keep a copy of CR register content taken just after we * leave the transactional state. @@ -217,7 +221,7 @@ void *ping(void *input) [ex_fp] "i" (FP_UNA_EXCEPTION), [ex_vec] "i" (VEC_UNA_EXCEPTION), [ex_vsx] "i" (VSX_UNA_EXCEPTION), - [counter] "r" (counter) + [counter] "r" (flags.counter) : "cr0", "ctr", "v10", "vs0", "vs10", "vs3", "vs32", "vs33", "vs34", "fr10" @@ -232,14 +236,14 @@ void *ping(void *input) if (expecting_failure() && !is_failure(cr_)) { printf("\n\tExpecting the transaction to fail, %s", "but it didn't\n\t"); - flags.result++; + rc = ERR_ADJUST; } /* Check if we were not expecting a failure and a it occurred. */ if (!expecting_failure() && is_failure(cr_)) { printf("\n\tUnexpected transaction failure 0x%02lx\n\t", failure_code()); - return (void *) -1; + rc = ERR_RETRY; } /* @@ -249,7 +253,7 @@ void *ping(void *input) if (is_failure(cr_) && !failure_is_unavailable()) { printf("\n\tUnexpected failure cause 0x%02lx\n\t", failure_code()); - return (void *) -1; + rc = ERR_RETRY; } /* 0x4 is a success and 0xa is a fail. See comment in is_failure(). */ @@ -276,7 +280,7 @@ void *ping(void *input) putchar('\n'); - return NULL; + return (void *)rc; } /* Thread to force context switch */ @@ -291,6 +295,55 @@ void *pong(void *not_used) sched_yield(); } +static void flags_set_counter(struct Flags *flags) +{ + uint64_t cr_; + int count = 0; + + do { + if (count == 0) + printf("\tTrying 0x%08" PRIx64 "... ", flags->counter); + else + printf("%d, ", count); + fflush(stdout); + asm ( + /* + * Wait an amount of context switches so + * load_fp and load_vec overflow and MSR.FP, + * MSR.VEC, and MSR.VSX become zero (off). + */ + " mtctr %[counter] ;" + + /* Decrement CTR branch if CTR non zero. */ + "1: bdnz 1b ;" + " tbegin. ;" + " beq tfail ;" + + /* Get a facility unavailable */ + " fadd 10, 10, 10 ;" + " tend. ;" + "tfail: ;" + + /* + * Give CR back to C so that it can check what + * happened. + */ + " mfcr %[cr_] ;" + + : [cr_] "+r" (cr_) + : [counter] "r" (flags->counter) + : "cr0", "ctr", "fr10" + ); + count++; + if (!is_failure(cr_) || !failure_is_unavailable()) { + count = 0; + flags->counter += COUNTER_INCREMENT; + putchar('\n'); + } + } while (count < 3); + printf("3\n"); +} + /* Function that creates a thread and launches the "ping" task. */ void test_fp_vec(int fp, int vec, pthread_attr_t *attr) { @@ -322,6 +375,17 @@ void test_fp_vec(int fp, int vec, pthread_attr_t *attr) if (rc) pr_err(rc, "pthread_join"); + if ((long)ret_value == ERR_ADJUST) { + printf("Adjusting the facility unavailable spin time...\n"); + /* + * Be a bit more agressive just now - we'd + * really like to have it work + */ + flags.counter += (2 * COUNTER_INCREMENT); + flags_set_counter(&flags); + printf("Now using 0x%08" PRIx64 "\n", flags.counter); + } + retries--; } while (ret_value != NULL && retries); @@ -340,6 +404,18 @@ int main(int argc, char **argv) pthread_attr_t attr; cpu_set_t cpuset; + /* + * Default counter for busy wait. + * 0x18000000 is a good baseline determined by experimentation + * on a POWER8 + * The autodetecting code will bump it up if it too low. + */ + flags.counter = 0x18000000; + + printf("Testing required spin time required for facility unavailable...\n"); + flags_set_counter(&flags); + printf("Spin time required for a reliable facility unavailable TM failure: 0x%" PRIx64 "\n", + flags.counter); /* Set only CPU 0 in the mask. Both threads will be bound to CPU 0. */ CPU_ZERO(&cpuset); CPU_SET(0, &cpuset);