From patchwork Fri Nov 22 04:17:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199199 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="nNJZL51N"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K39r1KBYz9sPf for ; Fri, 22 Nov 2019 15:19:59 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 79B36C2204B; Fri, 22 Nov 2019 04:19:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0E285C22029; Fri, 22 Nov 2019 04:19:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1DEF6C22048; Fri, 22 Nov 2019 04:19:52 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id DD5CFC21FCA for ; Fri, 22 Nov 2019 04:19:41 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id s3so6436785ioe.3 for ; Thu, 21 Nov 2019 20:19:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/6fT4V0OPWb4i67zz6DyGreFHnAAcNRz43CTXU+e3hg=; b=nNJZL51NuoNjmGhwNJCrTlq95BRiPJ+njxv3VMBwjOOXdB6xWQK9naoZoKlDl7KVlA AT9lWwVwWk1zoJBF+E19IRSoXhfRY5R7dLqJuxp7DHKQRfVn1JlS3V3paDsYNMPSGR6v fbbav0PgfdDa6y1n1yD7PhAWlW9pA8UbOHXO4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/6fT4V0OPWb4i67zz6DyGreFHnAAcNRz43CTXU+e3hg=; b=Y8+8EOEGVT694YS3hpbENlj/KbDAMrSmmd5gs/dvl5dzP0iEvz9apUj+YWUqWJ+GDV ps34uihR73MfSR92LfdAhDcXQLdFt8DzOuwygbTp5zKuPW39sfYBPJPXy5Uu1zM4WGnE Uy27GzlzwHwVeusS/ZIlvefiLMpfsjkd+hinbIRtiQdHFpfEwgY6yKMI+s7DKX9W7Kf4 Tn6/O2+xAERwDNpAorGZmg9SHLFsuD3YXOKAkvUQ1E+LoCii+TeP9ikIMenmT+Gpt+6v jjs/vc8Nm4oPH9/92GcEMYfuiS1g+cvJku8X5vemmMj7MZTXxgL1HB7Spo+gm4GTfreP aR/g== X-Gm-Message-State: APjAAAXFigPtGiVVu0T4PmKGStbopC3HWMqM/C7au/T99lHE7fwSYOgw TV0mu0bCoNd4CoO9Fzl7rUmQGAgdO+U= X-Google-Smtp-Source: APXvYqx2uQh+8l7OgDr9NTaspQ6ercG8uXZRUsHMBGbjOGeBMqx9lNAD6ox1f6v7pgdWQQq7DgFc7g== X-Received: by 2002:a02:b47:: with SMTP id 68mr12309995jad.49.1574396380550; Thu, 21 Nov 2019 20:19:40 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:40 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:26 -0700 Message-Id: <20191122041905.224686-2-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 001/100] binman: Add a library to access binman entries X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" SPL and TPL can access information about binman entries using link-time symbols but this is not available in U-Boot proper. Of course it could be made available, but the intention is to just read the device tree. Add support for this, so that U-Boot can locate entries. Signed-off-by: Simon Glass --- Changes in v4: - Add comments to functions Changes in v3: None Changes in v2: None common/board_r.c | 10 ++++++++++ include/binman.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ lib/Kconfig | 10 ++++++++++ lib/Makefile | 1 + lib/binman.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 114 insertions(+) create mode 100644 include/binman.h create mode 100644 lib/binman.c diff --git a/common/board_r.c b/common/board_r.c index c1ecb06b74..4253d0c61c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -15,6 +15,7 @@ #if defined(CONFIG_CMD_BEDBUG) #include #endif +#include #include #include #include @@ -342,6 +343,14 @@ static int initr_manual_reloc_cmdtable(void) } #endif +static int initr_binman(void) +{ + if (!CONFIG_IS_ENABLED(BINMAN_FDT)) + return 0; + + return binman_init(); +} + #if defined(CONFIG_MTD_NOR_FLASH) static int initr_flash(void) { @@ -692,6 +701,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_EFI_LOADER efi_memory_init, #endif + initr_binman, stdio_init_tables, initr_serial, initr_announce, diff --git a/include/binman.h b/include/binman.h new file mode 100644 index 0000000000..b462dc8542 --- /dev/null +++ b/include/binman.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Access to binman information at runtime + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#ifndef _BINMAN_H_ +#define _BINMAN_H_ + +/** + *struct binman_entry - information about a binman entry + * + * @image_pos: Position of entry in the image + * @size: Size of entry + */ +struct binman_entry { + u32 image_pos; + u32 size; +}; + +/** + * binman_entry_find() - Find a binman symbol + * + * This searches the binman information in the device tree for a symbol of the + * given name + * + * @name: Path to entry to examine (e.g. "/read-only/u-boot") + * @entry: Returns information about the entry + * @return 0 if OK, -ENOENT if the path is not found, other -ve value if the + * binman information is invalid (missing image-pos or size) + */ +int binman_entry_find(const char *name, struct binman_entry *entry); + +/** + * binman_init() - Set up the binman symbol information + * + * This locates the binary symbol information in the device tree ready for use + * + * @return 0 if OK, -ENOMEM if out of memory, -EINVAL if there is no binman node + */ +int binman_init(void); + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index b8a8509d72..67b9dd5792 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -7,6 +7,16 @@ config BCH This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction. +config BINMAN_FDT + bool "Allow access to binman information in the device tree" + depends on BINMAN + default y + help + This enables U-Boot to access information about binman entries, + stored in the device tree in a binman node. Typical uses are to + locate entries in the firmware image. See binman.h for the available + functionality. + config CC_OPTIMIZE_LIBS_FOR_SPEED bool "Optimize libraries for speed" help diff --git a/lib/Makefile b/lib/Makefile index d248d8626c..0c89b4896f 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91) += at91/ obj-$(CONFIG_OPTEE) += optee/ obj-$(CONFIG_AES) += aes.o +obj-$(CONFIG_$(SPL_TPL_)BINMAN_FDT) += binman.o ifndef API_BUILD ifneq ($(CONFIG_UT_UNICODE)$(CONFIG_EFI_LOADER),) diff --git a/lib/binman.c b/lib/binman.c new file mode 100644 index 0000000000..1774bdf2e5 --- /dev/null +++ b/lib/binman.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Intel +/* + * Access to binman information at runtime + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include + +struct binman_info { + ofnode image; +}; + +static struct binman_info *binman; + +int binman_entry_find(const char *name, struct binman_entry *entry) +{ + ofnode node; + int ret; + + node = ofnode_find_subnode(binman->image, name); + if (!ofnode_valid(node)) + return log_msg_ret("no binman node", -ENOENT); + + ret = ofnode_read_u32(node, "image-pos", &entry->image_pos); + if (ret) + return log_msg_ret("bad binman node1", ret); + ret = ofnode_read_u32(node, "size", &entry->size); + if (ret) + return log_msg_ret("bad binman node2", ret); + + return 0; +} + +int binman_init(void) +{ + binman = malloc(sizeof(struct binman_info)); + if (!binman) + return log_msg_ret("space for binman", -ENOMEM); + binman->image = ofnode_path("/binman"); + if (!ofnode_valid(binman->image)) + return log_msg_ret("binman node", -EINVAL); + + return 0; +} From patchwork Fri Nov 22 04:17:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199200 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="F9COK/49"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3C85CfSz9sPn for ; Fri, 22 Nov 2019 15:21:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6EB11C21FED; Fri, 22 Nov 2019 04:20:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8837CC22040; Fri, 22 Nov 2019 04:19:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7B210C22019; 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Thu, 21 Nov 2019 20:19:42 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:42 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:27 -0700 Message-Id: <20191122041905.224686-3-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Pavel Herrmann Subject: [U-Boot] [PATCH v4 002/100] dm: gpio: Allow control of GPIO uclass in SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass --- Changes in v4: - Disable SPL_DM_GPIO on omap35_logic to avoid a build error Changes in v3: None Changes in v2: - Fix the Kconfig condition to avoid build errors on snow arch/arm/include/asm/omap_gpio.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-davinci/include/mach/gpio.h | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 ++-- arch/arm/mach-omap2/omap3/board.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/gateworks/gw_ventana/Kconfig | 3 +++ board/toradex/apalis-imx8/apalis-imx8.c | 2 +- configs/omap35_logic_defconfig | 1 + drivers/gpio/Kconfig | 22 +++++++++++++++++++ drivers/gpio/Makefile | 4 +++- drivers/gpio/at91_gpio.c | 6 ++--- drivers/gpio/atmel_pio4.c | 2 +- drivers/gpio/da8xx_gpio.c | 7 +++--- drivers/gpio/da8xx_gpio.h | 2 +- drivers/gpio/mxc_gpio.c | 4 ++-- drivers/gpio/mxs_gpio.c | 4 ++-- drivers/gpio/omap_gpio.c | 6 ++--- drivers/gpio/sunxi_gpio.c | 8 +++---- drivers/i2c/i2c-uclass.c | 6 ++--- drivers/i2c/muxes/pca954x.c | 4 ++-- drivers/mmc/fsl_esdhc_imx.c | 13 ++++++----- drivers/mmc/omap_hsmmc.c | 2 +- drivers/net/designware.c | 10 ++++----- drivers/net/designware.h | 4 ++-- drivers/net/fec_mxc.c | 6 ++--- drivers/net/fec_mxc.h | 2 +- drivers/net/mvneta.c | 4 ++-- drivers/net/mvpp2.c | 8 +++---- drivers/net/sun8i_emac.c | 12 +++++----- drivers/pci/pci-aardvark.c | 4 ++-- drivers/pci/pcie_dw_mvebu.c | 4 ++-- drivers/spi/atmel_spi.c | 10 ++++----- drivers/spi/designware_spi.c | 4 ++-- drivers/tpm/tpm2_tis_spi.c | 2 +- include/config_uncmd_spl.h | 1 - include/configs/at91-sama5_common.h | 5 +++-- include/configs/gw_ventana.h | 1 - include/configs/mx6ul_14x14_evk.h | 1 + scripts/Makefile.uncmd_spl | 1 - 42 files changed, 111 insertions(+), 82 deletions(-) diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 20268fa084..151afa8f44 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -22,7 +22,7 @@ #include -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) /* Information about a GPIO bank */ struct omap_gpio_platdata { diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 91faf729ae..2daeb4fef8 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -133,7 +133,7 @@ /* * Other misc defines */ -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) #define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ #define ATMEL_BASE_PIO ATMEL_BASE_PIOA #endif diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index c150240962..e5a4053414 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -18,7 +18,7 @@ #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) #define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) #define gpio_status() gpio_info() #endif #define GPIO_NAME_SIZE 20 diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 03460c3eb7..e64942b716 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -116,7 +116,7 @@ U_BOOT_DEVICES(am33xx_i2c) = { }; #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) static const struct omap_gpio_platdata am33xx_gpio[] = { { 0, AM33XX_GPIO0_BASE }, { 1, AM33XX_GPIO1_BASE }, @@ -141,7 +141,7 @@ U_BOOT_DEVICES(am33xx_gpios) = { #endif #endif -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) static const struct gpio_bank gpio_bank_am33xx[] = { { (void *)AM33XX_GPIO0_BASE }, { (void *)AM33XX_GPIO1_BASE }, diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 658ef8c1f1..60de0d6052 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -33,7 +33,7 @@ extern omap3_sysinfo sysinfo; static void omap3_invalidate_l2_cache_secure(void); #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #if !CONFIG_IS_ENABLED(OF_CONTROL) /* Manually initialize GPIO banks when OF_CONTROL doesn't */ static const struct omap_gpio_platdata omap34xx_gpio[] = { diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index eba21647d9..56458ce495 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -25,7 +25,7 @@ u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) static struct gpio_bank gpio_bank_54xx[8] = { { (void *)OMAP54XX_GPIO1_BASE }, { (void *)OMAP54XX_GPIO2_BASE }, diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 76634a3a28..a114302428 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -49,7 +49,7 @@ int board_early_init_f(void) return 0; } -#if IS_ENABLED(CONFIG_DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) static void board_gpio_init(void) { /* TODO */ diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 4ba8314284..2ba5879d57 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -53,7 +53,7 @@ int board_early_init_f(void) return 0; } -#if IS_ENABLED(CONFIG_DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) static void board_gpio_init(void) { struct gpio_desc desc; diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig index 5d1bae41ac..fee910ca83 100644 --- a/board/gateworks/gw_ventana/Kconfig +++ b/board/gateworks/gw_ventana/Kconfig @@ -1,5 +1,8 @@ if TARGET_GW_VENTANA +config DM_GPIO + default y + config SYS_BOARD default "gw_ventana" diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index af48b56095..0e597011ae 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -50,7 +50,7 @@ int board_early_init_f(void) return 0; } -#if IS_ENABLED(CONFIG_DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) static void board_gpio_init(void) { /* TODO */ diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 3c9acd7e41..66bbb7235c 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -45,6 +45,7 @@ CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit" CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y CONFIG_SPL_OF_TRANSLATE=y +# CONFIG_SPL_DM_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c1ad5d64a3..447cf04578 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -14,6 +14,28 @@ config DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. +config SPL_DM_GPIO + bool "Enable Driver Model for GPIO drivers in SPL" + depends on DM_GPIO && SPL_DM && SPL_GPIO_SUPPORT + default y + help + Enable driver model for GPIO access in SPL. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + +config TPL_DM_GPIO + bool "Enable Driver Model for GPIO drivers in TPL" + depends on DM_GPIO && TPL_DM && TPL_GPIO_SUPPORT + default y + help + Enable driver model for GPIO access in TPL. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ccc49e2eb0..3612e66786 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -7,10 +7,12 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif -obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o +ifdef CONFIG_$(SPL_TPL_)GPIO obj-$(CONFIG_DM_74X164) += 74x164_gpio.o +endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 965becf77a..8d36d48fc8 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -210,7 +210,7 @@ int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup) return 0; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) static bool at91_get_port_output(struct at91_port *at91_port, int offset) { u32 mask, val; @@ -457,7 +457,7 @@ int at91_get_pio_value(unsigned port, unsigned pin) return 0; } -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) /* Common GPIO API */ int gpio_request(unsigned gpio, const char *label) @@ -499,7 +499,7 @@ int gpio_set_value(unsigned gpio, int value) } #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct at91_port_priv { struct at91_port *regs; diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 95a189a50f..8e6f32de1f 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -168,7 +168,7 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) return (readl(&port_base->pdsr) & mask) ? 1 : 0; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct atmel_pioctrl_data { u32 nbanks; diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 0a50c68d72..bd5a366aef 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -15,7 +15,7 @@ #include "da8xx_gpio.h" -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) #include #include @@ -377,7 +377,8 @@ static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio, _gpio_set_value(bank, gpio, value); return 0; } -#ifndef CONFIG_DM_GPIO + +#if !CONFIG_IS_ENABLED(DM_GPIO) void gpio_info(void) { @@ -428,7 +429,7 @@ int gpio_set_value(unsigned int gpio, int value) return _gpio_set_value(bank, gpio, value); } -#else /* CONFIG_DM_GPIO */ +#else /* DM_GPIO */ static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset) { diff --git a/drivers/gpio/da8xx_gpio.h b/drivers/gpio/da8xx_gpio.h index 1de9ec7f6f..849e8d2dcf 100644 --- a/drivers/gpio/da8xx_gpio.h +++ b/drivers/gpio/da8xx_gpio.h @@ -28,7 +28,7 @@ struct davinci_gpio_bank { #define MAX_NUM_GPIOS 144 #define GPIO_BIT(gp) ((gp) & 0x1F) -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) /* Information about a GPIO bank */ struct davinci_gpio_platdata { diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 64ab7a303f..6592d141d3 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -30,7 +30,7 @@ struct mxc_bank_info { struct gpio_regs *regs; }; -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) #define GPIO_TO_PORT(n) ((n) / 32) /* GPIO port description */ @@ -161,7 +161,7 @@ int gpio_direction_output(unsigned gpio, int value) } #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #include static int mxc_gpio_is_output(struct gpio_regs *regs, int offset) { diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 5795155e3e..77778e9ce5 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -128,7 +128,7 @@ int name_to_gpio(const char *name) return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT); } -#else /* CONFIG_DM_GPIO */ +#else /* DM_GPIO */ #include #include #include @@ -312,4 +312,4 @@ U_BOOT_DRIVER(gpio_mxs) = { .ofdata_to_platdata = mxs_ofdata_to_platdata, #endif }; -#endif /* CONFIG_DM_GPIO */ +#endif /* DM_GPIO */ diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 0031415d03..4249850f4b 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define OMAP_GPIO_DIR_OUT 0 #define OMAP_GPIO_DIR_IN 1 -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #define GPIO_PER_BANK 32 @@ -121,7 +121,7 @@ static int _get_gpio_value(const struct gpio_bank *bank, int gpio) return (__raw_readl(reg) & (1 << gpio)) != 0; } -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) static inline const struct gpio_bank *get_gpio_bank(int gpio) { @@ -377,4 +377,4 @@ U_BOOT_DRIVER(gpio_omap) = { #endif }; -#endif /* CONFIG_DM_GPIO */ +#endif /* !DM_GPIO */ diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 719efc2cef..9c3a4428e1 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -28,7 +28,7 @@ struct sunxi_gpio_platdata { int gpio_count; }; -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) static int sunxi_gpio_output(u32 pin, u32 val) { u32 dat; @@ -116,7 +116,7 @@ int sunxi_name_to_gpio(const char *name) return -1; return group * 32 + pin; } -#endif +#endif /* DM_GPIO */ int sunxi_name_to_gpio_bank(const char *name) { @@ -132,7 +132,7 @@ int sunxi_name_to_gpio_bank(const char *name) return -1; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) /* TODO(sjg@chromium.org): Remove this function and use device tree */ int sunxi_name_to_gpio(const char *name) { @@ -373,4 +373,4 @@ U_BOOT_DRIVER(gpio_sunxi) = { .bind = gpio_sunxi_bind, .probe = gpio_sunxi_probe, }; -#endif +#endif /* DM_GPIO */ diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index e47abf1833..88c13e76cb 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -11,7 +11,7 @@ #include #include #include -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #include #endif @@ -465,7 +465,7 @@ int i2c_get_chip_offset_len(struct udevice *dev) return chip->offset_len; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit) { if (bit) @@ -561,7 +561,7 @@ static int i2c_deblock_gpio(struct udevice *bus) { return -ENOSYS; } -#endif // CONFIG_DM_GPIO +#endif /* DM_GPIO */ int i2c_deblock(struct udevice *bus) { diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index a630ce991d..bb2935f8ec 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -125,7 +125,7 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev) static int pca954x_probe(struct udevice *dev) { - if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (CONFIG_IS_ENABLED(DM_GPIO)) { struct pca954x_priv *priv = dev_get_priv(dev); int err; @@ -146,7 +146,7 @@ static int pca954x_probe(struct udevice *dev) static int pca954x_remove(struct udevice *dev) { - if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (CONFIG_IS_ENABLED(DM_GPIO)) { struct pca954x_priv *priv = dev_get_priv(dev); if (dm_gpio_is_valid(&priv->gpio_mux_reset)) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 4099386313..840bb7803c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -149,7 +149,7 @@ struct fsl_esdhc_priv { struct udevice *vqmmc_dev; struct udevice *vmmc_dev; #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc cd_gpio; struct gpio_desc wp_gpio; #endif @@ -302,8 +302,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, return -ETIMEDOUT; } } else { -#ifdef CONFIG_DM_GPIO - if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { +#if CONFIG_IS_ENABLED(DM_GPIO) + if (dm_gpio_is_valid(&priv->wp_gpio) && + dm_gpio_get_value(&priv->wp_gpio)) { printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return -ETIMEDOUT; } @@ -1091,7 +1092,7 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) #if CONFIG_IS_ENABLED(DM_MMC) if (priv->non_removable) return 1; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) if (dm_gpio_is_valid(&priv->cd_gpio)) return dm_gpio_get_value(&priv->cd_gpio); #endif @@ -1453,7 +1454,7 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->non_removable = 1; } else { priv->non_removable = 0; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); #endif @@ -1463,7 +1464,7 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->wp_enable = 1; } else { priv->wp_enable = 0; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); #endif diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index bade129aea..8eecaafe47 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -183,7 +183,7 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label) { int ret; -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) if (!gpio_is_valid(gpio)) return -1; #endif diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 0031370085..8a2171a716 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -81,7 +81,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, return ret; } -#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) +#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) static int dw_mdio_reset(struct mii_dev *bus) { struct udevice *dev = bus->priv; @@ -127,7 +127,7 @@ static int dw_mdio_init(const char *name, void *priv) bus->read = dw_mdio_read; bus->write = dw_mdio_write; snprintf(bus->name, sizeof(bus->name), "%s", name); -#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) +#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) bus->reset = dw_mdio_reset; #endif @@ -806,12 +806,12 @@ const struct eth_ops designware_eth_ops = { int designware_eth_ofdata_to_platdata(struct udevice *dev) { struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct dw_eth_dev *priv = dev_get_priv(dev); #endif struct eth_pdata *pdata = &dw_pdata->eth_pdata; const char *phy_mode; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) int reset_flags = GPIOD_IS_OUT; #endif int ret = 0; @@ -828,7 +828,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) if (dev_read_bool(dev, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7048..3519a4167a 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -7,7 +7,7 @@ #ifndef _DW_ETH_H #define _DW_ETH_H -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #include #endif @@ -235,7 +235,7 @@ struct dw_eth_dev { #ifndef CONFIG_DM_ETH struct eth_device *dev; #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; #endif #ifdef CONFIG_CLK diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 131d1998a7..8478b6e8c6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1308,7 +1308,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) return 0; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) /* FEC GPIO reset */ static void fec_gpio_reset(struct fec_priv *priv) { @@ -1401,7 +1401,7 @@ static int fecmxc_probe(struct udevice *dev) } #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) fec_gpio_reset(priv); #endif /* Reset chip. */ @@ -1507,7 +1507,7 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, &priv->phy_reset_gpio, GPIOD_IS_OUT); if (ret < 0) diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 723b06a651..159aec8967 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -255,7 +255,7 @@ struct fec_priv { #ifdef CONFIG_DM_REGULATOR struct udevice *phy_supply; #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc phy_reset_gpio; uint32_t reset_delay; uint32_t reset_post_delay; diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 333be8ff28..5a39d333a0 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -275,7 +275,7 @@ struct mvneta_port { int init; int phyaddr; struct phy_device *phydev; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc phy_reset_gpio; #endif struct mii_dev *bus; @@ -1753,7 +1753,7 @@ static int mvneta_probe(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "phy-reset-gpios", 0, &pp->phy_reset_gpio, GPIOD_IS_OUT); diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index bd89725e77..dc81732ff0 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -976,7 +976,7 @@ struct mvpp2_port { int phy_node; int phyaddr; struct mii_dev *bus; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc phy_reset_gpio; struct gpio_desc phy_tx_disable_gpio; #endif @@ -4753,7 +4753,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) return -EINVAL; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "phy-reset-gpios", 0, &port->phy_reset_gpio, GPIOD_IS_OUT); gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0, @@ -4781,7 +4781,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) return 0; } -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) /* Port GPIO initialization */ static void mvpp2_gpio_init(struct mvpp2_port *port) { @@ -4814,7 +4814,7 @@ static int mvpp2_port_probe(struct udevice *dev, } mvpp2_port_power_up(port); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) mvpp2_gpio_init(port); #endif diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 0629b16e57..0b46044337 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -23,7 +23,7 @@ #include #include #include -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #include #endif @@ -141,7 +141,7 @@ struct emac_eth_dev { struct clk ephy_clk; struct reset_ctl tx_rst; struct reset_ctl ephy_rst; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; #endif }; @@ -695,7 +695,7 @@ err_tx_clk: return ret; } -#if defined(CONFIG_DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) static int sun8i_mdio_reset(struct mii_dev *bus) { struct udevice *dev = bus->priv; @@ -742,7 +742,7 @@ static int sun8i_mdio_init(const char *name, struct udevice *priv) bus->write = sun8i_mdio_write; snprintf(bus->name, sizeof(bus->name), name); bus->priv = (void *)priv; -#if defined(CONFIG_DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) bus->reset = sun8i_mdio_reset; #endif @@ -904,7 +904,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) const fdt32_t *reg; int node = dev_of_offset(dev); int offset = 0; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) int reset_flags = GPIOD_IS_OUT; #endif int ret; @@ -998,7 +998,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) printf("%s: Invalid RX delay value %d\n", __func__, sun8i_pdata->rx_delay_ps); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW; diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 864ac16f57..aa0b4bc845 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -610,7 +610,7 @@ static int pcie_advk_probe(struct udevice *dev) { struct pcie_advk *pcie = dev_get_priv(dev); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio, @@ -636,7 +636,7 @@ static int pcie_advk_probe(struct udevice *dev) } #else dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n"); -#endif /* CONFIG_DM_GPIO */ +#endif /* DM_GPIO */ pcie->first_busno = dev->seq; pcie->dev = pci_get_controller(dev); diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 95fb41966f..693591e375 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -476,7 +476,7 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) struct pcie_dw_mvebu *pcie = dev_get_priv(dev); struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio, @@ -496,7 +496,7 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) } #else debug("PCIE Reset on GPIO support is missing\n"); -#endif /* CONFIG_DM_GPIO */ +#endif /* DM_GPIO */ pcie->first_busno = dev->seq; diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index cf4de9ee1a..f076e92a93 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -17,7 +17,7 @@ #ifdef CONFIG_DM_SPI #include #endif -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) #include #endif @@ -228,7 +228,7 @@ struct atmel_spi_priv { unsigned int freq; /* Default frequency */ unsigned int mode; ulong bus_clk_rate; -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc cs_gpios[MAX_CS_COUNT]; #endif }; @@ -285,7 +285,7 @@ static int atmel_spi_release_bus(struct udevice *dev) static void atmel_spi_cs_activate(struct udevice *dev) { -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -300,7 +300,7 @@ static void atmel_spi_cs_activate(struct udevice *dev) static void atmel_spi_cs_deactivate(struct udevice *dev) { -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -468,7 +468,7 @@ static int atmel_spi_probe(struct udevice *bus) bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus); -#ifdef CONFIG_DM_GPIO +#if CONFIG_IS_ENABLED(DM_GPIO) struct atmel_spi_priv *priv = dev_get_priv(bus); int i; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 91e613e9cd..66ff8eeccd 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -126,7 +126,7 @@ static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val) static int request_gpio_cs(struct udevice *bus) { -#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(bus); int ret; @@ -373,7 +373,7 @@ static int poll_transfer(struct dw_spi_priv *priv) */ __weak void external_cs_manage(struct udevice *dev, bool on) { -#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(dev->parent); if (!dm_gpio_is_valid(&priv->cs_gpio)) diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 3d105fddba..713111f6c3 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -587,7 +587,7 @@ static int tpm_tis_spi_probe(struct udevice *dev) /* Use the TPM v2 stack */ priv->version = TPM_V2; - if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (CONFIG_IS_ENABLED(DM_GPIO)) { struct gpio_desc reset_gpio; ret = gpio_request_by_name(dev, "gpio-reset", 0, diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735ce7..31da6215b3 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -12,7 +12,6 @@ #ifndef CONFIG_SPL_DM #undef CONFIG_DM_SERIAL -#undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI #endif diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 6131277367..acd9e1ed62 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -9,6 +9,8 @@ #ifndef __AT91_SAMA5_COMMON_H #define __AT91_SAMA5_COMMON_H +#include + /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ @@ -18,11 +20,10 @@ #endif /* general purpose I/O */ -#ifndef CONFIG_DM_GPIO +#if !CONFIG_IS_ENABLED(DM_GPIO) #define CONFIG_AT91_GPIO #endif - /* * BOOTP options */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index e543061bff..c32d213ada 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -36,7 +36,6 @@ /* Driver Model */ #ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_GPIO #define CONFIG_DM_THERMAL #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 87f88693c5..0faad0a491 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +/* Note: This is incorrect and should move to Kconfig / defconfig */ #ifdef CONFIG_DM_GPIO #define CONFIG_DM_74X164 #endif diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index ba267d9ac6..6ea097d36d 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -6,7 +6,6 @@ ifdef CONFIG_SPL_BUILD ifndef CONFIG_SPL_DM CONFIG_DM_SERIAL= -CONFIG_DM_GPIO= CONFIG_DM_I2C= CONFIG_DM_SPI= CONFIG_DM_SPI_FLASH= From patchwork Fri Nov 22 04:17:28 2019 Content-Type: text/plain; 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bh=WFtpdnjPPHutWSZiDBdHOWkG8E6G8GnLLsCleZSMnRI=; b=pqkVIwEF1WTSGyBqe8eQNaOR+wpumkpRxVEYEuGIEAM1shEJ8cn/qBibc2TCrZsY8/ fJpmIUZD3VJRNHFh8eBkYpEbc8r0OLg0Lm1kW75cpl+kMshdzqQJSzMHCVevqlB0LNk5 nX6es4aYwGqmAUKT1cjLaOPmmOEtu2rHjM9o1dYTj6FgDwJyIpGmravoIx5V4ni1DuzT LnJfCEZa+jMsJoOvfjdn9eKEEksYp8HDG6hufrevsxW0VFqBDf/jV6w4aT90UFh7ae5v 3dgYOOOqL+CxnvA6ecopnIAOIWrgAaYcMEdhZzQpnd2pMMxTIuwSgz37MnWdIDr1q4JB yT0A== X-Gm-Message-State: APjAAAUswkf0woM3e03gBmVRZ6Q8n6fJkwhHANlmxVBG2iDqt1EPVr38 v5NT/BExtOiVT2xWZ7m7EwzbM1IGeGU= X-Google-Smtp-Source: APXvYqx2oPIk+yx0bHiVHDJo2Q5+ZBBYqJx9wEKLG1wu9dBgF9w6HG3Wyq7CB5P2mzv63aMmKfCa1Q== X-Received: by 2002:a6b:9254:: with SMTP id u81mr10632773iod.126.1574396384572; Thu, 21 Nov 2019 20:19:44 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:44 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:28 -0700 Message-Id: <20191122041905.224686-4-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Pavel Herrmann Subject: [U-Boot] [PATCH v4 003/100] dm: core: Fix offset_to_ofnode() with invalid offset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If the offset is -1 this function correctly sets up a null ofnode. But if the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it does the wrong thing. An offset of -1 in ofnode indicates that the ofnode is not valid. Any other negative value is not handled by ofnode_valid(). We could of course change that function, but it seems much better to always use the same value for an invalid node. Fix it by setting the offset to -1 if it is invalid for any reason. Signed-off-by: Simon Glass --- Changes in v4: - Update the commit message to be clearer, fix 'correct' typo Changes in v3: None Changes in v2: None include/dm/ofnode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 5c4cbf0998..4282169706 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -118,7 +118,7 @@ static inline ofnode offset_to_ofnode(int of_offset) if (of_live_active()) node.np = NULL; else - node.of_offset = of_offset; + node.of_offset = of_offset >= 0 ? of_offset : -1; return node; } From patchwork Fri Nov 22 04:17:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199207 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="kn7OLQhg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3HX0Ggwz9sNx for ; Fri, 22 Nov 2019 15:24:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A4BDAC220F4; Fri, 22 Nov 2019 04:21:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 91A5AC22048; Fri, 22 Nov 2019 04:20:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ACCE2C22024; Fri, 22 Nov 2019 04:19:56 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id BC50BC2202B for ; Fri, 22 Nov 2019 04:19:47 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id v17so1722306ilg.7 for ; Thu, 21 Nov 2019 20:19:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kd4jZB9zA9HuFjaYEh9xYpoSPDrMxaj9RLHyeT0bze0=; b=kn7OLQhgYp0hxfZne5Tddv5WBkYAyN4yu1J6rRFo/B225QtOu/WbzTxESUPRuko1zO /OtaXNKdIGNOGzre1Y6f/jPLH85gRqqMVvTkW62YPuqxmq8wKWjyy/3C2nNKazSrIHH3 D0d3cMEkt6Qb/uQKfwO/vcFlZ1RN0gu33Giaw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kd4jZB9zA9HuFjaYEh9xYpoSPDrMxaj9RLHyeT0bze0=; b=AdiScDiwC8uyCqbts61cpWXX4Z4TuAa2XZKoUTrq9qyGrYKHgi44j7PlFJ539MwfNr VLf7Fvocq/6Jd+H9uqVp6yVd5VC0A119mAga0DyUPi1s3TC5V0//y/MfuDloRkS/pmmQ qOUVLJtPkbZVU1m0kdoPdcRJxIeR3ws22GGltJrOJ/NI8yWFUIh92LpNNW0A1WNCSp1i YJpT/95HsXzC94K93FglwBLlckNNop4ReQGK5P3bPVk1I/hDpMPMKBVV9mrjZA9t/pcx gYY+/Z55gtUdnXoZlrVfPhkypZRL8mdblTrT7/BgJP0aCC5dsnfQsxS56FlsGU7cYbjA 2O7w== X-Gm-Message-State: APjAAAXHRsfIPEJC9P8P0En4/5LoXCcGPD4gNOvx2IbiY0LtNsxqcjLK seWko3bTGXoKFb2QBsTSpzXyDHsSOz0= X-Google-Smtp-Source: APXvYqw3zLa9jt/vPBscsn/1D/rDJ0VvQ0FV+xzc4UHES6mqAGTtjmPnaS/vHL00Rp9XDMGlNfk9mg== X-Received: by 2002:a92:a30d:: with SMTP id a13mr13878875ili.186.1574396386475; Thu, 21 Nov 2019 20:19:46 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:46 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:29 -0700 Message-Id: <20191122041905.224686-5-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Pavel Herrmann Subject: [U-Boot] [PATCH v4 004/100] dm: pci: Allow delaying auto-config until after relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass --- Changes in v4: - Change the behaviour to be a device-tree option - apollolake -> Apollo Lake Changes in v3: None Changes in v2: None doc/device-tree-bindings/pci/x86-pci.txt | 24 ++++++++++++++++++++++++ drivers/pci/pci-uclass.c | 15 ++++++++++----- include/pci.h | 9 ++++++++- 3 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 doc/device-tree-bindings/pci/x86-pci.txt diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt new file mode 100644 index 0000000000..3aa5bd9a46 --- /dev/null +++ b/doc/device-tree-bindings/pci/x86-pci.txt @@ -0,0 +1,24 @@ +x86 PCI DT details: +=================== + +Some options are available to affect how PCI operates on x86. + +Optional properties: +- u-boot,skip-auto-config-until-reloc : Don't set up PCI configuration until + after U-Boot has relocated. Normally if PCI is used before relocation, + this happens before relocation also. Some platforms set up static + configuration in TPL/SPL to reduce code size and boot time, since these + phases only know about a small subset of PCI devices. + +Example: + +pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + u-boot,skip-auto-config-until-reloc; +}; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 896cb6b23a..b09fb4f993 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -970,12 +970,15 @@ static int pci_uclass_pre_probe(struct udevice *bus) hose->bus = bus; hose->first_busno = bus->seq; hose->last_busno = bus->seq; + hose->skip_auto_config_until_reloc = + dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc"); return 0; } static int pci_uclass_post_probe(struct udevice *bus) { + struct pci_controller *hose = dev_get_uclass_priv(bus); int ret; debug("%s: probing bus %d\n", __func__, bus->seq); @@ -983,11 +986,13 @@ static int pci_uclass_post_probe(struct udevice *bus) if (ret) return ret; -#if CONFIG_IS_ENABLED(PCI_PNP) - ret = pci_auto_config_devices(bus); - if (ret < 0) - return ret; -#endif + if (CONFIG_IS_ENABLED(PCI_PNP) && + (!hose->skip_auto_config_until_reloc || + (gd->flags & GD_FLG_RELOC))) { + ret = pci_auto_config_devices(bus); + if (ret < 0) + return log_msg_ret("pci auto-config", ret); + } #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) /* diff --git a/include/pci.h b/include/pci.h index ff59ac0e69..de17d0ffba 100644 --- a/include/pci.h +++ b/include/pci.h @@ -571,15 +571,22 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev #define INDIRECT_TYPE_NO_PCIE_LINK 1 -/* +/** * Structure of a PCI controller (host bridge) * * With driver model this is dev_get_uclass_priv(bus) + * + * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has + * relocated. Normally if PCI is used before relocation, this happens + * before relocation also. Some platforms set up static configuration in + * TPL/SPL to reduce code size and boot time, since these phases only know + * about a small subset of PCI devices. This is normally false. */ struct pci_controller { #ifdef CONFIG_DM_PCI struct udevice *bus; struct udevice *ctlr; + bool skip_auto_config_until_reloc; #else struct pci_controller *next; #endif From patchwork Fri Nov 22 04:17:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199202 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="E0mZw5F5"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Dv6PZXz9sNx for ; Fri, 22 Nov 2019 15:22:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 828D6C22090; Fri, 22 Nov 2019 04:21:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 45F17C2204B; Fri, 22 Nov 2019 04:20:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DD9CCC21F94; Fri, 22 Nov 2019 04:19:56 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 82DC8C2203B for ; Fri, 22 Nov 2019 04:19:49 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id f6so1599997ilh.9 for ; Thu, 21 Nov 2019 20:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v1I1GfpYktVIqr83Di3TeAv+8Zp6qxZYNS6ulwEyz7A=; b=E0mZw5F5SqH6UHwBJ1vTXkY4cyRt8l2xURbAELGgwFWmPICN9rXGT2hhkTKLonRx0h qHXDM9m9PHFuD65EMpT3wt5qMXF1/vbmhxaG4m1/RHNVCvBr2H91xJOvLxywZHmfXNHU LwLrd0jkRTX3uaNWvsy17Se1ww2o7OTczKYUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1I1GfpYktVIqr83Di3TeAv+8Zp6qxZYNS6ulwEyz7A=; b=ax2sjVIMV5fEtAH5zhhPCAcuLHQOj8k8RDttZ4QzeFDxSKmD4gaY7dyQ+BFDBO3bKB KVrgrB15ECvOioRGSpVZPfgA8dEhMK8zKbETEQvk7q/jlH4v3rdhJuRZlUJQo8MhZeC8 ngS9lEJSw+HnZMxCJgGwo0WhEO5uA8FDCb5icNXuJY8oAnJ23SAgsUB63FGBTELBfLli QK3GoYjSGbgapmap9IYIxiwK0Em2EtgC9W2ZKsrcfEFIXAM/uH23a7W/BK9ITV25hx7c 3KkzFm/oR804wwFJuspfNAVKArmZVOp99A8PF5difLv5kUpipi2Rmq4mraK/xw2XpHFP /KsA== X-Gm-Message-State: APjAAAWZY2T6p0cBmRMGUj7l34J7A9HX29mRzzHElUwYE5qNk7AAN/tt IuDCF3pi+Y/nuRWzznWbkq4fRZ6ukGM= X-Google-Smtp-Source: APXvYqw5k2RAndQRFWhmcrGjv9kuVlWSfTDC2LO8ZPd/OP3pVUhioF+M9/J/ufWuGiMsDqMdSJXNmQ== X-Received: by 2002:a92:8404:: with SMTP id l4mr15282233ild.137.1574396388303; Thu, 21 Nov 2019 20:19:48 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:48 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:30 -0700 Message-Id: <20191122041905.224686-6-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Pavel Herrmann Subject: [U-Boot] [PATCH v4 005/100] dm: pci: Move pci_get_devfn() into a common file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass --- Changes in v4: - Add more documentation for pci_ofplat_get_devfn() - Mention that the return value is pci_dev_t - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn() Changes in v3: - Move the function to a common file instead of duplicating it - Update device type to pci_dev_t Changes in v2: None drivers/core/util.c | 20 +++++++++++++++++++ drivers/pci/pci-uclass.c | 16 --------------- include/dm/pci.h | 43 ++++++++++++++++++++++++++++++++++++++++ include/pci.h | 12 ++--------- 4 files changed, 65 insertions(+), 26 deletions(-) create mode 100644 include/dm/pci.h diff --git a/drivers/core/util.c b/drivers/core/util.c index 7dc1a2af02..69f83755f0 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include #include @@ -58,3 +60,21 @@ bool dm_ofnode_pre_reloc(ofnode node) #endif } #endif + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +int pci_get_devfn(struct udevice *dev) +{ + struct fdt_pci_addr addr; + int ret; + + /* Extract the devfn from fdt_pci_addr */ + ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, + "reg", &addr); + if (ret) { + if (ret != -ENOENT) + return -EINVAL; + } + + return addr.phys_hi & 0xff00; +} +#endif diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index b09fb4f993..3863262ebe 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1018,22 +1018,6 @@ static int pci_uclass_post_probe(struct udevice *bus) return 0; } -int pci_get_devfn(struct udevice *dev) -{ - struct fdt_pci_addr addr; - int ret; - - /* Extract the devfn from fdt_pci_addr */ - ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, - "reg", &addr); - if (ret) { - if (ret != -ENOENT) - return -EINVAL; - } - - return addr.phys_hi & 0xff00; -} - static int pci_uclass_child_post_bind(struct udevice *dev) { struct pci_child_platdata *pplat; diff --git a/include/dm/pci.h b/include/dm/pci.h new file mode 100644 index 0000000000..4faf09f05f --- /dev/null +++ b/include/dm/pci.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Google, Inc + */ + +#ifndef __DM_PCI_H +#define __DM_PCI_H + +struct udevice; + +/** + * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device + * + * Get devfn from fdt_pci_addr of the specified device + * + * This returns an int to avoid a dependency on pci.h + * + * @dev: PCI device + * @return devfn in bits 15...8 if found (pci_dev_t format), or -ENODEV if not + * found + */ +int pci_get_devfn(struct udevice *dev); + +/** + * pci_x86_ofplat_get_devfn() - Get the PCI dev/fn from of-platdata + * + * This function is used to obtain a PCI device/function from of-platdata + * register data. In this case the first cell of the 'reg' property contains + * the required information. + * + * This returns an int to avoid a dependency on pci.h + * + * @reg: reg value from dt-platdata.c array (first member). This is not a + * pointer type, since the caller may use fdt32_t or fdt64_t depending on + * the address sizes. + * @return device/function for that device (pci_dev_t format) + */ +static inline int pci_ofplat_get_devfn(u32 reg) +{ + return reg & 0xff00; +} + +#endif diff --git a/include/pci.h b/include/pci.h index de17d0ffba..8c761d8da3 100644 --- a/include/pci.h +++ b/include/pci.h @@ -482,6 +482,8 @@ #ifndef __ASSEMBLY__ +#include + #ifdef CONFIG_SYS_PCI_64BIT typedef u64 pci_addr_t; typedef u64 pci_size_t; @@ -1619,16 +1621,6 @@ int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, */ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); -/** - * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device - * - * Get devfn from fdt_pci_addr of the specified device - * - * @dev: PCI device - * @return devfn in bits 15...8 if found, -ENODEV if not found - */ -int pci_get_devfn(struct udevice *dev); - #endif /* CONFIG_DM_PCI */ /** From patchwork Fri Nov 22 04:17:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199206 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="FuuwHzVG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3HS0YfHz9sNx for ; Fri, 22 Nov 2019 15:24:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BCC41C220F7; Fri, 22 Nov 2019 04:22:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E4309C22019; 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bh=4CAlcRXBcvX/2FGY/UVHNAOP+NHFpMch/jlfLswluv8=; b=aqIUcGkQ9g/aZXno0/i2qDX9/Smjt94Ms77KzFH5QwaFONWF9ouNMV0MdjlwLWrJr8 ddo4ABxvWNyU5CPMB+XT6PHYNYuv1DHG5GmghqgxX1S4LKi4LyTpAEf+EVUckmqhJcM5 vPf2L05TeujW5r13rJKTZmw6IsZNKyjvn1fVkk00mQegisESU5YCiKayBND+X7q5YJU+ DwBEjwmVcZ4xkXALWTi5o3HgrJOt4kD2BOwKDjHk5MrHgzOseLSviyDAc8jm6kCoMfDL Z5QcoFchK1WSiHPLn+PnqDMnqHuMKjpD8nfRb84F7xfqTYNQwn0V6LrV696i4GCe14PG hKPQ== X-Gm-Message-State: APjAAAVOt+Yx2dEovc8s5R339vFjhj2axqGEZJ8vtWGSghNWpxGED8+/ 78xmOCXozVAmkLOqrvo2dgabBGAGubI= X-Google-Smtp-Source: APXvYqxTtCLJkzuDNMcz95FdYROt68oO3zOrQ9jPaTCs9SywxrenuIWc4SdBW6wjW8g9/E9GEQew5A== X-Received: by 2002:a92:5850:: with SMTP id m77mr15055133ilb.203.1574396389892; Thu, 21 Nov 2019 20:19:49 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:49 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:31 -0700 Message-Id: <20191122041905.224686-7-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Joe Hershberger Subject: [U-Boot] [PATCH v4 006/100] net: Move the checksum functions to lib/ X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These functions are used by code outside the network support, so move them to lib/ to be more accessible. Without this, the functions are only accessible if CONFIG_NET is defined. Many boards do not enable that option but still want to do checksums in this format. Fix up a few code-style nits while we are here. Signed-off-by: Simon Glass --- Changes in v4: - Expand commit message to better explain the need to checksum functions Changes in v3: None Changes in v2: None lib/Makefile | 2 +- lib/net_utils.c | 48 ++++++++++++++++++++++++++++++++++++++++ net/Makefile | 1 - net/checksum.c | 59 ------------------------------------------------- 4 files changed, 49 insertions(+), 61 deletions(-) delete mode 100644 net/checksum.c diff --git a/lib/Makefile b/lib/Makefile index 0c89b4896f..505527d58a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -76,7 +76,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o -obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o +obj-y += net_utils.o endif obj-$(CONFIG_ADDR_MAP) += addr_map.o obj-y += qsort.o diff --git a/lib/net_utils.c b/lib/net_utils.c index 9fb9d4a4b0..252290210f 100644 --- a/lib/net_utils.c +++ b/lib/net_utils.c @@ -41,3 +41,51 @@ struct in_addr string_to_ip(const char *s) addr.s_addr = htonl(addr.s_addr); return addr; } + +uint compute_ip_checksum(const void *vptr, uint nbytes) +{ + int sum, oddbyte; + const unsigned short *ptr = vptr; + + sum = 0; + while (nbytes > 1) { + sum += *ptr++; + nbytes -= 2; + } + if (nbytes == 1) { + oddbyte = 0; + ((u8 *)&oddbyte)[0] = *(u8 *)ptr; + ((u8 *)&oddbyte)[1] = 0; + sum += oddbyte; + } + sum = (sum >> 16) + (sum & 0xffff); + sum += (sum >> 16); + sum = ~sum & 0xffff; + + return sum; +} + +uint add_ip_checksums(uint offset, uint sum, uint new) +{ + ulong checksum; + + sum = ~sum & 0xffff; + new = ~new & 0xffff; + if (offset & 1) { + /* + * byte-swap the sum if it came from an odd offset; since the + * computation is endian-independent this works. + */ + new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00); + } + checksum = sum + new; + if (checksum > 0xffff) + checksum -= 0xffff; + + return (~checksum) & 0xffff; +} + +int ip_checksum_ok(const void *addr, uint nbytes) +{ + return !(compute_ip_checksum(addr, nbytes) & 0xfffe); +} diff --git a/net/Makefile b/net/Makefile index 2a700c8401..fef71b940a 100644 --- a/net/Makefile +++ b/net/Makefile @@ -5,7 +5,6 @@ #ccflags-y += -DDEBUG -obj-y += checksum.o obj-$(CONFIG_NET) += arp.o obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o diff --git a/net/checksum.c b/net/checksum.c deleted file mode 100644 index 16ef416356..0000000000 --- a/net/checksum.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause -/* - * This file was originally taken from the FreeBSD project. - * - * Copyright (c) 2001 Charles Mott - * Copyright (c) 2008 coresystems GmbH - * All rights reserved. - */ - -#include -#include - -unsigned compute_ip_checksum(const void *vptr, unsigned nbytes) -{ - int sum, oddbyte; - const unsigned short *ptr = vptr; - - sum = 0; - while (nbytes > 1) { - sum += *ptr++; - nbytes -= 2; - } - if (nbytes == 1) { - oddbyte = 0; - ((u8 *)&oddbyte)[0] = *(u8 *)ptr; - ((u8 *)&oddbyte)[1] = 0; - sum += oddbyte; - } - sum = (sum >> 16) + (sum & 0xffff); - sum += (sum >> 16); - sum = ~sum & 0xffff; - - return sum; -} - -unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new) -{ - unsigned long checksum; - - sum = ~sum & 0xffff; - new = ~new & 0xffff; - if (offset & 1) { - /* - * byte-swap the sum if it came from an odd offset; since the - * computation is endian independant this works. - */ - new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00); - } - checksum = sum + new; - if (checksum > 0xffff) - checksum -= 0xffff; - - return (~checksum) & 0xffff; -} - -int ip_checksum_ok(const void *addr, unsigned nbytes) -{ - return !(compute_ip_checksum(addr, nbytes) & 0xfffe); -} From patchwork Fri Nov 22 04:17:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199203 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Pci3FSvm"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3F54b98z9sNx for ; Fri, 22 Nov 2019 15:22:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4C4B8C2203C; Fri, 22 Nov 2019 04:21:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C0671C22044; Fri, 22 Nov 2019 04:20:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A5260C22045; Fri, 22 Nov 2019 04:19:56 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id 2E697C22036 for ; Fri, 22 Nov 2019 04:19:53 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id b26so4502588ion.7 for ; Thu, 21 Nov 2019 20:19:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CrhYCt2c3t/837Qc11enR1JPxun6oR/HGriYyla1pto=; b=Pci3FSvmuNBoJTkTB5citF/6AevXff3J0Rk/m/js/ZEBwyh+7fyPHb/nbKjiLw5Pw5 YGSQq9RURdGMfZg3GEd/lznjt56bHO+NnKQgwsFaz6G1Zb3sUvfmSlABXrpinnycjrLD qBT9kW3gSopNAjSUATt826GbldG48R7TJGTCI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CrhYCt2c3t/837Qc11enR1JPxun6oR/HGriYyla1pto=; b=aoA3ZFuj54pT7LQzftZsvZOEU3BBVKu5nD5oi4/qwgrmsJHlSLE591cIsrUqA3VLK4 NZQtWpzIfClj0iRRbpmFrJzYIZpaNLuKBapUt23O0R8ELExKPF+MILloSjrGNJks1rHD R7e3P43QXQxzePLd+dm6hMD1jnoKdvgylZwMHWb/v9wqQyODga7xLfPLVtmkThT+3W5H Qxu3Cp0WHzb1n4mo34TEBCCJBnQoGlod9+Zb8Aat9xNEQxVcYTLEP1u3qoVoMI3lkuQl +dB206IsBJr7vcqBraQ0pdDZuRyWcDY4gelOxDGlireYIodfeQOF1jskoVWQwvqlo1Q3 C2Rw== X-Gm-Message-State: APjAAAXr42FKxwgDoPmZF2PB5R09nRqo5/pNXMk18zCSczowdg9MsOpt mLJsRbNHyvLmPOpDPDDeWiOZWeBOH9E= X-Google-Smtp-Source: APXvYqw4iuqflpUWM2y5KTj7S+zpeybZcbEti5d+QY5r6RjWgDkrJd4+sV5EGvBASnAGbDZVQ3GlNg== X-Received: by 2002:a02:1042:: with SMTP id 63mr12237682jay.66.1574396391764; Thu, 21 Nov 2019 20:19:51 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:32 -0700 Message-Id: <20191121211845.v4.7.Ib37fe22adb7a6e5d3016907ecf589c8a8d932c8b@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 007/100] i2c: designware: Tidy up PCI support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is hacked into the driver at present. It seems better to have it as a separate driver that uses the base driver. Create a new file and put the X86 code into it. Actually the Baytrail settings should really come from the device tree. Note that 'has_max_speed' is added as well. This is currently always false but since only Baytrail provides the config, it does not affect operation for other devices. Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- Changes in v4: - Add a comment about the speed logic in __dw_i2c_set_bus_speed() - Add a comment in the commit message about why has_max_speed is added - Drop unwanted debug printf("bad\n") - Fix indentation nit - Rename new file to designware_i2c_pci.c Changes in v3: None Changes in v2: None drivers/i2c/Makefile | 3 + drivers/i2c/designware_i2c.c | 106 +++++-------------------------- drivers/i2c/designware_i2c.h | 35 ++++++++++ drivers/i2c/designware_i2c_pci.c | 79 +++++++++++++++++++++++ 4 files changed, 134 insertions(+), 89 deletions(-) create mode 100644 drivers/i2c/designware_i2c_pci.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c2f75d8755..f5a471f887 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -14,6 +14,9 @@ obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o +ifdef CONFIG_DM_PCI +obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o +endif obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 6daa90e744..99b7d09bb2 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -13,34 +13,6 @@ #include #include "designware_i2c.h" -struct dw_scl_sda_cfg { - u32 ss_hcnt; - u32 fs_hcnt; - u32 ss_lcnt; - u32 fs_lcnt; - u32 sda_hold; -}; - -#ifdef CONFIG_X86 -/* BayTrail HCNT/LCNT/SDA hold time */ -static struct dw_scl_sda_cfg byt_config = { - .ss_hcnt = 0x200, - .fs_hcnt = 0x55, - .ss_lcnt = 0x200, - .fs_lcnt = 0x99, - .sda_hold = 0x6, -}; -#endif - -struct dw_i2c { - struct i2c_regs *regs; - struct dw_scl_sda_cfg *scl_sda_cfg; - struct reset_ctl_bulk resets; -#if CONFIG_IS_ENABLED(CLK) - struct clk clk; -#endif -}; - #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) { @@ -90,7 +62,9 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, unsigned int ena; int i2c_spd; - if (speed >= I2C_MAX_SPEED) + /* Allow max speed if there is no config , or the config allows it */ + if (speed >= I2C_MAX_SPEED && + (!scl_sda_cfg || scl_sda_cfg->has_max_speed)) i2c_spd = IC_SPEED_MODE_MAX; else if (speed >= I2C_FAST_SPEED) i2c_spd = IC_SPEED_MODE_FAST; @@ -106,7 +80,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); switch (i2c_spd) { -#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */ case IC_SPEED_MODE_MAX: cntl |= IC_CON_SPD_SS; if (scl_sda_cfg) { @@ -119,7 +92,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, writel(hcnt, &i2c_base->ic_hs_scl_hcnt); writel(lcnt, &i2c_base->ic_hs_scl_lcnt); break; -#endif case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS; @@ -565,24 +537,19 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, return ret; } -static int designware_i2c_probe(struct udevice *bus) +static int designware_i2c_ofdata_to_platdata(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus); - int ret; - if (device_is_on_pci_bus(bus)) { -#ifdef CONFIG_DM_PCI - /* Save base address from PCI BAR */ - priv->regs = (struct i2c_regs *) - dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); -#ifdef CONFIG_X86 - /* Use BayTrail specific timing values */ - priv->scl_sda_cfg = &byt_config; -#endif -#endif - } else { - priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); - } + priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); + + return 0; +} + +int designware_i2c_probe(struct udevice *bus) +{ + struct dw_i2c *priv = dev_get_priv(bus); + int ret; ret = reset_get_bulk(bus, &priv->resets); if (ret) @@ -606,7 +573,7 @@ static int designware_i2c_probe(struct udevice *bus) return __dw_i2c_init(priv->regs, 0, 0); } -static int designware_i2c_remove(struct udevice *dev) +int designware_i2c_remove(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev); @@ -618,30 +585,7 @@ static int designware_i2c_remove(struct udevice *dev) return reset_release_bulk(&priv->resets); } -static int designware_i2c_bind(struct udevice *dev) -{ - static int num_cards; - char name[20]; - - /* Create a unique device name for PCI type devices */ - if (device_is_on_pci_bus(dev)) { - /* - * ToDo: - * Setting req_seq in the driver is probably not recommended. - * But without a DT alias the number is not configured. And - * using this driver is impossible for PCIe I2C devices. - * This can be removed, once a better (correct) way for this - * is found and implemented. - */ - dev->req_seq = num_cards; - sprintf(name, "i2c_designware#%u", num_cards++); - device_set_name(dev, name); - } - - return 0; -} - -static const struct dm_i2c_ops designware_i2c_ops = { +const struct dm_i2c_ops designware_i2c_ops = { .xfer = designware_i2c_xfer, .probe_chip = designware_i2c_probe_chip, .set_bus_speed = designware_i2c_set_bus_speed, @@ -656,28 +600,12 @@ U_BOOT_DRIVER(i2c_designware) = { .name = "i2c_designware", .id = UCLASS_I2C, .of_match = designware_i2c_ids, - .bind = designware_i2c_bind, + .ofdata_to_platdata = designware_i2c_ofdata_to_platdata, .probe = designware_i2c_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .remove = designware_i2c_remove, - .flags = DM_FLAG_OS_PREPARE, + .flags = DM_FLAG_OS_PREPARE, .ops = &designware_i2c_ops, }; -#ifdef CONFIG_X86 -static struct pci_device_id designware_pci_supported[] = { - /* Intel BayTrail has 7 I2C controller located on the PCI bus */ - { PCI_VDEVICE(INTEL, 0x0f41) }, - { PCI_VDEVICE(INTEL, 0x0f42) }, - { PCI_VDEVICE(INTEL, 0x0f43) }, - { PCI_VDEVICE(INTEL, 0x0f44) }, - { PCI_VDEVICE(INTEL, 0x0f45) }, - { PCI_VDEVICE(INTEL, 0x0f46) }, - { PCI_VDEVICE(INTEL, 0x0f47) }, - {}, -}; - -U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported); -#endif - #endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index 20ff20d9b8..48766d0806 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -7,6 +7,8 @@ #ifndef __DW_I2C_H_ #define __DW_I2C_H_ +#include + struct i2c_regs { u32 ic_con; /* 0x00 */ u32 ic_tar; /* 0x04 */ @@ -131,4 +133,37 @@ struct i2c_regs { #define I2C_FAST_SPEED 400000 #define I2C_STANDARD_SPEED 100000 +/** + * struct dw_scl_sda_cfg - I2C timing configuration + * + * @has_max_speed: Support maximum speed (1Mbps) + * @ss_hcnt: Standard speed high time in ns + * @fs_hcnt: Fast speed high time in ns + * @ss_lcnt: Standard speed low time in ns + * @fs_lcnt: Fast speed low time in ns + * @sda_hold: SDA hold time + */ +struct dw_scl_sda_cfg { + bool has_max_speed; + u32 ss_hcnt; + u32 fs_hcnt; + u32 ss_lcnt; + u32 fs_lcnt; + u32 sda_hold; +}; + +struct dw_i2c { + struct i2c_regs *regs; + struct dw_scl_sda_cfg *scl_sda_cfg; + struct reset_ctl_bulk resets; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +extern const struct dm_i2c_ops designware_i2c_ops; + +int designware_i2c_probe(struct udevice *bus); +int designware_i2c_remove(struct udevice *dev); + #endif /* __DW_I2C_H_ */ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c new file mode 100644 index 0000000000..e8fc6f2a90 --- /dev/null +++ b/drivers/i2c/designware_i2c_pci.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Copyright 2019 Google Inc + */ + +#include +#include +#include "designware_i2c.h" + +/* BayTrail HCNT/LCNT/SDA hold time */ +static struct dw_scl_sda_cfg byt_config = { + .ss_hcnt = 0x200, + .fs_hcnt = 0x55, + .ss_lcnt = 0x200, + .fs_lcnt = 0x99, + .sda_hold = 0x6, +}; + +static int designware_i2c_pci_probe(struct udevice *dev) +{ + struct dw_i2c *priv = dev_get_priv(dev); + + /* Save base address from PCI BAR */ + priv->regs = (struct i2c_regs *) + dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL)) + /* Use BayTrail specific timing values */ + priv->scl_sda_cfg = &byt_config; + + return designware_i2c_probe(dev); +} + +static int designware_i2c_pci_bind(struct udevice *dev) +{ + static int num_cards; + char name[20]; + + /* + * Create a unique device name for PCI type devices + * ToDo: + * Setting req_seq in the driver is probably not recommended. + * But without a DT alias the number is not configured. And + * using this driver is impossible for PCIe I2C devices. + * This can be removed, once a better (correct) way for this + * is found and implemented. + */ + dev->req_seq = num_cards; + sprintf(name, "i2c_designware#%u", num_cards++); + device_set_name(dev, name); + + return 0; +} + +U_BOOT_DRIVER(i2c_designware_pci) = { + .name = "i2c_designware_pci", + .id = UCLASS_I2C, + .bind = designware_i2c_pci_bind, + .probe = designware_i2c_pci_probe, + .priv_auto_alloc_size = sizeof(struct dw_i2c), + .remove = designware_i2c_remove, + .flags = DM_FLAG_OS_PREPARE, + .ops = &designware_i2c_ops, +}; + +static struct pci_device_id designware_pci_supported[] = { + /* Intel BayTrail has 7 I2C controller located on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x0f41) }, + { PCI_VDEVICE(INTEL, 0x0f42) }, + { PCI_VDEVICE(INTEL, 0x0f43) }, + { PCI_VDEVICE(INTEL, 0x0f44) }, + { PCI_VDEVICE(INTEL, 0x0f45) }, + { PCI_VDEVICE(INTEL, 0x0f46) }, + { PCI_VDEVICE(INTEL, 0x0f47) }, + {}, +}; + +U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported); 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Thu, 21 Nov 2019 20:19:53 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:53 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:33 -0700 Message-Id: <20191121211845.v4.8.I0ca3df8c37005f3314cc4231c4131cb607c4643f@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 008/100] i2c: designware: Avoid using static data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Drivers are not allowed to use static data since they may be used in SPL where BSS is not available. It is possible that driver model may provide support for numbering devices in the future. But for now, move this to global_data. Signed-off-by: Simon Glass --- Changes in v4: - Add new patch to drop static data in designware i2c driver Changes in v3: None Changes in v2: None arch/x86/include/asm/global_data.h | 1 + drivers/i2c/designware_i2c_pci.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 7f3ada06f6..0e7b946205 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -96,6 +96,7 @@ struct arch_global_data { ulong table; /* Table pointer from previous loader */ int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; + int dw_i2c_num_cards; /* Used by designware i2c driver */ #ifdef CONFIG_SEABIOS u32 high_table_ptr; u32 high_table_limit; diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index e8fc6f2a90..8d6bb37f5c 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -34,7 +34,6 @@ static int designware_i2c_pci_probe(struct udevice *dev) static int designware_i2c_pci_bind(struct udevice *dev) { - static int num_cards; char name[20]; /* @@ -45,9 +44,13 @@ static int designware_i2c_pci_bind(struct udevice *dev) * using this driver is impossible for PCIe I2C devices. * This can be removed, once a better (correct) way for this * is found and implemented. + * + * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would + * be possible. We cannot use static data in drivers since they may be + * used in SPL or before relocation. */ - dev->req_seq = num_cards; - sprintf(name, "i2c_designware#%u", num_cards++); + dev->req_seq = gd->arch.dw_i2c_num_cards++; + sprintf(name, "i2c_designware#%u", dev->req_seq); device_set_name(dev, name); return 0; From patchwork Fri Nov 22 04:17:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199214 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="OU++dXqL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Qd5pZCz9sNx for ; Fri, 22 Nov 2019 15:31:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5D048C22026; Fri, 22 Nov 2019 04:22:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 31B1EC22053; Fri, 22 Nov 2019 04:20:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BCB71C22016; Fri, 22 Nov 2019 04:20:01 +0000 (UTC) Received: from mail-il1-f193.google.com (mail-il1-f193.google.com [209.85.166.193]) by lists.denx.de (Postfix) with ESMTPS id 1E7CDC2203B for ; Fri, 22 Nov 2019 04:19:57 +0000 (UTC) Received: by mail-il1-f193.google.com with SMTP id o18so5548834ils.12 for ; Thu, 21 Nov 2019 20:19:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rxx6ggr23kWg5iF5PqkIaGCtawmFTVUGEb60u6AhV5s=; b=OU++dXqLmpUzawr8XSqOnCuJuPr3gfX76X3tBbLrYk4uVDpgth4wVrAOQ4MbvEGqxn 6ISNDtmXU7CU6v2IkKGbqCNgiEVYRogVRqw/VuV7xROakO/+UahO3NzphPCvqh8Ghy1X GtfyzzaT9YzWdp4Lrio29yO1K98NTmQzCb3HA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rxx6ggr23kWg5iF5PqkIaGCtawmFTVUGEb60u6AhV5s=; b=hN+cjChEtI3Ax6mcDefCLXXkBA1DcNAtUPoGtvMhcDXpC+OVW+/lFh34hEg0CgK5CX hiU4BkvuLwAQiMUcqBJ+Xgk9fMcybjB0uBNjPFXaza9X2LZdEgpQrCi77fJVzgIfXmu/ u5vvrZY2moGOnqgMh46JFCvwYXqR66xPbq1wz7f9FK8BdH59PtZqRs5d4Hb/722Y+riq A16BXi9klYsN2KGfXoLW3iw7zRZ9k5N6+MPDzfPvPkdKLxHDE5OyoOsY+ZPL+3Q8NPzD de45dDGG/g2jDehvbHQq8LWxibUgOqG7/DWwBmnor9Vp78MrbSjFm+AWBrUGLokNEkXl H3Hg== X-Gm-Message-State: APjAAAXrB4MPEKAvXJroTHUk35Rg8X3yhxiouOfwLAM7hMYvBfiHxWlU g+mOjHUDXul+4HnerdRVsJFAMDHGwB4= X-Google-Smtp-Source: APXvYqwFD0G0kpdHkdfQTGS5cxEu6Pe99OKqMQ49ol2fbkAolg11vw1dgsLPuZkdf1aNvPX3lb802Q== X-Received: by 2002:a92:b00f:: with SMTP id x15mr9939574ilh.248.1574396395871; Thu, 21 Nov 2019 20:19:55 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:34 -0700 Message-Id: <20191121211845.v4.9.I7e114f1fc9a5e4062ac176a63135c5791dbed927@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 009/100] i2c: designware: Support use in SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Allow this driver to set up an IO address in SPL using an 'early-regs' property. This allows SPL to use the I2C driver without having to enable the full PCI stack. Also split out ofdata_to_platdata in designware driver since this is more correct, and more convenient for the new logic. Signed-off-by: Simon Glass --- Changes in v4: - Add new patch to allow designware I2C driver to work in SPL Changes in v3: None Changes in v2: None drivers/i2c/designware_i2c_pci.c | 46 +++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 8d6bb37f5c..2bf90eaa4b 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -7,6 +7,7 @@ #include #include +#include #include "designware_i2c.h" /* BayTrail HCNT/LCNT/SDA hold time */ @@ -18,17 +19,49 @@ static struct dw_scl_sda_cfg byt_config = { .sda_hold = 0x6, }; -static int designware_i2c_pci_probe(struct udevice *dev) +/* Have a weak function for now - possibly should be a new uclass */ +__weak void lpss_reset_release(void *regs); + +static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev); + if (spl_phase() < PHASE_SPL) { + u32 base; + int ret; + + ret = dev_read_u32(dev, "early-regs", &base); + if (ret) + return log_msg_ret("early-regs", ret); + + /* Set i2c base address */ + dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + + /* Enable memory access and bus master */ + dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + } + + if (spl_phase() < PHASE_BOARD_F) { + /* Handle early, fixed mapping into a different address space */ + priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0); + } else { + priv->regs = (struct i2c_regs *) + dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + } + if (!priv->regs) + return -EINVAL; + /* Save base address from PCI BAR */ - priv->regs = (struct i2c_regs *) - dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL)) /* Use BayTrail specific timing values */ priv->scl_sda_cfg = &byt_config; + return 0; +} + +static int designware_i2c_pci_probe(struct udevice *dev) +{ return designware_i2c_probe(dev); } @@ -56,10 +89,17 @@ static int designware_i2c_pci_bind(struct udevice *dev) return 0; } +static const struct udevice_id designware_i2c_pci_ids[] = { + { .compatible = "snps,designware-i2c-pci" }, + { } +}; + U_BOOT_DRIVER(i2c_designware_pci) = { .name = "i2c_designware_pci", .id = UCLASS_I2C, + .of_match = designware_i2c_pci_ids, .bind = designware_i2c_pci_bind, + .ofdata_to_platdata = designware_i2c_pci_ofdata_to_platdata, .probe = designware_i2c_pci_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .remove = designware_i2c_remove, From patchwork Fri Nov 22 04:17:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199222 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:19:57 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:57 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:35 -0700 Message-Id: <20191122041905.224686-8-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 010/100] x86: spi: Add helper functions for Intel Fast SPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Add support for of-platdata for TPL - Add the missing header file - Change Fast-SPI driver into a helper file used by ICH SPI - Don't include write() and erase() in TPL - Drop 'a4' comment for register offset - Merge in patch "x86: Add support for booting from Fast SPI" - Reorder file so that write() and erase() are together - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/intel_common/Makefile | 1 + arch/x86/cpu/intel_common/fast_spi.c | 73 ++++++++++++++++++++++++++++ arch/x86/include/asm/fast_spi.h | 68 ++++++++++++++++++++++++++ arch/x86/include/asm/spl.h | 1 + 4 files changed, 143 insertions(+) create mode 100644 arch/x86/cpu/intel_common/fast_spi.c create mode 100644 arch/x86/include/asm/fast_spi.h diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 07f27c29ec..dfbc29f047 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif obj-y += cpu.o +obj-y += fast_spi.o obj-y += lpc.o ifndef CONFIG_TARGET_EFI_APP obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c new file mode 100644 index 0000000000..a6e3d0a5bf --- /dev/null +++ b/arch/x86/cpu/intel_common/fast_spi.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +/* + * Returns bios_start and fills in size of the BIOS region. + */ +static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs, + uint *bios_size) +{ + ulong bios_start, bios_end; + + /* + * BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and + * Limit. Base and Limit fields are in units of 4K. + */ + u32 val = readl(®s->bfp); + + bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12; + bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> + SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12; + *bios_size = bios_end - bios_start; + + return bios_start; +} + +int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep, + uint *offsetp) +{ + struct fast_spi_regs *regs; + ulong bar, base, mmio_base; + + /* Special case to find mapping without probing the device */ + pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32); + mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK; + regs = (struct fast_spi_regs *)mmio_base; + base = fast_spi_get_bios_region(regs, map_sizep); + *map_basep = (u32)-*map_sizep - base; + *offsetp = base; + + return 0; +} + +int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base) +{ + /* Program Temporary BAR for SPI */ + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, + mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY, + PCI_SIZE_32); + + /* Enable Bus Master and MMIO Space */ + pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY, PCI_SIZE_8); + + /* + * Disable the BIOS write protect so write commands are allowed. + * Enable Prefetching and caching. + */ + pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL, + SPIBAR_BIOS_CONTROL_EISS | + SPIBAR_BIOS_CONTROL_CACHE_DISABLE, + SPIBAR_BIOS_CONTROL_WPD | + SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8); + + return 0; +} diff --git a/arch/x86/include/asm/fast_spi.h b/arch/x86/include/asm/fast_spi.h new file mode 100644 index 0000000000..6894298526 --- /dev/null +++ b/arch/x86/include/asm/fast_spi.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Intel Corporation. + */ + +#ifndef ASM_FAST_SPI_H +#define ASM_FAST_SPI_H + +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +struct fast_spi_regs { + u32 bfp; + u32 hsfsts_ctl; + u32 faddr; + u32 dlock; + + u32 fdata[0x10]; + + u32 fracc; + u32 freg[12]; + u32 fpr[5]; + u32 gpr0; + u32 spare2; + u32 sts_ctl; + u16 preop; + u16 optype; + u8 opmenu[8]; + + u32 spare3; + u32 fdoc; + u32 fdod; + u32 spare4; + u32 afc; + u32 vscc[2]; + u32 ptinx; + u32 ptdata; +}; +check_member(fast_spi_regs, ptdata, 0xd0); + +/* Bit definitions for BFPREG (0x00) register */ +#define SPIBAR_BFPREG_PRB_MASK 0x7fff +#define SPIBAR_BFPREG_PRL_SHIFT 16 +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) + +/* PCI configuration registers */ +#define SPIBAR_BIOS_CONTROL 0xdc +#define SPIBAR_BIOS_CONTROL_WPD BIT(0) +#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE BIT(1) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE BIT(3) +#define SPIBAR_BIOS_CONTROL_EISS BIT(5) +#define SPIBAR_BIOS_CONTROL_BILD BIT(7) + +/** + * fast_spi_get_bios_mmap() - Get memory map for SPI flash + * + * @pdev: PCI device to use (this is the Fast SPI device) + * @map_basep: Returns base memory address for mapped SPI + * @map_sizep: Returns size of mapped SPI + * @offsetp: Returns start offset of SPI flash where the map works + * correctly (offsets before this are not visible) + * @return 0 (always) + */ +int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep, + uint *offsetp); + +int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base); + +#endif /* ASM_FAST_SPI_H */ diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h index 1bef4877eb..cc6cac08f2 100644 --- a/arch/x86/include/asm/spl.h +++ b/arch/x86/include/asm/spl.h @@ -11,6 +11,7 @@ enum { BOOT_DEVICE_SPI_MMAP = 10, + BOOT_DEVICE_FAST_SPI, BOOT_DEVICE_CROS_VBOOT, }; From patchwork Fri Nov 22 04:17:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199231 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:19:59 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:19:59 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:36 -0700 Message-Id: <20191122041905.224686-9-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jerry Van Baren Subject: [U-Boot] [PATCH v4 011/100] fdt: Show the preprocessed .dts file on error X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When device-tree compilation fails it is sometimes tricky to see which line is broken, since the input file to dtc is a pre-processed version of the device tree. Add a line that points to the file that needs to be checked: When the error is in the main .dts file, output is something like this: output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47 syntax error FATAL ERROR: Unable to parse input tree but in fact looking at that file shows nothing useful: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) Instead we need to look at the preprocessed file, which shows: 163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1) Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is not being resolved by the preprocessor. This commit adds an additional useful message: Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors Note that if the error is reported in an included file, such as u-boot.dtsi then the output is the following: Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error FATAL ERROR: Unable to parse input tree But again, if the error is due to a preprocessor failure, like this: filename = CONFIG_IFW_INPUT_FILE; then you can't tell what the problem is by looking at the source. All you see is the original code: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; }; intel-fsp-m { filename = CONFIG_FSP_FILE_M; }; Everything looks fine. But looking at the output of the preprocessor: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; intel-fsp-m { filename = "fsp_m.bin"; }; This shows that the filename (normally "fitimage.bin") has not been inserted the preprocess, leading to the realisation that the value should be CONFIG_IFWI_INPUT_FILE. If the above does not make sense, I encourage people to try introducing errors in the device tree preprocessed values. Signed-off-by: Simon Glass --- Changes in v4: - One last desperate attempt to try to explain the purpose of this commit - Update the message to mention the preprocessed file, not un-preprocessed Changes in v3: - Update example error message to better show the intended purpose Changes in v2: None scripts/Makefile.lib | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ef116e0e0a..c10cd83a0a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -300,7 +300,9 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ - -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + -d $(depfile).dtc.tmp $(dtc-tmp) || \ + (echo "Check $(shell pwd)/$(pre-tmp) for errors" && false) \ + ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \ sed -i "s:$(pre-tmp):$(<):" $(depfile) From patchwork Fri Nov 22 04:17:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199242 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Blf34odd"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3n70xS9z9sNx for ; Fri, 22 Nov 2019 15:47:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C93B4C22063; Fri, 22 Nov 2019 04:24:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3A5F6C22039; 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This makes it impossible to do any in that needs driver model but must run before devices are problem (as needed with Intel's FSP-S, for example). In any case it is not a good idea to tie probing of particular drivers too closely to the DM init. Create a new function to init the timer and put it a bit later in the sequence. Signed-off-by: Simon Glass --- Changes in v4: - Add new patch to move early-timer init later Changes in v3: None Changes in v2: None common/board_r.c | 19 ++++++++++++++----- drivers/pinctrl/Kconfig | 14 ++++++++++++++ 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 4253d0c61c..e31e9c5c16 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -306,16 +306,24 @@ static int initr_dm(void) bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R); if (ret) return ret; -#ifdef CONFIG_TIMER_EARLY - ret = dm_timer_init(); - if (ret) - return ret; -#endif return 0; } #endif +static int initr_dm_devices(void) +{ + int ret; + + if (IS_ENABLED(CONFIG_TIMER_EARLY)) { + ret = dm_timer_init(); + if (ret) + return ret; + } + + return 0; +} + static int initr_bootstage(void) { bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); @@ -702,6 +710,7 @@ static init_fnc_t init_sequence_r[] = { efi_memory_init, #endif initr_binman, + initr_dm_devices, stdio_init_tables, initr_serial, initr_announce, diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index eadcfd6652..449f614eb2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -82,6 +82,13 @@ config SPL_PINCTRL This option is an SPL-variant of the PINCTRL option. See the help of PINCTRL for details. +config TPL_PINCTRL + bool "Support pin controllers in TPL" + depends on TPL && TPL_DM + help + This option is an TPL variant of the PINCTRL option. + See the help of PINCTRL for details. + config SPL_PINCTRL_FULL bool "Support full pin controllers in SPL" depends on SPL_PINCTRL && SPL_OF_CONTROL @@ -91,6 +98,13 @@ config SPL_PINCTRL_FULL This option is an SPL-variant of the PINCTRL_FULL option. See the help of PINCTRL_FULL for details. +config TPL_PINCTRL_FULL + bool "Support full pin controllers in TPL" + depends on TPL_PINCTRL && TPL_OF_CONTROL + help + This option is an TPL-variant of the PINCTRL_FULL option. + See the help of PINCTRL_FULL for details. + config SPL_PINCTRL_GENERIC bool "Support generic pin controllers in SPL" depends on SPL_PINCTRL_FULL From patchwork Fri Nov 22 04:17:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199212 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="AEBr93hZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3JP0Yx8z9sNx for ; Fri, 22 Nov 2019 15:25:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B427AC22075; Fri, 22 Nov 2019 04:23:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 84336C21FF8; Fri, 22 Nov 2019 04:20:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C0C64C21FD1; Fri, 22 Nov 2019 04:20:08 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id C23B5C22034 for ; Fri, 22 Nov 2019 04:20:04 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id u17so5600426ilq.5 for ; Thu, 21 Nov 2019 20:20:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=25Cg4xB1fwDcrpgh8MvhgTHGAzVMv/y95fNU5sao7aA=; b=AEBr93hZFLMuA3TXZY+NShEhSoSukOAJ0MdtavTr9alSf2gqzdqTO4FKTvmTYH7/gS qekInnd+FYP+CyDDP2tpm3aeZ1mCHhAYgBvHi1OcC12Z5C7uQieklEHtth6OCQb8bpTw gkoCMtiLU93vsIu8CCVxj41EW87OvpALBWMN0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=25Cg4xB1fwDcrpgh8MvhgTHGAzVMv/y95fNU5sao7aA=; b=ZXuf0MUqXYYk3g0xdrRFMupzw/fZB9d2aolUfxlHwjStgg9ag41vUqdjD9O95PlRwM EpreD386A3LgMC0+yWTWF3Gb9wTT9hivmSz6X9fyCfeJWErSX49/+afP4VBn7wE7ESqg Tq31/5Aeu5+3Fxs4rExiLXujbAJZXL3W0/NwHERHLQOogBrbcFlSNvxqTF230Fx4d66Y eV1bTX4zaiSf3wis2kDX7XVX3WG9Be0ATCbENX+kIrpSPZ50vK4jG74iGvmRqEQCZ7/6 J9vuzuEjCiUNNPYxoEyogyA7C5p3OMdpubmDj4g6+rEqj9G6Q4pFpxjRTpaUCtvA6MYs FFmQ== X-Gm-Message-State: APjAAAUPT/cUvLCiTRxZDnR3qb5IUvY5uJyPLfkgN3fXZE0fXZsQZYpZ gThDRgwG+B4gwU3pZtZ5W9pfsQ24o58= X-Google-Smtp-Source: APXvYqxpr+02rsPtq2ye4U7uSRhSF21YPXeBGrDJ6Edw+t3EWHxNVmDzCsfKo9QoePfNWdMaE/5l8w== X-Received: by 2002:a92:35c1:: with SMTP id c62mr14740475ilf.47.1574396403410; Thu, 21 Nov 2019 20:20:03 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:03 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:38 -0700 Message-Id: <20191121211845.v4.13.I9633e5ca32e4ba58f994626da8dfb5b377482d41@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Joe Hershberger Subject: [U-Boot] [PATCH v4 013/100] RFC: sandbox: net: Suppress the MAC-address warnings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These warnings appear every thing sandbox is run (see below) and dwarf the actual useful output. Suppress them in two ways: 1. For the mismatch warnings, only set the ethaddr environment variables when running tests. 2. For the 'MAC address from ROM' warning, never print this on sandbox. Signed-off-by: Simon Glass --- Unfortunately this breaks the tests so is not applicable as is: $ /tmp/b/sandbox/u-boot -T -c "ut dm eth_prime" U-Boot 2019.10-00508-g95f6257285-dirty (Oct 13 2019 - 09:21:34 -0600) Model: sandbox DRAM: 128 MiB WDT: Started with servicing (60s timeout) MMC: mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD) In: serial Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: Error: eth@10002000 address not set. eth-1: eth@10002000 Error: eth@10003000 address not set. , eth-1: eth@10003000 Error: sbe5 address not set. , eth-1: sbe5 Error: eth@10004000 address not set. , eth-1: eth@10004000 Test: dm_test_eth_prime: eth.c Test: dm_test_eth_prime: eth.c (flat tree) Failures: 0 Old output: U-Boot 2019.10-rc2 Model: sandbox DRAM: 128 MiB Warning: host_lo MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:44 Warning: host_enp5s0 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:45 Warning: host_eth6 using MAC address from ROM Warning: host_docker0 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:46 Warning: host_docker_gwbridge using MAC address from ROM Warning: host_veth1118e68 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:47 WDT: Not found! MMC: In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, eth4: host_docker_gwbridge, eth5: host_veth1118e68 Error: eth@10002000 address not set. , eth-1: eth@10002000 Test 'pmc_base' not found Warning: host_lo MAC addresses don't match: Address in ROM is 2a:24:9a:31:90:f8 Address in environment is 00:00:11:22:33:44 Warning: host_enp5s0 MAC addresses don't match: Address in ROM is ce:23:d9:74:6f:6c Address in environment is 00:00:11:22:33:45 Warning: host_eth6 using MAC address from ROM Warning: host_docker0 MAC addresses don't match: Address in ROM is ee:22:1c:3b:be:bc Address in environment is 00:00:11:22:33:46 Warning: host_docker_gwbridge using MAC address from ROM Warning: host_veth1118e68 MAC addresses don't match: Address in ROM is ae:20:9e:3d:a4:9f Address in environment is 00:00:11:22:33:47 New output: U-Boot 2019.10 Model: sandbox DRAM: 128 MiB WDT: Not found! MMC: In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, eth4: host_docker_gwbridge, eth5: host_vethc7e1b9e Error: eth@10002000 address not set. , eth-1: eth@10002000 Hit any key to stop autoboot: 0 => Changes in v4: None Changes in v3: - Only supress the 'MAC address from ROM' warning on sandbox - Set the environment variables at runtime to avoid other warnings Changes in v2: None arch/sandbox/cpu/state.c | 12 ++++++++++-- arch/sandbox/include/asm/state.h | 5 ++++- cmd/nvedit.c | 8 ++++++++ include/configs/sandbox.h | 7 ++----- include/env.h | 12 ++++++++++++ net/eth-uclass.c | 11 +++++++++-- test/dm/test-main.c | 2 +- 7 files changed, 46 insertions(+), 11 deletions(-) diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index dee5fde4f7..70b278e4e2 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -351,7 +351,7 @@ bool state_get_skip_delays(void) return state->skip_delays; } -void state_reset_for_test(struct sandbox_state *state) +void state_reset_for_test(struct sandbox_state *state, bool eth_vars) { /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; @@ -367,6 +367,14 @@ void state_reset_for_test(struct sandbox_state *state) */ INIT_LIST_HEAD(&state->mapmem_head); state->next_tag = state->ram_size; + + if (eth_vars) { + /* set up some environment variables needed by the eth tests */ + env_set_for_test("ethaddr", "00:00:11:22:33:44"); + env_set_for_test("eth1addr", "00:00:11:22:33:45"); + env_set_for_test("eth3addr", "00:00:11:22:33:46"); + env_set_for_test("eth5addr", "00:00:11:22:33:47"); + } } int state_init(void) @@ -377,7 +385,7 @@ int state_init(void) state->ram_buf = os_malloc(state->ram_size); assert(state->ram_buf); - state_reset_for_test(state); + state_reset_for_test(state, false); /* * Example of how to use GPIOs: * diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index ad3e94beb9..4fa3b094a9 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -251,8 +251,11 @@ bool state_get_skip_delays(void); * state_reset_for_test() - Reset ready to re-run tests * * This clears out any test state ready for another test run. + * + * @param state Sandbox state to update + * @param eth_vars Set environment variables for eth tests */ -void state_reset_for_test(struct sandbox_state *state); +void state_reset_for_test(struct sandbox_state *state, bool eth_vars); /** * state_show() - Show information about the sandbox state diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 99a3bc57b1..6a01d755bb 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -299,6 +299,14 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) return 0; } +int env_set_for_test(const char *varname, const char *value) +{ + const char * const argv[4] = { "setenv", varname, value, NULL }; + + assert(value); + return _do_env_set(0, 3, (char * const *)argv, 0); +} + int env_set(const char *varname, const char *varvalue) { const char * const argv[4] = { "setenv", varname, varvalue, NULL }; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5d75021ed6..02e553c4b1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -98,11 +98,8 @@ "stderr=serial,vidconsole\0" #endif -#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ - "eth1addr=00:00:11:22:33:45\0" \ - "eth3addr=00:00:11:22:33:46\0" \ - "eth5addr=00:00:11:22:33:47\0" \ - "ipaddr=1.2.3.4\0" +/* Note that some ethernet variables are set in state_reset_for_test() */ +#define SANDBOX_ETH_SETTINGS "ipaddr=1.2.3.4\0" #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ diff --git a/include/env.h b/include/env.h index b72239f6a5..bc48a72cde 100644 --- a/include/env.h +++ b/include/env.h @@ -145,6 +145,18 @@ int env_get_yesno(const char *var); */ int env_set(const char *varname, const char *value); +/** + * env_set_for_test() - Set the value of a variable for testing + * + * This works as if the variable value was defined in the built-in environment, + * so uses a flags value of 0. This should only be used in tests. + * + * @varname: Variable to adjust + * @value: Value to set for the variable (cannot be NULL) + * @return 0 if OK, 1 on error + */ +int env_set_for_test(const char *varname, const char *value); + /** * env_get_ulong() - Return an environment variable as an integer value * diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 3bd98b01ad..6c19536138 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -485,6 +485,12 @@ static int eth_post_probe(struct udevice *dev) struct eth_device_priv *priv = dev->uclass_priv; struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[ARP_HLEN]; + /* + * These warnings always appear on sandbox and are not useful. They have + * been here for some time and the issue has not been resolved. So for + * now, disable them. + */ + bool show_warnings = !IS_ENABLED(CONFIG_SANDBOX); #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct eth_ops *ops = eth_get_ops(dev); @@ -538,8 +544,9 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + if (show_warnings) + printf("\nWarning: %s using MAC address from ROM\n", + dev->name); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 72648162a9..14a520944e 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -28,7 +28,7 @@ static int dm_test_init(struct unit_test_state *uts, bool of_live) memset(dms, '\0', sizeof(*dms)); gd->dm_root = NULL; memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); - state_reset_for_test(state_get_current()); + state_reset_for_test(state_get_current(), true); #ifdef CONFIG_OF_LIVE /* Determine whether to make the live tree available */ From patchwork Fri Nov 22 04:17:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199211 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="lcg2kj39"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3J972BSz9sNx for ; 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Thu, 21 Nov 2019 20:20:05 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:04 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:39 -0700 Message-Id: <20191122041905.224686-11-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 014/100] Revert "RFC: sandbox: net: Suppress the MAC-address warnings" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/sandbox/cpu/state.c | 12 ++---------- arch/sandbox/include/asm/state.h | 5 +---- cmd/nvedit.c | 8 -------- include/configs/sandbox.h | 7 +++++-- include/env.h | 12 ------------ net/eth-uclass.c | 11 ++--------- test/dm/test-main.c | 2 +- 7 files changed, 11 insertions(+), 46 deletions(-) diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 70b278e4e2..dee5fde4f7 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -351,7 +351,7 @@ bool state_get_skip_delays(void) return state->skip_delays; } -void state_reset_for_test(struct sandbox_state *state, bool eth_vars) +void state_reset_for_test(struct sandbox_state *state) { /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; @@ -367,14 +367,6 @@ void state_reset_for_test(struct sandbox_state *state, bool eth_vars) */ INIT_LIST_HEAD(&state->mapmem_head); state->next_tag = state->ram_size; - - if (eth_vars) { - /* set up some environment variables needed by the eth tests */ - env_set_for_test("ethaddr", "00:00:11:22:33:44"); - env_set_for_test("eth1addr", "00:00:11:22:33:45"); - env_set_for_test("eth3addr", "00:00:11:22:33:46"); - env_set_for_test("eth5addr", "00:00:11:22:33:47"); - } } int state_init(void) @@ -385,7 +377,7 @@ int state_init(void) state->ram_buf = os_malloc(state->ram_size); assert(state->ram_buf); - state_reset_for_test(state, false); + state_reset_for_test(state); /* * Example of how to use GPIOs: * diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 4fa3b094a9..ad3e94beb9 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -251,11 +251,8 @@ bool state_get_skip_delays(void); * state_reset_for_test() - Reset ready to re-run tests * * This clears out any test state ready for another test run. - * - * @param state Sandbox state to update - * @param eth_vars Set environment variables for eth tests */ -void state_reset_for_test(struct sandbox_state *state, bool eth_vars); +void state_reset_for_test(struct sandbox_state *state); /** * state_show() - Show information about the sandbox state diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 6a01d755bb..99a3bc57b1 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -299,14 +299,6 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) return 0; } -int env_set_for_test(const char *varname, const char *value) -{ - const char * const argv[4] = { "setenv", varname, value, NULL }; - - assert(value); - return _do_env_set(0, 3, (char * const *)argv, 0); -} - int env_set(const char *varname, const char *varvalue) { const char * const argv[4] = { "setenv", varname, varvalue, NULL }; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 02e553c4b1..5d75021ed6 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -98,8 +98,11 @@ "stderr=serial,vidconsole\0" #endif -/* Note that some ethernet variables are set in state_reset_for_test() */ -#define SANDBOX_ETH_SETTINGS "ipaddr=1.2.3.4\0" +#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth1addr=00:00:11:22:33:45\0" \ + "eth3addr=00:00:11:22:33:46\0" \ + "eth5addr=00:00:11:22:33:47\0" \ + "ipaddr=1.2.3.4\0" #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ diff --git a/include/env.h b/include/env.h index bc48a72cde..b72239f6a5 100644 --- a/include/env.h +++ b/include/env.h @@ -145,18 +145,6 @@ int env_get_yesno(const char *var); */ int env_set(const char *varname, const char *value); -/** - * env_set_for_test() - Set the value of a variable for testing - * - * This works as if the variable value was defined in the built-in environment, - * so uses a flags value of 0. This should only be used in tests. - * - * @varname: Variable to adjust - * @value: Value to set for the variable (cannot be NULL) - * @return 0 if OK, 1 on error - */ -int env_set_for_test(const char *varname, const char *value); - /** * env_get_ulong() - Return an environment variable as an integer value * diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 6c19536138..3bd98b01ad 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -485,12 +485,6 @@ static int eth_post_probe(struct udevice *dev) struct eth_device_priv *priv = dev->uclass_priv; struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[ARP_HLEN]; - /* - * These warnings always appear on sandbox and are not useful. They have - * been here for some time and the issue has not been resolved. So for - * now, disable them. - */ - bool show_warnings = !IS_ENABLED(CONFIG_SANDBOX); #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct eth_ops *ops = eth_get_ops(dev); @@ -544,9 +538,8 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - if (show_warnings) - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + printf("\nWarning: %s using MAC address from ROM\n", + dev->name); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 14a520944e..72648162a9 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -28,7 +28,7 @@ static int dm_test_init(struct unit_test_state *uts, bool of_live) memset(dms, '\0', sizeof(*dms)); gd->dm_root = NULL; memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); - state_reset_for_test(state_get_current(), true); + state_reset_for_test(state_get_current()); #ifdef CONFIG_OF_LIVE /* Determine whether to make the live tree available */ From patchwork Fri Nov 22 04:17:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199205 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="brgmxUdx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3H44zFDz9sNx for ; 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Thu, 21 Nov 2019 20:20:07 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:06 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:40 -0700 Message-Id: <20191122041905.224686-12-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 015/100] x86: timer: use a timer base of 0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass --- Changes in v4: - Enable option for slimbootloader, coreboot, efi - Reverse the sense of the CONFIG option Changes in v3: None Changes in v2: None arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/cpu/slimbootloader/Kconfig | 1 + drivers/timer/Kconfig | 14 ++++++++++++++ drivers/timer/tsc_timer.c | 3 ++- lib/efi/Kconfig | 1 + 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 93f61f2fa4..c8e6a889d0 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -24,5 +24,6 @@ config SYS_COREBOOT imply CMD_CBFS imply FS_CBFS imply CBMEM_CONSOLE + imply X86_TSC_READ_BASE endif diff --git a/arch/x86/cpu/slimbootloader/Kconfig b/arch/x86/cpu/slimbootloader/Kconfig index 3ea4c9958c..58a9ca01a9 100644 --- a/arch/x86/cpu/slimbootloader/Kconfig +++ b/arch/x86/cpu/slimbootloader/Kconfig @@ -17,3 +17,4 @@ config SYS_SLIMBOOTLOADER imply USB_EHCI_HCD imply USB_XHCI_HCD imply E1000 + imply X86_TSC_READ_BASE diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 5f4bc6edb6..41f9755133 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -174,6 +174,20 @@ config X86_TSC_TIMER help Select this to enable Time-Stamp Counter (TSC) timer for x86. +config X86_TSC_READ_BASE + bool "Read the TSC timer base on start-up" + depends on X86_TSC_TIMER + help + On x86 platforms the TSC timer tick starts at the value 0 on reset. + This it makes no sense to read the timer on boot and use that as the + base, since we will miss some time taken to load U-Boot, etc. This + delay is controlled by the SoC and we cannot reduce it, but for + bootstage we want to record the time since reset as accurately as + possible. + + The only exception is when U-Boot is used as a secondary bootloader, + where this option should be enabled. + config MTK_TIMER bool "MediaTek timer support" depends on TIMER diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 637c8ff25a..a11a82f21a 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -396,7 +396,8 @@ static void tsc_timer_ensure_setup(bool early) { if (gd->arch.tsc_inited) return; - gd->arch.tsc_base = rdtsc(); + if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE)) + gd->arch.tsc_base = rdtsc(); if (!gd->arch.clock_rate) { unsigned long fast_calibrate; diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig index 919e314a0c..93b8564492 100644 --- a/lib/efi/Kconfig +++ b/lib/efi/Kconfig @@ -1,6 +1,7 @@ config EFI bool "Support running U-Boot from EFI" depends on X86 + imply X86_TSC_READ_BASE help U-Boot can be started from EFI on certain platforms. This allows EFI to perform most of the system init and then jump to U-Boot for From patchwork Fri Nov 22 04:17:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199208 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="gAQRC6mx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Hd3jpvz9sNx for ; Fri, 22 Nov 2019 15:25:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0F29AC22003; Fri, 22 Nov 2019 04:23:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CE70FC21FCA; Fri, 22 Nov 2019 04:20:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B1273C21C3F; Fri, 22 Nov 2019 04:20:14 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id 760BBC2204D for ; Fri, 22 Nov 2019 04:20:10 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id z26so2873776iot.8 for ; Thu, 21 Nov 2019 20:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ydYkg9hUJU/WV83Pzb9TsXtF4XVCqswBlauavxng/BE=; b=gAQRC6mxFcxO4i16ZkBMNQfox39a/ZhxqalpQbHUoFqN+OvYBiF0ExWVz/PHPKgQOr qXAv6suqHhYNjEC8wxyGSyFMKdu1ExmdYKrCG7KcoC32MGoRW2XLlrp/hyx6cYkUJWZL Y9/REBAXnVP3u8qP2sammlZMpMKLIKMMzlb2I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ydYkg9hUJU/WV83Pzb9TsXtF4XVCqswBlauavxng/BE=; b=XcTALugyDdd2KjC0MlfIoYF9bCN8/Sbws2+i5d+7JLC47H0kNCmN3slD1wFecfrnVI aUxf4RKYeE94mVDtBVTskLv1kHv03cYpX3jmESOBZVpLFgZ+P/WluKRlh1iLQTJxHBgF KqepF8ACvxHUpPZPtDqtVxMULAtv4GTvkIzBE14ZdMAR/NAaOvV8PhIzANvQtYNkRl+m UzYoj7aKc00gLWCQ+5h5w8rCqRSVq0j1ylKZpworg4ev5InmHY1PQuAqXycksvZScK7C it/jeCnLYbzNq/9DQz0h7T/CptUkiuA/Gprrkq+ZeUHjZmnCGIN1sA15P2r0DtuyAZUz Z4jg== X-Gm-Message-State: APjAAAUWmmy0loC6K56PaWpwVStevEN6d8E6LDuT2FmVuw5FtPmNVdSh BjOPfJeYXzF1SCGgmibFUiQ5wmGlgy8= X-Google-Smtp-Source: APXvYqznCm+tbnH6r37S/KnsinxobZdEE8b1bqIklQtUknc9ox/MWbjCoVzed2px4FhQ4N+FZaeRkA== X-Received: by 2002:a5d:9592:: with SMTP id a18mr10709378ioo.186.1574396409057; Thu, 21 Nov 2019 20:20:09 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:08 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:41 -0700 Message-Id: <20191122041905.224686-13-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 016/100] x86: timer: Reduce timer code size in TPL on Intel CPUs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass --- Changes in v4: - Update commit message to indicate that CPU-identity bug is fixed Changes in v3: None Changes in v2: None drivers/timer/Kconfig | 9 +++++++++ drivers/timer/tsc_timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 41f9755133..96cc49273f 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -188,6 +188,15 @@ config X86_TSC_READ_BASE The only exception is when U-Boot is used as a secondary bootloader, where this option should be enabled. +config TPL_X86_TSC_TIMER_NATIVE + bool "x86 TSC timer uses native calibration" + depends on TPL && X86_TSC_TIMER + help + Selects native timer calibration for TPL and don't include the other + methods in the code. This helps to reduce code size in TPL and works + on fairly modern Intel chips. Code-size reductions is about 700 + bytes. + config MTK_TIMER bool "MediaTek timer support" depends on TIMER diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index a11a82f21a..ffa2ac74c3 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -49,8 +49,7 @@ static unsigned long native_calibrate_tsc(void) return 0; crystal_freq = tsc_info.ecx / 1000; - - if (!crystal_freq) { + if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) { switch (gd->arch.x86_model) { case INTEL_FAM6_SKYLAKE_MOBILE: case INTEL_FAM6_SKYLAKE_DESKTOP: @@ -406,6 +405,10 @@ static void tsc_timer_ensure_setup(bool early) if (fast_calibrate) goto done; + /* Reduce code size by dropping other methods */ + if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE)) + panic("no timer"); + fast_calibrate = cpu_mhz_from_cpuid(); if (fast_calibrate) goto done; From patchwork Fri Nov 22 04:17:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199213 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Drop some superfluous functions to reduce code size. Add a simple CPU detection algorithm which just supports Intel and AMD, since we only support TPL on Intel, so far. Signed-off-by: Simon Glass --- Changes in v4: - Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead - Fix 'what' typo Changes in v3: None Changes in v2: None arch/x86/cpu/cpu.c | 4 ++++ arch/x86/cpu/i386/cpu.c | 41 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 41 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 9ee4b0294a..4795863b33 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -45,6 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_TPL_BUILD static const char *const x86_vendor_name[] = { [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", @@ -57,6 +58,7 @@ static const char *const x86_vendor_name[] = { [X86_VENDOR_NSC] = "NSC", [X86_VENDOR_SIS] = "SiS", }; +#endif int __weak x86_cleanup_before_linux(void) { @@ -113,6 +115,7 @@ int icache_status(void) return 1; } +#ifndef CONFIG_TPL_BUILD const char *cpu_vendor_name(int vendor) { const char *name; @@ -123,6 +126,7 @@ const char *cpu_vendor_name(int vendor) return name; } +#endif char *cpu_get_name(char *name) { diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 31663714a0..1b0ca0c90b 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -57,6 +58,8 @@ struct cpuinfo_x86 { uint8_t x86_mask; }; +/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */ +#ifndef CONFIG_TPL_BUILD /* * List of cpu vendor strings along with their normalized * id values. @@ -77,6 +80,7 @@ static const struct { { X86_VENDOR_NSC, "Geode by NSC", }, { X86_VENDOR_SIS, "SiS SiS SiS ", }, }; +#endif static void load_ds(u32 segment) { @@ -198,6 +202,7 @@ static inline int test_cyrix_52div(void) return (unsigned char) (test >> 8) == 0x02; } +#ifndef CONFIG_TPL_BUILD /* * Detect a NexGen CPU running without BIOS hypercode new enough * to have CPUID. (Thanks to Herbert Oppmann) @@ -218,6 +223,7 @@ static int deep_magic_nexgen_probe(void) : "=a" (ret) : : "cx", "dx"); return ret; } +#endif static bool has_cpuid(void) { @@ -229,6 +235,7 @@ static bool has_mtrr(void) return cpuid_edx(0x00000001) & (1 << 12) ? true : false; } +#ifndef CONFIG_TPL_BUILD static int build_vendor_name(char *vendor_name) { struct cpuid_result result; @@ -241,14 +248,40 @@ static int build_vendor_name(char *vendor_name) return result.eax; } +#endif static void identify_cpu(struct cpu_device_id *cpu) { + cpu->device = 0; /* fix gcc 4.4.4 warning */ + + /* + * Do a quick and dirty check to save space - Intel and AMD only and + * just the vendor. This is enough for most TPL code. + */ + if (spl_phase() == PHASE_TPL) { + struct cpuid_result result; + + result = cpuid(0x00000000); + switch (result.ecx >> 24) { + case 'l': /* GenuineIntel */ + cpu->vendor = X86_VENDOR_INTEL; + break; + case 'D': /* AuthenticAMD */ + cpu->vendor = X86_VENDOR_AMD; + break; + default: + cpu->vendor = X86_VENDOR_ANY; + break; + } + return; + } + +/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */ +#ifndef CONFIG_TPL_BUILD char vendor_name[16]; int i; vendor_name[0] = '\0'; /* Unset */ - cpu->device = 0; /* fix gcc 4.4.4 warning */ /* Find the id and vendor_name */ if (!has_cpuid()) { @@ -264,9 +297,8 @@ static void identify_cpu(struct cpu_device_id *cpu) /* Detect NexGen with old hypercode */ else if (deep_magic_nexgen_probe()) memcpy(vendor_name, "NexGenDriven", 13); - } - if (has_cpuid()) { - int cpuid_level; + } else { + int cpuid_level; cpuid_level = build_vendor_name(vendor_name); vendor_name[12] = '\0'; @@ -286,6 +318,7 @@ static void identify_cpu(struct cpu_device_id *cpu) break; } } +#endif } static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) From patchwork Fri Nov 22 04:17:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199265 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="S+ZdZkDE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K43R1xRLz9s7T for ; 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Thu, 21 Nov 2019 20:20:13 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:12 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:43 -0700 Message-Id: <20191122041905.224686-15-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 018/100] x86: Drop unnecessary interrupt code for TPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't expect an exception in TPL and don't need to set up interrupts in TPL. Drop this whole file. Signed-off-by: Simon Glass --- Changes in v4: - Drop the whole interrupt file for TPL Changes in v3: None Changes in v2: None arch/x86/cpu/i386/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile index 0c47252610..18e152074a 100644 --- a/arch/x86/cpu/i386/Makefile +++ b/arch/x86/cpu/i386/Makefile @@ -5,5 +5,7 @@ obj-y += call64.o obj-y += cpu.o +ifndef CONFIG_TPL_BUILD obj-y += interrupt.o +endif obj-y += setjmp.o From patchwork Fri Nov 22 04:17:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199224 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="RKJMqvuB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Xb5Wk2z9sNx for ; Fri, 22 Nov 2019 15:36:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 614BDC21FCA; Fri, 22 Nov 2019 04:26:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1D0F7C22077; Fri, 22 Nov 2019 04:21:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 651B6C22026; Fri, 22 Nov 2019 04:20:30 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id AD49BC2200D for ; Fri, 22 Nov 2019 04:20:16 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id j20so6349324ioo.11 for ; Thu, 21 Nov 2019 20:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=daI/6cJYXsJJD2LKpB5a9EfOJKHjrVh5F/saFbS2P60=; b=RKJMqvuB4YwTlCX9yM50CZcNafRLCWKizSP9WKIC2cTCX1dUnOgrLYQhGzxZYvT+tz EhVXhCAELobyK/Tk58BULO96zxgDg6Ww04tSq2Y3yjJ9WWsr2CiC+bAkza4+5SAr2nlK eqKwJuXGSbTpbqgBijrS8iLPkP5saf94b8fKA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=daI/6cJYXsJJD2LKpB5a9EfOJKHjrVh5F/saFbS2P60=; b=gf/5CRkBq1SWbP0iL5Fvb6nUdtaFSid0cc0GvvUcThQgHJJl7QuWkMWapEtKTKcGt7 ZpsZ73fHcZukC9jId9pSt0oH7EkwR2rLXQYwOXkE5FAKZVZXbmyyRdXVG0eBSfm9YHIi Mi4OUWvlt08dgYW85cJl/Ot0NZo1iv4zi60MXc39VPuijRZ2svLPhQ42D8pJ2AVEvnpi gwKew6Q9JaDtfcIa3jN8mCo0IVTFw/Ph8O4X7YsVUSNX+A3YKQIomRhEy6grsd/93X4R XCwejxiJl+PaUytZfJnN7gFxb+a0TKc53tuNOWphOBkDsbRsETHiwUjGegENC+9eqGP0 ed7g== X-Gm-Message-State: APjAAAWCYfMtTPETegPBHcnoqoDYtPWvBhsnw4DQj1kE656NIJkoirGm DrvGvmwbqiwb5LdDL+9KjL+KpU5eqwo= X-Google-Smtp-Source: APXvYqxXnVkKpHl7bJvECDAXn+V5rgdeq3TmiK+c+7DwUqkCQxm3XFUgvtloGKO7w3FiXvaqOnQldw== X-Received: by 2002:a6b:fd0b:: with SMTP id c11mr11377451ioi.203.1574396415283; Thu, 21 Nov 2019 20:20:15 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:14 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:44 -0700 Message-Id: <20191122041905.224686-16-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Lukasz Majewski Subject: [U-Boot] [PATCH v4 019/100] x86: power: Add an ACPI PMC uclass X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Intel x86 SoCs have a power manager/controller which handles several power-related aspects of the platform. Add a uclass for this, with a few useful operations. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: - Fix alpha order in Kconfig - Switch over to use pinctrl for pad init/config Changes in v3: - Rename power-mgr uclass to acpi-pmc Changes in v2: None drivers/power/Kconfig | 2 + drivers/power/acpi_pmc/Kconfig | 25 +++ drivers/power/acpi_pmc/Makefile | 5 + drivers/power/acpi_pmc/acpi-pmc-uclass.c | 188 +++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/power/acpi_pmc.h | 185 ++++++++++++++++++++++ 6 files changed, 406 insertions(+) create mode 100644 drivers/power/acpi_pmc/Kconfig create mode 100644 drivers/power/acpi_pmc/Makefile create mode 100644 drivers/power/acpi_pmc/acpi-pmc-uclass.c create mode 100644 include/power/acpi_pmc.h diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 9495dca33b..cb2c6fe3eb 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,5 +1,7 @@ menu "Power" +source "drivers/power/acpi_pmc/Kconfig" + source "drivers/power/domain/Kconfig" source "drivers/power/pmic/Kconfig" diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig new file mode 100644 index 0000000000..472a61a9fd --- /dev/null +++ b/drivers/power/acpi_pmc/Kconfig @@ -0,0 +1,25 @@ +config ACPI_PMC + bool "Power Manager (x86 PMC) support" + help + Enable support for an x86-style power-management controller which + provides features including checking whether the system started from + resume, powering off the system and enabling/disabling the reset + mechanism. + +config SPL_ACPI_PMC + bool "Power Manager (x86 PMC) support in SPL" + default y if ACPI_PMC + help + Enable support for an x86-style power-management controller which + provides features including checking whether the system started from + resume, powering off the system and enabling/disabling the reset + mechanism. + +config TPL_ACPI_PMC + bool "Power Manager (x86 PMC) support in TPL" + default y if ACPI_PMC + help + Enable support for an x86-style power-management controller which + provides features including checking whether the system started from + resume, powering off the system and enabling/disabling the reset + mechanism. diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile new file mode 100644 index 0000000000..7c1ba05c9f --- /dev/null +++ b/drivers/power/acpi_pmc/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c new file mode 100644 index 0000000000..653c71b948 --- /dev/null +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_ACPI_PMC + +#include +#include +#include +#include +#include +#include + +enum { + PM1_STS = 0x00, + PM1_EN = 0x02, + PM1_CNT = 0x04, + + GPE0_STS = 0x20, + GPE0_EN = 0x30, +}; + +struct tco_regs { + u32 tco_rld; + u32 tco_sts; + u32 tco1_cnt; + u32 tco_tmr; +}; + +enum { + TCO_STS_TIMEOUT = 1 << 3, + TCO_STS_SECOND_TO_STS = 1 << 17, + TCO1_CNT_HLT = 1 << 11, +}; + +static void pmc_fill_pm_reg_info(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + int i; + + upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS); + upriv->pm1_en = inw(upriv->acpi_base + PM1_EN); + upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT); + + log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt); + + for (i = 0; i < GPE0_REG_MAX; i++) { + upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4); + upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4); + log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, + upriv->gpe0_sts[i], i, upriv->gpe0_en[i]); + } +} + +int pmc_disable_tco_base(ulong tco_base) +{ + struct tco_regs *regs = (struct tco_regs *)tco_base; + + debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT); + setio_32(®s->tco1_cnt, TCO1_CNT_HLT); + + return 0; +} + +int pmc_init(struct udevice *dev) +{ + const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); + int ret; + + pmc_fill_pm_reg_info(dev); + if (!ops->init) + return -ENOSYS; + + ret = ops->init(dev); + if (ret) + return log_msg_ret("Failed to init pmc", ret); + +#ifdef DEBUG + pmc_dump_info(dev); +#endif + + return 0; +} + +int pmc_prev_sleep_state(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); + int prev_sleep_state = ACPI_S0; /* Default to S0 */ + + if (upriv->pm1_sts & WAK_STS) { + switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; + break; + case ACPI_S5: + prev_sleep_state = ACPI_S5; + break; + default: + break; + } + + /* Clear SLP_TYP */ + outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT); + } + + if (!ops->prev_sleep_state) + return prev_sleep_state; + + return ops->prev_sleep_state(dev, prev_sleep_state); +} + +int pmc_disable_tco(struct udevice *dev) +{ + const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); + + pmc_fill_pm_reg_info(dev); + if (!ops->disable_tco) + return -ENOSYS; + + return ops->disable_tco(dev); +} + +int pmc_global_reset_set_enable(struct udevice *dev, bool enable) +{ + const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); + + if (!ops->global_reset_set_enable) + return -ENOSYS; + + return ops->global_reset_set_enable(dev, enable); +} + +void pmc_dump_info(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + int i; + + printf("Device: %s\n", dev->name); + printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n", + upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2, + upriv->gpe_cfg); + printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt); + + for (i = 0; i < GPE0_REG_MAX; i++) { + printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, + upriv->gpe0_sts[i], i, upriv->gpe0_en[i]); + } + + printf("prsts: %08x\n", upriv->prsts); + printf("tco_sts: %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts); + printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", + upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3); +} + +int pmc_ofdata_to_uc_platdata(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + int ret; + + ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask); + if (ret) + return log_msg_ret("no gpe0-dwx-mask", ret); + ret = dev_read_u32(dev, "gpe0-dwx-shift-base", + &upriv->gpe0_dwx_shift_base); + if (ret) + return log_msg_ret("no gpe0-dwx-shift-base", ret); + ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg); + if (ret) + return log_msg_ret("no gpe0-sts", ret); + upriv->gpe0_sts_reg += upriv->acpi_base; + ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg); + if (ret) + return log_msg_ret("no gpe0-en", ret); + upriv->gpe0_en_reg += upriv->acpi_base; + + return 0; +} + +UCLASS_DRIVER(acpi_pmc) = { + .id = UCLASS_ACPI_PMC, + .name = "power-mgr", + .per_device_auto_alloc_size = sizeof(struct acpi_pmc_upriv), +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 0c563d898b..8431ad9c44 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -28,6 +28,7 @@ enum uclass_id { UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */ /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */ UCLASS_ADC, /* Analog-to-digital converter */ UCLASS_AHCI, /* SATA disk controller */ UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h new file mode 100644 index 0000000000..1f50c23f5f --- /dev/null +++ b/include/power/acpi_pmc.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ACPI_PMC_H +#define __ACPI_PMC_H + +enum { + GPE0_REG_MAX = 4, +}; + +/** + * struct acpi_pmc_upriv - holds common data for the x86 PMC + * + * @pmc_bar0: Base address 0 of PMC + * @pmc_bar1: Base address 2 of PMC + * @acpi_base: Base address of ACPI block + * @pm1_sts: PM1 status + * @pm1_en: PM1 enable + * @pm1_cnt: PM1 control + * @gpe_cfg: Address of GPE_CFG register + * @gpe0_dwx_mask: Mask to use for each GPE0 (typically 7 or 0xf) + * @gpe0_dwx_shift_base: Base shift value to use for GPE0 (0 or 4) + * @gpe0_sts_req: GPE0 status register offset + * @gpe0_en_req: GPE0 enable register offset + * @gpe0_sts: GPE0 status values + * @gpe0_en: GPE0 enable values + * @gpe0_dw: GPE0 DW values + * @gpe0_count: Number of GPE0 registers + * @tco1_sts: TCO1 status + * @tco2_sts: TCO2 status + * @prsts: Power and reset status + * @gen_pmcon1: General power mgmt configuration 1 + * @gen_pmcon2: General power mgmt configuration 2 + * @gen_pmcon3: General power mgmt configuration 3 + */ +struct acpi_pmc_upriv { + void *pmc_bar0; + void *pmc_bar2; + u32 acpi_base; + u16 pm1_sts; + u16 pm1_en; + u32 pm1_cnt; + u32 *gpe_cfg; + u32 gpe0_dwx_mask; + u32 gpe0_dwx_shift_base; + u32 gpe0_sts_reg; + u32 gpe0_en_reg; + u32 gpe0_sts[GPE0_REG_MAX]; + u32 gpe0_en[GPE0_REG_MAX]; + u32 gpe0_dw[GPE0_REG_MAX]; + int gpe0_count; + u16 tco1_sts; + u16 tco2_sts; + u32 prsts; + u32 gen_pmcon1; + u32 gen_pmcon2; + u32 gen_pmcon3; +}; + +struct acpi_pmc_ops { + /** + * init() - Set up the PMC for use + * + * This reads the current state of the PMC. Most of the state is read + * automatically by the uclass since it is common. + * + * This is optional. + * + * @dev: PMC device to use + * @return 0 if OK, -ve on error + */ + int (*init)(struct udevice *dev); + + /** + * prev_sleep_state() - Get the previous sleep state (optional) + * + * This reads various state registers and returns the sleep state from + * which the system woke. If this method is not provided, the uclass + * will return a calculated value. + * + * This is optional. + * + * @dev: PMC device to use + * @prev_sleep_state: Previous sleep state as calculated by the uclass. + * The method can use this as the return value or calculate its + * own. + * + * @return enum acpi_sleep_state indicating the previous sleep state + * (ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error + */ + int (*prev_sleep_state)(struct udevice *dev, int prev_sleep_state); + + /** + * disable_tco() - Disable the timer/counter + * + * Disables the timer/counter in the PMC + * + * This is optional. + * + * @dev: PMC device to use + * @return 0 + */ + int (*disable_tco)(struct udevice *dev); + + /** + * global_reset_set_enable() - Enable/Disable global reset + * + * Enable or disable global reset. If global reset is enabled, both hard + * reset and soft reset will trigger global reset, where both host and + * TXE are reset. This is cleared on cold boot, hard reset, soft reset + * and Sx. + * + * This is optional. + * + * @dev: PMC device to use + * @enable: true to enable global reset, false to disable + * @return 0 + */ + int (*global_reset_set_enable)(struct udevice *dev, bool enable); +}; + +#define acpi_pmc_get_ops(dev) ((struct acpi_pmc_ops *)(dev)->driver->ops) + +/** + * init() - Set up the PMC for use + * + * This reads the current state of the PMC. This reads in the common registers, + * then calls the device's init() method to read the SoC-specific registers. + * + * @return 0 if OK, -ve on error + */ +int pmc_init(struct udevice *dev); + +/** + * pmc_prev_sleep_state() - Get the previous sleep state + * + * This reads various state registers and returns the sleep state from + * which the system woke. + * + * @return enum acpi_sleep_state indicating the previous sleep state + * (ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error + */ +int pmc_prev_sleep_state(struct udevice *dev); + +/** + * pmc_disable_tco() - Disable the timer/counter + * + * Disables the timer/counter in the PMC + * + * @dev: PMC device to use + * @return 0 + */ +int pmc_disable_tco(struct udevice *dev); + +/** + * pmc_global_reset_set_enable() - Enable/Disable global reset + * + * Enable or disable global reset. If global reset is enabled, both hard + * reset and soft reset will trigger global reset, where both host and + * TXE are reset. This is cleared on cold boot, hard reset, soft reset + * and Sx. + * + * @dev: PMC device to use + * @enable: true to enable global reset, false to disable + * @return 0 + */ +int pmc_global_reset_set_enable(struct udevice *dev, bool enable); + +int pmc_ofdata_to_uc_platdata(struct udevice *dev); + +int pmc_disable_tco_base(ulong tco_base); + +void pmc_dump_info(struct udevice *dev); + +/** + * pmc_gpe_init() - Set up general-purpose events + * + * @dev: PMC device + * @return 0 if OK, -ve on error + */ +int pmc_gpe_init(struct udevice *dev); + +#endif From patchwork Fri Nov 22 04:17:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199268 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="JSI1T2BP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K44g4PZKz9s7T for ; Fri, 22 Nov 2019 16:00:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4BCADC22094; Fri, 22 Nov 2019 04:27:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5769BC22043; Fri, 22 Nov 2019 04:21:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 17C17C22047; Fri, 22 Nov 2019 04:20:30 +0000 (UTC) Received: from mail-il1-f194.google.com (mail-il1-f194.google.com [209.85.166.194]) by lists.denx.de (Postfix) with ESMTPS id C6622C2205D for ; Fri, 22 Nov 2019 04:20:18 +0000 (UTC) Received: by mail-il1-f194.google.com with SMTP id q15so5580368ils.8 for ; Thu, 21 Nov 2019 20:20:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=26W9FLhz+dDbkloX/oORYzIStii8LLtdjSMYfx8d+G4=; b=JSI1T2BPwYDagJVt++uchsG98VZFaFt1+i2IGMYGNTz7TorcsYVev0AGdJtCPoDb1V 4/XhZcqfaTwm4Xroq/XA2SWWm48RTjtkgqy2FksWJuPup3ZT4ofdMOtKwty0LTeV1F4J RtAT6Cf1y19/BqJNvcVYTY4xFeL/LENf/dB+U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=26W9FLhz+dDbkloX/oORYzIStii8LLtdjSMYfx8d+G4=; b=mNucYOdSwxL5mvhVUziUc6Bvey+2e868WGFP5hGtNu8GAz/xelGchB3268Sv80MmWz 6mfBH0CiDF0+hUnqy+yUDRL023Zm/iu2reZt10YS9NViCG6aoNbBfcQLqFQbqJUyBRqr 0GopwnqjFepWGAiMJ6mSsWd5UU5pVGTGKqvcPskHyuUefvCxh3MUDwM2tfKrN2Mm/X8G LI/loz97aJSCLZfxs6RUWMJa7nCOUCkqxpEdoIsfbFsp9cyLq15TOQXAYDCCDtDmVnt/ WsBPieyuy5xA5CUKky6Sj3wjWqVOo8P5ST+xp+oaEFjp6YL2AJa4UJScwbCyF7uW5XHR fVNQ== X-Gm-Message-State: APjAAAUWmcGLjfkLKy2d96BPRvjbNNqNOlEML+PR+Gd34XeZYmwbw4TY WgGTMBv1xvx+4pEWcE+k3I32YmlcI3A= X-Google-Smtp-Source: APXvYqyjBm6szYfORyL/CLNz2T1wRJX5xG/8pA2j6w9ucEiC4OojeGAAGAV7RSqmiHY6FqxLB3Gv8g== X-Received: by 2002:a92:bbdd:: with SMTP id x90mr253281ilk.286.1574396417424; Thu, 21 Nov 2019 20:20:17 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:17 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:45 -0700 Message-Id: <20191122041905.224686-17-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 020/100] x86: sandbox: Add a PMC emulator and test X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a simple PMC for sandbox to permit tests to run. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Rename power-mgr uclass to acpi-pmc - Tidy up Makefile rules to reduce duplication Changes in v2: None arch/Kconfig | 2 + arch/sandbox/dts/sandbox.dtsi | 14 ++ arch/sandbox/dts/test.dts | 14 ++ arch/sandbox/include/asm/test.h | 1 + drivers/Makefile | 1 + drivers/power/acpi_pmc/Kconfig | 9 ++ drivers/power/acpi_pmc/Makefile | 1 + drivers/power/acpi_pmc/pmc_emul.c | 246 ++++++++++++++++++++++++++++++ drivers/power/acpi_pmc/sandbox.c | 97 ++++++++++++ test/dm/Makefile | 1 + test/dm/pmc.c | 33 ++++ 11 files changed, 419 insertions(+) create mode 100644 drivers/power/acpi_pmc/pmc_emul.c create mode 100644 drivers/power/acpi_pmc/sandbox.c create mode 100644 test/dm/pmc.c diff --git a/arch/Kconfig b/arch/Kconfig index 141e48bc43..8094e18663 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -133,6 +133,8 @@ config SANDBOX imply PHYLIB imply DM_MDIO imply DM_MDIO_MUX + imply ACPI_PMC + imply ACPI_PMC_SANDBOX config SH bool "SuperH architecture" diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index f09bc70b0d..7bf144f532 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -100,6 +100,17 @@ }; pci-controller { + pci@1e,0 { + compatible = "sandbox,pmc"; + reg = <0xf000 0 0 0 0>; + sandbox,emul = <&pmc_emul>; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + gpe0-dw = <6 7 9>; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; + pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; @@ -109,6 +120,9 @@ emul { compatible = "sandbox,pci-emul-parent"; + pmc_emul: emul@1e,0 { + compatible = "sandbox,pmc-emul"; + }; swap_case_emul: emul@1f,0 { compatible = "sandbox,swap-case"; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index fdb08f2111..99905677ab 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -471,6 +471,17 @@ 0x01000810 0 0 0 0>; sandbox,emul = <&swap_case_emul0_1>; }; + pci@1e,0 { + compatible = "sandbox,pmc"; + reg = <0xf000 0 0 0 0>; + sandbox,emul = <&pmc_emul1e>; + acpi-base = <0x400>; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + gpe0-dw = <6 7 9>; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; pci@1f,0 { compatible = "pci-generic"; /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */ @@ -491,6 +502,9 @@ swap_case_emul0_1f: emul0@1f,0 { compatible = "sandbox,swap-case"; }; + pmc_emul1e: emul@1e,0 { + compatible = "sandbox,pmc-emul"; + }; }; pci1: pci-controller1 { diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index b885e1a14f..fa40d21f3f 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -13,6 +13,7 @@ #define SANDBOX_PCI_VENDOR_ID 0x1234 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 +#define SANDBOX_PCI_PMC_EMUL_ID 0x5677 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL diff --git a/drivers/Makefile b/drivers/Makefile index 0befeddfcb..4f460edc95 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index 472a61a9fd..fcd50e36ca 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -23,3 +23,12 @@ config TPL_ACPI_PMC provides features including checking whether the system started from resume, powering off the system and enabling/disabling the reset mechanism. + +config ACPI_PMC_SANDBOX + bool "Test power manager (PMC) for sandbox" + depends on ACPI_PMC && SANDBOX + help + This driver emulates a PMC (Power-Management Controller) so that + the uclass logic can be tested. You can use the 'pmc' command to + access information from the driver. It uses I/O access to read + from the PMC. diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile index 7c1ba05c9f..115788f109 100644 --- a/drivers/power/acpi_pmc/Makefile +++ b/drivers/power/acpi_pmc/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o diff --git a/drivers/power/acpi_pmc/pmc_emul.c b/drivers/power/acpi_pmc/pmc_emul.c new file mode 100644 index 0000000000..15cc7acaf3 --- /dev/null +++ b/drivers/power/acpi_pmc/pmc_emul.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCI emulation device for an x86 Power-Management Controller (PMC) + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +/** + * struct pmc_emul_platdata - platform data for this device + * + * @command: Current PCI command value + * @bar: Current base address values + */ +struct pmc_emul_platdata { + u16 command; + u32 bar[6]; +}; + +enum { + MEMMAP_SIZE = 0x80, +}; + +static struct pci_bar { + int type; + u32 size; +} barinfo[] = { + { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { PCI_BASE_ADDRESS_SPACE_IO, 256 }, +}; + +struct pmc_emul_priv { + u8 regs[MEMMAP_SIZE]; +}; + +static int sandbox_pmc_emul_read_config(struct udevice *emul, uint offset, + ulong *valuep, enum pci_size_t size) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + *valuep = plat->command; + break; + case PCI_HEADER_TYPE: + *valuep = 0; + break; + case PCI_VENDOR_ID: + *valuep = SANDBOX_PCI_VENDOR_ID; + break; + case PCI_DEVICE_ID: + *valuep = SANDBOX_PCI_PMC_EMUL_ID; + break; + case PCI_CLASS_DEVICE: + if (size == PCI_SIZE_8) { + *valuep = SANDBOX_PCI_CLASS_SUB_CODE; + } else { + *valuep = (SANDBOX_PCI_CLASS_CODE << 8) | + SANDBOX_PCI_CLASS_SUB_CODE; + } + break; + case PCI_CLASS_CODE: + *valuep = SANDBOX_PCI_CLASS_CODE; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, + barinfo[barnum].size); + break; + } + case PCI_CAPABILITY_LIST: + *valuep = PCI_CAP_ID_PM_OFFSET; + break; + } + + return 0; +} + +static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset, + ulong value, enum pci_size_t size) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + plat->command = value; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + debug("w bar %d=%lx\n", barnum, value); + *bar = value; + /* space indicator (bit#0) is read-only */ + *bar |= barinfo[barnum].type; + break; + } + } + + return 0; +} + +static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr, + int *barnump, unsigned int *offsetp) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + int barnum; + + for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { + unsigned int size = barinfo[barnum].size; + u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; + + if (addr >= base && addr < base + size) { + *barnump = barnum; + *offsetp = addr - base; + return 0; + } + } + *barnump = -1; + + return -ENOENT; +} + +static int sandbox_pmc_emul_read_io(struct udevice *dev, unsigned int addr, + ulong *valuep, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 4) + *valuep = offset; + else if (barnum == 0) + *valuep = offset; + + return 0; +} + +static int sandbox_pmc_emul_write_io(struct udevice *dev, unsigned int addr, + ulong value, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + return 0; +} + +static int sandbox_pmc_emul_map_physmem(struct udevice *dev, + phys_addr_t addr, unsigned long *lenp, + void **ptrp) +{ + struct pmc_emul_priv *priv = dev_get_priv(dev); + unsigned int offset, avail; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 0) { + *ptrp = priv->regs + offset; + avail = barinfo[0].size - offset; + if (avail > barinfo[0].size) + *lenp = 0; + else + *lenp = min(*lenp, (ulong)avail); + + return 0; + } + + return -ENOENT; +} + +static int sandbox_pmc_probe(struct udevice *dev) +{ + struct pmc_emul_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < MEMMAP_SIZE; i++) + priv->regs[i] = i; + + return 0; +} + +static struct dm_pci_emul_ops sandbox_pmc_emul_emul_ops = { + .read_config = sandbox_pmc_emul_read_config, + .write_config = sandbox_pmc_emul_write_config, + .read_io = sandbox_pmc_emul_read_io, + .write_io = sandbox_pmc_emul_write_io, + .map_physmem = sandbox_pmc_emul_map_physmem, +}; + +static const struct udevice_id sandbox_pmc_emul_ids[] = { + { .compatible = "sandbox,pmc-emul" }, + { } +}; + +U_BOOT_DRIVER(sandbox_pmc_emul_emul) = { + .name = "sandbox_pmc_emul_emul", + .id = UCLASS_PCI_EMUL, + .of_match = sandbox_pmc_emul_ids, + .ops = &sandbox_pmc_emul_emul_ops, + .probe = sandbox_pmc_probe, + .priv_auto_alloc_size = sizeof(struct pmc_emul_priv), + .platdata_auto_alloc_size = sizeof(struct pmc_emul_platdata), +}; + +static struct pci_device_id sandbox_pmc_emul_supported[] = { + { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) }, + {}, +}; + +U_BOOT_PCI_DEVICE(sandbox_pmc_emul_emul, sandbox_pmc_emul_supported); diff --git a/drivers/power/acpi_pmc/sandbox.c b/drivers/power/acpi_pmc/sandbox.c new file mode 100644 index 0000000000..7fbbf97b45 --- /dev/null +++ b/drivers/power/acpi_pmc/sandbox.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox PMC for testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_ACPI_PMC + +#include +#include +#include +#include + +#define GPIO_GPE_CFG 0x1050 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +#define GEN_PMCON2 0x1024 +#define GEN_PMCON3 0x1028 + +/* Offset of TCO registers from ACPI base I/O address */ +#define TCO_REG_OFFSET 0x60 +#define TCO1_STS 0x64 +#define TCO2_STS 0x66 +#define TCO1_CNT 0x68 +#define TCO2_CNT 0x6a + +struct sandbox_pmc_priv { + ulong base; +}; + +static int sandbox_pmc_fill_power_state(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS); + upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS); + + upriv->prsts = readl(upriv->pmc_bar0 + PRSTS); + upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1); + upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2); + upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3); + + return 0; +} + +static int sandbox_prev_sleep_state(struct udevice *dev, int prev_sleep_state) +{ + return prev_sleep_state; +} + +static int sandbox_disable_tco(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET); + + return 0; +} + +static int sandbox_pmc_probe(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct udevice *bus; + ulong base; + + uclass_first_device(UCLASS_PCI, &bus); + base = dm_pci_read_bar32(dev, 0); + if (base == FDT_ADDR_T_NONE) + return log_msg_ret("No base address", -EINVAL); + upriv->pmc_bar0 = map_sysmem(base, 0x2000); + upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG); + + return pmc_ofdata_to_uc_platdata(dev); +} + +static struct acpi_pmc_ops sandbox_pmc_ops = { + .init = sandbox_pmc_fill_power_state, + .prev_sleep_state = sandbox_prev_sleep_state, + .disable_tco = sandbox_disable_tco, +}; + +static const struct udevice_id sandbox_pmc_ids[] = { + { .compatible = "sandbox,pmc" }, + { } +}; + +U_BOOT_DRIVER(pmc_sandbox) = { + .name = "pmc_sandbox", + .id = UCLASS_ACPI_PMC, + .of_match = sandbox_pmc_ids, + .probe = sandbox_pmc_probe, + .ops = &sandbox_pmc_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_pmc_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 0c2fd5cb5e..10a19a00c9 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o +obj-$(CONFIG_ACPI_PMC) += pmc.o obj-$(CONFIG_DM_PWM) += pwm.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o diff --git a/test/dm/pmc.c b/test/dm/pmc.c new file mode 100644 index 0000000000..1a222838ab --- /dev/null +++ b/test/dm/pmc.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for power-management controller uclass (PMC) + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +/* Base test of the PMC uclass */ +static int dm_test_pmc_base(struct unit_test_state *uts) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_ACPI_PMC, &dev)); + + ut_assertok(pmc_disable_tco(dev)); + ut_assertok(pmc_init(dev)); + ut_assertok(pmc_prev_sleep_state(dev)); + + /* Check some values to see that I/O works */ + upriv = dev_get_uclass_priv(dev); + ut_asserteq(0x24, upriv->gpe0_sts[1]); + ut_asserteq(0x64, upriv->tco1_sts); + + return 0; +} +DM_TEST(dm_test_pmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Fri Nov 22 04:17:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199271 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:20:19 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:19 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:46 -0700 Message-Id: <20191122041905.224686-18-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Lukasz Majewski Subject: [U-Boot] [PATCH v4 021/100] x86: power: Add a 'pmc' command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a simple command to show information about the PMC. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Rename power-mgr uclass to acpi-pmc Changes in v2: None arch/Kconfig | 1 + cmd/Kconfig | 8 ++++++ cmd/Makefile | 1 + cmd/pmc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+) create mode 100644 cmd/pmc.c diff --git a/arch/Kconfig b/arch/Kconfig index 8094e18663..e1f1fcd275 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -135,6 +135,7 @@ config SANDBOX imply DM_MDIO_MUX imply ACPI_PMC imply ACPI_PMC_SANDBOX + imply CMD_PMC config SH bool "SuperH architecture" diff --git a/cmd/Kconfig b/cmd/Kconfig index cf982ff65e..acf04dc6ac 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -228,6 +228,14 @@ config CMD_LICENSE help Print GPL license text +config CMD_PMC + bool "pmc" + help + Provides access to the Intel Power-Management Controller (PMC) so + that its state can be examined. This does not currently support + changing the state but it is still useful for debugging and seeing + what is going on. + config CMD_REGINFO bool "reginfo" depends on PPC diff --git a/cmd/Makefile b/cmd/Makefile index 2d723ea0f0..7d54220531 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -108,6 +108,7 @@ ifdef CONFIG_PCI obj-$(CONFIG_CMD_PCI) += pci.o endif obj-$(CONFIG_CMD_PINMUX) += pinmux.o +obj-$(CONFIG_CMD_PMC) += pmc.o obj-$(CONFIG_CMD_PXE) += pxe.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_CMD_QFW) += qfw.o diff --git a/cmd/pmc.c b/cmd/pmc.c new file mode 100644 index 0000000000..cafeba9fcc --- /dev/null +++ b/cmd/pmc.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel PMC command + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include + +static int get_pmc_dev(struct udevice **devp) +{ + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) { + printf("Could not find device (err=%d)\n", ret); + return ret; + } + ret = pmc_init(dev); + if (ret) { + printf("Could not init device (err=%d)\n", ret); + return ret; + } + *devp = dev; + + return 0; +} + +static int do_pmc_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + int ret; + + ret = get_pmc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + return 0; +} + +static int do_pmc_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + int ret; + + ret = get_pmc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + pmc_dump_info(dev); + + return 0; +} + +static cmd_tbl_t cmd_pmc_sub[] = { + U_BOOT_CMD_MKENT(init, 0, 1, do_pmc_init, "", ""), + U_BOOT_CMD_MKENT(info, 0, 1, do_pmc_info, "", ""), +}; + +static int do_pmc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const cmd_tbl_t *cp; + + if (argc < 2) /* no subcommand */ + return cmd_usage(cmdtp); + + cp = find_cmd_tbl(argv[1], &cmd_pmc_sub[0], ARRAY_SIZE(cmd_pmc_sub)); + if (!cp) + return CMD_RET_USAGE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + pmc, 2, 1, do_pmc, "Power-management controller info", + "info - read state and show info about the PMC\n" + "pmc init - read state from the PMC\n" + ); From patchwork Fri Nov 22 04:17:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199246 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="oCpZyyWB"; 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Thu, 21 Nov 2019 20:20:21 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:21 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:47 -0700 Message-Id: <20191122041905.224686-19-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 022/100] pci: Add support for p2sb uclass X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. This adds a uclass and enables it for sandbox. Signed-off-by: Simon Glass --- Changes in v4: - Adjust condition for binding children Changes in v3: None Changes in v2: None configs/sandbox_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/misc/Kconfig | 33 ++++++ drivers/misc/Makefile | 1 + drivers/misc/p2sb-uclass.c | 209 ++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/p2sb.h | 127 +++++++++++++++++++++ 7 files changed, 373 insertions(+) create mode 100644 drivers/misc/p2sb-uclass.c create mode 100644 include/p2sb.h diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ee0ec3f233..d02c910afe 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -149,6 +149,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 55f7954c76..c0313b8cc6 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -134,6 +134,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 82bb093c56..71643af9c2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -226,6 +226,39 @@ config NUVOTON_NCT6102D disable the legacy UART, the watchdog or other devices in the Nuvoton Super IO chips on X86 platforms. +config P2SB + bool "Intel Primary-to-Sideband Bus" + depends on X86 || SANDBOX + help + This enables support for the Intel Primary-to-Sideband bus, + abbreviated to P2SB. The P2SB is used to access various peripherals + such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI + space. The space is segmented into different channels and peripherals + are accessed by device-specific means within those channels. Devices + should be added in the device tree as subnodes of the P2SB. A + Peripheral Channel Register? (PCR) API is provided to access those + devices - see pcr_readl(), etc. + +config SPL_P2SB + bool "Intel Primary-to-Sideband Bus in SPL" + depends on SPL && (X86 || SANDBOX) + help + The Primary-to-Sideband bus is used to access various peripherals + through memory-mapped I/O in a large chunk of PCI space. The space is + segmented into different channels and peripherals are accessed by + device-specific means within those channels. Devices should be added + in the device tree as subnodes of the p2sb. + +config TPL_P2SB + bool "Intel Primary-to-Sideband Bus in TPL" + depends on TPL && (X86 || SANDBOX) + help + The Primary-to-Sideband bus is used to access various peripherals + through memory-mapped I/O in a large chunk of PCI space. The space is + segmented into different channels and peripherals are accessed by + device-specific means within those channels. Devices should be added + in the device tree as subnodes of the p2sb. + config PWRSEQ bool "Enable power-sequencing drivers" depends on DM diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 55976d6be5..78b598b367 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o +obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o obj-$(CONFIG_QFW) += qfw.o diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c new file mode 100644 index 0000000000..c9aab7d21c --- /dev/null +++ b/drivers/misc/p2sb-uclass.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Uclass for Primary-to-sideband bus, used to access various peripherals + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PCR_COMMON_IOSF_1_0 1 + +static void *_pcr_reg_address(struct udevice *dev, uint offset) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + struct udevice *p2sb = dev_get_parent(dev); + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb); + uintptr_t reg_addr; + + /* Create an address based off of port id and offset */ + reg_addr = upriv->mmio_base; + reg_addr += pplat->pid << PCR_PORTID_SHIFT; + reg_addr += offset; + + return map_sysmem(reg_addr, 4); +} + +/* + * The mapping of addresses via the SBREG_BAR assumes the IOSF-SB + * agents are using 32-bit aligned accesses for their configuration + * registers. For IOSF versions greater than 1_0, IOSF-SB + * agents can use any access (8/16/32 bit aligned) for their + * configuration registers + */ +static inline void check_pcr_offset_align(uint offset, uint size) +{ + const size_t align = PCR_COMMON_IOSF_1_0 ? sizeof(uint32_t) : size; + + assert(IS_ALIGNED(offset, align)); +} + +uint pcr_read32(struct udevice *dev, uint offset) +{ + void *ptr; + uint val; + + /* Ensure the PCR offset is correctly aligned */ + assert(IS_ALIGNED(offset, sizeof(uint32_t))); + + ptr = _pcr_reg_address(dev, offset); + val = readl(ptr); + unmap_sysmem(ptr); + + return val; +} + +uint pcr_read16(struct udevice *dev, uint offset) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint16_t)); + + return readw(_pcr_reg_address(dev, offset)); +} + +uint pcr_read8(struct udevice *dev, uint offset) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint8_t)); + + return readb(_pcr_reg_address(dev, offset)); +} + +/* + * After every write one needs to perform a read an innocuous register to + * ensure the writes are completed for certain ports. This is done for + * all ports so that the callers don't need the per-port knowledge for + * each transaction. + */ +static void write_completion(struct udevice *dev, uint offset) +{ + readl(_pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t)))); +} + +void pcr_write32(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + assert(IS_ALIGNED(offset, sizeof(indata))); + + writel(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_write16(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint16_t)); + + writew(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_write8(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint8_t)); + + writeb(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data32; + + data32 = pcr_read32(dev, offset); + data32 &= ~clr; + data32 |= set; + pcr_write32(dev, offset, data32); +} + +void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data16; + + data16 = pcr_read16(dev, offset); + data16 &= ~clr; + data16 |= set; + pcr_write16(dev, offset, data16); +} + +void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data8; + + data8 = pcr_read8(dev, offset); + data8 &= ~clr; + data8 |= set; + pcr_write8(dev, offset, data8); +} + +int p2sb_set_port_id(struct udevice *dev, int portid) +{ + struct udevice *ps2b; + struct p2sb_child_platdata *pplat; + + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) + return -ENOSYS; + + uclass_find_first_device(UCLASS_P2SB, &ps2b); + if (!ps2b) + return -EDEADLK; + dev->parent = ps2b; + + /* + * We must allocate this, since when the device was bound it did not + * have a parent. + * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc + */ + dev->parent_platdata = malloc(sizeof(*pplat)); + if (!dev->parent_platdata) + return -ENOMEM; + pplat = dev_get_parent_platdata(dev); + pplat->pid = portid; + + return 0; +} + +static int p2sb_child_post_bind(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; +#endif + + return 0; +} + +static int p2sb_post_bind(struct udevice *dev) +{ + if (spl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA)) + return dm_scan_fdt_dev(dev); + + return 0; +} + +UCLASS_DRIVER(p2sb) = { + .id = UCLASS_P2SB, + .name = "p2sb", + .per_device_auto_alloc_size = sizeof(struct p2sb_uc_priv), + .post_bind = p2sb_post_bind, + .child_post_bind = p2sb_child_post_bind, + .per_child_platdata_auto_alloc_size = + sizeof(struct p2sb_child_platdata), +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 8431ad9c44..c1bab17ad1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -70,6 +70,7 @@ enum uclass_id { UCLASS_NOP, /* No-op devices */ UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_NVME, /* NVM Express device */ + UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */ UCLASS_PANEL, /* Display panel, such as an LCD */ UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ UCLASS_PCH, /* x86 platform controller hub */ diff --git a/include/p2sb.h b/include/p2sb.h new file mode 100644 index 0000000000..370f127058 --- /dev/null +++ b/include/p2sb.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#ifndef __p2sb_h +#define __p2sb_h + +/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ +#define PCR_PORTID_SHIFT 16 + +/** + * struct p2sb_child_platdata - Information about each child of a p2sb device + * + * @pid: Port ID for this child + */ +struct p2sb_child_platdata { + uint pid; +}; + +/** + * struct p2sb_uc_priv - information for the uclass about each device + * + * This must be set up by the driver when it is probed + * + * @mmio_base: Base address of P2SB region + */ +struct p2sb_uc_priv { + uint mmio_base; +}; + +/** + * struct p2sb_ops - Operations for the P2SB (none at present) + */ +struct p2sb_ops { +}; + +#define p2sb_get_ops(dev) ((struct p2sb_ops *)(dev)->driver->ops) + +/** + * pcr_read32/16/8() - Read from a PCR device + * + * Reads data from a PCR device within the P2SB + * + * @dev: Device to read from + * @offset: Offset within device to read + * @return value read + */ +uint pcr_read32(struct udevice *dev, uint offset); +uint pcr_read16(struct udevice *dev, uint offset); +uint pcr_read8(struct udevice *dev, uint offset); + +/** + * pcr_read32/16/8() - Write to a PCR device + * + * Writes data to a PCR device within the P2SB + * + * @dev: Device to write to + * @offset: Offset within device to write + * @data: Data to write + */ +void pcr_write32(struct udevice *dev, uint offset, uint data); +void pcr_write16(struct udevice *dev, uint offset, uint data); +void pcr_write8(struct udevice *dev, uint offset, uint data); + +/** + * pcr_clrsetbits32/16/8() - Update a PCR device + * + * Updates dat in a PCR device within the P2SB + * + * This reads from the device, clears and set bits, then writes back. + * + * new_data = (old_data & ~clr) | set + * + * @dev: Device to update + * @offset: Offset within device to update + * @clr: Bits to clear after reading + * @set: Bits to set before writing + */ +void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set); +void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set); +void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set); + +static inline void pcr_setbits32(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits32(dev, offset, 0, set); +} + +static inline void pcr_setbits16(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits16(dev, offset, 0, set); +} + +static inline void pcr_setbits8(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits8(dev, offset, 0, set); +} + +static inline void pcr_clrbits32(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits32(dev, offset, clr, 0); +} + +static inline void pcr_clrbits16(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits16(dev, offset, clr, 0); +} + +static inline void pcr_clrbits8(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits8(dev, offset, clr, 0); +} + +/** + * p2sb_set_port_id() - Set the port ID for a p2sb child device + * + * This must be called in a device's bind() method when OF_PLATDATA is used + * since the uclass cannot access the device's of-platdata. + * + * @dev: Child device (whose parent is UCLASS_P2SB) + * @portid: Port ID of child device + * @return 0 if OK, -ENODEV is the p2sb device could not be found + */ +int p2sb_set_port_id(struct udevice *dev, int portid); + +#endif From patchwork Fri Nov 22 04:17:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199261 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XPB10WmC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K40B2SXtz9sPc for ; Fri, 22 Nov 2019 15:56:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1BB34C22096; Fri, 22 Nov 2019 04:25:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 656EBC2207A; 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Signed-off-by: Simon Glass --- Changes in v4: - Split out into a separate patch Changes in v3: None Changes in v2: None arch/sandbox/cpu/state.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index dee5fde4f7..cd46e000f5 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -356,6 +356,7 @@ void state_reset_for_test(struct sandbox_state *state) /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; state->sysreset_allowed[SYSRESET_POWER_OFF] = true; + state->allow_memio = false; memset(&state->wdt, '\0', sizeof(state->wdt)); memset(state->spi, '\0', sizeof(state->spi)); From patchwork Fri Nov 22 04:17:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199229 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="PUv6Hl65"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3b117xvz9sPc for ; Fri, 22 Nov 2019 15:38:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id ECAE8C2203D; Fri, 22 Nov 2019 04:25:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ADC1CC22074; Fri, 22 Nov 2019 04:20:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C10ADC2203E; Fri, 22 Nov 2019 04:20:41 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id 12A03C2206B for ; Fri, 22 Nov 2019 04:20:27 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id j13so6460585ioe.0 for ; Thu, 21 Nov 2019 20:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zvZQ/tzNg1P7Ua1N76Arz+UZqfznud08yOtjYTI44Mc=; b=PUv6Hl65EdMhpl8xVr38gbmJ6gPpuC9bHsbjjHk79ebYQnMUJYWSYcsAIckVFoFzX+ DhWd8EJDfC5RxKxXYUpajE9vd57nSIAMve/ru4VVSax3JsQLXVCLhZpE0Y8FUSXyArHs IoVXIfvldKQRGawdPrCUAQ72uir7NFA9KxMbY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zvZQ/tzNg1P7Ua1N76Arz+UZqfznud08yOtjYTI44Mc=; b=KSlmYSSEU+8AzOtcWJ/1IvYUtol3AbNA8Lb92q9JcY3AHTNm0+2NhpCyskqoPlZayh QaAsar0K9kFW0BZiEz2O89tOSoNYPwew2siM8miiyMtaWEvdLihDbBczOjP3uOiwYnf/ skgEhyNm/ngaDklcVRC9VPjJF6kA56yRtvosiZJg5cFPie9/xMhMHmmvfr3IVOQgHnzM 5LQrdM8HosffvVC28zjB/DY7msT8OFwfbH+AX7qjbUxhc6zGcvZerI7/3c+vCYaFKT4x yMwFJZaFl7YybvW7beq+SXzjjuD7HBs+2YzfG5dv5tIHsKuz1x9rgQma3G5eGLmyBp0X r4Uw== X-Gm-Message-State: APjAAAV3vJg23XtUGZUNbUS7SbISjtZubSCfOpqy4UsQmeyZlcxqYywU nMc8DLX93nyJHEILmhBwxgUDpIX7THM= X-Google-Smtp-Source: APXvYqzGgYrmEDHANaRpKmYSFfKYXsN9u6TMumtekCu3ihE7rd6xC/qqMKL6XNN3lqnbJCeUF3Ku6g== X-Received: by 2002:a5e:8e49:: with SMTP id r9mr16389ioo.47.1574396425572; Thu, 21 Nov 2019 20:20:25 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:25 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:49 -0700 Message-Id: <20191121211845.v4.24.I838b4b33c91a8000743aea498b139d915e95de4a@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 024/100] sandbox: Add PCI driver and test for p2sb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality. Signed-off-by: Simon Glass --- Changes in v4: - Drop change to message about a missing uclass - Drop empty operations struct since p2sb does not need it - Drop pmic_pm8916 driver name and use a sandbox name instead - Split out mmio changes into a separate patch Changes in v3: - Fix build errors in sandbox_spl, etc Changes in v2: None arch/sandbox/dts/test.dts | 13 ++ arch/sandbox/include/asm/test.h | 1 + configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 3 +- configs/sandbox_flattree_defconfig | 3 + configs/sandbox_spl_defconfig | 2 + configs/tools-only_defconfig | 2 + drivers/misc/Makefile | 2 + drivers/misc/p2sb_emul.c | 272 +++++++++++++++++++++++++++++ drivers/misc/p2sb_sandbox.c | 40 +++++ drivers/misc/sandbox_adder.c | 60 +++++++ test/dm/Makefile | 1 + test/dm/p2sb.c | 28 +++ 13 files changed, 428 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/p2sb_emul.c create mode 100644 drivers/misc/p2sb_sandbox.c create mode 100644 drivers/misc/sandbox_adder.c create mode 100644 test/dm/p2sb.c diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 99905677ab..9c8c4e2709 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -471,6 +471,16 @@ 0x01000810 0 0 0 0>; sandbox,emul = <&swap_case_emul0_1>; }; + p2sb-pci@2,0 { + compatible = "sandbox,p2sb"; + reg = <0x02001010 0 0 0 0>; + sandbox,emul = <&p2sb_emul>; + + adder { + intel,p2sb-port-id = <3>; + compatible = "sandbox,adder"; + }; + }; pci@1e,0 { compatible = "sandbox,pmc"; reg = <0xf000 0 0 0 0>; @@ -502,6 +512,9 @@ swap_case_emul0_1f: emul0@1f,0 { compatible = "sandbox,swap-case"; }; + p2sb_emul: emul@2,0 { + compatible = "sandbox,p2sb-emul"; + }; pmc_emul1e: emul@1e,0 { compatible = "sandbox,pmc-emul"; }; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index fa40d21f3f..fdb0ecfed1 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -14,6 +14,7 @@ #define SANDBOX_PCI_VENDOR_ID 0x1234 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 #define SANDBOX_PCI_PMC_EMUL_ID 0x5677 +#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index b0abf99386..26f84292e6 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -81,6 +81,8 @@ CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d02c910afe..8068d7e5e3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -130,6 +130,8 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y +CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y @@ -149,7 +151,6 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y -CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index b50f750d06..4b24f1e89a 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -65,6 +65,8 @@ CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SANDBOX_CLK_CCF=y @@ -115,6 +117,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index c0313b8cc6..06b3b744ac 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -86,6 +86,8 @@ CONFIG_DEBUG_DEVRES=y # CONFIG_SPL_SIMPLE_BUS is not set CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index 4808b49850..35f5ca7406 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -11,6 +11,8 @@ CONFIG_OF_HOSTFILE=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_IP_DEFRAG=y # CONFIG_UDP_FUNCTION_FASTBOOT is not set +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_SANDBOX_GPIO=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 78b598b367..44c9e3ef08 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -10,8 +10,10 @@ obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_SANDBOX) += sandbox_adder.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o obj-$(CONFIG_SANDBOX) += swap_case.o endif diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c new file mode 100644 index 0000000000..c3795c59c0 --- /dev/null +++ b/drivers/misc/p2sb_emul.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCI emulation device for an x86 Primary-to-Sideband bus + * + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#define LOG_CATEGORY UCLASS_MISC +#define LOG_DEBUG + +#include +#include +#include +#include +#include +#include + +/** + * struct p2sb_emul_platdata - platform data for this device + * + * @command: Current PCI command value + * @bar: Current base address values + */ +struct p2sb_emul_platdata { + u16 command; + u32 bar[6]; +}; + +enum { + /* This emulator supports 16 different devices */ + MEMMAP_SIZE = 16 << PCR_PORTID_SHIFT, +}; + +static struct pci_bar { + int type; + u32 size; +} barinfo[] = { + { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, +}; + +struct p2sb_emul_priv { + u8 regs[16]; +}; + +static int sandbox_p2sb_emul_read_config(struct udevice *emul, uint offset, + ulong *valuep, enum pci_size_t size) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + *valuep = plat->command; + break; + case PCI_HEADER_TYPE: + *valuep = PCI_HEADER_TYPE_NORMAL; + break; + case PCI_VENDOR_ID: + *valuep = SANDBOX_PCI_VENDOR_ID; + break; + case PCI_DEVICE_ID: + *valuep = SANDBOX_PCI_P2SB_EMUL_ID; + break; + case PCI_CLASS_DEVICE: + if (size == PCI_SIZE_8) { + *valuep = SANDBOX_PCI_CLASS_SUB_CODE; + } else { + *valuep = (SANDBOX_PCI_CLASS_CODE << 8) | + SANDBOX_PCI_CLASS_SUB_CODE; + } + break; + case PCI_CLASS_CODE: + *valuep = SANDBOX_PCI_CLASS_CODE; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, + barinfo[barnum].size); + break; + } + case PCI_CAPABILITY_LIST: + *valuep = PCI_CAP_ID_PM_OFFSET; + break; + } + + return 0; +} + +static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset, + ulong value, enum pci_size_t size) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + plat->command = value; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + log_debug("w bar %d=%lx\n", barnum, value); + *bar = value; + /* space indicator (bit#0) is read-only */ + *bar |= barinfo[barnum].type; + break; + } + } + + return 0; +} + +static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr, + int *barnump, unsigned int *offsetp) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + int barnum; + + for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { + unsigned int size = barinfo[barnum].size; + u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; + + if (addr >= base && addr < base + size) { + *barnump = barnum; + *offsetp = addr - base; + return 0; + } + } + *barnump = -1; + + return -ENOENT; +} + +static int sandbox_p2sb_emul_read_io(struct udevice *dev, unsigned int addr, + ulong *valuep, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 4) + *valuep = offset; + else if (barnum == 0) + *valuep = offset; + + return 0; +} + +static int sandbox_p2sb_emul_write_io(struct udevice *dev, unsigned int addr, + ulong value, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + return 0; +} + +static int find_p2sb_channel(struct udevice *emul, uint offset, + struct udevice **devp) +{ + uint pid = offset >> PCR_PORTID_SHIFT; + struct udevice *p2sb, *dev; + int ret; + + ret = sandbox_pci_get_client(emul, &p2sb); + if (ret) + return log_msg_ret("No client", ret); + + device_foreach_child(dev, p2sb) { + struct p2sb_child_platdata *pplat = + dev_get_parent_platdata(dev); + + log_debug(" - child %s, pid %d, want %d\n", dev->name, + pplat->pid, pid); + if (pid == pplat->pid) { + *devp = dev; + return 0; + } + } + + return -ENOENT; +} + +static int sandbox_p2sb_emul_map_physmem(struct udevice *dev, + phys_addr_t addr, unsigned long *lenp, + void **ptrp) +{ + struct p2sb_emul_priv *priv = dev_get_priv(dev); + struct udevice *child; + unsigned int offset; + int barnum; + int ret; + + log_debug("map %x: ", (uint)addr); + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return log_msg_ret("Cannot find bar", ret); + log_debug("bar %d, offset %x\n", barnum, offset); + + if (barnum != 0) + return log_msg_ret("Unknown BAR", -EINVAL); + + ret = find_p2sb_channel(dev, offset, &child); + if (ret) + return log_msg_ret("Cannot find channel", ret); + + offset &= ((1 << PCR_PORTID_SHIFT) - 1); + ret = axi_read(child, offset, priv->regs, AXI_SIZE_32); + if (ret) + return log_msg_ret("Child read failed", ret); + *ptrp = priv->regs + (offset & 3); + *lenp = 4; + + return 0; +} + +static struct dm_pci_emul_ops sandbox_p2sb_emul_emul_ops = { + .read_config = sandbox_p2sb_emul_read_config, + .write_config = sandbox_p2sb_emul_write_config, + .read_io = sandbox_p2sb_emul_read_io, + .write_io = sandbox_p2sb_emul_write_io, + .map_physmem = sandbox_p2sb_emul_map_physmem, +}; + +static const struct udevice_id sandbox_p2sb_emul_ids[] = { + { .compatible = "sandbox,p2sb-emul" }, + { } +}; + +U_BOOT_DRIVER(sandbox_p2sb_emul_emul) = { + .name = "sandbox_p2sb_emul_emul", + .id = UCLASS_PCI_EMUL, + .of_match = sandbox_p2sb_emul_ids, + .ops = &sandbox_p2sb_emul_emul_ops, + .priv_auto_alloc_size = sizeof(struct p2sb_emul_priv), + .platdata_auto_alloc_size = sizeof(struct p2sb_emul_platdata), +}; + +static struct pci_device_id sandbox_p2sb_emul_supported[] = { + { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) }, + {}, +}; + +U_BOOT_PCI_DEVICE(sandbox_p2sb_emul_emul, sandbox_p2sb_emul_supported); diff --git a/drivers/misc/p2sb_sandbox.c b/drivers/misc/p2sb_sandbox.c new file mode 100644 index 0000000000..fb4dd786ab --- /dev/null +++ b/drivers/misc/p2sb_sandbox.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox P2SB for testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_P2SB + +#include +#include +#include +#include + +struct sandbox_p2sb_priv { + ulong base; +}; + +static int sandbox_p2sb_probe(struct udevice *dev) +{ + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); + + upriv->mmio_base = dm_pci_read_bar32(dev, 0); + printf("mmio base %x\n", upriv->mmio_base); + + return 0; +} + +static const struct udevice_id sandbox_p2sb_ids[] = { + { .compatible = "sandbox,p2sb" }, + { } +}; + +U_BOOT_DRIVER(p2sb_sandbox) = { + .name = "p2sb_sandbox", + .id = UCLASS_P2SB, + .of_match = sandbox_p2sb_ids, + .probe = sandbox_p2sb_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_p2sb_priv), +}; diff --git a/drivers/misc/sandbox_adder.c b/drivers/misc/sandbox_adder.c new file mode 100644 index 0000000000..df262e6255 --- /dev/null +++ b/drivers/misc/sandbox_adder.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox adder for p2sb testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_MISC + +#include +#include +#include +#include +#include +#include + +struct sandbox_adder_priv { + ulong base; +}; + +int sandbox_adder_read(struct udevice *dev, ulong address, void *data, + enum axi_size_t size) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + u32 *val = data; + + *val = pplat->pid << 24 | address; + + return 0; +} + +int sandbox_adder_write(struct udevice *dev, ulong address, void *data, + enum axi_size_t size) +{ + return 0; +} + +static int sandbox_adder_probe(struct udevice *dev) +{ + return 0; +} + +static struct axi_ops sandbox_adder_ops = { + .read = sandbox_adder_read, + .write = sandbox_adder_write, +}; + +static const struct udevice_id sandbox_adder_ids[] = { + { .compatible = "sandbox,adder" }, + { } +}; + +U_BOOT_DRIVER(adder_sandbox) = { + .name = "sandbox_adder", + .id = UCLASS_AXI, + .of_match = sandbox_adder_ids, + .probe = sandbox_adder_probe, + .ops = &sandbox_adder_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_adder_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 10a19a00c9..129ccb3b49 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -32,6 +32,7 @@ obj-y += ofnode.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_P2SB) += p2sb.o obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c new file mode 100644 index 0000000000..ccb75cf375 --- /dev/null +++ b/test/dm/p2sb.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for Primary-to-Sideband bus (P2SB) + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include + +/* Base test of the PMC uclass */ +static int dm_test_p2sb_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + sandbox_set_enable_memio(true); + ut_assertok(uclass_get_device_by_name(UCLASS_AXI, "adder", &dev)); + ut_asserteq(0x03000004, pcr_read32(dev, 4)); + ut_asserteq(0x300, pcr_read16(dev, 6)); + ut_asserteq(4, pcr_read8(dev, 4)); + + return 0; +} +DM_TEST(dm_test_p2sb_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Fri Nov 22 04:17:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199233 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Thu, 21 Nov 2019 20:20:27 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:27 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:50 -0700 Message-Id: <20191121211845.v4.25.I6e887ca4f819fa15009bbcb90062498a58f8c135@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 025/100] x86: Move UCLASS_IRQ into a separate file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations. Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86. Signed-off-by: Simon Glass --- Changes in v4: - Drop itss uclass in Makefile - Fix 'enabled' typo - apollolake -> Apollo Lake Changes in v3: - Add two more operations to IRQ - Use the IRQ uclass instead of creating a new ITSS uclass Changes in v2: None arch/Kconfig | 1 + arch/x86/cpu/irq.c | 5 --- drivers/misc/Kconfig | 9 ++++ drivers/misc/Makefile | 1 + drivers/misc/irq-uclass.c | 53 +++++++++++++++++++++++ include/irq.h | 88 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 152 insertions(+), 5 deletions(-) create mode 100644 drivers/misc/irq-uclass.c create mode 100644 include/irq.h diff --git a/arch/Kconfig b/arch/Kconfig index e1f1fcd275..6865e1f909 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -186,6 +186,7 @@ config X86 imply USB_HOST_ETHER imply PCH imply RTC_MC146818 + imply IRQ # Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DM diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 3adc155818..cb183496b7 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -370,8 +370,3 @@ U_BOOT_DRIVER(irq_router_drv) = { .probe = irq_router_probe, .priv_auto_alloc_size = sizeof(struct irq_router), }; - -UCLASS_DRIVER(irq) = { - .id = UCLASS_IRQ, - .name = "irq", -}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 71643af9c2..f18aa8f7ba 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -203,6 +203,15 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +config IRQ + bool "Intel Interrupt controller" + depends on X86 || SANDBOX + help + This enables support for Intel interrupt controllers, including ITSS. + Some devices have extra features, such as Apollo Lake. The + device has its own uclass since there are several operations + involved. + config JZ4780_EFUSE bool "Ingenic JZ4780 eFUSE support" depends on ARCH_JZ47XX diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 44c9e3ef08..28313e4a65 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_FS_LOADER) += fs_loader.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o +obj-$(CONFIG_IRQ) += irq-uclass.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c new file mode 100644 index 0000000000..d5182cf149 --- /dev/null +++ b/drivers/misc/irq-uclass.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Bin Meng + */ + +#include +#include +#include + +int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->route_pmc_gpio_gpe) + return -ENOSYS; + + return ops->route_pmc_gpio_gpe(dev, pmc_gpe_num); +} + +int irq_set_polarity(struct udevice *dev, uint irq, bool active_low) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->set_polarity) + return -ENOSYS; + + return ops->set_polarity(dev, irq, active_low); +} + +int irq_snapshot_polarities(struct udevice *dev) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->snapshot_polarities) + return -ENOSYS; + + return ops->snapshot_polarities(dev); +} + +int irq_restore_polarities(struct udevice *dev) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->restore_polarities) + return -ENOSYS; + + return ops->restore_polarities(dev); +} + +UCLASS_DRIVER(irq) = { + .id = UCLASS_IRQ, + .name = "irq", +}; diff --git a/include/irq.h b/include/irq.h new file mode 100644 index 0000000000..01ded64f16 --- /dev/null +++ b/include/irq.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * IRQ is a type of interrupt controller used on recent Intel SoC. + * + * Copyright 2019 Google LLC + */ + +#ifndef __irq_H +#define __irq_H + +/** + * struct irq_ops - Operations for the IRQ + */ +struct irq_ops { + /** + * route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ + int (*route_pmc_gpio_gpe)(struct udevice *dev, uint pmc_gpe_num); + + /** + * set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ + int (*set_polarity)(struct udevice *dev, uint irq, bool active_low); + + /** + * snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ + int (*snapshot_polarities)(struct udevice *dev); + + /** + * restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ + int (*restore_polarities)(struct udevice *dev); +}; + +#define irq_get_ops(dev) ((struct irq_ops *)(dev)->driver->ops) + +/** + * irq_route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ +int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num); + +/** + * irq_set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ +int irq_set_polarity(struct udevice *dev, uint irq, bool active_low); + +/** + * irq_snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ +int irq_snapshot_polarities(struct udevice *dev); + +/** + * irq_restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ +int irq_restore_polarities(struct udevice *dev); + +#endif From patchwork Fri Nov 22 04:17:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199225 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Thu, 21 Nov 2019 20:20:29 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:29 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:51 -0700 Message-Id: <20191121211845.v4.26.I026619a2340394947b85c9cecc4a97bff912dcb8@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 026/100] sandbox: Add a test for IRQ X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a simple sandbox test for this uclass. Signed-off-by: Simon Glass --- Changes in v4: - Drop itss uclass change in Makefile (now in previous patch) - Drop sandbox defconfig change now that p2sb change is correct - Enable IRQ for sandbox64 too to avoid build error Changes in v3: - Change the sandbox test from ITSS to IRQ Changes in v2: None arch/sandbox/dts/test.dts | 4 +++ configs/sandbox64_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/irq_sandbox.c | 55 ++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/irq.c | 32 +++++++++++++++++ 8 files changed, 96 insertions(+) create mode 100644 drivers/misc/irq_sandbox.c create mode 100644 test/dm/irq.c diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9c8c4e2709..57513a449f 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -353,6 +353,10 @@ vss-microvolts = <0>; }; + irq { + compatible = "sandbox,irq"; + }; + lcd { u-boot,dm-pre-reloc; compatible = "sandbox,lcd-sdl"; diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 26f84292e6..9273cd2d8c 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -112,6 +112,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 4b24f1e89a..19238f8cb8 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -98,6 +98,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 06b3b744ac..f1f66356d8 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -118,6 +118,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_MMC_SANDBOX=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 28313e4a65..d4e8638dea 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_IRQ) += irq-uclass.o +obj-$(CONFIG_SANDBOX) += irq_sandbox.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c new file mode 100644 index 0000000000..6dda1a4c44 --- /dev/null +++ b/drivers/misc/irq_sandbox.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for interrupts + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include + +static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low) +{ + if (irq > 10) + return -EINVAL; + + return 0; +} + +static int sandbox_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +{ + if (pmc_gpe_num > 10) + return -ENOENT; + + return pmc_gpe_num + 1; +} + +static int sandbox_snapshot_polarities(struct udevice *dev) +{ + return 0; +} + +static int sandbox_restore_polarities(struct udevice *dev) +{ + return 0; +} + +static const struct irq_ops sandbox_irq_ops = { + .route_pmc_gpio_gpe = sandbox_route_pmc_gpio_gpe, + .set_polarity = sandbox_set_polarity, + .snapshot_polarities = sandbox_snapshot_polarities, + .restore_polarities = sandbox_restore_polarities, +}; + +static const struct udevice_id sandbox_irq_ids[] = { + { .compatible = "sandbox,irq"}, + { } +}; + +U_BOOT_DRIVER(sandbox_irq_drv) = { + .name = "sandbox_irq", + .id = UCLASS_IRQ, + .of_match = sandbox_irq_ids, + .ops = &sandbox_irq_ops, +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 129ccb3b49..a268783169 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_SOUND) += i2s.o +obj-y += irq.o obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o diff --git a/test/dm/irq.c b/test/dm/irq.c new file mode 100644 index 0000000000..726189c59f --- /dev/null +++ b/test/dm/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for irq uclass + * + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +/* Base test of the irq uclass */ +static int dm_test_irq_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_IRQ, &dev)); + + ut_asserteq(5, irq_route_pmc_gpio_gpe(dev, 4)); + ut_asserteq(-ENOENT, irq_route_pmc_gpio_gpe(dev, 14)); + + ut_assertok(irq_set_polarity(dev, 4, true)); + ut_asserteq(-EINVAL, irq_set_polarity(dev, 14, true)); + + ut_assertok(irq_snapshot_polarities(dev)); + ut_assertok(irq_restore_polarities(dev)); + + return 0; +} +DM_TEST(dm_test_irq_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); From patchwork Fri Nov 22 04:17:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199227 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="b4cqxtG1"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3YQ28hzz9sNx for ; Fri, 22 Nov 2019 15:36:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1F1EC220A1; Fri, 22 Nov 2019 04:28:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8EDF0C2204D; Fri, 22 Nov 2019 04:21:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C5E2DC22038; Fri, 22 Nov 2019 04:20:47 +0000 (UTC) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by lists.denx.de (Postfix) with ESMTPS id D2FF1C22026 for ; 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Thu, 21 Nov 2019 20:20:32 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:32 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:52 -0700 Message-Id: <20191122041905.224686-20-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 027/100] x86: Define the SPL image start X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Define this symbol so that we can use binman symbols correctly. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/cpu/u-boot-spl.lds | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index c1e9bfbf66..e6c22895b3 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -17,7 +17,10 @@ SECTIONS . = IMAGE_TEXT_BASE; /* Location of bootcode in flash */ __text_start = .; - .text : { *(.text*); } + .text : { + __image_copy_start = .; + *(.text*); + } . = ALIGN(4); From patchwork Fri Nov 22 04:17:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199215 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="OdsfyLLD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Qf2hssz9sPc for ; Fri, 22 Nov 2019 15:31:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D19E6C22054; Fri, 22 Nov 2019 04:28:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 010F3C22062; Fri, 22 Nov 2019 04:21:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EA57DC22087; Fri, 22 Nov 2019 04:20:47 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id 0A406C22062 for ; Fri, 22 Nov 2019 04:20:36 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id i11so6342101iol.13 for ; Thu, 21 Nov 2019 20:20:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MSbjghv2P1Eq+yDXzVJfoWPRqXhmbyNNyC33mPqNM6I=; b=OdsfyLLDJkGInFtpX8j02y9TbKjox1RVmNsOGXQkW77OufQ2tOwqSWaROFnn3enQf5 F8Pp3eVjeB9zdx7ByOcM5oPRkj5269EOuTJO80GjcxjxSPuaXb2AtZhMRkXSUp0PDvfm ZxCgPOz8T+91D/VK4L/ZE8UG5I7SgVsHVGf2U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MSbjghv2P1Eq+yDXzVJfoWPRqXhmbyNNyC33mPqNM6I=; b=eafoHBh4/Ijd27C0ZQY4b2qhXYyeqqnRqc8c9O0llITK28Eb5XA+Wp5kUD+QmUhgpp CXXCK69VjhHoPj/TKmtTRvbr/OyDIng8Ty96inSNqOxOWwk3dAZsCNmgpgbeKLv1dO5Z KLNq8IsTfbmaLbYvQWNY22Kx426xrtzAX0eOsgBS79hc+mPyhHfcwp3LqCOfI+IuCiHW U5QxN1ie8P8/cIql6V076ucdYcQoW8owqb2mvpFAv5tfuhuXBtJlaotx5GElMrwL1GDZ 5hkejiWOIKZrOT+aO04ptNRZhgRr3oF3DeTJ9BzJq1xUxy71KJENe+mOVfAwNNmZhxUm eeqw== X-Gm-Message-State: APjAAAUkL8N+6n29r0mjyfXuN7286CZ2cOoCWPbbL/32AdqHzbReuYiv v55+h2tGfy4FM0YyzLfjX+yTxGAcXGE= X-Google-Smtp-Source: APXvYqxCg4spZkQYxTBnQaglGE/O/xSJZr2EQk70KVv3gzXZiOlcjgmc9II/pChXEEIx542dhRkl7g== X-Received: by 2002:a5d:8b85:: with SMTP id p5mr11371565iol.9.1574396434872; Thu, 21 Nov 2019 20:20:34 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:34 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:53 -0700 Message-Id: <20191122041905.224686-21-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 028/100] x86: Reduce mrccache record alignment size X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: None Changes in v2: None arch/x86/include/asm/mrccache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 40fda856ff..abf5818223 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -7,7 +7,7 @@ #ifndef _ASM_MRCCACHE_H #define _ASM_MRCCACHE_H -#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_ALIGN 0x100 #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ ('C' << 16) | ('D'<<24)) From patchwork Fri Nov 22 04:17:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199267 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="SSlWM3xf"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K44P3C9Yz9s7T for ; Fri, 22 Nov 2019 16:00:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2D189C22105; Fri, 22 Nov 2019 04:28:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.5 required=5.0 tests=RCVD_IN_MSPIKE_H2, TVD_PH_BODY_ACCOUNTS_PRE, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E7108C2206E; Fri, 22 Nov 2019 04:21:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 92469C22029; Fri, 22 Nov 2019 04:20:52 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 524AAC22070 for ; Fri, 22 Nov 2019 04:20:41 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id v17so1723797ilg.7 for ; Thu, 21 Nov 2019 20:20:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LOCJxhZrME4lQpT/x77E/MQzr3HTP43VFirvUPZIcdk=; b=SSlWM3xf+LiMcYMwYjo8sOFdC39LMEhwyh2p/XTPI24LvJHSTHNo/chOmV8mgSZjiF Jh7qvZv73ZVWXf34CZS/DuRCHV10DiJ5PcsabbcI+o3oXzbERoSs0wHHyJNqHm0NMYL6 c+aKPKfIqAVwJlc/iFQWVXDGW77IKvpuG03UM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LOCJxhZrME4lQpT/x77E/MQzr3HTP43VFirvUPZIcdk=; b=KqvvANnhgev2zgcHvvqty+/GMvlJHMSkRSJcbUEav+Nzq2jZZZHzLd6gi1VgoLcCuB GV1viVZTyyb34LX9LUSEAqMp2/78smtdgr4NfOVwCiWQ8S0UHaLBmjRrRwjfJ5WFEfxt uxohp/FZOAYODkEu06ZhlUjW5NtLdHo6zPlvgdGTcKw8Trrgi5eavRal2zUPOq0Vnz0r +f8eAYpYFhS0o8f71HmbPbN2AsoAHDi36UNjDLaUcMpg0UNiBqksqOTJ5aDDQFWNgV7T DXp9raj8I4pOQ9aZa8f6qzinOpmDi7eXlS5WV7/D+Flzee+0AjAL0G1ldrm4k7rNgwyv Jk6A== X-Gm-Message-State: APjAAAVvA3Z2IOA/wZgA8rUdIcaUGo4k0bQ8YuoYBKq50vyzhtPHoqlE EyAwa4rPGEpQEeXXAybU1la9jqAZFQs= X-Google-Smtp-Source: APXvYqzYOUWOy4FLpyexYzAuKMJFbEEWRGnhvdZD+J+ImwwAbiIZfGdN8queaXGGzTmdzk6Bt5rTxQ== X-Received: by 2002:a92:db44:: with SMTP id w4mr13934469ilq.126.1574396436941; Thu, 21 Nov 2019 20:20:36 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:36 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:54 -0700 Message-Id: <20191121211845.v4.29.I73b4396e3d9bb2ef5dd5d745e4f7df6652047567@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 029/100] x86: Correct mrccache find_next_mrc_cache() calculation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This should take account of the end of the new cache record since a record cannot extend beyond the end of the flash region. This problem was not seen before due to the alignment of the relatively small amount of MRC data. But with Apollo Lake the MRC data is about 45KB, even if most of it is zeroes. Fix this bug and update the parameter name to be less confusing. Signed-off-by: Simon Glass --- Changes in v4: - Add comments about MRC-cache records being the same size - apollolake -> Apollo Lake Changes in v3: - Add an extra size parameter to the find_next_mrc_cache() function Changes in v2: None arch/x86/lib/mrccache.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 33bb52039b..9d56685d36 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -80,21 +80,31 @@ struct mrc_data_container *mrccache_find_current(struct mrc_region *entry) /** * find_next_mrc_cache() - get next cache entry * + * This moves to the next cache entry in the region, making sure it has enough + * space to hold data of size @data_size. + * * @entry: MRC cache flash area * @cache: Entry to start from + * @data_size: Required data size of the new entry. Note that we assume that + * all cache entries are the same size * * @return next cache entry if found, NULL if we got to the end */ static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry, - struct mrc_data_container *cache) + struct mrc_data_container *prev, int data_size) { + struct mrc_data_container *cache; ulong base_addr, end_addr; base_addr = entry->base + entry->offset; end_addr = base_addr + entry->length; - cache = next_mrc_block(cache); - if ((ulong)cache >= end_addr) { + /* + * We assume that all cache entries are the same size, but let's use + * data_size here for clarity. + */ + cache = next_mrc_block(prev); + if ((ulong)cache + mrc_block_size(data_size) > end_addr) { /* Crossed the boundary */ cache = NULL; debug("%s: no available entries found\n", __func__); @@ -131,7 +141,7 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, /* Move to the next block, which will be the first unused block */ if (cache) - cache = find_next_mrc_cache(entry, cache); + cache = find_next_mrc_cache(entry, cache, cur->data_size); /* * If we have got to the end, erase the entire mrc-cache area and start From patchwork Fri Nov 22 04:17:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199220 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="dvYUrKJF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3W668X8z9sNx for ; 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Thu, 21 Nov 2019 20:20:39 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:38 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:55 -0700 Message-Id: <20191122041905.224686-22-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 030/100] x86: Adjust mrccache_get_region() to use livetree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Change the algorithm to first find the flash device then read the properties using the livetree API. With this change the device is not probed so this needs to be done in mrccache_save(). Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Update mrccache livetree patch to just convert to livetree Changes in v2: None arch/x86/lib/mrccache.c | 55 +++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 9d56685d36..50c72bf962 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -206,45 +208,37 @@ int mrccache_reserve(void) int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) { - const void *blob = gd->fdt_blob; - int node, mrc_node; + struct udevice *dev; + ofnode mrc_node; u32 reg[2]; int ret; - /* Find the flash chip within the SPI controller node */ - node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); - if (node < 0) { - debug("%s: Cannot find SPI flash\n", __func__); - return -ENOENT; - } - - if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) { - debug("%s: Cannot find memory map\n", __func__); - return -EINVAL; - } + /* + * Find the flash chip within the SPI controller node. Avoid probing + * the device here since it may put it into a strange state where the + * memory map cannot be read. + */ + ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("Cannot find SPI flash\n", ret); + ret = dev_read_u32_array(dev, "memory-map", reg, 2); + if (ret) + return log_msg_ret("Cannot find memory map\n", ret); entry->base = reg[0]; /* Find the place where we put the MRC cache */ - mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); - if (mrc_node < 0) { - debug("%s: Cannot find node\n", __func__); - return -EPERM; - } + mrc_node = dev_read_subnode(dev, "rw-mrc-cache"); + if (!ofnode_valid(mrc_node)) + return log_msg_ret("Cannot find node", -EPERM); - if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) { - debug("%s: Cannot find address\n", __func__); - return -EINVAL; - } + ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2); + if (ret) + return log_msg_ret("Cannot find address", ret); entry->offset = reg[0]; entry->length = reg[1]; - if (devp) { - ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - devp); - debug("ret = %d\n", ret); - if (ret) - return ret; - } + if (devp) + *devp = dev; return 0; } @@ -262,6 +256,9 @@ int mrccache_save(void) gd->arch.mrc_output_len); ret = mrccache_get_region(&sf, &entry); + if (ret) + goto err_entry; + ret = device_probe(sf); if (ret) goto err_entry; data = (struct mrc_data_container *)gd->arch.mrc_output; From patchwork Fri Nov 22 04:17:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199254 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:20:41 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:40 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:56 -0700 Message-Id: <20191122041905.224686-23-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 031/100] x86: Adjust mrccache_get_region() to support get_mmap() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It is now possible to obtain the memory map for a SPI controllers instead of having it hard-coded in the device tree. Update the code to support this. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: - Use SPI mmap() instead of SPI flash arch/x86/lib/mrccache.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 50c72bf962..7136166be6 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -210,6 +210,9 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) { struct udevice *dev; ofnode mrc_node; + ulong map_base; + uint map_size; + uint offset; u32 reg[2]; int ret; @@ -221,10 +224,15 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); if (ret) return log_msg_ret("Cannot find SPI flash\n", ret); - ret = dev_read_u32_array(dev, "memory-map", reg, 2); - if (ret) - return log_msg_ret("Cannot find memory map\n", ret); - entry->base = reg[0]; + ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset); + if (!ret) { + entry->base = map_base; + } else { + ret = dev_read_u32_array(dev, "memory-map", reg, 2); + if (ret) + return log_msg_ret("Cannot find memory map\n", ret); + entry->base = reg[0]; + } /* Find the place where we put the MRC cache */ mrc_node = dev_read_subnode(dev, "rw-mrc-cache"); @@ -239,6 +247,8 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) if (devp) *devp = dev; + debug("MRC cache in '%s', offset %x, len %x, base %x\n", + dev->name, entry->offset, entry->length, entry->base); return 0; } From patchwork Fri Nov 22 04:17:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199239 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; 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Thu, 21 Nov 2019 20:20:43 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:42 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:57 -0700 Message-Id: <20191122041905.224686-24-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 032/100] x86: Add a new global_data member for the cache record X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present we reuse the mrc_output char * to also point to the cache record after it has been set up. This is confusing and doesn't save much data space. Add a new mrc_cache member instead. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/include/asm/global_data.h | 2 ++ arch/x86/lib/mrccache.c | 11 +++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 0e7b946205..3212b006eb 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ #include +#include enum pei_boot_mode_t { PEI_BOOT_NONE = 0, @@ -93,6 +94,7 @@ struct arch_global_data { /* MRC training data to save for the next boot */ char *mrc_output; unsigned int mrc_output_len; + struct mrc_data_container *mrc_cache; ulong table; /* Table pointer from previous loader */ int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 7136166be6..6e561fe528 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -188,8 +188,7 @@ static void mrccache_setup(void *data) cache->reserved = 0; memcpy(cache->data, gd->arch.mrc_output, cache->data_size); - /* gd->arch.mrc_output now points to the container */ - gd->arch.mrc_output = (char *)cache; + gd->arch.mrc_cache = cache; } int mrccache_reserve(void) @@ -255,7 +254,7 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) int mrccache_save(void) { - struct mrc_data_container *data; + struct mrc_data_container *cache; struct mrc_region entry; struct udevice *sf; int ret; @@ -271,10 +270,10 @@ int mrccache_save(void) ret = device_probe(sf); if (ret) goto err_entry; - data = (struct mrc_data_container *)gd->arch.mrc_output; - ret = mrccache_update(sf, &entry, data); + cache = gd->arch.mrc_cache; + ret = mrccache_update(sf, &entry, cache); if (!ret) { - debug("Saved MRC data with checksum %04x\n", data->checksum); + debug("Saved MRC data with checksum %04x\n", cache->checksum); } else if (ret == -EEXIST) { debug("MRC data is the same as last time, skipping save\n"); ret = 0; From patchwork Fri Nov 22 04:17:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199238 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="bU2W3Nwo"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3ly31Gdz9sNx for ; Fri, 22 Nov 2019 15:46:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 17443C22044; Fri, 22 Nov 2019 04:28:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0E8E3C2206D; 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Update it to remove the goto, returning errors as they happen. While we are here, use hex for the data size since this is the norm in U-Boot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: - Move an additional error handling fix from a future patch Changes in v2: None arch/x86/lib/mrccache.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 6e561fe528..712bacd5d2 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -168,7 +168,7 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, cur); if (ret) { debug("Failed to write to SPI flash\n"); - return ret; + return log_msg_ret("Cannot update mrccache", ret); } return 0; @@ -261,28 +261,23 @@ int mrccache_save(void) if (!gd->arch.mrc_output_len) return 0; - debug("Saving %d bytes of MRC output data to SPI flash\n", + debug("Saving %#x bytes of MRC output data to SPI flash\n", gd->arch.mrc_output_len); ret = mrccache_get_region(&sf, &entry); if (ret) - goto err_entry; + return log_msg_ret("Cannot get region", ret); ret = device_probe(sf); if (ret) - goto err_entry; + return log_msg_ret("Cannot probe device", ret); cache = gd->arch.mrc_cache; ret = mrccache_update(sf, &entry, cache); - if (!ret) { + if (!ret) debug("Saved MRC data with checksum %04x\n", cache->checksum); - } else if (ret == -EEXIST) { + else if (ret == -EEXIST) debug("MRC data is the same as last time, skipping save\n"); - ret = 0; - } -err_entry: - if (ret) - debug("%s: Failed: %d\n", __func__, ret); - return ret; + return 0; } int mrccache_spl_save(void) From patchwork Fri Nov 22 04:17:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199247 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="BtxevnvV"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3rp428Rz9sNx for ; Fri, 22 Nov 2019 15:50:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 310B6C22086; Fri, 22 Nov 2019 04:30:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C841CC22054; Fri, 22 Nov 2019 04:22:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C6CFC22056; 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Thu, 21 Nov 2019 20:20:47 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:47 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:17:59 -0700 Message-Id: <20191122041905.224686-26-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 034/100] x86: Update mrccache to support multiple caches X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With Apollo Lake we need to support a normal cache, which almost never changes and a much smaller 'variable' cache which changes every time. Update the code to add a cache type, use an array for the caches and use a for loop to iterate over the caches. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Move line related to variable-cache into the next patch Changes in v2: None arch/x86/cpu/broadwell/sdram.c | 8 ++- arch/x86/cpu/ivybridge/sdram.c | 8 ++- arch/x86/cpu/quark/dram.c | 8 ++- arch/x86/include/asm/global_data.h | 21 +++++-- arch/x86/include/asm/mrccache.h | 11 +++- arch/x86/lib/fsp/fsp_common.c | 2 +- arch/x86/lib/fsp1/fsp_dram.c | 8 ++- arch/x86/lib/mrccache.c | 88 ++++++++++++++++++++---------- 8 files changed, 106 insertions(+), 48 deletions(-) diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index b31d78c092..107c04691b 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -82,7 +82,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data) struct mrc_region entry; int ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); @@ -168,12 +168,14 @@ int dram_init(void) pei_data->data_to_save); /* S3 resume: don't save scrambler seed or MRC data */ if (pei_data->boot_mode != SLEEP_STATE_S3) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + /* * This will be copied to SDRAM in reserve_arch(), then written * to SPI flash in mrccache_save() */ - gd->arch.mrc_output = (char *)pei_data->data_to_save; - gd->arch.mrc_output_len = pei_data->data_to_save_size; + mrc->buf = (char *)pei_data->data_to_save; + mrc->len = pei_data->data_to_save_size; } gd->arch.pei_meminfo = pei_data->meminfo; diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 8a58d0383d..8b03406666 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -115,7 +115,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data) ret = read_seed_from_cmos(pei_data); if (ret) return ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); @@ -537,12 +537,14 @@ int dram_init(void) /* S3 resume: don't save scrambler seed or MRC data */ if (pei_data->boot_mode != PEI_BOOT_RESUME) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + /* * This will be copied to SDRAM in reserve_arch(), then written * to SPI flash in mrccache_save() */ - gd->arch.mrc_output = (char *)pei_data->mrc_output; - gd->arch.mrc_output_len = pei_data->mrc_output_len; + mrc->buf = (char *)pei_data->mrc_output; + mrc->len = pei_data->mrc_output_len; ret = write_seeds_to_cmos(pei_data); if (ret) debug("Failed to write seeds to CMOS: %d\n", ret); diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 51f9659ab1..3994355112 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -22,7 +22,7 @@ static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) struct mrc_region entry; int ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; @@ -152,9 +152,11 @@ int dram_init(void) #ifdef CONFIG_ENABLE_MRC_CACHE cache = malloc(sizeof(struct mrc_timings)); if (cache) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); - gd->arch.mrc_output = cache; - gd->arch.mrc_output_len = sizeof(struct mrc_timings); + mrc->buf = cache; + mrc->len = sizeof(struct mrc_timings); } #endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3212b006eb..190b604e0f 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -67,6 +67,21 @@ struct mtrr_request { uint64_t size; }; +/** + * struct mrc_output - holds the MRC data + * + * @buf: MRC training data to save for the next boot. This is set to point to + * the raw data after SDRAM init is complete. Then mrccache_setup() + * turns it into a proper cache record with a checksum + * @len: Length of @buf + * @cache: Resulting cache record + */ +struct mrc_output { + char *buf; + uint len; + struct mrc_data_container *cache; +}; + /* Architecture-specific global data */ struct arch_global_data { u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16); @@ -91,10 +106,8 @@ struct arch_global_data { struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; int mtrr_req_count; int has_mtrr; - /* MRC training data to save for the next boot */ - char *mrc_output; - unsigned int mrc_output_len; - struct mrc_data_container *mrc_cache; + /* MRC training data */ + struct mrc_output mrc[MRC_TYPE_COUNT]; ulong table; /* Table pointer from previous loader */ int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index abf5818223..b81e2b2fb6 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -27,6 +27,13 @@ struct mrc_region { u32 length; }; +/* Types of MRC data */ +enum mrc_type_t { + MRC_TYPE_NORMAL, + + MRC_TYPE_COUNT, +}; + struct udevice; /** @@ -84,6 +91,7 @@ int mrccache_reserve(void); * triggers PCI bus enumeration during which insufficient memory issue * might be exposed and it causes subsequent SPI flash probe fails). * + * @type: Type of MRC data to use * @devp: Returns pointer to the SPI flash device * @entry: Position and size of MRC cache in SPI flash * @return 0 if success, -ENOENT if SPI flash node does not exist in the @@ -91,7 +99,8 @@ int mrccache_reserve(void); * tree, -EINVAL if MRC region properties format is incorrect, other error * if SPI flash probe failed. */ -int mrccache_get_region(struct udevice **devp, struct mrc_region *entry); +int mrccache_get_region(enum mrc_type_t type, struct udevice **devp, + struct mrc_region *entry); /** * mrccache_save() - save MRC data to the SPI flash diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 40ba866d77..c1c30ce0eb 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -63,7 +63,7 @@ void *fsp_prepare_mrc_cache(void) struct mrc_region entry; int ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return NULL; diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 6a3349b42a..5ef89744b9 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -15,9 +15,11 @@ int dram_init(void) if (ret) return ret; - if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) - gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, - &gd->arch.mrc_output_len); + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + + mrc->buf = fsp_get_nvs_data(gd->arch.hob_list, &mrc->len); + } return 0; } diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 712bacd5d2..1278737ce4 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -174,38 +174,45 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, return 0; } -static void mrccache_setup(void *data) +static void mrccache_setup(struct mrc_output *mrc, void *data) { struct mrc_data_container *cache = data; u16 checksum; cache->signature = MRC_DATA_SIGNATURE; - cache->data_size = gd->arch.mrc_output_len; - checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size); + cache->data_size = mrc->len; + checksum = compute_ip_checksum(mrc->buf, cache->data_size); debug("Saving %d bytes for MRC output data, checksum %04x\n", cache->data_size, checksum); cache->checksum = checksum; cache->reserved = 0; - memcpy(cache->data, gd->arch.mrc_output, cache->data_size); + memcpy(cache->data, mrc->buf, cache->data_size); - gd->arch.mrc_cache = cache; + mrc->cache = cache; } int mrccache_reserve(void) { - if (!gd->arch.mrc_output_len) - return 0; + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + struct mrc_output *mrc = &gd->arch.mrc[i]; - /* adjust stack pointer to store pure cache data plus the header */ - gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); - mrccache_setup((void *)gd->start_addr_sp); + if (!mrc->len) + continue; - gd->start_addr_sp &= ~0xf; + /* adjust stack pointer to store pure cache data plus header */ + gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE); + mrccache_setup(mrc, (void *)gd->start_addr_sp); + + gd->start_addr_sp &= ~0xf; + } return 0; } -int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) +int mrccache_get_region(enum mrc_type_t type, struct udevice **devp, + struct mrc_region *entry) { struct udevice *dev; ofnode mrc_node; @@ -246,31 +253,33 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) if (devp) *devp = dev; - debug("MRC cache in '%s', offset %x, len %x, base %x\n", - dev->name, entry->offset, entry->length, entry->base); + debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n", + type, dev->name, entry->offset, entry->length, entry->base); return 0; } -int mrccache_save(void) +static int mrccache_save_type(enum mrc_type_t type) { struct mrc_data_container *cache; + struct mrc_output *mrc; struct mrc_region entry; struct udevice *sf; int ret; - if (!gd->arch.mrc_output_len) + mrc = &gd->arch.mrc[type]; + if (!mrc->len) return 0; - debug("Saving %#x bytes of MRC output data to SPI flash\n", - gd->arch.mrc_output_len); - - ret = mrccache_get_region(&sf, &entry); + log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n", + mrc->len, type); + ret = mrccache_get_region(type, &sf, &entry); if (ret) return log_msg_ret("Cannot get region", ret); ret = device_probe(sf); if (ret) return log_msg_ret("Cannot probe device", ret); - cache = gd->arch.mrc_cache; + cache = mrc->cache; + ret = mrccache_update(sf, &entry, cache); if (!ret) debug("Saved MRC data with checksum %04x\n", cache->checksum); @@ -280,17 +289,36 @@ int mrccache_save(void) return 0; } +int mrccache_save(void) +{ + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + int ret; + + ret = mrccache_save_type(i); + if (ret) + return ret; + } + + return 0; +} + int mrccache_spl_save(void) { - void *data; - int size; - - size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE; - data = malloc(size); - if (!data) - return log_msg_ret("Allocate MRC cache block", -ENOMEM); - mrccache_setup(data); - gd->arch.mrc_output = data; + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + struct mrc_output *mrc = &gd->arch.mrc[i]; + void *data; + int size; + + size = mrc->len + MRC_DATA_HEADER_SIZE; + data = malloc(size); + if (!data) + return log_msg_ret("Allocate MRC cache block", -ENOMEM); + mrccache_setup(mrc, data); + } return mrccache_save(); } From patchwork Fri Nov 22 04:18:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199258 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Thu, 21 Nov 2019 20:20:49 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:49 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:00 -0700 Message-Id: <20191122041905.224686-27-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 035/100] x86: Add mrccache support for a 'variable' cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for a second cache type, for Apollo Lake. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Move the mrccache_get_region() change into this patch Changes in v2: None arch/x86/include/asm/mrccache.h | 1 + arch/x86/lib/mrccache.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index b81e2b2fb6..0917cf2470 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -30,6 +30,7 @@ struct mrc_region { /* Types of MRC data */ enum mrc_type_t { MRC_TYPE_NORMAL, + MRC_TYPE_VAR, MRC_TYPE_COUNT, }; diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 1278737ce4..10949d249e 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -241,7 +241,8 @@ int mrccache_get_region(enum mrc_type_t type, struct udevice **devp, } /* Find the place where we put the MRC cache */ - mrc_node = dev_read_subnode(dev, "rw-mrc-cache"); + mrc_node = dev_read_subnode(dev, type == MRC_TYPE_NORMAL ? + "rw-mrc-cache" : "rw-var-mrc-cache"); if (!ofnode_valid(mrc_node)) return log_msg_ret("Cannot find node", -EPERM); From patchwork Fri Nov 22 04:18:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199269 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="kV2PNzri"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K44n2L5Zz9s7T for ; Fri, 22 Nov 2019 16:00:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 121ABC2214A; Fri, 22 Nov 2019 04:29:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5038C22038; Fri, 22 Nov 2019 04:21:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AEE32C22051; Fri, 22 Nov 2019 04:21:04 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 6EF93C2203F for ; Fri, 22 Nov 2019 04:20:54 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id a7so5581375ild.6 for ; Thu, 21 Nov 2019 20:20:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X2hl/w0vDCGXU3sbTip+wPW48/nKPlgdCxNnkTYykdQ=; b=kV2PNzriytWqDYfbhOcqbA31DgWnc1w4UM3h1Xql+PWjOWrUT+LMwb/+KtO9wouPEZ BrF1mJjiqdqroFaYVTLsCngrim8ysrwzHDfQzc49qa5fEXStMc86wILuBuBAaL3VDuDi BCP3HyMWP4ooc6MnwGiiPl6ileINVWHSJevbY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X2hl/w0vDCGXU3sbTip+wPW48/nKPlgdCxNnkTYykdQ=; b=S7Nczclnn9f6F6HZtoqBMuIRqq9EyUGcFKEBK15XMu7vz9hSG5Q3kE5udo1QFSoQHK qv462j/5MWAK1yCzaxUVWooafNhDQ9b1XsuX7v0tiqXGMMpd5vPA4avorxa9NSZrVRrP PL5paXvW+TcysQmcz8BRm1EyI575iDlTdXgWlHcPKKOfa9z/YgX7DFkL23xmb2m89fpL px4FW9aVbYC9mbwDtIARGIsttGeE36kCTC+9B8SC/2+nQ+wpFdyKB3N7HcBGMQ/vMiGN +/7JU1dm+fFu1R8w5wAE1BfQYCAn/IQY/paUkxQUji8+ae5g0bZ46HfclB+EX6EjDxqp 8l0Q== X-Gm-Message-State: APjAAAWNkAi6Qhbsdu2TSqzskBPl733sxc699Av8vu1kE4eS6hcttUmL 4RhjsBhQjfIoN0qndpfyJYvduZyILeA= X-Google-Smtp-Source: APXvYqzI/KCYLJEojMh9hSh68hu7Sdd/D5gNpWz+Q9qE4IYIzGUZ3b6aSdIDLuOAZviG+Ga96kMlxg== X-Received: by 2002:a05:6e02:cc3:: with SMTP id c3mr1661261ilj.141.1574396451877; Thu, 21 Nov 2019 20:20:51 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:01 -0700 Message-Id: <20191121211845.v4.36.I12b19a0093a729c728c3f0fc7d0e8ef7bb42392c@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 036/100] x86: Don't export mrccache_update() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This function is only used within the implementation so make it static. Signed-off-by: Simon Glass --- Changes in v4: - Add new patch to make mrccache_update() static Changes in v3: None Changes in v2: None arch/x86/include/asm/mrccache.h | 15 --------------- arch/x86/lib/mrccache.c | 16 ++++++++++++++-- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 0917cf2470..d6b7529073 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -48,21 +48,6 @@ struct udevice; */ struct mrc_data_container *mrccache_find_current(struct mrc_region *entry); -/** - * mrccache_update() - update the MRC cache with a new record - * - * This writes a new record to the end of the MRC cache region. If the new - * record is the same as the latest record then the write is skipped - * - * @sf: SPI flash to write to - * @entry: Position and size of MRC cache in SPI flash - * @cur: Record to write - * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, -EINVAL if the record is not valid, other error if SPI write failed - */ -int mrccache_update(struct udevice *sf, struct mrc_region *entry, - struct mrc_data_container *cur); - /** * mrccache_reserve() - reserve MRC data on the stack * diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 10949d249e..b9420a4cab 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -118,8 +118,20 @@ static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry, return cache; } -int mrccache_update(struct udevice *sf, struct mrc_region *entry, - struct mrc_data_container *cur) +/** + * mrccache_update() - update the MRC cache with a new record + * + * This writes a new record to the end of the MRC cache region. If the new + * record is the same as the latest record then the write is skipped + * + * @sf: SPI flash to write to + * @entry: Position and size of MRC cache in SPI flash + * @cur: Record to write + * @return 0 if updated, -EEXIST if the record is the same as the latest + * record, -EINVAL if the record is not valid, other error if SPI write failed + */ +static int mrccache_update(struct udevice *sf, struct mrc_region *entry, + struct mrc_data_container *cur) { struct mrc_data_container *cache; ulong offset; From patchwork Fri Nov 22 04:18:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199221 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ZKzjO5+R"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3WC1DLgz9sPc for ; Fri, 22 Nov 2019 15:35:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C2550C220AE; Fri, 22 Nov 2019 04:31:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 90CEAC2203A; Fri, 22 Nov 2019 04:22:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A137EC2203A; Fri, 22 Nov 2019 04:21:04 +0000 (UTC) Received: from mail-il1-f196.google.com (mail-il1-f196.google.com [209.85.166.196]) by lists.denx.de (Postfix) with ESMTPS id 375BDC22077 for ; Fri, 22 Nov 2019 04:20:55 +0000 (UTC) Received: by mail-il1-f196.google.com with SMTP id i6so5559763ilr.11 for ; Thu, 21 Nov 2019 20:20:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bhEJJx2zA69nav4SM7sZox2a+6rUyysQXqiiKsrh+YM=; b=ZKzjO5+RoeSBLs9uPLWFStq6/k0DnciL5148EJVjzinDmRwiVFsqqeP82iHbaMB3aN HTTiKjTHzV8BYxLmUCRDDqKcPhT6X+dbB71YEcuKjcuK9YbyICcSOqYIzBQsrK550HqE 1gEM3aU+xTPyr280m1gKRl1U3sWTVYF25Vaxw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bhEJJx2zA69nav4SM7sZox2a+6rUyysQXqiiKsrh+YM=; b=NQrdtaRXLcBT0KOx7J7ZYNjkkxrklKNht+LHmMNBobw0eo+cpMMoLAdB9TYn4MDTFU 19dJ++qgEKWSHxdtLZiWpUFNGUeinPUfSEsbAJhX1nybOxWH0mhJd+cyXJTalBrDWzQf ZXYVd6bdphqkIR6ELTaAEfC4Eu1L5jLFxHCAr5YaVxlFANmN2aLG6Aye02tfRJdWztCP U2O8k5D2bDK70pE3ErrHQNC4dgmtPRs2gUQy47Dwso9z6kV1JsuLIm/QNnrSQn/XeRVw MctkLbW+9TXIoJIlq3uKwicLYgGHlFNnx7AYQG3jUCL0OOIfE82O6fXzB3jPBrRoyPMz sVQQ== X-Gm-Message-State: APjAAAW/oCUznH1SDiDjEWzVLIg0Z4rj2JlNQlsJNVZ8HHLY/2CvCwoP YfZ2H+TvFNF/hC7y1iMS4ThhJQ0Zhk4= X-Google-Smtp-Source: APXvYqyidQ9XlfBuXoTNR/xUyFAfCRIw6Mml3eH2cL1v3dXjKrfgjKYYW2Gc/m30Yy30QnSMz033xA== X-Received: by 2002:a92:d645:: with SMTP id x5mr13687106ilp.219.1574396454063; Thu, 21 Nov 2019 20:20:54 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:53 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:02 -0700 Message-Id: <20191122041905.224686-28-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 037/100] x86: Move fsp_prepare_mrc_cache() to fsp1 directory X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This function needs to be different for FSP2, so move the existing function into the fsp1 directory. Since it is only called from one file, drop it from the header file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/include/asm/fsp/fsp_support.h | 7 ------- arch/x86/lib/fsp/fsp_common.c | 20 -------------------- arch/x86/lib/fsp1/fsp_common.c | 20 ++++++++++++++++++++ 3 files changed, 20 insertions(+), 27 deletions(-) diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 4ac27d26f5..29e511415c 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -143,13 +143,6 @@ int fsp_init_phase_pci(void); */ int fsp_scan_for_ram_size(void); -/** - * fsp_prepare_mrc_cache() - Find the DRAM training data from the MRC cache - * - * @return pointer to data, or NULL if no cache or no data found in the cache - */ -void *fsp_prepare_mrc_cache(void); - /** * fsp_notify() - FSP notification wrapper function * diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index c1c30ce0eb..6b7a614e92 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -57,26 +57,6 @@ void board_final_cleanup(void) debug("OK\n"); } -void *fsp_prepare_mrc_cache(void) -{ - struct mrc_data_container *cache; - struct mrc_region entry; - int ret; - - ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); - if (ret) - return NULL; - - cache = mrccache_find_current(&entry); - if (!cache) - return NULL; - - debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, - cache->data, cache->data_size, cache->checksum); - - return cache->data; -} - #ifdef CONFIG_HAVE_ACPI_RESUME int fsp_save_s3_stack(void) { diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index e8066d8de3..ec9c218778 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -18,6 +18,26 @@ DECLARE_GLOBAL_DATA_PTR; +static void *fsp_prepare_mrc_cache(void) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); + if (ret) + return NULL; + + cache = mrccache_find_current(&entry); + if (!cache) + return NULL; + + debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, + cache->data, cache->data_size, cache->checksum); + + return cache->data; +} + int arch_fsp_init(void) { void *nvs; From patchwork Fri Nov 22 04:18:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199252 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="MDb4MUwr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3t84Y9Cz9sPJ for ; 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Thu, 21 Nov 2019 20:20:56 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:03 -0700 Message-Id: <20191122041905.224686-29-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 038/100] x86: Set the DRAM banks to reflect real location X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present with fsp a single DRAM bank is added which extends to the whole size of memory. However there is typically only 2GB of memory available below the 4GB boundary, and this is what is used by U-Boot while running in 32-bit mode. Scan the tables to set the banks correct. The first bank is set to memory below 4GB, and the rest of memory is put into subsequent banks. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Move mtrr_add_request() call to next patch Changes in v2: None arch/x86/lib/fsp/fsp_dram.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 2d1023068f..3ede9b73fe 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -37,8 +37,36 @@ int fsp_scan_for_ram_size(void) int dram_init_banksize(void) { + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t low_end; + uint bank; + + low_end = 0; + for (bank = 1, hdr = gd->arch.hob_list; + bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); + hdr = get_next_hob(hdr)) { + if (hdr->type != HOB_TYPE_RES_DESC) + continue; + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type != RES_SYS_MEM && + res_desc->type != RES_MEM_RESERVED) + continue; + if (res_desc->phys_start < (1ULL << 32)) { + low_end = max(low_end, + res_desc->phys_start + res_desc->len); + continue; + } + + gd->bd->bi_dram[bank].start = res_desc->phys_start; + gd->bd->bi_dram[bank].size = res_desc->len; + log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, + gd->bd->bi_dram[bank].size); + } + + /* Add the memory below 4GB */ gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[0].size = low_end; return 0; } From patchwork Fri Nov 22 04:18:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199216 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:20:58 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:20:57 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:04 -0700 Message-Id: <20191122041905.224686-30-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 039/100] x86: Set up the MTRR for SDRAM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set up MTRRs for the FST SDRAM regions to improve performance. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Move mtrr_add_request() call into this patch Changes in v2: None arch/x86/lib/fsp/fsp_dram.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 3ede9b73fe..9ca898a0cd 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -8,6 +8,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -60,6 +61,8 @@ int dram_init_banksize(void) gd->bd->bi_dram[bank].start = res_desc->phys_start; gd->bd->bi_dram[bank].size = res_desc->len; + mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, + res_desc->len); log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, gd->bd->bi_dram[bank].size); } @@ -68,6 +71,8 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = low_end; + mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end); + return 0; } From patchwork Fri Nov 22 04:18:05 2019 Content-Type: text/plain; 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Also, SPI flash is seldom needed in TPL. Drop these options. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Don't imply SPI flash either - Rewrite commit message Changes in v2: None arch/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 6865e1f909..54de91afb3 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -204,14 +204,11 @@ config X86 imply SPL_SYSCON # TPL imply TPL_DM - imply TPL_OF_LIBFDT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_GPIO_SUPPORT imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SERIAL_SUPPORT - imply TPL_SPI_FLASH_SUPPORT - imply TPL_SPI_SUPPORT imply TPL_OF_CONTROL imply TPL_TIMER imply TPL_REGMAP From patchwork Fri Nov 22 04:18:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199230 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="I5o2jbzS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3cc1w8dz9sNx for ; Fri, 22 Nov 2019 15:39:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DAC76C22035; Fri, 22 Nov 2019 04:29:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B5098C21FF7; Fri, 22 Nov 2019 04:22:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E0E9FC2209D; Fri, 22 Nov 2019 04:21:06 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 41279C2204D for ; Fri, 22 Nov 2019 04:21:03 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id u17so5602036ilq.5 for ; Thu, 21 Nov 2019 20:21:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZvqJyFt9qvbmXwcwngSIyPMzfa3C8X/cb2yXnMRZN8=; b=I5o2jbzSkV+ZOEiWzbNCFqaeaGf9wlRNAYI1naAMGW18pN9w19CeWn4MIznsZU+o1H iyoaoLrKUUKZ9YjQQ3qiwCpoI5ne1oKiFV4g6TpxJOFo0f5kFMRE9RAnKD5Rmv598u2W NVSWvwmVeAqUSWiPRlEW/CQYjBIOdYEtCTrkQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZvqJyFt9qvbmXwcwngSIyPMzfa3C8X/cb2yXnMRZN8=; b=Pg0iPOPAInv7gCWH+lt1WYy7V9PsRidN+EvGJ96OWAaXgaSal7wOfP7o41vPWOdAK/ tjLUl/SVPTWozApNooXCU8Lsf7Th4O6frwoDzCbjX/NKT9IwrldVzDfZDr8HYOfCFaty kmVQmOC51M+DfsqleHDzuB5/s62fL8IxIAhIHt7zW1wcXedEEocX6SOCNOb7McCecl/D aMIn6HX4zbKT6Gw+807AZ46f0KdhJEP9tYRGrymJi2bKxid+Gdm2TfEqGe9jpAp0ilCu UAw9p2TGhmNU8dy+2T+cWhrRBqjKISbg6OQFICaP52tEH8T3SXVDvEUOglBEMwRG5Kje Al5w== X-Gm-Message-State: APjAAAVOj5BUUFVi98T+AfEUZJsfTUYumRQ2E/cpFDWD6HLmKqWLoOd7 V5svRumBoqA4g3nBeO9fVGwKnqyWLfs= X-Google-Smtp-Source: APXvYqytouVCTth/v8vbIhrKmhZrOWEezteBb8R+xVgFVEskMwpYl9yezzAPmNliFohu25DfgQWNOA== X-Received: by 2002:a92:dd12:: with SMTP id n18mr14862389ilm.9.1574396462068; Thu, 21 Nov 2019 20:21:02 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:01 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:06 -0700 Message-Id: <20191122041905.224686-32-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 041/100] x86: Allow removal of standard PCH drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These drivers are not needed on all platforms. While they are small, it is useful in TPL to drop then. Add Kconfig control to allow this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: - Change 'queensbay' to 'baytrail' in help - Fix 'proides' typo drivers/pch/Kconfig | 18 ++++++++++++++++++ drivers/pch/Makefile | 4 ++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig index 18f006de24..c49a92885a 100644 --- a/drivers/pch/Kconfig +++ b/drivers/pch/Kconfig @@ -7,3 +7,21 @@ config PCH northbridge / southbridge architecture that was previously used. The PCH allows for higher performance since the memory functions are handled in the CPU. + +config X86_PCH7 + bool "Add support for Intel PCH7" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This + dates from about 2011 and is used on baytrail, for example. The + PCH provides access to the GPIO and SPI base addresses, among other + functions. + +config X86_PCH9 + bool "Add support for Intel PCH9" + default y if X86 + help + Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This + dates from about 2015 and is used on baytrail, for example. The + PCH provides access to the GPIO and SPI base addresses, among other + functions. diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index 8ea6b7852a..d5de3e48be 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pch-uclass.o -obj-y += pch7.o -obj-y += pch9.o +obj-$(CONFIG_X86_PCH7) += pch7.o +obj-$(CONFIG_X86_PCH9) += pch9.o obj-$(CONFIG_SANDBOX) += sandbox_pch.o From patchwork Fri Nov 22 04:18:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199218 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="k+k3kEyS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Tm4tslz9sNx for ; Fri, 22 Nov 2019 15:33:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 431C4C220A3; Fri, 22 Nov 2019 04:30:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 612A2C220A6; Fri, 22 Nov 2019 04:22:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 96F8DC22016; Fri, 22 Nov 2019 04:21:08 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 69B28C22038 for ; Fri, 22 Nov 2019 04:21:05 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id r9so5569375ilq.10 for ; Thu, 21 Nov 2019 20:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3+9E9jjwK8ioVfcQOVEXkdvIIw2kz8KdR+gdSEZ5EWg=; b=k+k3kEyS5vMuCs3l0uthFLC0jIVrvscoWlee34t/Sy/WxFX+UMRnRnUMK2gzzrNI2W TdxtuU06CPamCxOwDEymTqpQkousL1CVemEd57VxrVHPc+qmIYWGrDB+IOKXXTOVqgaA A46W90OPnG16UC7k1JFFTuvWdovFCQUvLjuug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3+9E9jjwK8ioVfcQOVEXkdvIIw2kz8KdR+gdSEZ5EWg=; b=brd+HQKHvokzme303RG40+f7NhGr5E5Q9UG3WIoVLXNoJV2/nJg06afLSME6RAGF+Y JOp/jwzWxfrKxxCDoFtVT+WA94RoMkPk1s5ahJ/TjCMM/6KS7pEQpTPNJwRJdWfINmWC SsDbOO+SRm+nB+duN1hpHbhLCrfA2JoEy48PGRKiOYApdN/bXbrB0nZCa65TT+tgbGOX G8IBF/H/39R4SWNtiJtt7YbaWx1TDeadAXKCh//NY4li4l0xFYPMNEVqG3N0xheE47HI ZgaeGoHVIDHOBDwjYEaOijuwnqGyr+1y6l7OLpkzSdcdWz7b8GVIBNcPDtJSnRJSTEns vEEg== X-Gm-Message-State: APjAAAV+0DugrOsX49d5y15gBxDalK4Cvs1mHtWuvUKhj0rVI34dczkN YYtTAsTCBB/ew7Audt+e2aBBDKUjMrM= X-Google-Smtp-Source: APXvYqxEwfUPcGvM5MGsQfB8dwEREmJfbL5bzOGwTelkDRI5UzRjs5TDuPI0Ez6a88VzrjpUzWV1yg== X-Received: by 2002:a92:7e18:: with SMTP id z24mr14001964ilc.276.1574396464101; Thu, 21 Nov 2019 20:21:04 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:03 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:07 -0700 Message-Id: <20191122041905.224686-33-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 042/100] x86: Allow interrupt to happen once X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the interrupt table is included in all phases of U-Boot. Allow it to be omitted, e.g. in TPL, to reduce size. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: - Move write_pirq_routing_table() to avoid 64-bit build error Changes in v2: None arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/irq.c | 8 -------- arch/x86/lib/pirq_routing.c | 10 ++++++++++ 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 6296b55ff8..b6a010ea32 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -53,7 +53,7 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-y += irq.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index cb183496b7..ed9938f7f7 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -350,14 +350,6 @@ int irq_router_probe(struct udevice *dev) return 0; } -ulong write_pirq_routing_table(ulong addr) -{ - if (!gd->arch.pirq_routing_table) - return addr; - - return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); -} - static const struct udevice_id irq_router_ids[] = { { .compatible = "intel,irq-router" }, { } diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index e5f0e61424..17bd2fcb9b 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, bool irq_already_routed[]) { @@ -131,3 +133,11 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) return addr + rt->size; } + +ulong write_pirq_routing_table(ulong addr) +{ + if (!gd->arch.pirq_routing_table) + return addr; + + return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); +} From patchwork Fri Nov 22 04:18:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199248 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/lib/fsp/Makefile | 3 +++ arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c | 2 +- arch/x86/lib/fsp1/Makefile | 1 - 3 files changed, 4 insertions(+), 2 deletions(-) rename arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c (98%) diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 9e34856473..da6c0a886a 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,4 +4,7 @@ obj-y += fsp_common.o obj-y += fsp_dram.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o +endif obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp1/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c similarity index 98% rename from arch/x86/lib/fsp1/fsp_graphics.c rename to arch/x86/lib/fsp/fsp_graphics.c index 52e71334f9..91d2d08557 100644 --- a/arch/x86/lib/fsp1/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/fsp1/Makefile b/arch/x86/lib/fsp1/Makefile index 870de71bd7..1cf5e54191 100644 --- a/arch/x86/lib/fsp1/Makefile +++ b/arch/x86/lib/fsp1/Makefile @@ -5,5 +5,4 @@ obj-y += fsp_car.o obj-y += fsp_common.o obj-y += fsp_dram.o -obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o obj-y += fsp_support.o From patchwork Fri Nov 22 04:18:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199281 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Thu, 21 Nov 2019 20:21:08 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:07 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:09 -0700 Message-Id: <20191122041905.224686-35-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 044/100] x86: fsp: Correct wrong header inlude in fsp_support.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This generic FSP file should include the generic FSP support header, not the FSP1 version. Fix it. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/lib/fsp/fsp_support.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 983888fd74..ee228117d1 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include u32 fsp_get_usable_lowmem_top(const void *hob_list) From patchwork Fri Nov 22 04:18:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199249 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="aLKuvA6Z"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3s22Z19z9sNx for ; Fri, 22 Nov 2019 15:50:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F0335C22035; Fri, 22 Nov 2019 04:33:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2EB67C2204E; Fri, 22 Nov 2019 04:23:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D2DDBC220D3; Fri, 22 Nov 2019 04:21:16 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 2DE1BC2207E for ; Fri, 22 Nov 2019 04:21:12 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id q15so5581821ils.8 for ; Thu, 21 Nov 2019 20:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UEYTP0IItnrUZNaUHh29s2MWXRrxjUuaVUGqR6mufxI=; b=aLKuvA6ZAkScSCg429wvgzZjQgQEBbmssiipo+veURmj35CwEZdy5MUUfJp0xx1oor QMljuSaT3W12/I45F10PFm0hBVjTFCv/i6AwwOLRUN/SiI6X7ayuLagO6x46qFzSX4IO vDcsV+5SEL3HhPThYznP08cDKqszgu2vdbVuM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UEYTP0IItnrUZNaUHh29s2MWXRrxjUuaVUGqR6mufxI=; b=brjIIF4gkYu8ae1dfQZTh37INEN65tBoVmavaXJdiIrQ7CFXPtudeAOn6Cn5hCCAA5 grMIB5Iu/vIVto4So2G5lVMth5Iori2LGHGuPYGRtxVvEWRyZPfU84BT2GlMoy3SXqSd eg9ZN75OhySXcJcIbAHlIToMq4h5Vn5IC4EHoUisp46tFbPbFe7L0UfSw4PM7+Fk2PFA y51b7vflVzVY/giMc3aqDI9fSXIsS+EiBCeuMUKo34JxmfxoTBadj3x3XIm8w7SVStCG sxTzx80gfmMuR98Bf8v+96OhiJ7tg/Xzxpmrue8GLbDENT7E3vs5J+ELX1tVsBqSbdGT 4aDw== X-Gm-Message-State: APjAAAXNv6PqcbZR7XNRSDUZ5QZVSQQqWKVjpNa40b4izZu8VaJTUMNa jX4UCGperEB7K6Xq04IUmOjjcw6kwXg= X-Google-Smtp-Source: APXvYqwm1axsxMBNs4SMpIRPE6tucTKPXg5R9dzCVohB7tZhGFrWdPjt0FoQSoCTqHbV07Sy24o80A== X-Received: by 2002:a92:bbdd:: with SMTP id x90mr256213ilk.286.1574396470295; Thu, 21 Nov 2019 20:21:10 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:09 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:10 -0700 Message-Id: <20191121211845.v4.45.I0512e7ba867ac1ce6eedd4f8239f1af9456eb796@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 045/100] x86: fsp: Add FSP2 base support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass --- Changes in v4: - Add a LOG_CATEGORY for silicon init - Drop duplicate VBT file CONFIG - Enable HAVE_VBT for FSP2 also - Explain the 'twisty headers' comment - Fix FSP_M reference to refer to FSP_S in commit message - Fix comment on fsp_silicon_init() - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Rename get_coreboot_fsp() and add comments - Switch over to use pinctrl for pad init/config - Use lower-case pinctrl in arch_cpu_init_dm() Changes in v3: - Add a proper implementation of fsp_notify - Add an fsp: tag - Add bootstage timing for memory-mapped reads - Add fsp_locate_fsp to locate an fsp component - Add fspm_done() hook - Add support for FSP-S component and VBT - Simplify types for fsp_locate_fsp() - Switch mmap to use SPI instead of SPI flash Changes in v2: None arch/x86/Kconfig | 54 ++++++- arch/x86/include/asm/fsp2/fsp_api.h | 63 ++++++++ arch/x86/include/asm/fsp2/fsp_internal.h | 97 +++++++++++++ arch/x86/lib/fsp2/Makefile | 10 ++ arch/x86/lib/fsp2/fsp_common.c | 13 ++ arch/x86/lib/fsp2/fsp_dram.c | 77 ++++++++++ arch/x86/lib/fsp2/fsp_init.c | 174 +++++++++++++++++++++++ arch/x86/lib/fsp2/fsp_meminit.c | 97 +++++++++++++ arch/x86/lib/fsp2/fsp_silicon_init.c | 54 +++++++ arch/x86/lib/fsp2/fsp_support.c | 135 ++++++++++++++++++ include/bootstage.h | 3 + 11 files changed, 774 insertions(+), 3 deletions(-) create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h create mode 100644 arch/x86/lib/fsp2/Makefile create mode 100644 arch/x86/lib/fsp2/fsp_common.c create mode 100644 arch/x86/lib/fsp2/fsp_dram.c create mode 100644 arch/x86/lib/fsp2/fsp_init.c create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c create mode 100644 arch/x86/lib/fsp2/fsp_silicon_init.c create mode 100644 arch/x86/lib/fsp2/fsp_support.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 17a6fe6d3d..6bac5d5fe8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -326,7 +326,7 @@ config X86_RAMTEST config FLASH_DESCRIPTOR_FILE string "Flash descriptor binary filename" - depends on HAVE_INTEL_ME + depends on HAVE_INTEL_ME || FSP_VERSION2 default "descriptor.bin" help The filename of the file to use as flash descriptor in the @@ -411,6 +411,54 @@ config FSP_ADDR The default base address of 0xfffc0000 indicates that the binary must be located at offset 0xc0000 from the beginning of a 1MB flash device. +if FSP_VERSION2 + +config FSP_FILE_T + string "Firmware-Support-Package binary filename (Temp RAM)" + default "fsp_t.bin" + help + The filename of the file to use for the temporary-RAM init phase from + the Firmware-Support-Package binary. Put this in the board directory. + It is used to set up an initial area of RAM which can be used for the + stack and other purposes, while bringing up the main system DRAM. + +config FSP_ADDR_T + hex "Firmware-Support-Package binary location (Temp RAM)" + default 0xffff8000 + help + FSP is not Position-Independent Code (PIC) and FSP components have to + be rebased if placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + +config FSP_FILE_M + string "Firmware-Support-Package binary filename (Memory Init)" + default "fsp_m.bin" + help + The filename of the file to use for the RAM init phase from the + Firmware Support Package binary. Put this in the board directory. + It is used to set up the main system DRAM and runs in SPL, once + temporary RAM (CAR) is working. + +config FSP_FILE_S + string "Firmware-Support-Package binary filename (Silicon Init)" + default "fsp_s.bin" + help + The filename of the file to use for the Silicon init phase from the + Firmware Support Package binary. Put this in the board directory. + It is used to set up the silicon to work correctly and must be + executed after DRAM is running. + +config IFWI_INPUT_FILE + string "Filename containing FIT (Firmware Interface Table) with IFWI" + default "fitimage.bin" + help + The IFWI is obtained by running a tool on this file to extract the + IFWI. Put this in the board directory. The IFWI contains U-Boot TPL, + microcode and other internal items. + +endif + config FSP_TEMP_RAM_ADDR hex depends on FSP_VERSION1 @@ -595,7 +643,7 @@ config VGA_BIOS_ADDR config HAVE_VBT bool "Add a Video BIOS Table (VBT) image" - depends on FSP_VERSION1 + depends on HAVE_FSP help Select this option if you have a Video BIOS Table (VBT) image that you would like to add to your ROM. This is normally required if you @@ -629,7 +677,7 @@ config VBT_ADDR config VIDEO_FSP bool "Enable FSP framebuffer driver support" - depends on HAVE_VBT && DM_VIDEO + depends on (HAVE_VBT || FSP_VERSION2) && DM_VIDEO help Turn on this option to enable a framebuffer driver when U-Boot is using Video BIOS Table (VBT) image for FSP firmware to initialize diff --git a/arch/x86/include/asm/fsp2/fsp_api.h b/arch/x86/include/asm/fsp2/fsp_api.h new file mode 100644 index 0000000000..af1e8857b9 --- /dev/null +++ b/arch/x86/include/asm/fsp2/fsp_api.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * (Written by Alexandru Gagniuc for Intel Corp.) + * Mostly taken from coreboot fsp2_0/memory_init.c + */ + +#ifndef __ASM_FSP2_API_H +#define __ASM_FSP2_API_H + +#include + +struct fspm_upd; +struct fsps_upd; +struct hob_header; + +enum fsp_boot_mode { + FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, + FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01, + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02, + FSP_BOOT_ON_S4_RESUME = 0x05, + FSP_BOOT_ON_S3_RESUME = 0x11, + FSP_BOOT_ON_FLASH_UPDATE = 0x12, + FSP_BOOT_IN_RECOVERY_MODE = 0x20 +}; + +struct __packed fsp_upd_header { + u64 signature; + u8 revision; + u8 reserved[23]; +}; + +/** + * fsp_memory_init() - Init the SDRAM + * + * @s3wake: true if we are booting from resume, so cannot reinit the mememory + * from scatch since we will lose its contents + * @use_spi_flash: true to use the fast SPI driver to read FSP, otherwise use + * mapped SPI + * @return 0 if OK, -ve on error + */ +int fsp_memory_init(bool s3wake, bool use_spi_flash); + +typedef asmlinkage int (*fsp_memory_init_func)(struct fspm_upd *params, + struct hob_header **hobp); + +/** + * fsp_silicon_init() - Init the silicon + * + * This calls the FSP's 'silicon init' entry point + * + * @s3wake: true if we are booting from resume, so cannot reinit the mememory + * from scatch since we will lose its contents + * @use_spi_flash: true to use the fast SPI driver to read FSP, otherwise use + * mapped SPI + * @return 0 if OK, -ve on error + */ +int fsp_silicon_init(bool s3wake, bool use_spi_flash); + +typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params); + +#endif diff --git a/arch/x86/include/asm/fsp2/fsp_internal.h b/arch/x86/include/asm/fsp2/fsp_internal.h new file mode 100644 index 0000000000..f751fbf961 --- /dev/null +++ b/arch/x86/include/asm/fsp2/fsp_internal.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * Mostly taken from coreboot + */ + +#ifndef __ASM_FSP_INTERNAL_H +#define __ASM_FSP_INTERNAL_H + +struct binman_entry; +struct fsp_header; +struct fspm_upd; +struct fsps_upd; + +enum fsp_type_t { + FSP_M, + FSP_S, +}; + +int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, + struct fsp_header **fspp); + +/** + * fsp_locate_fsp() - Locate an FSP component + * + * This finds an FSP component by various methods. It is not as general-purpose + * as it looks, since it expects FSP-M to be requested in SPL (only), and FSP-S + * to be requested in U-Boot proper. + * + * @type: Component to locate + * @entry: Returns location of component + * @use_spi_flash: true to read using the Fast SPI driver, false to use + * memory-mapped SPI flash + * @devp: Returns northbridge device + * @hdrp: Returns FSP header + * @rom_offsetp: If non-NULL, returns the offset to add to any image position to + * find the memory-mapped location of that position. For example, for ROM + * position 0x1000, it will be mapped into 0x1000 + *rom_offsetp. + */ +int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, + bool use_spi_flash, struct udevice **devp, + struct fsp_header **hdrp, ulong *rom_offsetp); + +/** + * arch_fsps_preinit() - Perform init needed before calling FSP-S + * + * This allows use of probed drivers and PCI so is a convenient place to do any + * init that is needed before FSP-S is called. After this, U-Boot relocates and + * calls arch_fsp_init_r() before PCI is probed, and that function is not + * allowed to probe PCI before calling FSP-S. + */ +int arch_fsps_preinit(void); + +/** + * fspm_update_config() - Set up the config structure for FSP-M + * + * @dev: Hostbridge device containing config + * @upd: Config data to fill in + * @return 0 if OK, -ve on error + */ +int fspm_update_config(struct udevice *dev, struct fspm_upd *upd); + +/** + * fspm_done() - Indicate that memory init is complete + * + * This allows the board to do whatever post-init it needs before things + * continue. + * + * @dev: Hostbridge device + * @return 0 if OK, -ve on error + */ +int fspm_done(struct udevice *dev); + +/** + * fsps_update_config() - Set up the config structure for FSP-S + * + * @dev: Hostbridge device containing config + * @rom_offset: Value to add to convert from ROM offset to memory-mapped address + * @upd: Config data to fill in + * @return 0 if OK, -ve on error + */ +int fsps_update_config(struct udevice *dev, ulong rom_offset, + struct fsps_upd *upd); + +/** + * prepare_mrc_cache() - Read the MRC cache into the product-data struct + * + * This looks for cached Memory-reference code (MRC) data and stores it into + * @upd for use by the FSP-M binary. + * + * @return 0 if OK, -ENOENT if no data (whereupon the caller can continue and + * expect a slower boot), other -ve value on other error + */ +int prepare_mrc_cache(struct fspm_upd *upd); + +#endif diff --git a/arch/x86/lib/fsp2/Makefile b/arch/x86/lib/fsp2/Makefile new file mode 100644 index 0000000000..ddbe2d0db2 --- /dev/null +++ b/arch/x86/lib/fsp2/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += fsp_common.o +obj-y += fsp_dram.o +obj-y += fsp_init.o +obj-y += fsp_meminit.o +obj-y += fsp_silicon_init.o +obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c new file mode 100644 index 0000000000..f69456e43a --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include + +int arch_fsp_init(void) +{ + return 0; +} diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c new file mode 100644 index 0000000000..7d1b150ef0 --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int dram_init(void) +{ + int ret; + + if (spl_phase() == PHASE_SPL) { +#ifdef CONFIG_HAVE_ACPI_RESUME + bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; +#else + bool s3wake = false; +#endif + + ret = fsp_memory_init(s3wake, BOOT_FROM_FAST_SPI_FLASH); + if (ret) { + debug("Memory init failed (err=%x)\n", ret); + return ret; + } + + /* The FSP has already set up DRAM, so grab the info we need */ + ret = fsp_scan_for_ram_size(); + if (ret) + return ret; + +#ifdef CONFIG_ENABLE_MRC_CACHE + gd->arch.mrc[MRC_TYPE_NORMAL].buf = + fsp_get_nvs_data(gd->arch.hob_list, + &gd->arch.mrc[MRC_TYPE_NORMAL].len); + gd->arch.mrc[MRC_TYPE_VAR].buf = + fsp_get_var_nvs_data(gd->arch.hob_list, + &gd->arch.mrc[MRC_TYPE_VAR].len); + log_debug("normal %x, var %x\n", + gd->arch.mrc[MRC_TYPE_NORMAL].len, + gd->arch.mrc[MRC_TYPE_VAR].len); +#endif + } else { +#if CONFIG_IS_ENABLED(HANDOFF) + struct spl_handoff *ho = gd->spl_handoff; + + if (!ho) { + debug("No SPL handoff found\n"); + return -ESTRPIPE; + } + gd->ram_size = ho->ram_size; + handoff_load_dram_banks(ho); +#endif + ret = arch_fsps_preinit(); + if (ret) + return log_msg_ret("fsp_s_preinit", ret); + } + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#if CONFIG_IS_ENABLED(HANDOFF) + struct spl_handoff *ho = gd->spl_handoff; + + return ho->arch.usable_ram_top; +#endif + + return gd->ram_top; +} diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c new file mode 100644 index 0000000000..bcc385e876 --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + ofnode node; + int ret; + + /* Make sure pads are set up early in U-Boot */ + if (spl_phase() != PHASE_BOARD_F) + return 0; + + /* Probe all pinctrl devices to set up the pads */ + ret = uclass_first_device_err(UCLASS_PINCTRL, &dev); + if (ret) + return log_msg_ret("no fsp pinctrl", ret); + node = ofnode_path("fsp"); + if (!ofnode_valid(node)) + return log_msg_ret("no fsp params", -EINVAL); + ret = pinctrl_config_pads_for_node(dev, node); + if (ret) + return log_msg_ret("pad config", ret); + + return ret; +} + +#if !defined(CONFIG_TPL_BUILD) +binman_sym_declare(ulong, intel_fsp_m, image_pos); +binman_sym_declare(ulong, intel_fsp_m, size); + +/** + * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS + * + * This looks up an FSP in a CBFS. It is used mostly for testing, when booting + * U-Boot from a hybrid image containing coreboot as the first-stage bootloader. + * + * @type; Type to look up (only FSP_M supported at present) + * @map_base: Base memory address for mapped SPI + * @entry: Returns an entry containing the position of the FSP image + */ +static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base, + struct binman_entry *entry) +{ + /* + * Use a hard-coded position of CBFS in the ROM for now. It would be + * possible to read the position using the FMAP in the ROM, but since + * this code is only used for development, it doesn't seem worth it. + * Use the 'cbfstool layout' command to get these values, e.g.: + * 'COREBOOT' (CBFS, size 1814528, offset 2117632) + */ + ulong cbfs_base = 0x205000; + ulong cbfs_size = 0x1bb000; + struct cbfs_priv *cbfs; + int ret; + + ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs); + if (ret) + return ret; + if (!ret) { + const struct cbfs_cachenode *node; + + node = cbfs_find_file(cbfs, "fspm.bin"); + if (!node) + return log_msg_ret("fspm node", -ENOENT); + + entry->image_pos = (ulong)node->data; + entry->size = node->data_length; + } + + return 0; +} + +int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, + bool use_spi_flash, struct udevice **devp, + struct fsp_header **hdrp, ulong *rom_offsetp) +{ + ulong mask = CONFIG_ROM_SIZE - 1; + struct udevice *dev; + ulong rom_offset = 0; + uint map_size; + ulong map_base; + uint offset; + int ret; + + /* + * Find the devices but don't probe them, since we don't want to + * auto-config PCI before silicon init runs + */ + ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return log_msg_ret("Cannot get northbridge", ret); + if (!use_spi_flash) { + struct udevice *sf; + + /* Just use the SPI driver to get the memory map */ + ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf); + if (ret) + return log_msg_ret("Cannot get SPI flash", ret); + ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset); + if (ret) + return log_msg_ret("Could not get flash mmap", ret); + } + + if (spl_phase() >= PHASE_BOARD_F) { + if (type != FSP_S) + return -EPROTONOSUPPORT; + ret = binman_entry_find("intel-fsp-s", entry); + if (ret) + return log_msg_ret("binman entry", ret); + if (!use_spi_flash) + rom_offset = (map_base & mask) - CONFIG_ROM_SIZE; + } else { + ret = -ENOENT; + if (false) + /* Support using a hybrid image build by coreboot */ + ret = get_cbfs_fsp(type, map_base, entry); + if (ret) { + ulong mask = CONFIG_ROM_SIZE - 1; + + if (type != FSP_M) + return -EPROTONOSUPPORT; + entry->image_pos = binman_sym(ulong, intel_fsp_m, + image_pos); + entry->size = binman_sym(ulong, intel_fsp_m, size); + if (entry->image_pos != BINMAN_SYM_MISSING) { + ret = 0; + if (use_spi_flash) + entry->image_pos &= mask; + else + entry->image_pos += (map_base & mask); + } else { + ret = -ENOENT; + } + } + } + if (ret) + return log_msg_ret("Cannot find FSP", ret); + entry->image_pos += rom_offset; + + /* + * Account for the time taken to read memory-mapped SPI flash since in + * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI. + */ + if (!use_spi_flash) + bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); + ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash, + hdrp); + if (!use_spi_flash) + bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); + if (ret) + return log_msg_ret("fsp_get_header", ret); + *devp = dev; + if (rom_offsetp) + *rom_offsetp = rom_offset; + + return 0; +} +#endif diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c new file mode 100644 index 0000000000..bf30c47989 --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * (Written by Alexandru Gagniuc for Intel Corp.) + * Mostly taken from coreboot fsp2_0/memory_init.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int prepare_mrc_cache_type(enum mrc_type_t type, + struct mrc_data_container **cachep) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(type, NULL, &entry); + if (ret) + return ret; + cache = mrccache_find_current(&entry); + if (!cache) + return -ENOENT; + + log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size); + *cachep = cache; + + return 0; +} + +int prepare_mrc_cache(struct fspm_upd *upd) +{ + struct mrc_data_container *cache; + int ret; + + ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache); + if (ret) + return log_msg_ret("Cannot get normal cache", ret); + upd->arch.nvs_buffer_ptr = cache->data; + + ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache); + if (ret) + return log_msg_ret("Cannot get var cache", ret); + upd->config.variable_nvs_buffer_ptr = cache->data; + + return 0; +} + +int fsp_memory_init(bool s3wake, bool use_spi_flash) +{ + struct fspm_upd upd, *fsp_upd; + fsp_memory_init_func func; + struct binman_entry entry; + struct fsp_header *hdr; + struct hob_header *hob; + struct udevice *dev; + int ret; + + ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL); + if (ret) + return log_msg_ret("locate FSP", ret); + debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size); + + /* Copy over the default config */ + fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off); + if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE) + return log_msg_ret("Bad UPD signature", -EPERM); + memcpy(&upd, fsp_upd, sizeof(upd)); + + ret = fspm_update_config(dev, &upd); + if (ret) + return log_msg_ret("Could not setup config", ret); + + debug("SDRAM init..."); + bootstage_start(BOOTSTATE_ID_ACCUM_FSP_M, "fsp-m"); + func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); + ret = func(&upd, &hob); + bootstage_accum(BOOTSTATE_ID_ACCUM_FSP_M); + if (ret) + return log_msg_ret("SDRAM init fail\n", ret); + + gd->arch.hob_list = hob; + debug("done\n"); + + ret = fspm_done(dev); + if (ret) + return log_msg_ret("fsm_done\n", ret); + + return 0; +} diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c new file mode 100644 index 0000000000..d7ce43e1eb --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * + * Mostly taken from coreboot fsp2_0/silicon_init.c + */ + +#define LOG_CATEGORY UCLASS_NORTHBRIDGE + +#include +#include +#include +#include +#include +#include +#include + +int fsp_silicon_init(bool s3wake, bool use_spi_flash) +{ + struct fsps_upd upd, *fsp_upd; + fsp_silicon_init_func func; + struct fsp_header *hdr; + struct binman_entry entry; + struct udevice *dev; + ulong rom_offset = 0; + int ret; + + ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr, + &rom_offset); + if (ret) + return log_msg_ret("locate FSP", ret); + gd->arch.fsp_s_hdr = hdr; + + /* Copy over the default config */ + fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off); + if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE) + return log_msg_ret("Bad UPD signature", -EPERM); + memcpy(&upd, fsp_upd, sizeof(upd)); + + ret = fsps_update_config(dev, rom_offset, &upd); + if (ret) + return log_msg_ret("Could not setup config", ret); + log_debug("Silicon init..."); + bootstage_start(BOOTSTATE_ID_ACCUM_FSP_S, "fsp-s"); + func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init); + ret = func(&upd); + bootstage_accum(BOOTSTATE_ID_ACCUM_FSP_S); + if (ret) + return log_msg_ret("Silicon init fail\n", ret); + log_debug("done\n"); + + return 0; +} diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c new file mode 100644 index 0000000000..ba8316aa1a --- /dev/null +++ b/arch/x86/lib/fsp2/fsp_support.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +/* The amount of the FSP header to probe to obtain what we need */ +#define PROBE_BUF_SIZE 0x180 + +/* Not needed in SPL apparently */ +#define SAFETY_MARGIN 0 + +int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, + struct fsp_header **fspp) +{ + static efi_guid_t guid = FSP_HEADER_GUID; + struct fv_ext_header *exhdr; + struct fsp_header *fsp; + struct ffs_file_header *file_hdr; + struct fv_header *fv; + struct raw_section *raw; + void *ptr, *base; + u8 buf[PROBE_BUF_SIZE]; + struct udevice *dev; + int ret; + + /* + * There are quite a very steps to work through all the headers in this + * file and the structs have similar names. Turn on debugging if needed + * to understand what is going wrong. + * + * You are in a maze of twisty little headers all alike. + */ + debug("offset=%x buf=%x\n", (uint)offset, (uint)buf); + if (use_spi_flash) { + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("Cannot find flash device", ret); + ret = spi_flash_read_dm(dev, offset, PROBE_BUF_SIZE, buf); + if (ret) + return log_msg_ret("Cannot read flash", ret); + } else { + memcpy(buf, (void *)offset, PROBE_BUF_SIZE); + } + + /* Initalise the FSP base */ + ptr = buf; + fv = ptr; + + /* Check the FV signature, _FVH */ + debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign); + if (fv->sign != EFI_FVH_SIGNATURE) + return log_msg_ret("Base FV signature", -EINVAL); + + /* Go to the end of the FV header and align the address */ + debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off); + ptr += fv->ext_hdr_off; + exhdr = ptr; + ptr += ALIGN(exhdr->ext_hdr_size, 8); + debug("ptr=%x\n", ptr - (void *)buf); + + /* Check the FFS GUID */ + file_hdr = ptr; + if (memcmp(&file_hdr->name, &guid, sizeof(guid))) + return log_msg_ret("Base FFS GUID", -ENXIO); + /* Add the FFS header size to find the raw section header */ + ptr = file_hdr + 1; + + raw = ptr; + debug("raw->type = %x\n", raw->type); + if (raw->type != EFI_SECTION_RAW) + return log_msg_ret("Section type not RAW", -ENOEXEC); + + /* Add the raw section header size to find the FSP header */ + ptr = raw + 1; + fsp = ptr; + + /* Check the FSPH header */ + debug("fsp %x\n", (uint)fsp); + if (fsp->sign != EFI_FSPH_SIGNATURE) + return log_msg_ret("Base FSPH signature", -EACCES); + + base = (void *)fsp->img_base; + debug("Image base %x\n", (uint)base); + debug("Image addr %x\n", (uint)fsp->fsp_mem_init); + if (use_spi_flash) { + ret = spi_flash_read_dm(dev, offset, size + SAFETY_MARGIN, + base); + if (ret) + return log_msg_ret("Could not read FPS-M", ret); + } else { + memcpy(base, (void *)offset, size + SAFETY_MARGIN); + } + ptr = base + (ptr - (void *)buf); + *fspp = ptr; + + return 0; +} + +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) +{ + fsp_notify_f notify; + struct fsp_notify_params params; + struct fsp_notify_params *params_ptr; + u32 status; + + if (!fsp_hdr) + fsp_hdr = gd->arch.fsp_s_hdr; + + if (!fsp_hdr) + return log_msg_ret("no FSP", -ENOENT); + + notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify); + params.phase = phase; + params_ptr = ¶ms; + + /* + * Use ASM code to ensure correct parameter is on the stack for + * FspNotify as U-Boot is using different ABI from FSP + */ + asm volatile ( + "pushl %1;" /* push notify phase */ + "call *%%eax;" /* call FspNotify */ + "addl $4, %%esp;" /* clean up the stack */ + : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr) + ); + + return status; +} diff --git a/include/bootstage.h b/include/bootstage.h index d105ae0181..82f0307ef1 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -202,6 +202,9 @@ enum bootstage_id { BOOTSTATE_ID_ACCUM_DM_SPL, BOOTSTATE_ID_ACCUM_DM_F, BOOTSTATE_ID_ACCUM_DM_R, + BOOTSTATE_ID_ACCUM_FSP_M, + BOOTSTATE_ID_ACCUM_FSP_S, + BOOTSTAGE_ID_ACCUM_MMAP_SPI, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, From patchwork Fri Nov 22 04:18:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199296 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="EyHZyUR/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Mp4ZGjz9sPc for ; Fri, 22 Nov 2019 16:13:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0F338C220C7; Fri, 22 Nov 2019 04:42:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 98F7FC22047; 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bh=Q4mSuVBdJV35VpXov1bUUtrPxpE5pCP04bKMsFlcV30=; b=m2tbiynupR7OeYE6bqZ+37KFrBMCLWw6yHrRjOXKRG8enaiRFfLtWnWncAKpgkWY3i smCRBb0HXdRbJjymyWXEZO41Sq0QQO1xWPDpNhziD07kDNkZBLMKtJpqZwtXXtlgoqG3 NgrG3vWzWa6epaeJNBhz6MOf5w7sikeubr1s0uTVjp/MwiaArl4demPXoSQhN6T8rwZE YY1lOTSIAHVgQ0M40LoRMlQIfLIFrUcsT+FGS4wnf42uARJSzmy0Z9JxkjAiLMAdSMaH Y9Sxw9H5ZWP/BO1jX6JEUblqHuijbj6kbO6wBTpnc0225/WZiDn6aSoFmcVwWk64tDtO AdEg== X-Gm-Message-State: APjAAAUKHzuoScs/TJKEzJHX/cFTwev8Zwrh2xqWWdnD2wZexeRony53 OcA8hLwr+s2qbqtq478c3dezyNl1xXY= X-Google-Smtp-Source: APXvYqxVTrULVtoANMGdc5RFSpza2u7tPtY0Ornis/+NzZ0spNjf0twfX5B8Dl6sih+UjZHbSC9++A== X-Received: by 2002:a6b:f117:: with SMTP id e23mr11641398iog.286.1574396479239; Thu, 21 Nov 2019 20:21:19 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:18 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:11 -0700 Message-Id: <20191122041905.224686-36-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 046/100] x86: fsp: Set up an MTRR for the graphics frame buffer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The FSP-S may do this but at least for coral it does not. Set this up so that graphics is not deathly slow. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/lib/fsp/fsp_graphics.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 91d2d08557..226c7e66b3 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -97,6 +98,9 @@ static int fsp_video_probe(struct udevice *dev) if (ret) goto err; + mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20); + mtrr_commit(true); + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, vesa->bits_per_pixel); From patchwork Fri Nov 22 04:18:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199219 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Wk2ZFAxO"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3VB4684z9sNx for ; Fri, 22 Nov 2019 15:34:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 36B47C22089; Fri, 22 Nov 2019 04:31:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B3215C220C2; Fri, 22 Nov 2019 04:22:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9EE39C220AA; Fri, 22 Nov 2019 04:21:25 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id 88DDBC22087 for ; Fri, 22 Nov 2019 04:21:22 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id b26so4505348ion.7 for ; Thu, 21 Nov 2019 20:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tWoPBD7DWqcmwHb6gG/wIxPo24Dndp6TVR/PUsOL1zg=; b=Wk2ZFAxO2Pb7ww8Bim02323GnhhwLP6ROqcsEy4gz69ZGITDHNEp/q9bgaFVGEm0f3 UGCKw9nVi0mdPlEqGC/R3Azs+tj9a+l9G7/5wO6dPZYCz6W6EIPv8uBmEezt4TnrKe8c kudwz6Kiqbf3s8T4tByCkbRx6mpyWoliajgsE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tWoPBD7DWqcmwHb6gG/wIxPo24Dndp6TVR/PUsOL1zg=; b=AbaiXAitJAMORcgqTCE03dgx3nZdxJp3vcws4zvYFx1d6azdzxRoNkCjARqK/Cq14n Z5DAmjS4H1P3RMCw46B7HRBINun2OQDxVToiIr2LkFDx/RrjQeR72/VPmrH47+TSri3Q CIEN6u73ySEF8kHczXzzuTuhirC/HibLNMYb3yQ1Tjm/zEalXlo/3SgNExoG6vDQNx2c VweKuXk0iBOT2m/i2vnRZXiY3QldfzFw38/pUK1vZu9NLmQF7TOq+QcgFMHoYk/NQ2yr ydaY0DWYlhyOabB/C2uQ+3GZwYLu7ewxwfblhUHzhQxykkdC3FEE12CKVutxUJ5UjC1o uPNQ== X-Gm-Message-State: APjAAAX5CfiEBZ6nfYfyH+d5IdWI89aeVOHyMBVJl2HZRcgpPsoWWHsz MhQh0YkF692jX6edU0fcYUzsV6UgNZM= X-Google-Smtp-Source: APXvYqymaTTvKmM2IF7eeWMhvIQUkHFUn9CTyNd/DBLOurJcqnCLjJuFm6zHzsFzoKGVscse6jasmQ== X-Received: by 2002:a6b:bd06:: with SMTP id n6mr4164086iof.165.1574396481378; Thu, 21 Nov 2019 20:21:21 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:21 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:12 -0700 Message-Id: <20191122041905.224686-37-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 047/100] x86: fsp: Add a new arch_fsp_init_r() hook X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With FSP2 we need to run silicon init early after relocation. Add a new hook for this. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None common/board_r.c | 3 +++ include/init.h | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/common/board_r.c b/common/board_r.c index e31e9c5c16..9113ace43c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -710,6 +710,9 @@ static init_fnc_t init_sequence_r[] = { efi_memory_init, #endif initr_binman, +#ifdef CONFIG_FSP_VERSION2 + arch_fsp_init_r, +#endif initr_dm_devices, stdio_init_tables, initr_serial, diff --git a/include/init.h b/include/init.h index afc953d51e..43602029bc 100644 --- a/include/init.h +++ b/include/init.h @@ -65,6 +65,17 @@ int mach_cpu_init(void); */ int arch_fsp_init(void); +/** + * arch_fsp_init() - perform post-relocation firmware support package init + * + * Where U-Boot relies on binary blobs to handle part of the system init, this + * function can be used to set up the blobs. This is used on some Intel + * platforms. + * + * Return: 0 + */ +int arch_fsp_init_r(void); + int dram_init(void); /** From patchwork Fri Nov 22 04:18:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199299 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="H1871DXR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4NR46yXz9sPW for ; Fri, 22 Nov 2019 16:14:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3D208C2214A; Fri, 22 Nov 2019 04:42:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E414CC2208A; Fri, 22 Nov 2019 04:30:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 45C57C22034; Fri, 22 Nov 2019 04:21:27 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id A928CC2205A for ; Fri, 22 Nov 2019 04:21:24 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id v17so6360165iol.12 for ; Thu, 21 Nov 2019 20:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a+vezvUJyX4FtmngDh8RHgRcqkbbc1CePGauNS8OTjY=; b=H1871DXRPGHFDweG84F6iQs5vqLlWrihmi+8rmuaksiokpApSKmJpPVFGm+R0Ni0IU 9Vw6Xt4s7hc5IcgLW7Uxqp9YyNV/lC1OTDGjHwwnPxXSVEQWWR19zdrWA7xIYeDdnteW rKacoPBFFCczxo9LpEiUv/hniPl6i9jpOflpU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a+vezvUJyX4FtmngDh8RHgRcqkbbc1CePGauNS8OTjY=; b=iiM1SDLtGxA2lX2kZnTMfjQlvdZmW8GLFCaB1EbqfVgI4Jbe/10M6vz1oz0NofBTwW ZeiVnBmTuTkL0w05ZASBk2IMIR2EcVuO2RKA/+dTmCnkTfE5aSwNCQijs+ixwD/GebPF wzlXHKL8zSScLtogxGSvT1NL+89lw2yjLmmsnFnciu7OYqjAVcdxjaWCfz8GGjcpNGp3 kZXU5SxWrvrbpitu5rebnyBHTic5MJPNTiXgn2KPHk0QdL87+3m4Qhn2dZv5vtrmObHF frwZV5wqI8RapZZxOlOFYB1Z0oDJeiN6C6VQWYjI2lX7qxjsFg9pryUgprJFw2ICOqKs kCSw== X-Gm-Message-State: APjAAAXwSMBGRrejni4//lUiGEMUv8UDokW9482klj1pJ1AF8Kd/H+kU 2RAMZZWSvCn7yMPcDuQCy/x5jIHa4Qs= X-Google-Smtp-Source: APXvYqxOolc1UuEotqrVu9h9z9Mci/dXwFyT7tnGvdegfAblFq6UTdYPgWpct5LXrQWUjp13v2F4Pw== X-Received: by 2002:a5d:81c8:: with SMTP id t8mr10354348iol.204.1574396483503; Thu, 21 Nov 2019 20:21:23 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:23 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:13 -0700 Message-Id: <20191122041905.224686-38-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 048/100] x86: fsp: Allow remembering the location of FSP-S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" FSP-S is used by the notify call after it has been used for silicon init. To avoid having to load it again, add a field to store the location. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/include/asm/global_data.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 190b604e0f..f4c1839104 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -120,6 +120,9 @@ struct arch_global_data { int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ ulong backup_mem; /* Backup memory address for S3 */ #endif +#ifdef CONFIG_FSP_VERSION2 + struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ +#endif }; #endif From patchwork Fri Nov 22 04:18:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199245 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="jmVH7fNL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3r211Lpz9sPc for ; Fri, 22 Nov 2019 15:49:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1EEA2C22063; Fri, 22 Nov 2019 04:31:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0015BC220BA; Fri, 22 Nov 2019 04:23:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E28DDC22016; Fri, 22 Nov 2019 04:21:30 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id DCE65C22048 for ; Fri, 22 Nov 2019 04:21:26 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id s3so6439996ioe.3 for ; Thu, 21 Nov 2019 20:21:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D5ehskBhFX6RDjqRiOth8a6O9Dvk08LlZsYzMvvXXB4=; b=jmVH7fNLpaD6s/CSLL8F5XTqAQVBMN3+8MdVTZeODZpXMqK+8IGue2QUOJFsP+bp9c 2teAwo5coNz8ld2ghTSj5YXs+DOhLJnTUkZ7BZ0bj8ZaGte910dhKN+Nr9PtEHa9eKrZ OmD/MZkKQMGecDpLJDj2Lc1itv6pRUipkxzxI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D5ehskBhFX6RDjqRiOth8a6O9Dvk08LlZsYzMvvXXB4=; b=XgFrFLbPuzx6zDrRtfnzS5qJb4F6igGPawrh8lNoSKklsr/wnRSjvMwCVaHbnh62QA QgHQn74ssQMtC7GiKAsikeGvbqwW3eOs/A3fd+A6zYH+ZwDHhXnZBRQS+UPJTzEbuiWq /xMX4+J4/+C95wlHZyDrp4MKtSyHpAmOYQ4QcJ5dNrsRuy9waU+kbAmGKK23VsA+g+aE ni1MAFTKhnm/xUT5sFlyPqIRhf3a3WzKB3AbfIr1XcSEFXbcSleeLUW4olrU/a1vMd7y kZkwrQj0LmX9jqRix3OlMtK0FFo02ufeXQmaGmown0twYCrC7y+u5GkFhEL8ONpFTzNS RFtA== X-Gm-Message-State: APjAAAXo6cSuYzd8SrAWSHCRN77QIDcyO5zenqvBq35CLk09b2u3HdId eJxcLou9Pdn0OdZ+8jc/VjBJqIvNfYg= X-Google-Smtp-Source: APXvYqz/1ZjpzN6hH6W8p78/2Er2GOx65Mpjtk5gWvET7l/SILeLLmflDfPkJj/thX2jY9T1ot+rrw== X-Received: by 2002:a5e:de08:: with SMTP id e8mr11033148iok.4.1574396485600; Thu, 21 Nov 2019 20:21:25 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:25 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:14 -0700 Message-Id: <20191122041905.224686-39-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 049/100] x86: fsp: Make the notify API call common X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new common API file. Signed-off-by: Simon Glass --- Changes in v4: - Drop incorrect coreboot reference from header file Changes in v3: None Changes in v2: None arch/x86/include/asm/fsp/fsp_api.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_api.h | 21 +++------------------ 2 files changed, 27 insertions(+), 18 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_api.h diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h new file mode 100644 index 0000000000..e9ac86b2da --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_FSP_API_H +#define __ASM_FSP_API_H + +enum fsp_phase { + /* Notification code for post PCI enuermation */ + INIT_PHASE_PCI = 0x20, + /* Notification code before transferring control to the payload */ + INIT_PHASE_BOOT = 0x40 +}; + +struct fsp_notify_params { + /* Notification phase used for NotifyPhase API */ + enum fsp_phase phase; +}; + +/* FspNotify API function prototype */ +typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params); + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_api.h b/arch/x86/include/asm/fsp1/fsp_api.h index f2d70799f3..524da5feb7 100644 --- a/arch/x86/include/asm/fsp1/fsp_api.h +++ b/arch/x86/include/asm/fsp1/fsp_api.h @@ -4,11 +4,11 @@ * Copyright (C) 2014, Bin Meng */ -#ifndef __FSP_API_H__ -#define __FSP_API_H__ +#ifndef __FSP1_API_H__ +#define __FSP1_API_H__ #include - +#include /* * FSP common configuration structure. * This needs to be included in the platform-specific struct fsp_config_data. @@ -46,22 +46,7 @@ struct common_buf { u32 reserved[6]; /* Reserved */ }; -enum fsp_phase { - /* Notification code for post PCI enuermation */ - INIT_PHASE_PCI = 0x20, - /* Notification code before transfering control to the payload */ - INIT_PHASE_BOOT = 0x40 -}; - -struct fsp_notify_params { - /* Notification phase used for NotifyPhase API */ - enum fsp_phase phase; -}; - /* FspInit API function prototype */ typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params); -/* FspNotify API function prototype */ -typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params); - #endif From patchwork Fri Nov 22 04:18:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199279 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ZZEECz96"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4BP6Xq2z9s7T for ; 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Thu, 21 Nov 2019 20:21:27 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:27 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:15 -0700 Message-Id: <20191122041905.224686-40-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 050/100] x86: Don't include the BIOS emulator in TPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ca0ca1066b..5cd4587480 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -4,9 +4,11 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. ifndef CONFIG_X86_64 +ifndef CONFIG_TPL_BUILD obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o +endif obj-y += string.o endif ifndef CONFIG_SPL_BUILD From patchwork Fri Nov 22 04:18:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199236 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="gOOyX+6U"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3jJ6XSgz9sPc for ; Fri, 22 Nov 2019 15:43:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6169CC22043; Fri, 22 Nov 2019 04:38:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 79B88C220DA; Fri, 22 Nov 2019 04:24:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 98B89C220D6; Fri, 22 Nov 2019 04:21:35 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 08766C22046 for ; Fri, 22 Nov 2019 04:21:31 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id q15so5582323ils.8 for ; Thu, 21 Nov 2019 20:21:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ZsGDqZiwfEx/Uamd0Tbi/B2AErAlUsHhRmaIrsZaNQ=; b=gOOyX+6Ui7wkFXFXa1wkkYX1FZwwkag+TivK12Mbil9tWRrGFBypNZsj7IqfvFUBD9 TGEHaId7TzEBFdc98CPe1nodP5DmXkccLiako0rkPixxoLR5lIvZUwzSi24uXftgl71K M8cWJF1AaUevptrRBbiDKCohJ+VgmGt038sTo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4ZsGDqZiwfEx/Uamd0Tbi/B2AErAlUsHhRmaIrsZaNQ=; b=m/qo+0wZ5rdPvMQgIVUpffTyGI/b3bXFnpXp6QUagG29+Odi3UY58kozYDgmZUfKyd fE5z3A/mDYZdd96xKKuovpdL+kZw4LfCfweQ+BEDTRD7YlQQXddZ+vp93gAxNQIHkFKt yU0UfLsooNx7xT/SsY4T3710+RfhOPxixI22WjxXNO/3703PV9jCNMNfxnJIKMGiD8rS kDAT1V/5DWxlzHcBZJ3AIYtJsg+582NS3AcQ7KOhKLtTGgF+lRQw1AxQ5n9pvMxYLlkb wW/eqxA7ba+D+wZcFY587QvfjEOBV+MATyBcMyd2nUCVohwAtpWhW+6J318ky5m3nSg1 U8hg== X-Gm-Message-State: APjAAAWPvogAbfPVsnifddu9ht7JVpqVaVvCuWSNEtc9u2TP+E+uiZ1q xQrkRDnagslf+ZmuDl1zF0xYfObdHHY= X-Google-Smtp-Source: APXvYqw+G+OMzFuQfwq5y0blrC3rBsNm60B7//I1r2h2ziRr9d+byfQHkRu8aaf6Ru+Cum89FQqSFQ== X-Received: by 2002:a92:7786:: with SMTP id s128mr14702256ilc.204.1574396489836; Thu, 21 Nov 2019 20:21:29 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:29 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:16 -0700 Message-Id: <20191121211845.v4.51.I8927290f40075722d16217b170ef701463930bfd@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 051/100] x86: Add an option to include a FIT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Many Intel SoCs require a FIT in order to boot properly. Add an option to include this and enable it by default. This term can be confused with FIT (Flat Image Tree) in U-Boot so the CONFIG option has to include 'X86'. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Add help to CONFIG_FIT and don't make it 'default y' - Rename X86_HAS_FIT to HAVE_X86_FIT - Update commit message to explain why HAVE_FIT woudl be confusing Changes in v2: None arch/x86/Kconfig | 8 ++++++++ arch/x86/dts/u-boot.dtsi | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6bac5d5fe8..ea50b2f54d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -217,6 +217,14 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 +config HAVE_X86_FIT + bool + help + Enable inclusion of an Intel Firmware Interface Table (FIT) into the + image. This table is supposed to point to microcode and the like. So + far it is just a fixed table with the minimum set of headers, so that + it is actually present. + config X86_LOAD_FROM_32_BIT bool "Boot from a 32-bit program" help diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 0e87b88e10..33441c7c80 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -82,6 +82,12 @@ u-boot-ucode { align = <16>; }; +#ifdef CONFIG_HAVE_X86_FIT + intel-fit { + }; + intel-fit-ptr { + }; +#endif #ifdef CONFIG_HAVE_MRC intel-mrc { offset = ; From patchwork Fri Nov 22 04:18:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199284 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="TPVqO6vK"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Fj27g9z9sPW for ; Fri, 22 Nov 2019 16:08:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F30F1C221C6; Fri, 22 Nov 2019 04:37:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A2BEAC220E3; Fri, 22 Nov 2019 04:24:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1E5B0C220F8; Fri, 22 Nov 2019 04:21:37 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id ADBEFC2206E for ; Fri, 22 Nov 2019 04:21:33 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id i11so6343914iol.13 for ; Thu, 21 Nov 2019 20:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AA8KVnI7soQ2hjoVc3dIHN8265ZzI/+cd7gIwqNxMng=; b=TPVqO6vKh3SUBLk8nv/4D0Eo2ZdM6xkScpIqdcKL4sRy9sY3+htSf1vgHa+Me9QI7/ +334Dn7x043ytj4uzfLhKvzjfU1n1gL/FF17ObbgGzrSM3u+69JsiXeTpLF1bW5TlRQG H8YbZo1wX5NCsXjwHfCdG9Qc9DZ6CCLDaMovo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AA8KVnI7soQ2hjoVc3dIHN8265ZzI/+cd7gIwqNxMng=; b=WTVjGPDuRGaXvP+EGA/Q0HuCzQtkv5xrJHPnWOe2DjD0Pl1dcywJTSXtdZRO9+mRI/ iP2YfbfhfBLlDyJwv9LGagV+ErL606y+ZsUI5Qm27z8fdRi6fbSyOot8nxGYSpPGpTjp xpwuU2uQ+U1wPtJqxITXMdpSgzGybxYoIvoOAI9JYT7HtJGgFuoWBn+yOczKzYdqKQWG g2PSdBXxfSIyffR7UEjc0HAyGxzgRNFu+t/pE+wN0CMNPGOjCJllueVo/l1ezfH6ZCof lGO1FJc32bMoYacrjAHiLOyfrxOSDzZbDexKLCI2FAWn7T+hDE0TSkDzIhLb9gTeFZvM 8cCQ== X-Gm-Message-State: APjAAAUEa4B0WDmaktIVTkYErVJKC6sZu/KblD3pqltNw9RckwQfL2gw ukq7V4Wbwou+JcFmvo0UvsvIZPtkx4Q= X-Google-Smtp-Source: APXvYqxtaJID4f2VNeYavtwVinU6v7iF1rXV7FbH7LOnRnTewYtSgiYfktQzoZiWuDsc+DvUsFfpMQ== X-Received: by 2002:a02:880c:: with SMTP id r12mr12072495jai.100.1574396492014; Thu, 21 Nov 2019 20:21:32 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:31 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:17 -0700 Message-Id: <20191121211845.v4.52.Ibeea8fe70533e9257b72be6f9f7347beb745a9aa@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 052/100] x86: Add support for newer CAR schemes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass --- Changes in v4: - Adjust - Fix up license header - Fix various code-style problems - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion - Use car_init_ret to return - Use post_code() calls consistent with car.S Changes in v3: - Drop dead code - Drop unneeded Kconfig file - Use a macro for is-power-of-two Changes in v2: None arch/x86/Kconfig | 16 + arch/x86/cpu/intel_common/Makefile | 8 + arch/x86/cpu/intel_common/car2.S | 448 ++++++++++++++++++++++++ arch/x86/cpu/intel_common/car2_uninit.S | 87 +++++ arch/x86/include/asm/processor.h | 12 +- 5 files changed, 564 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ea50b2f54d..3dde26ca93 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -879,4 +879,20 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config INTEL_CAR_CQOS + bool "Support Intel Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up a portion of L2 cache for + CAR and use the remainder for actual caching. + +# +# Each bit in QOS mask controls this many bytes. This is calculated as: +# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS +# +config CACHE_QOS_SIZE_PER_BIT + hex + depends on INTEL_CAR_CQOS + default 0x20000 # 128 KB + endmenu diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index dfbc29f047..09212cee04 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -8,6 +8,14 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif + +ifdef CONFIG_INTEL_CAR_CQOS +obj-$(CONFIG_TPL_BUILD) += car2.o +ifndef CONFIG_SPL_BUILD +obj-y += car2_uninit.o +endif +endif + obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o diff --git a/arch/x86/cpu/intel_common/car2.S b/arch/x86/cpu/intel_common/car2.S new file mode 100644 index 0000000000..086f987477 --- /dev/null +++ b/arch/x86/cpu/intel_common/car2.S @@ -0,0 +1,448 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This file was modified from the coreboot version. + * + * Copyright (C) 2015-2016 Intel Corp. + */ + +#include +#include +#include +#include +#include +#include + +#define KiB 1024 + +#define IS_POWER_OF_2(x) (!((x) & ((x) - 1))) + +.global car_init +car_init: + post_code(POST_CAR_START) + + /* + * Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. + */ +check_for_clean_reset: + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz no_reset + /* perform warm reset */ + movw $IO_PORT_RESET, %dx + movb $(SYS_RST | RST_CPU), %al + outb %al, %dx + +no_reset: + post_code(POST_CAR_SIPI) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(POST_CAR_MTRR) + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(POST_CAR_UNCACHEABLE) + + /* Configure default memory type to uncacheable (UC) */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + /* Clear enable bits and set default type to UC */ + and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ + MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* + * Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + post_code(POST_CAR_BASE_ADDRESS) + +#if IS_POWER_OF_2(CONFIG_DCACHE_RAM_SIZE) + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov $MTRR_PHYS_MASK(0), %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr +#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK_MSR(0), %ecx + mov $(512 * KiB), %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + + mov $MTRR_PHYS_BASE_MSR(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK_MSR(1), %ecx + mov $(256 * KiB), %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr +#else +#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" +#endif + post_code(POST_CAR_FILL) + + /* Enable variable MTRRs */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + or $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable caching */ + mov %cr0, %eax + and $~(X86_CR0_CD | X86_CR0_NW), %eax + invd + mov %eax, %cr0 + +#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) + jmp car_nem +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) + jmp car_cqos +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) + jmp car_nem_enhanced +#else +#error "No CAR mechanism selected: +#endif + jmp car_init_ret + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000_MSR + .word MTRR_FIX_16K_80000_MSR + .word MTRR_FIX_16K_A0000_MSR + .word MTRR_FIX_4K_C0000_MSR + .word MTRR_FIX_4K_C8000_MSR + .word MTRR_FIX_4K_D0000_MSR + .word MTRR_FIX_4K_D8000_MSR + .word MTRR_FIX_4K_E0000_MSR + .word MTRR_FIX_4K_E8000_MSR + .word MTRR_FIX_4K_F0000_MSR + .word MTRR_FIX_4K_F8000_MSR +fixed_mtrr_list_size = . - fixed_mtrr_list + +#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +.global car_nem +car_nem: + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x2, %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret + +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +.global car_cqos +car_cqos: + /* + * Create CBM_LEN_MASK based on CBM_LEN + * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0] + */ + mov $0x10, %eax + mov $0x2, %ecx + cpuid + and $0x1f, %eax + add $1, %al + + mov $1, %ebx + mov %al, %cl + shl %cl, %ebx + sub $1, %ebx + + /* Store the CBM_LEN_MASK in mm3 for later use */ + movd %ebx, %mm3 + + /* + * Disable both L1 and L2 prefetcher. For yet-to-understood reason, + * prefetchers slow down filling cache with rep stos in CQOS mode. + */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr + +#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE) +/* + * If CAR size is set to full L2 size, mask is calculated as all-zeros. + * This is not supported by the CPU/uCode. + */ +#error "CQOS CAR may not use whole L2 cache area" +#endif + + /* Calculate how many bits to be used for CAR */ + xor %edx, %edx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ + mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ + div %ecx /* result is in eax */ + mov %eax, %ecx /* save to ecx */ + mov $1, %ebx + shl %cl, %ebx + sub $1, %ebx /* resulting mask is is in ebx */ + + /* Set this mask for initial cache fill */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov %ebx, %eax + wrmsr + + /* Set CLOS selector to 0 */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ + wrmsr + + /* We will need to block CAR region from evicts */ + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov %ebx, %eax + xor $~0, %eax /* invert 32 bits */ + + /* + * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit + * Mask Length. + */ + movd %mm3, %ebx + and %ebx, %eax + wrmsr + + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + + post_code(0x27) + + /* Cache is populated. Use mask 1 that will block evicts */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ + or $1, %edx /* select mask 1 */ + wrmsr + + /* Enable prefetchers */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret + +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +.global car_nem_enhanced +car_nem_enhanced: + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + post_code(0x26) + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +find_llc_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz find_llc_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence create Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * LLC Ways -> LLC_WAY_MASK_1: + * 4: 0x000E + * 8: 0x00FE + * 12: 0x0FFE + * 16: 0xFFFE + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $MSR_IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $MSR_IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set MSR_IA32_PQR_ASSOC = 0x02 + * + * Possible values: + * 0: Default value, no way mask should be applied + * 1: Apply way mask 1 to LLC + * 2: Apply way mask 2 to LLC + * 3: Shouldn't be use in NEM Mode + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + /* + * Set MSR_IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + post_code(0x27) + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $MSR_EVICT_CTL, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret +#endif + +#if CONFIG_IS_ENABLED(X86_16BIT_INIT) +_dt_ucode_base_size: + /* These next two fields are filled in by binman */ +.globl ucode_base +ucode_base: /* Declared in microcode.h */ + .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ + .long 0 /* microcode size */ + .long CONFIG_SYS_MONITOR_BASE /* code region base */ + .long CONFIG_SYS_MONITOR_LEN /* code region size */ +#endif diff --git a/arch/x86/cpu/intel_common/car2_uninit.S b/arch/x86/cpu/intel_common/car2_uninit.S new file mode 100644 index 0000000000..aba3a5381e --- /dev/null +++ b/arch/x86/cpu/intel_common/car2_uninit.S @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Intel Corp. + * Copyright 2019 Google LLC + * Taken from coreboot file exit_car.S + */ + +#include +#include +#include + +.text +.global car_uninit +car_uninit: + + /* + * Retrieve return address from stack as it will get trashed below if + * execution is utilizing the cache-as-ram stack. + */ + pop %ebx + + /* Disable MTRRs */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax + wrmsr + +#ifdef CONFIG_INTEL_CAR_NEM +.global car_nem_teardown +car_nem_teardown: + + /* invalidate cache contents */ + invd + + /* Knock down bit 1 then bit 0 of NEM control not combining steps */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +.global car_cqos_teardown +car_cqos_teardown: + + /* Go back to all-evicting mode, set both masks to all-1s */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* Reset CLOS selector to 0 */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx + wrmsr + +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +.global car_nem_enhanced_teardown +car_nem_enhanced_teardown: + + /* invalidate cache contents */ + invd + + /* Knock down bit 1 then bit 0 of NEM control not combining steps */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + + /* Reset CLOS selector to 0 */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx + wrmsr +#endif + + /* Return to caller */ + jmp *%ebx diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index f1d9977bcb..d7b6836786 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -25,8 +25,6 @@ /* Length of the public header on Intel microcode blobs */ #define UCODE_HEADER_LEN 0x30 -#ifndef __ASSEMBLY__ - /* * This register is documented in (for example) the Intel Atom Processor E3800 * Product Family Datasheet in "PCU - Power Management Controller (PMC)". @@ -37,11 +35,11 @@ */ #define IO_PORT_RESET 0xcf9 -enum { - SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ - RST_CPU = 1 << 2, /* initiate reset */ - FULL_RST = 1 << 3, /* full power cycle */ -}; +#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */ +#define RST_CPU (1 << 2) /* initiate reset */ +#define FULL_RST (1 << 3) /* full power cycle */ + +#ifndef __ASSEMBLY__ static inline __attribute__((always_inline)) void cpu_hlt(void) { From patchwork Fri Nov 22 04:18:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199285 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="l7mjQJSW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4G20RL5z9sPW for ; Fri, 22 Nov 2019 16:08:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B8054C22156; Fri, 22 Nov 2019 04:32:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A4479C2204F; Fri, 22 Nov 2019 04:23:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 72611C22051; Fri, 22 Nov 2019 04:21:38 +0000 (UTC) Received: from mail-il1-f196.google.com (mail-il1-f196.google.com [209.85.166.196]) by lists.denx.de (Postfix) with ESMTPS id 3A5C5C22029 for ; Fri, 22 Nov 2019 04:21:35 +0000 (UTC) Received: by mail-il1-f196.google.com with SMTP id q1so5554884ile.13 for ; Thu, 21 Nov 2019 20:21:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZY8rJhQXfvjymdCgPCQTixoCfcqAFBeDpvFtMLQTugU=; b=l7mjQJSWd6joORl2k7GT42WvG9IQNHIODcewVUhvLBYV2+7LwrNlC8dpUr6UR6seXM 7B6Styqzq1M0YNpCZIza2Fpd7ZVoxbUqI8q+QRflX5KwDYsN9fQkxlkASnD6CYnm2sfU oyQYfeOmZAQcAa8M2PzPCbAsnVVkvTi23y2Js= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZY8rJhQXfvjymdCgPCQTixoCfcqAFBeDpvFtMLQTugU=; b=R7QOf+gATCbdY9xyZWT9mLtH+dVixwhMDV51YtOCMZtkDx8zo490Kvmdh92qOQXmVX g2mSX7X06Iy4tOThu0HCsTkvgapQug76jaJHqZSuy/KAaHB6BBhf/nBCcHpaxe9gZS3y mRnQpdbW2tVvHFXHiRHKoYzexDh4kOiPJAKNurtHX431dIJpUVWb7psbXRiQJnEzD3aw E0fjZH0UpmHPMzMFd/IaornmKm4VWCd5dMtSaHASqQisT5fPN5+5objodR4W7kUd0uCs TO98Oz02Qdbjgi78B84mPNRQzc4aETdEZzBZ3GN0/m3PJyeOfCCkvoYTt46lAtkWANeU GgYQ== X-Gm-Message-State: APjAAAW/VPKAxUZkWGajdtHIfCTbQ8oyuRdxHIyDQgXNeIEUsYelYFyD 0qKbMm7z19BqQ2v6l7LiYbEnU55OcvM= X-Google-Smtp-Source: APXvYqyc5ErGc4UmwF60NmISCfBVO/+7TeyKltpC+zfe+39IqpPDwQoSLM6safUFzPmzdiEpCJav/A== X-Received: by 2002:a92:d58e:: with SMTP id a14mr14437768iln.4.1574396494060; Thu, 21 Nov 2019 20:21:34 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:33 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:18 -0700 Message-Id: <20191121211845.v4.53.I9f8b22481950b80d46830a0bf034376ea97b564e@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 053/100] x86: Disable microcode section for FSP2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE Changes in v2: None arch/x86/Kconfig | 4 ++++ arch/x86/dts/u-boot.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3dde26ca93..a1c5f5526c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -588,6 +588,10 @@ config HAVE_REFCODE broadwell) U-Boot will be missing some critical setup steps. Various peripherals may fail to work. +config HAVE_MICROCODE + bool + default y if !FSP_VERSION2 + config SMP bool "Enable Symmetric Multiprocessing" default n diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 33441c7c80..850fe3ac11 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -37,11 +37,13 @@ }; #endif #ifdef CONFIG_TPL +#ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = ; }; u-boot-tpl-dtb { }; +#endif u-boot-spl { offset = ; }; @@ -77,11 +79,16 @@ offset = ; }; #endif +#ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; +#else + u-boot-dtb { + }; +#endif #ifdef CONFIG_HAVE_X86_FIT intel-fit { }; From patchwork Fri Nov 22 04:18:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199235 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="YmFwud0o"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3j86pyQz9sNx for ; Fri, 22 Nov 2019 15:43:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 19E44C2205C; Fri, 22 Nov 2019 04:38:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0A73DC220DE; Fri, 22 Nov 2019 04:24:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7D800C21F79; Fri, 22 Nov 2019 04:21:40 +0000 (UTC) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by lists.denx.de (Postfix) with ESMTPS id 38328C2208C for ; Fri, 22 Nov 2019 04:21:37 +0000 (UTC) Received: by mail-io1-f66.google.com with SMTP id k1so6403435ioj.6 for ; Thu, 21 Nov 2019 20:21:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QRHaAwHJaZ9GICDK/G3/oRBMezFErjcFVmeEDm8g6y8=; b=YmFwud0o/GWk3+LN1zr2g4JgVHRLZh6t21uYtnCF78ajFNKDiRPihW2uaXMjFtkR8v DmzH3yRG5LF1WxNazGhW05HaPXiRBg1v20PxbNQgGmwzLjYHoLCvePl/PsSmUlNxdNFT 2BDwq7NQUrSq0JcqvCTDg3Ho5S2j6K7K8QhtA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QRHaAwHJaZ9GICDK/G3/oRBMezFErjcFVmeEDm8g6y8=; b=o1RPif6yIAAyfV1C9Da0qUcwNriNhRt5sCen7/3zoTpBixF0gtRzDwwwmBY9V78oW0 Tujo1gbcbeUfNsXU7dBEfjR0TR2DFm0Wqtmj9c+C2ib7EtCnkbmPZUTl9OlmPgGnCT3k pHafZYrxrvGAJOAfQstjdXUTdCL5cCr7gy3V1xdLQA+pjhc8fG6BnCNS25PmaNTuftWL e2vpw/ttHy2VZ+GDJ5fv4PjEA0UXZdM3LsEAj8Ka6LV6gDTv1xV/7W7yZikdk8GahMp0 OOq/ljb42YuQp2J6OBszcRlh9UmYTZRIS31BGm5+VaZE3AokSpib7siQm/BcPAGKXqN/ lfHw== X-Gm-Message-State: APjAAAVeXNLnuIQssV5pvcMyxP2BV6TV5AbL9FSquMlU2+aKNrEqC6k/ TcABb1xyfCAi3BVLV1V1k7MwLyWNKqE= X-Google-Smtp-Source: APXvYqz2GZVY+npUL56NJsyR6yBpw+Tmt0A4IUw5x5bpRJP0F+FHqRujl/VHQ/b9p5Mt3+NQUdCTZw== X-Received: by 2002:a05:6638:237:: with SMTP id f23mr11915829jaq.51.1574396496000; Thu, 21 Nov 2019 20:21:36 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:35 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:19 -0700 Message-Id: <20191121211845.v4.54.I08cd7ac69a3df3dd505599bb29c0bde000e70026@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 054/100] x86: Update the fsp command for FSP2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The current 'fsp' command only works with FSP1. Update it to handle FSP2 as well. Convert everything to hex which is what U-Boot uses. Signed-off-by: Simon Glass --- Changes in v4: - Explain why FSP-M cannot be shown - Use hex for size values also Changes in v3: - Convert code to use hex increased of decimal - Update the 'fsp' command for FSP2, instead of disabling it Changes in v2: None cmd/x86/fsp.c | 65 ++++++++++++++++++++++++++++++++++----------------- 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c index b3b663021b..6e485fb144 100644 --- a/cmd/x86/fsp.c +++ b/cmd/x86/fsp.c @@ -5,23 +5,38 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct fsp_header *hdr = fsp_find_header(); - u32 img_addr = hdr->img_base; - char *sign = (char *)&hdr->sign; + struct fsp_header *hdr; + u32 img_addr; + char *sign; + uint addr; int i; - printf("FSP : binary 0x%08x, header 0x%08x\n", - CONFIG_FSP_ADDR, (int)hdr); +#ifdef CONFIG_FSP_VERSION2 + /* + * Only FSP-S is displayed. FSP-M was used in SPL but may not still be + * around, and we didn't keep a pointer to it. + */ + hdr = gd->arch.fsp_s_hdr; + img_addr = hdr->img_base; + addr = img_addr; +#else + addr = CONFIG_FSP_ADDR; + hdr = fsp_find_header(); + img_addr = hdr->img_base; +#endif + sign = (char *)&hdr->sign; + + printf("FSP : binary %08x, header %08x\n", addr, (int)hdr); printf("Header : sign "); for (i = 0; i < sizeof(hdr->sign); i++) printf("%c", *sign++); - printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev); + printf(", size %x, rev %d\n", hdr->hdr_len, hdr->hdr_rev); printf("Image : rev "); if (hdr->hdr_rev == FSP_HEADER_REVISION_1) { printf("%d.%d", @@ -34,24 +49,32 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(", id "); for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++) printf("%c", hdr->img_id[i]); - printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size); - if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { + printf(", addr %08x, size %x\n", img_addr, hdr->img_size); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { printf("GFX :%ssupported\n", hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un"); } - printf("VPD : addr 0x%08x, size %d\n", + printf("VPD : addr %08x, size %x\n", hdr->cfg_region_off + img_addr, hdr->cfg_region_size); - printf("\nNumber of APIs Supported : %d\n", hdr->api_num); - printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr); - printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr); - printf("\tFspNotify : 0x%08x\n", hdr->fsp_notify + img_addr); - if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { - printf("\tMemoryInit : 0x%08x\n", - hdr->fsp_mem_init + img_addr); - printf("\tTempRamExit : 0x%08x\n", - hdr->fsp_tempram_exit + img_addr); - printf("\tSiliconInit : 0x%08x\n", - hdr->fsp_silicon_init + img_addr); + if (hdr->hdr_rev <= FSP_HEADER_REVISION_2) + printf("\nNumber of APIs Supported : %d\n", hdr->api_num); + if (hdr->fsp_tempram_init) + printf("\tTempRamInit : %08x\n", + hdr->fsp_tempram_init + img_addr); + if (hdr->fsp_init) + printf("\tFspInit : %08x\n", hdr->fsp_init + img_addr); + if (hdr->fsp_notify) + printf("\tFspNotify : %08x\n", hdr->fsp_notify + img_addr); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { + if (hdr->fsp_mem_init) + printf("\tMemoryInit : %08x\n", + hdr->fsp_mem_init + img_addr); + if (hdr->fsp_tempram_exit) + printf("\tTempRamExit : %08x\n", + hdr->fsp_tempram_exit + img_addr); + if (hdr->fsp_silicon_init) + printf("\tSiliconInit : %08x\n", + hdr->fsp_silicon_init + img_addr); } return 0; From patchwork Fri Nov 22 04:18:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199259 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:21:37 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:37 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:20 -0700 Message-Id: <20191121211845.v4.55.Iadb1b14aeaac177957bd01637bbfb821fbda34bb@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 055/100] x86: Update .dtsi file for FSP2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Include the IFWI section and the FSP-M binary. The FSP-T binary is not currently used, as CAR is set up manually. Also drop the FSP binary as this relates only to FSP1. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Add FSP-S and VBT also - Drop VBT as we already have it elsewhere Changes in v2: None arch/x86/dts/u-boot.dtsi | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 850fe3ac11..14e3c13072 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -100,12 +100,42 @@ offset = ; }; #endif -#ifdef CONFIG_HAVE_FSP +#ifdef CONFIG_FSP_VERSION1 intel-fsp { filename = CONFIG_FSP_FILE; offset = ; }; #endif +#ifdef CONFIG_FSP_VERSION2 + intel-descriptor { + filename = CONFIG_FLASH_DESCRIPTOR_FILE; + }; + intel-ifwi { + filename = CONFIG_IFWI_INPUT_FILE; + convert-fit; + + section { + size = <0x8000>; + ifwi-replace; + ifwi-subpart = "IBBP"; + ifwi-entry = "IBBL"; + u-boot-tpl { + }; + x86-start16-tpl { + offset = <0x7800>; + }; + x86-reset16-tpl { + offset = <0x7ff0>; + }; + }; + }; + intel-fsp-m { + filename = CONFIG_FSP_FILE_M; + }; + intel-fsp-s { + filename = CONFIG_FSP_FILE_S; + }; +#endif #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; From patchwork Fri Nov 22 04:18:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199228 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Tv1vk3JE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Z638H2z9sNx for ; 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Thu, 21 Nov 2019 20:21:39 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:39 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:21 -0700 Message-Id: <20191121211845.v4.56.I453a662d790c8ee5e3ec1a27c8e29feb84d03087@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 056/100] x86: Add an option to control the position of U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass --- Changes in v4: - Rename option to HAVE_SYS_TEXT_BASE Changes in v3: None Changes in v2: None Kconfig | 9 ++++++--- arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 18 +++--------------- configs/chromebook_samus_tpl_defconfig | 1 + 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/Kconfig b/Kconfig index cda4f58ff7..85e0eb642c 100644 --- a/Kconfig +++ b/Kconfig @@ -544,9 +544,14 @@ config SYS_EXTRA_OPTIONS configuration to Kconfig. Since this option will be removed sometime, new boards should not use this option. -config SYS_TEXT_BASE +config HAVE_SYS_TEXT_BASE + bool depends on !NIOS2 && !XTENSA depends on !EFI_APP + default y + +config SYS_TEXT_BASE + depends on HAVE_SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I @@ -555,8 +560,6 @@ config SYS_TEXT_BASE help The address in memory that U-Boot will be running from, initially. - - config SYS_CLK_FREQ depends on ARC || ARCH_SUNXI || MPC83xx int "CPU clock frequency" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a1c5f5526c..e105fda2f2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -899,4 +899,9 @@ config CACHE_QOS_SIZE_PER_BIT depends on INTEL_CAR_CQOS default 0x20000 # 128 KB +config X86_OFFSET_U_BOOT + hex "Offset of U-Boot in ROM image" + depends on HAVE_SYS_TEXT_BASE + default SYS_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 14e3c13072..d84c64880a 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -50,7 +50,7 @@ u-boot-spl-dtb { }; u-boot { - offset = ; + offset = ; }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { @@ -60,23 +60,11 @@ type = "u-boot-dtb-with-ucode"; }; u-boot { - /* - * TODO(sjg@chromium.org): - * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But - * for boards with textbase in SDRAM we cannot do this. Just use - * an assumed-valid value (1MB before the end of flash) here so - * that we can actually build an image for coreboot, etc. - * We need a better solution, perhaps a separate Kconfig. - */ -#if CONFIG_SYS_TEXT_BASE == 0x1110000 - offset = <0xfff00000>; -#else - offset = ; -#endif + offset = ; }; #else u-boot-with-ucode-ptr { - offset = ; + offset = ; }; #endif #ifdef CONFIG_HAVE_MICROCODE diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 28f23cfe12..c7f125eaa4 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -13,6 +13,7 @@ CONFIG_HAVE_REFCODE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_SPL_TEXT_BASE=0xffe70000 +CONFIG_X86_OFFSET_U_BOOT=0xfff00000 CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SHOW_BOOT_PROGRESS=y From patchwork Fri Nov 22 04:18:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199282 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="iQknaIaG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Dk4k6Yz9sPW for ; Fri, 22 Nov 2019 16:07:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5489AC22019; Fri, 22 Nov 2019 04:32:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5039DC22050; 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bh=quaVCGnEMrpirM+SBY4SHmBmNEgxzAAqRfZVlPakR/8=; b=WohPzJWsVMCGmUs28hp4D2ZfAhXdW0h40uUBXgVax4n9XfSOSEDkhG6KWW7YV6iDfB mOgr1nPCE3giLmQtPHsxDi+NppLLY4+5hI/Tue8XY3fmyHt1kKLoCjA2Zr6kiqFf0zpl Sx7BPcy7XvDOwLGNyc0fdfGTqgG7t/HsZerp1W3Ud3p+6Eb/fdd9lZnkMlRqAJewF7Bt S/2wg6fY1d0ZOPUFu4mGNFLUAkjoxyreTLmhRoLYVPIZCb+arRArfC3w1vOb5iPsmSdT PBbFdfW3r/69nXygpD5Ue8GSm8FvQ1aQEiXXNLDk63/uusG4FsvVz5Dnjkq4GXlF4zDJ MDaQ== X-Gm-Message-State: APjAAAUCKcdeOXFp3Y4lxn/q3miyxebdimrnGW1IunKi5+IcJwZgggum N9mwP+/id+u7CoNK2HMBfJBL0J/aks0= X-Google-Smtp-Source: APXvYqyaskeAxsJCE3ScsxTktsmb51Eh8dAR5tph98GPI9gVJUtNiuLz5dGz0juyXHuSGS+ZSOg1sw== X-Received: by 2002:a02:2b03:: with SMTP id h3mr11769386jaa.93.1574396501981; Thu, 21 Nov 2019 20:21:41 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:41 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:22 -0700 Message-Id: <20191122041905.224686-41-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 057/100] x86: Add an option to control the position of SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Add SPL condition to the option Changes in v2: None arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e105fda2f2..ae96e69f86 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -904,4 +904,9 @@ config X86_OFFSET_U_BOOT depends on HAVE_SYS_TEXT_BASE default SYS_TEXT_BASE +config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on SPL && X86 + default SPL_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index d84c64880a..fad3e7c951 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -45,7 +45,7 @@ }; #endif u-boot-spl { - offset = ; + offset = ; }; u-boot-spl-dtb { }; @@ -54,7 +54,7 @@ }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { - offset = ; + offset = ; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode"; From patchwork Fri Nov 22 04:18:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199226 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XAxNujxg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3YM6qqnz9sNx for ; Fri, 22 Nov 2019 15:36:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 9CF8AC2210E; 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Thu, 21 Nov 2019 20:21:43 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:43 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:23 -0700 Message-Id: <20191121211845.v4.58.I0e435466cc9099c61a9ea7f648498d6db7195d74@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 058/100] x86: Add an fdtmap and image-header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/dts/u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index fad3e7c951..5ebff4f407 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -124,6 +124,8 @@ filename = CONFIG_FSP_FILE_S; }; #endif + fdtmap { + }; #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; @@ -169,5 +171,8 @@ offset = ; }; #endif + image-header { + location = "end"; + }; }; #endif From patchwork Fri Nov 22 04:18:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199223 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="fc90ScZa"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3Wf3BK2z9sNx for ; Fri, 22 Nov 2019 15:35:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1C3ECC220CC; Fri, 22 Nov 2019 04:31:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 644BFC220C4; Fri, 22 Nov 2019 04:22:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 93716C220BE; Fri, 22 Nov 2019 04:21:51 +0000 (UTC) Received: from mail-il1-f196.google.com (mail-il1-f196.google.com [209.85.166.196]) by lists.denx.de (Postfix) with ESMTPS id DAB2BC22054 for ; Fri, 22 Nov 2019 04:21:46 +0000 (UTC) Received: by mail-il1-f196.google.com with SMTP id u17so5603070ilq.5 for ; Thu, 21 Nov 2019 20:21:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sdT77zPXxeBGgNrXPyAYux8JBUKmGTUat8HOepHseek=; b=fc90ScZa9b+4h984W5gB/N0HjaDX6YPHly/AjEDDK7EcBEfojT5jFcHKYBNxuy0UdK m4sgHIWUrRn1+InXcJnAGREeybfrPKzJMMs160XUF+iscvcb6v/fXdGvmGDL0+ZOgPEv L7GawRbqXRodhx59KJinR7brxzfnQ23dzPMtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sdT77zPXxeBGgNrXPyAYux8JBUKmGTUat8HOepHseek=; b=JBtww1qTWk+ZjBS6GI9bABe5a6DOVpoTO+hSZUe2wPr0Y4N6QIHpmJZQ3ubwccFrZq nN9ukKUZCiSl2suIFgrGyVcBnPF8QbY9pSIJsANQbs0uzHQ0DePPbbydn/Q5Lx/Vbo7a Q2zhm+GS6L6gF2ydgdT0XI7vg6myxmYaQqz1uM0AyAs+c3FAxe2Aa+Dn22yBM47Indgb gZPcBeqOU+aShYueI4fyh5iVa0RuuhY85YOaHRmJOD0kBorvkAOMvwHWyS82R6RAcuF2 ZrcvaYwQTXVVJv4voi7JB2m5iX7zHedJSo/bfjQN/7TdyFIlqgh9mkGuqnTxNEHd1Mc5 a0Qw== X-Gm-Message-State: APjAAAWI4cAOuwiP/MLdJCcLISpJ65YbLryGRoSSZWW/q33V3z3gZpFO ucbbx5TWXJDQX+G0F/3R1BW78FchQgs= X-Google-Smtp-Source: APXvYqxKmDcWJkcC8q/GpCBbgz+mUvSpXia5xgxaD4JnkoilfHX41gPKS3A7TO2u+pbv8BrZ1Yp2Fg== X-Received: by 2002:a92:350a:: with SMTP id c10mr14181882ila.140.1574396505721; Thu, 21 Nov 2019 20:21:45 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:45 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:24 -0700 Message-Id: <20191122041905.224686-42-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 059/100] x86: Don't repeat microcode in U-Boot if not needed X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present if SPL sets up the microcode then it is still included in U-Boot as well. This is wasteful as microcode is large. Adjust the logic in the image to prevent this. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/dts/u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 5ebff4f407..e0cca58640 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -63,9 +63,16 @@ offset = ; }; #else +# ifdef CONFIG_SPL + u-boot { + offset = ; + }; +# else + /* If there is no SPL then we need to put microcode in U-Boot */ u-boot-with-ucode-ptr { offset = ; }; +# endif #endif #ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { From patchwork Fri Nov 22 04:18:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199266 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Cv18ByjI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K44L2HdVz9s7T for ; Fri, 22 Nov 2019 16:00:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A2FB4C22111; Fri, 22 Nov 2019 04:33:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D0250C220BE; Fri, 22 Nov 2019 04:23:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A3E24C220BD; Fri, 22 Nov 2019 04:21:54 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id EDAF8C2205A for ; Fri, 22 Nov 2019 04:21:48 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id q15so5582754ils.8 for ; Thu, 21 Nov 2019 20:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTFehJs1yuY8EA3EhNy/khazYXHD6CqOKYQBaCv2zpo=; b=Cv18ByjIIsZnCruV963kwni85OV0l98N/+ubAiDejMb7uqN+OUKUCYAm7+YFSbPGFF GOfcD9H9L3oSo94EKVm9zLQMQnh/hcrOOiauQYH74OzW1bCtJHoM3H7eiycJv1e/JWm3 zcu1qOSTs6Vrz1ZSyXe2VatGhHQktDffzJPgo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTFehJs1yuY8EA3EhNy/khazYXHD6CqOKYQBaCv2zpo=; b=Pr4nNtGq5VNPXqroBW2LYnbEY8HzdvtAqclKGjmCsXtcxec/A7THemoQiB/mw+vKUI AWhm2Ydp07oKpJYM4y4G2exsmSvug0tQtvpTKhb4Zot3lpLuC3eZYiTP3kFXavMI6T9x 1b+nqE0FK6WgEg/U2GYqnL+bfDksdoMgp8sQM+3nTlxXT6R2aTey3ww/Yz7FZ+jN0cjc UClA1/ztoqf8loT5CnyXQc/eS/HrlXbS35KilXjytQ0lfXSJ8Tj7xILIrxBjKxmhHgKb gs42T29xPxnd+9aRSxoJo861lsxnntGqE1GNzXT9D+h80tqRO5BzSgfmZGbBRMprLc5U q59w== X-Gm-Message-State: APjAAAXw7jdGAgu20rfbTOrnhHYHvD+XbGjdOWC5mIPfxOiW6xVOd3Tz StBbx34UeRnn3JuDH6h07ShSlRQq8pw= X-Google-Smtp-Source: APXvYqzRQTXhQW4tUsab9nSjOsLR2MxCUptAh98B+wbsCIBIOe6HDtLcHVGgv8zBr6WYhqIL5yQsAQ== X-Received: by 2002:a92:afd5:: with SMTP id v82mr15022247ill.294.1574396507804; Thu, 21 Nov 2019 20:21:47 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:47 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:25 -0700 Message-Id: <20191122041905.224686-43-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 060/100] x86: Separate out U-Boot and device tree in ROM image X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/dts/u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index e0cca58640..ccb72b3511 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -49,9 +49,11 @@ }; u-boot-spl-dtb { }; - u-boot { + u-boot-nodtb { offset = ; }; + u-boot-dtb { + }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { offset = ; From patchwork Fri Nov 22 04:18:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199241 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Z42jeRkZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3mX39ySz9sNx for ; Fri, 22 Nov 2019 15:46:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0C5CCC22054; Fri, 22 Nov 2019 04:42:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9773BC22041; Fri, 22 Nov 2019 04:28:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B717CC2203D; Fri, 22 Nov 2019 04:21:55 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id E7007C22084 for ; Fri, 22 Nov 2019 04:21:50 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id u24so4688268iob.5 for ; Thu, 21 Nov 2019 20:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L7IanU400h7CfphqgZ1NP8yfaeug9cNCTvunnVa0E/s=; b=Z42jeRkZ++eZH6HvDxDe1LwSmNDliQrUU2ok5f7YUXlBRRhKD6tyVFx1cZRPCntjlk oogWdJrAAKoA2c7xzjvYqudK49haGBCtzJeL6JPGiUIzA7t5ZkO+PoH/Bi2cFVqDUMR/ mAYTKXV8s96ArGPAMtkYvSRVIHUZIN0ySR1xA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L7IanU400h7CfphqgZ1NP8yfaeug9cNCTvunnVa0E/s=; b=t6j6ZT2pgimsG+WC30rmjoGh2WCedZb0N/cgikHWfEjq88MypxXLVd30ibnewzeKtp WS2/+QF6zxSCl2A+/ZDLrIrLgwv+1/OBopkMJNcXHDT3lOp5Wn70PWPw2oxiFyvUmeud j0ikz/A6AhrLy3pefgKLT8KpOR332WtX90eyTHxyG94Z5T9E248v2KlUgyJeGvaOOdUA i/YbjrjiHHSKpb/NotIlhyELV6cUg30DZmXKYZzQG+LHvfBYXukdEf3AwsSgRIh2zS4J STtwPBcnjJZZrB5YKqEQSzHZcCT5hIBLMfXWUydhJM8IMLC6FGxzbQTYSqzMlPy/PEzo Rw0w== X-Gm-Message-State: APjAAAVfeElLkMvOV+yNYI09fRQMapzv++OTVnoL5Q+BdEDnDIQy1DBu S+9EP1zxyje4B97g18+pbNLaWDYyxqM= X-Google-Smtp-Source: APXvYqz40s5j7ivzfrVNWttRvXv1k5b7WAXlmEhvDl+jSXltMA5YSKrHB1VnTVGKQ1DLCnG5FqKwlg== X-Received: by 2002:a6b:e61a:: with SMTP id g26mr11100882ioh.141.1574396509774; Thu, 21 Nov 2019 20:21:49 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:49 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:26 -0700 Message-Id: <20191122041905.224686-44-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 061/100] x86: Make MSR_PKG_POWER_SKU common X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is used on several boards so add it to the common file. Also add a useful power-limit value while we are here. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/x86/include/asm/arch-broadwell/cpu.h | 1 - arch/x86/include/asm/arch-ivybridge/model_206ax.h | 1 - arch/x86/include/asm/msr-index.h | 9 ++++++++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h b/arch/x86/include/asm/arch-broadwell/cpu.h index 3bc3bd6609..2b39a76fbd 100644 --- a/arch/x86/include/asm/arch-broadwell/cpu.h +++ b/arch/x86/include/asm/arch-broadwell/cpu.h @@ -27,7 +27,6 @@ #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU 0x614 #define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_VR_MISC_CONFIG2 0x636 diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 4839ebc312..5c066294bc 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -43,7 +43,6 @@ #define MSR_PP1_CURRENT_CONFIG 0x602 #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU 0x614 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 #define MSR_CONFIG_TDP_LEVEL1 0x649 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 5bc8b6c22c..79a9369de1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -241,10 +241,17 @@ #define PKG_POWER_LIMIT_CLAMP (1 << 16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f +/* + * For Mobile, RAPL default PL1 time window value set to 28 seconds. + * RAPL time window calculation defined as follows: + * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e #define MSR_PKG_ENERGY_STATUS 0x00000611 #define MSR_PKG_PERF_STATUS 0x00000613 -#define MSR_PKG_POWER_INFO 0x00000614 +#define MSR_PKG_POWER_SKU 0x614 #define MSR_DRAM_POWER_LIMIT 0x00000618 #define MSR_DRAM_ENERGY_STATUS 0x00000619 From patchwork Fri Nov 22 04:18:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199294 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="QXo1vW1s"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Ln52MRz9sPW for ; Fri, 22 Nov 2019 16:12:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 57512C221FA; Fri, 22 Nov 2019 04:37:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EE890C220DC; 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bh=J1A+rSNNyCfvB+aN9DwdSo+QEsTND6P93CPTFg+aWlo=; b=PfPEqjA2708Uq63do34SS9SRcxFCCjTDpYwil5qKCINzSAFQO1z2mISnoSNhJh4jF0 LgQWrs28S4abcrJuFXjoJdnIdnawqXG9NPFtENa0K8/YGc29QufeMnUS/znHRyx4ZdBd HrTDk+bfhmf0dwis/i0Pc8FWm53HK6TnpiKrvU+xbtUEzrrIG+l0zcamNiQ8+gkU8Fkw THPvI76Ros1JXp2S74Lz4ki29gxq1hEhaXwjzlw1kJH4sZVv5QO6OWLCPR1JqWd9FOqs 5qIqSSstFi7cejZYuWb1IdchiIhMS2aTbssHFwu48tiYNZ8LiGjyVwyhLp16/aVgipc2 zJ+Q== X-Gm-Message-State: APjAAAWKdCec4UFh4blUalEIq53Ba0bZOumElQRAjx24q5LVSVKemi5S YeBM9Z8EW7Xtk6pfym9pKe+/pnx2c7Q= X-Google-Smtp-Source: APXvYqynFrnXYF9jCYXya+X2yz6awPh6O8gDF2ah0ZYmtXuuFnk8xJHkd169CwhwnsVxiS91vOuVzA== X-Received: by 2002:a92:a30d:: with SMTP id a13mr13885199ili.186.1574396511954; Thu, 21 Nov 2019 20:21:51 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:27 -0700 Message-Id: <20191122041905.224686-45-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 062/100] spi: Correct operations check in dm_spi_xfer() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 9 +-------- drivers/spi/spi-uclass.c | 5 ++++- include/spi.h | 2 +- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index fbb58c783e..a4e4ad55c6 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -493,13 +493,6 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } -static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - printf("ICH SPI: Only supports memory operations\n"); - return -1; -} - static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -612,7 +605,7 @@ static const struct spi_controller_mem_ops ich_controller_mem_ops = { }; static const struct dm_spi_ops ich_spi_ops = { - .xfer = ich_spi_xfer, + /* xfer is not supported */ .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 665611f7e2..af910e9efc 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -85,11 +85,14 @@ int dm_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus); if (bus->uclass->uc_drv->id != UCLASS_SPI) return -EOPNOTSUPP; + if (!ops->xfer) + return -ENOSYS; - return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags); + return ops->xfer(dev, bitlen, dout, din, flags); } int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, diff --git a/include/spi.h b/include/spi.h index 6fbb4336ce..ba2c8406b2 100644 --- a/include/spi.h +++ b/include/spi.h @@ -224,7 +224,7 @@ void spi_release_bus(struct spi_slave *slave); int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); /** - * SPI transfer + * SPI transfer (optional if mem_ops is used) * * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks * "bitlen" bits in the SPI MISO port. That's just the way SPI works. From patchwork Fri Nov 22 04:18:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199280 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="KlwskD55"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4CF5KShz9sPW for ; Fri, 22 Nov 2019 16:06:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2F9F2C22199; Fri, 22 Nov 2019 04:39:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 06DDCC21FF8; Fri, 22 Nov 2019 04:26:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5F99BC22070; Fri, 22 Nov 2019 04:22:00 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 1F45AC2208E for ; Fri, 22 Nov 2019 04:21:55 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id q15so5582907ils.8 for ; Thu, 21 Nov 2019 20:21:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=psnfyBBOWgWdxDQ/lc2S7/d61lpeKqotqLsWzvJGUu0=; b=KlwskD55wnxd74ALBe/lHJL7fvDSXpnxaYQD81TNQHY+BuCXTzUhL+xVZGYatX5fk4 HQtugIhdZaE8NgQ2kkEWttEWBzPTlXV00HcGuW9RhuqbzjTWvpkh/ESySbfC2Zq4Mkfa q9ABojfSCGbt7doDbVlHKuBme+yq0FjAYTwSY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=psnfyBBOWgWdxDQ/lc2S7/d61lpeKqotqLsWzvJGUu0=; b=UeVhTdsAV1QRZapDY2Kj+pyjKlI4MCj/6bMOSNIdhjj/5ZXyjwVHAIiDIft+SaYGev i+qkertkjMSW0M88zSTvHYgPStF/EFtZtRC+lfgDJlc5jchCgYS2k/hS5BXW/c2i8kyY K3OXNRdJfhPqmLF8cO4JjlfPePWaARVZGirc5LcHNwfYlGVPzZVNEIh7Nzh8HtL7Y4td 4Fd12dagPg5Ig3BzDS9UXWfGdLKgd4KYTIPpF+XmxkYLxJTAY3O1Gw4FGiLgDKE+JAoM F2RlC0q+i8UuFcgS44nK0eXejoTH9hEvRVb2mvn7aSnmID6MrM1YdOs9SxA/m+IIzDtr sCXg== X-Gm-Message-State: APjAAAV0AmVH0KOZGxwHymgEElThrvlAu/a03upqYrM0v8tvWKOPCzvf dm0jmYwB+/N9TTnapgzruSyk3xTZv9M= X-Google-Smtp-Source: APXvYqxnuPnFFe1roI+hWtLQA/MNMjAI3BHu2ELWOUBhY6urWzxtvwhRPU736TilNNbqqVBaz9BVrA== X-Received: by 2002:a92:5850:: with SMTP id m77mr15061733ilb.203.1574396513919; Thu, 21 Nov 2019 20:21:53 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:53 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:28 -0700 Message-Id: <20191122041905.224686-46-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 063/100] x86: spi: Don't enable SPI_FLASH_BAR by default X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't normally need this on x86 unless the size of SPI flash devices is larger than 16MB. This can be enabled by particular SoCs as needed, since it adds to code size. Drop the default enabling of this option on x86. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8588866489..fae2040af8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -142,7 +142,6 @@ config FSL_DSPI config ICH_SPI bool "Intel ICH SPI driver" - imply SPI_FLASH_BAR help Enable the Intel ICH SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Intel From patchwork Fri Nov 22 04:18:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199289 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="iiUxa+VH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4HP70Sdz9sPW for ; Fri, 22 Nov 2019 16:09:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B0B59C2219A; Fri, 22 Nov 2019 04:39:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 22114C2205C; Fri, 22 Nov 2019 04:26:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B903C22039; Fri, 22 Nov 2019 04:22:02 +0000 (UTC) Received: from mail-il1-f194.google.com (mail-il1-f194.google.com [209.85.166.194]) by lists.denx.de (Postfix) with ESMTPS id 1106FC22097 for ; Fri, 22 Nov 2019 04:21:57 +0000 (UTC) Received: by mail-il1-f194.google.com with SMTP id p6so5636420ilp.1 for ; Thu, 21 Nov 2019 20:21:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KjnLRd7uBj69VhEk93FX2Xc1oWaPZNy6yxJMJ0W+dYY=; b=iiUxa+VHSs9O0P9+o3+Wh49qOMFmR2BJ42poo9Ha2LI8ryQiNsgSvWDVkc1I47n3sy KpbEL2leyG3zEhmCx1VO6rioATclBjxhu9sgH58Uq3+GBW263XH+hu57I9b/qUW8mBzf +Tk+a4BtodbYCxRqinAhBtvw+eRkJT37jsbrs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KjnLRd7uBj69VhEk93FX2Xc1oWaPZNy6yxJMJ0W+dYY=; b=Iu4k9Y2Lkjxbp8yQDUpj9Q46wxNkwrTbCc7u60GKF8lZ3weny2HqXJ9lzPiie9/iYL E75nL7FqTePvFf0rwnT+4peu/qm11lGwKExMNbBcFXyvc6rGWLDy27zHEzn2QxFxR9jC 3QPDS6LuavyTYaey/LAa4BY70jDvzEmG6NRLpkxJBe1gYDVDGdFW3Q42BmKwYKGy9EPj 43ykbnqUEfXE6SqXUDrzMDfRl2BhaAs+UWYlwg1NV/Eh61uyUg/xQncLb+Axem5rg5W5 F7fCZUJxavpckFh0iO27K3RJeupU5fU9G88cuHVjJCv1LApM3Qn4uOSGPNJYZrRaU8US kU9Q== X-Gm-Message-State: APjAAAWRyFZvcRngLYlDW2UggX9pqJN/WF5JxUMNrO0hmw+YPDUgC6vi ReN3gYgWjbSNfUzj9zDLeNWLbGKYjBs= X-Google-Smtp-Source: APXvYqy9UuYch74RUAdu9QWgx4qS0brxwmiNHsXsaBD2v49QafqVnoAgbfLCbU5+y3D5Uk9DxMt+dQ== X-Received: by 2002:a05:6e02:cc3:: with SMTP id c3mr1664395ilj.141.1574396515831; Thu, 21 Nov 2019 20:21:55 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:21:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:29 -0700 Message-Id: <20191122041905.224686-47-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 064/100] spi: ich: Move init function just above probe() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 122 +++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index a4e4ad55c6..3eb4599ba2 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -112,67 +112,6 @@ static int ich9_can_do_33mhz(struct udevice *dev) return speed == 1; } -static int ich_init_controller(struct udevice *dev, - struct ich_spi_platdata *plat, - struct ich_spi_priv *ctlr) -{ - ulong sbase_addr; - void *sbase; - - /* SBASE is similar */ - pch_get_spi_base(dev->parent, &sbase_addr); - sbase = (void *)sbase_addr; - debug("%s: sbase=%p\n", __func__, sbase); - - if (plat->ich_version == ICHV_7) { - struct ich7_spi_regs *ich7_spi = sbase; - - ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich7_spi->opmenu); - ctlr->optype = offsetof(struct ich7_spi_regs, optype); - ctlr->addr = offsetof(struct ich7_spi_regs, spia); - ctlr->data = offsetof(struct ich7_spi_regs, spid); - ctlr->databytes = sizeof(ich7_spi->spid); - ctlr->status = offsetof(struct ich7_spi_regs, spis); - ctlr->control = offsetof(struct ich7_spi_regs, spic); - ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); - ctlr->preop = offsetof(struct ich7_spi_regs, preop); - ctlr->base = ich7_spi; - } else if (plat->ich_version == ICHV_9) { - struct ich9_spi_regs *ich9_spi = sbase; - - ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich9_spi->opmenu); - ctlr->optype = offsetof(struct ich9_spi_regs, optype); - ctlr->addr = offsetof(struct ich9_spi_regs, faddr); - ctlr->data = offsetof(struct ich9_spi_regs, fdata); - ctlr->databytes = sizeof(ich9_spi->fdata); - ctlr->status = offsetof(struct ich9_spi_regs, ssfs); - ctlr->control = offsetof(struct ich9_spi_regs, ssfc); - ctlr->speed = ctlr->control + 2; - ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); - ctlr->preop = offsetof(struct ich9_spi_regs, preop); - ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); - ctlr->pr = &ich9_spi->pr[0]; - ctlr->base = ich9_spi; - } else { - debug("ICH SPI: Unrecognised ICH version %d\n", - plat->ich_version); - return -EINVAL; - } - - /* Work out the maximum speed we can support */ - ctlr->max_speed = 20000000; - if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) - ctlr->max_speed = 33000000; - debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", - plat->ich_version, ctlr->base, ctlr->max_speed); - - ich_set_bbar(ctlr, 0); - - return 0; -} - static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) { if (plat->ich_version == ICHV_7) { @@ -493,6 +432,67 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } +static int ich_init_controller(struct udevice *dev, + struct ich_spi_platdata *plat, + struct ich_spi_priv *ctlr) +{ + ulong sbase_addr; + void *sbase; + + /* SBASE is similar */ + pch_get_spi_base(dev->parent, &sbase_addr); + sbase = (void *)sbase_addr; + debug("%s: sbase=%p\n", __func__, sbase); + + if (plat->ich_version == ICHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; + + ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich7_spi->opmenu); + ctlr->optype = offsetof(struct ich7_spi_regs, optype); + ctlr->addr = offsetof(struct ich7_spi_regs, spia); + ctlr->data = offsetof(struct ich7_spi_regs, spid); + ctlr->databytes = sizeof(ich7_spi->spid); + ctlr->status = offsetof(struct ich7_spi_regs, spis); + ctlr->control = offsetof(struct ich7_spi_regs, spic); + ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); + ctlr->preop = offsetof(struct ich7_spi_regs, preop); + ctlr->base = ich7_spi; + } else if (plat->ich_version == ICHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; + + ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich9_spi->opmenu); + ctlr->optype = offsetof(struct ich9_spi_regs, optype); + ctlr->addr = offsetof(struct ich9_spi_regs, faddr); + ctlr->data = offsetof(struct ich9_spi_regs, fdata); + ctlr->databytes = sizeof(ich9_spi->fdata); + ctlr->status = offsetof(struct ich9_spi_regs, ssfs); + ctlr->control = offsetof(struct ich9_spi_regs, ssfc); + ctlr->speed = ctlr->control + 2; + ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); + ctlr->preop = offsetof(struct ich9_spi_regs, preop); + ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); + ctlr->pr = &ich9_spi->pr[0]; + ctlr->base = ich9_spi; + } else { + debug("ICH SPI: Unrecognised ICH version %d\n", + plat->ich_version); + return -EINVAL; + } + + /* Work out the maximum speed we can support */ + ctlr->max_speed = 20000000; + if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) + ctlr->max_speed = 33000000; + debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", + plat->ich_version, ctlr->base, ctlr->max_speed); + + ich_set_bbar(ctlr, 0); + + return 0; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); From patchwork Fri Nov 22 04:18:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199217 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 63 ++++++++++++++++++++++++++++++++--------------- drivers/spi/ich.h | 1 + 2 files changed, 44 insertions(+), 20 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 3eb4599ba2..4d61be02ec 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -98,13 +98,14 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) /* @return 1 if the SPI flash supports the 33MHz speed */ static int ich9_can_do_33mhz(struct udevice *dev) { + struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; /* Observe SPI Descriptor Component Section 0 */ - dm_pci_write_config32(dev->parent, 0xb0, 0x1000); + dm_pci_write_config32(priv->pch, 0xb0, 0x1000); /* Extract the Write/Erase SPI Frequency from descriptor */ - dm_pci_read_config32(dev->parent, 0xb4, &fdod); + dm_pci_read_config32(priv->pch, 0xb4, &fdod); /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ speed = (fdod >> 21) & 7; @@ -432,6 +433,37 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } +static int ich_protect_lockdown(struct udevice *dev) +{ + struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); + int ret = -ENOSYS; + + /* Disable the BIOS write protect so write commands are allowed */ + if (priv->pch) + ret = pch_set_spi_protect(priv->pch, false); + if (ret == -ENOSYS) { + u8 bios_cntl; + + bios_cntl = ich_readb(priv, priv->bcr); + bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl |= 1; /* Write Protect Disable (WPD) */ + ich_writeb(priv, bios_cntl, priv->bcr); + } else if (ret) { + debug("%s: Failed to disable write-protect: err=%d\n", + __func__, ret); + return ret; + } + + /* Lock down SPI controller settings if required */ + if (plat->lockdown) { + ich_spi_config_opcode(dev); + spi_lock_down(plat, priv->base); + } + + return 0; +} + static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) @@ -497,30 +529,15 @@ static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); struct ich_spi_priv *priv = dev_get_priv(dev); - uint8_t bios_cntl; int ret; ret = ich_init_controller(dev, plat, priv); if (ret) return ret; - /* Disable the BIOS write protect so write commands are allowed */ - ret = pch_set_spi_protect(dev->parent, false); - if (ret == -ENOSYS) { - bios_cntl = ich_readb(priv, priv->bcr); - bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ - bios_cntl |= 1; /* Write Protect Disable (WPD) */ - ich_writeb(priv, bios_cntl, priv->bcr); - } else if (ret) { - debug("%s: Failed to disable write-protect: err=%d\n", - __func__, ret); - return ret; - } - /* Lock down SPI controller settings if required */ - if (plat->lockdown) { - ich_spi_config_opcode(dev); - spi_lock_down(plat, priv->base); - } + ret = ich_protect_lockdown(dev); + if (ret) + return ret; priv->cur_speed = priv->max_speed; @@ -579,9 +596,15 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); int node = dev_of_offset(dev); int ret; + /* Find a PCH if there is one */ + uclass_first_device(UCLASS_PCH, &priv->pch); + if (!priv->pch) + priv->pch = dev_get_parent(dev); + ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); if (ret == 0) { plat->ich_version = ICHV_7; diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 3dfb2aaff1..77057878a5 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -191,6 +191,7 @@ struct ich_spi_priv { ulong max_speed; /* Maximum bus speed in MHz */ ulong cur_speed; /* Current bus speed */ struct spi_trans trans; /* current transaction in progress */ + struct udevice *pch; /* PCH, used to control SPI access */ }; #endif /* _ICH_H_ */ From patchwork Fri Nov 22 04:18:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199263 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="EmqDZcjX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K40s5TKJz9sPc for ; Fri, 22 Nov 2019 15:57:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7ADBEC22109; Fri, 22 Nov 2019 04:32:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 30A40C220CD; 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It has the same effect and is shorter. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 4d61be02ec..6460144560 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -597,28 +597,16 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); struct ich_spi_priv *priv = dev_get_priv(dev); - int node = dev_of_offset(dev); - int ret; /* Find a PCH if there is one */ uclass_first_device(UCLASS_PCH, &priv->pch); if (!priv->pch) priv->pch = dev_get_parent(dev); - ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); - if (ret == 0) { - plat->ich_version = ICHV_7; - } else { - ret = fdt_node_check_compatible(gd->fdt_blob, node, - "intel,ich9-spi"); - if (ret == 0) - plat->ich_version = ICHV_9; - } + plat->ich_version = dev_get_driver_data(dev); + plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node, - "intel,spi-lock-down"); - - return ret; + return 0; } static const struct spi_controller_mem_ops ich_controller_mem_ops = { @@ -639,8 +627,8 @@ static const struct dm_spi_ops ich_spi_ops = { }; static const struct udevice_id ich_spi_ids[] = { - { .compatible = "intel,ich7-spi" }, - { .compatible = "intel,ich9-spi" }, + { .compatible = "intel,ich7-spi", ICHV_7 }, + { .compatible = "intel,ich9-spi", ICHV_9 }, { } }; From patchwork Fri Nov 22 04:18:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199232 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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Thu, 21 Nov 2019 20:22:01 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:01 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:32 -0700 Message-Id: <20191122041905.224686-50-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 067/100] spi: ich: Fix header order X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move the header files into the right order. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 6460144560..eeb4c274b8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -13,9 +14,8 @@ #include #include #include -#include #include -#include +#include #include "ich.h" From patchwork Fri Nov 22 04:18:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199251 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="htJNJczd"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3sw0RVhz9sPJ for ; Fri, 22 Nov 2019 15:51:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BD0EDC22046; Fri, 22 Nov 2019 04:31:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 671E0C220A8; Fri, 22 Nov 2019 04:22:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 68DF3C2204A; Fri, 22 Nov 2019 04:22:08 +0000 (UTC) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by lists.denx.de (Postfix) with ESMTPS id E613EC22054 for ; Fri, 22 Nov 2019 04:22:04 +0000 (UTC) Received: by mail-io1-f68.google.com with SMTP id k13so6381743ioa.9 for ; Thu, 21 Nov 2019 20:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XiEKiVXIHtYG8SiCcjgsWK4rkG8U/4av76ww+y4/Wr4=; b=htJNJczd4S4DkzpFRTQt/lYl9r9A9c3/sXbIaON/uJLorlF3T2dNM1fT5oiz3+1kDT 7kFGeJSZ9bLFrGIpwxa8B7Mae0jACTvzqiJmIpZjOK8n0AEvA/R+Xdt++RBtw0O0m6xW Ul9P0cFkrvl2sZbYZ+vFaZxAVuxVaN8Nb4JSA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XiEKiVXIHtYG8SiCcjgsWK4rkG8U/4av76ww+y4/Wr4=; b=iZxzFvGEOJZe070di8ZvNsxaOC4RGq7iWU+1X7lklAei1vy/ecK1aUgOIhrG2yF+Mf 8JPUZJxM5UDFC6BNwHy8/gt62t0Qovkb/y14MMjp+VDdvzBc57LjGwQR3hDsYG5l+xnz NCfQo1GG6xPdfyu2aYa3n0sz25lFh+8fVKeTYLtr2ZmwkaRyRltt8H17eUAppFC7smPz KDZuIJTj0mjcxou5UdWnbvNDqKCSzitYg7Lq9zjvZam4Ac259nDkE23PwYHdqO9Af4TB p364+wIVq3wdZg4wW6jIP83uC00L5zxm97kBz70F83Wk7yDw1zMzHUzvMmV1DphKK5rT LubA== X-Gm-Message-State: APjAAAUaz9m76+qPl8hVQP9mVwsSBLe2mhfRA7fjgUX7qoe9U4OgJoAg GznRJ2rqese95RyQ9n43P6OV5q8hljo= X-Google-Smtp-Source: APXvYqxeA7TQ10PoB3e2F7icJO3GCwdR86+Na37mUNnN5iGQFm1zDOjnY6iI6KYHZ4iB/7tlxpYaIA== X-Received: by 2002:a5e:8e49:: with SMTP id r9mr20382ioo.47.1574396523769; Thu, 21 Nov 2019 20:22:03 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:03 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:33 -0700 Message-Id: <20191122041905.224686-51-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 068/100] spi: ich: Various small tidy-ups X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index eeb4c274b8..b83dfb854d 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -5,6 +5,8 @@ * This file is derived from the flashrom project. */ +#define LOG_CATEGORY UCLASS_SPI + #include #include #include @@ -19,8 +21,6 @@ #include "ich.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef DEBUG_TRACE #define debug_trace(fmt, args...) debug(fmt, ##args) #else @@ -96,7 +96,7 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) } /* @return 1 if the SPI flash supports the 33MHz speed */ -static int ich9_can_do_33mhz(struct udevice *dev) +static bool ich9_can_do_33mhz(struct udevice *dev) { struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; @@ -173,8 +173,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, } if (opcode_index == ctlr->menubytes) { - printf("ICH SPI: Opcode %x not found\n", - trans->opcode); + debug("ICH SPI: Opcode %x not found\n", trans->opcode); return -EINVAL; } @@ -182,8 +181,8 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, optype = (optypes >> (opcode_index * 2)) & 0x3; if (optype != trans->type) { - printf("ICH SPI: Transaction doesn't fit type %d\n", - optype); + debug("ICH SPI: Transaction doesn't fit type %d\n", + optype); return -ENOSPC; } return opcode_index; @@ -214,9 +213,9 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, } udelay(10); } + debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n", + status, bitmask, wait_til_set, status & bitmask); - printf("ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); return -ETIMEDOUT; } From patchwork Fri Nov 22 04:18:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199240 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="npsEWRPt"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3mC5Hf6z9sNx for ; Fri, 22 Nov 2019 15:46:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4753BC2203A; Fri, 22 Nov 2019 04:33:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7F3B5C220D5; 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It reduces the amount of casting needed. Update the code and move the struct to the C file at the same time, as we will need to use with of-platdata. Signed-off-by: Simon Glass --- Changes in v4: - Use priv->pch instead of dev->parent Changes in v3: None Changes in v2: None drivers/spi/ich.c | 27 +++++++++++++-------------- drivers/spi/ich.h | 5 ----- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index b83dfb854d..08c37ca4ab 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -27,6 +27,12 @@ #define debug_trace(x, args...) #endif +struct ich_spi_platdata { + enum ich_version ich_version; /* Controller version, 7 or 9 */ + bool lockdown; /* lock down controller settings? */ + ulong mmio_base; /* Base of MMIO registers */ +}; + static u8 ich_readb(struct ich_spi_priv *priv, int reg) { u8 value = readb(priv->base + reg); @@ -467,16 +473,9 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { - ulong sbase_addr; - void *sbase; - - /* SBASE is similar */ - pch_get_spi_base(dev->parent, &sbase_addr); - sbase = (void *)sbase_addr; - debug("%s: sbase=%p\n", __func__, sbase); - + ctlr->base = (void *)plat->mmio_base; if (plat->ich_version == ICHV_7) { - struct ich7_spi_regs *ich7_spi = sbase; + struct ich7_spi_regs *ich7_spi = ctlr->base; ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); @@ -488,9 +487,8 @@ static int ich_init_controller(struct udevice *dev, ctlr->control = offsetof(struct ich7_spi_regs, spic); ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); ctlr->preop = offsetof(struct ich7_spi_regs, preop); - ctlr->base = ich7_spi; } else if (plat->ich_version == ICHV_9) { - struct ich9_spi_regs *ich9_spi = sbase; + struct ich9_spi_regs *ich9_spi = ctlr->base; ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); @@ -505,7 +503,6 @@ static int ich_init_controller(struct udevice *dev, ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; - ctlr->base = ich9_spi; } else { debug("ICH SPI: Unrecognised ICH version %d\n", plat->ich_version); @@ -516,8 +513,8 @@ static int ich_init_controller(struct udevice *dev, ctlr->max_speed = 20000000; if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) ctlr->max_speed = 33000000; - debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", - plat->ich_version, ctlr->base, ctlr->max_speed); + debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n", + plat->ich_version, plat->mmio_base, ctlr->max_speed); ich_set_bbar(ctlr, 0); @@ -605,6 +602,8 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); + pch_get_spi_base(priv->pch, &plat->mmio_base); + return 0; } diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 77057878a5..623b2c547a 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -168,11 +168,6 @@ enum ich_version { ICHV_9, }; -struct ich_spi_platdata { - enum ich_version ich_version; /* Controller version, 7 or 9 */ - bool lockdown; /* lock down controller settings? */ -}; - struct ich_spi_priv { int opmenu; int menubytes; From patchwork Fri Nov 22 04:18:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199283 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Bt7GSryB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Dm3y6Gz9sPc for ; Fri, 22 Nov 2019 16:07:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4BCC2C2219B; Fri, 22 Nov 2019 04:38:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B432CC220F1; Fri, 22 Nov 2019 04:24:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C3488C220C0; Fri, 22 Nov 2019 04:22:11 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id E350FC22054 for ; Fri, 22 Nov 2019 04:22:08 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id z26so2877526iot.8 for ; Thu, 21 Nov 2019 20:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4r9xY2c2OMdngS4txJdSw4Tyjvcks9v6DJs0N+Ne98A=; b=Bt7GSryB0h0qn6rWmG/3llnwkftxMjRvPToFL6fSBGhB1QbsRQIbcCsU9fLbytk+HB JPBBUBbR/wInNsndFHPqGckMZyzcrIo2uif2X4/OVSaOqZJuqFPvPzLAk9EniZ6+4bqm /9q+0GvRMsKDKlWHaqoiV3GsX/vw6ioeZHmVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4r9xY2c2OMdngS4txJdSw4Tyjvcks9v6DJs0N+Ne98A=; b=Hq6z3DnliPKKQaLEKza+j3XIh756mEwjz22Qq2MH7pH72DNWCnd7Xv8rO8t3k4P4GQ zXZwTF+JRkvx4xiy87mEdTh8lYP7tiZHuENvhBOa+cF+cZUS+Vsfy75P4LnIRGCsEltD Qjb9jmY72wSPl7fCnwxpoJhuHqhtwxHOtvzENh5b5GXn6G1fwMVKqi0HoaQcPEtCbcLf jlrO7l9AGBGKH9cuvcRTxXa+AotBAIGIlKK+5Z3D9phkIR0ezejlJzZOHin3O573lGNk YPvMpjEguR7Le2sgpxovKPKB5oex1xLwEsvs0kb09SzF4382vTB90mceKrfZ3Gnv/tve /hcg== X-Gm-Message-State: APjAAAVH4hH5ac+XflYuHgtfPvAqAP1QjNRRZeiMidRMYPu0jO6A/L6E lntV0wErGvvs4nTlTWnP7pjfNH6dKZk= X-Google-Smtp-Source: APXvYqwKsGZaz2407hJV54hvdHEzGLAHVytwukG5jFSeKkEYj8E2YEj0ErK8USFZBYLx0MxJpLHlNw== X-Received: by 2002:a6b:ba04:: with SMTP id k4mr11438614iof.131.1574396527624; Thu, 21 Nov 2019 20:22:07 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:07 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:35 -0700 Message-Id: <20191121211845.v4.70.I9b25f07ad6fbccec824c9d46fc6c9b998699e68d@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Pavel Herrmann Subject: [U-Boot] [PATCH v4 070/100] dm: doc: Add a note about of-platdata and header files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We don't want to include dt-structs.h in header files, so add a note about that. Signed-off-by: Simon Glass --- Changes in v4: - Add a patch to explain of-platdata and header files Changes in v3: None Changes in v2: None doc/driver-model/of-plat.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/driver-model/of-plat.rst b/doc/driver-model/of-plat.rst index 557957d2a1..034a68bb4e 100644 --- a/doc/driver-model/of-plat.rst +++ b/doc/driver-model/of-plat.rst @@ -279,6 +279,12 @@ For example: }; +Note that struct mmc_platdata is defined in the C file, not in a header. This +is to avoid needing to include dt-structs.h in a header file. The idea is to +keep the use of each of-platdata struct to the smallest possible code area. +There is just one driver C file for each struct, that can convert from the +of-platdata struct to the standard one used by the driver. + In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is still used to allocate space for the platform data. This is different from the normal behaviour and is triggered by the use of of-platdata (strictly From patchwork Fri Nov 22 04:18:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199275 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="NV1fQ9S0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K48z3vWgz9s7T for ; Fri, 22 Nov 2019 16:04:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 40EBAC22181; Fri, 22 Nov 2019 04:41:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 13E22C22077; Fri, 22 Nov 2019 04:27:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3B83BC220F9; Fri, 22 Nov 2019 04:22:14 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id EDBCDC2204A for ; Fri, 22 Nov 2019 04:22:10 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id z26so2877589iot.8 for ; Thu, 21 Nov 2019 20:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vsQRvs3iJJIWBu/sGlfJfwm8esKu9h0UXAxp5OcA8vw=; b=NV1fQ9S0RBntIeguwfEcUEQOYVPZ3vWA4lk/goM9WZak4s73NMFwz2N45++CgBEGdy d5RLt+OYqQn5TUHUpZiJeUB1Dlw95pjb3jI61rE6HegSQaCu8HC9JRQ5W91p2IN1Kf/N 9ciWCQXVRsVKQFO1Mv7eYbURqsrM99OYvURHs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vsQRvs3iJJIWBu/sGlfJfwm8esKu9h0UXAxp5OcA8vw=; b=C7DIVuC94Dw3ziEHUzPaHqL+0N9mJdhk5+AvAXKI7erOGIFPGi62XDBUC3qf7RiFnh 4J0UC97Ptl7vMl/Advd1ewCjPRyhwT8jNPEd1O56vVFabTH1h/TGRai2J4L+EM3+j/l+ rpJOdwwuSNaG2L/K/62IrIZqpmdbtnPNdfPDydStNPNiqCaL+yDTB1Nzhxo0U4YmbqY/ uLIKiWoTzpx2KZCVU89jkEh42/7HXRjVCQCqbPJ5uziy5/jRPp2IJIqxKjIm54Cmi4LX cBUFuAmf7MV+N73Ef7JGJiINU0+B77IO0Ks7XMmzfMbgb3Nk1fngxM08kYxaOdEf3EjY 9Lew== X-Gm-Message-State: APjAAAWj3QY+6eRqxWgKc/Yqi9IlIM1PrHg/pUQf0EseTa255tdNkXbX ZpJnuk0yqsJbCIdYNZ0MBbsPvqRC9pY= X-Google-Smtp-Source: APXvYqwg1k0JvkTLxyCL8cUXWmKILMTHWtjvtTBWScPf0hgQ1h5bisfdiFpRWVVOALJrfa100UXkJQ== X-Received: by 2002:a5d:8b85:: with SMTP id p5mr11375361iol.9.1574396529801; Thu, 21 Nov 2019 20:22:09 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:09 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:36 -0700 Message-Id: <20191122041905.224686-52-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 071/100] spi: ich: Correct max-size bug in ich_spi_adjust_size() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This incorrectly shortens read operations if there is a maximum write size but no maximum read size. Fix it. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 08c37ca4ab..17b7a0ba0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -425,9 +425,11 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) page_offset = do_div(aux, ICH_BOUNDARY); } - if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) { - op->data.nbytes = min(ICH_BOUNDARY - page_offset, - slave->max_read_size); + if (op->data.dir == SPI_MEM_DATA_IN) { + if (slave->max_read_size) { + op->data.nbytes = min(ICH_BOUNDARY - page_offset, + slave->max_read_size); + } } else if (slave->max_write_size) { op->data.nbytes = min(ICH_BOUNDARY - page_offset, slave->max_write_size); From patchwork Fri Nov 22 04:18:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199255 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="IWTXAWvP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3wc3CCJz9sPJ for ; Fri, 22 Nov 2019 15:53:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A2C39C220DE; Fri, 22 Nov 2019 04:31:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24464C220B7; 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Add of-platdata support for this using the "intel,fast-spi" compatible string. Signed-off-by: Simon Glass --- Changes in v4: - Use the new pci_ofplat_get_devfn() function Changes in v3: None Changes in v2: None drivers/spi/ich.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 17b7a0ba0b..7d66b900c8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -28,9 +29,13 @@ #endif struct ich_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_fast_spi dtplat; +#endif enum ich_version ich_version; /* Controller version, 7 or 9 */ bool lockdown; /* lock down controller settings? */ ulong mmio_base; /* Base of MMIO registers */ + pci_dev_t bdf; /* PCI address used by of-platdata */ }; static u8 ich_readb(struct ich_spi_priv *priv, int reg) @@ -594,6 +599,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ich_spi_priv *priv = dev_get_priv(dev); /* Find a PCH if there is one */ @@ -603,8 +610,13 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); +#else + plat->ich_version = ICHV_APL; + plat->mmio_base = plat->dtplat.early_regs[0]; + plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base); return 0; } @@ -632,8 +644,8 @@ static const struct udevice_id ich_spi_ids[] = { { } }; -U_BOOT_DRIVER(ich_spi) = { - .name = "ich_spi", +U_BOOT_DRIVER(intel_fast_spi) = { + .name = "intel_fast_spi", .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops, From patchwork Fri Nov 22 04:18:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199295 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Add support for this into the SPI driver, as an option. Signed-off-by: Simon Glass --- Changes in v4: - Fix comment for exec_sync_hwseq_xfer() - apollolake -> Apollo Lake Changes in v3: None Changes in v2: None drivers/spi/ich.c | 205 +++++++++++++++++++++++++++++++++++++++++++++- drivers/spi/ich.h | 39 +++++++++ 2 files changed, 241 insertions(+), 3 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 7d66b900c8..32d7ebce57 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include "ich.h" @@ -36,6 +38,7 @@ struct ich_spi_platdata { bool lockdown; /* lock down controller settings? */ ulong mmio_base; /* Base of MMIO registers */ pci_dev_t bdf; /* PCI address used by of-platdata */ + bool hwseq; /* Use hardware sequencing (not s/w) */ }; static u8 ich_readb(struct ich_spi_priv *priv, int reg) @@ -245,7 +248,8 @@ static void ich_spi_config_opcode(struct udevice *dev) ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); } -static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +static int ich_spi_exec_op_swseq(struct spi_slave *slave, + const struct spi_mem_op *op) { struct udevice *bus = dev_get_parent(slave->dev); struct ich_spi_platdata *plat = dev_get_platdata(bus); @@ -416,6 +420,197 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return 0; } +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross page boundary. + */ +static uint get_xfer_len(u32 offset, int len, int page_size) +{ + uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + uint bytes_left = ALIGN(offset, page_size) - offset; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +/* Fill FDATAn FIFO in preparation for a write transaction */ +static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data, + uint len) +{ + memcpy(regs->fdata, data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data */ +static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len) +{ + memcpy(dest, regs->fdata, len); +} + +/* Fire up a transfer using the hardware sequencer */ +static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle, + uint offset, uint len) +{ + /* Make sure all W1C status bits get cleared */ + u32 hsfsts; + + hsfsts = readl(®s->hsfsts_ctl); + hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK); + hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE; + + /* Set up transaction parameters */ + hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT; + hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK; + hsfsts |= HSFSTS_FGO; + + writel(offset, ®s->faddr); + writel(hsfsts, ®s->hsfsts_ctl); +} + +static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset) +{ + ulong start; + u32 hsfsts; + + start = get_timer(0); + do { + hsfsts = readl(®s->hsfsts_ctl); + if (hsfsts & HSFSTS_FCERR) { + debug("SPI transaction error at offset %x HSFSTS = %08x\n", + offset, hsfsts); + return -EIO; + } + if (hsfsts & HSFSTS_AEL) + return -EPERM; + + if (hsfsts & HSFSTS_FDONE) + return 0; + } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS); + + debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n", + offset, hsfsts, (uint)get_timer(start)); + + return -ETIMEDOUT; +} + +/** + * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing + * + * This waits until complete or timeout + * + * @regs: SPI registers + * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t) + * @offset: Offset to access + * @len: Number of bytes to transfer (can be 0) + * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error + * (AEL), -ETIMEDOUT on timeout + */ +static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle, + uint offset, uint len) +{ + start_hwseq_xfer(regs, hsfsts_cycle, offset, len); + + return wait_for_hwseq_xfer(regs, offset); +} + +static int ich_spi_exec_op_hwseq(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct spi_flash *flash = dev_get_uclass_priv(slave->dev); + struct udevice *bus = dev_get_parent(slave->dev); + struct ich_spi_priv *priv = dev_get_priv(bus); + struct fast_spi_regs *regs = priv->base; + uint page_size; + uint offset; + int cycle; + uint len; + bool out; + int ret; + u8 *buf; + + offset = op->addr.val; + len = op->data.nbytes; + + switch (op->cmd.opcode) { + case SPINOR_OP_RDID: + cycle = HSFSTS_CYCLE_RDID; + break; + case SPINOR_OP_READ_FAST: + cycle = HSFSTS_CYCLE_READ; + break; + case SPINOR_OP_PP: + cycle = HSFSTS_CYCLE_WRITE; + break; + case SPINOR_OP_WREN: + /* Nothing needs to be done */ + return 0; + case SPINOR_OP_WRSR: + cycle = HSFSTS_CYCLE_WR_STATUS; + break; + case SPINOR_OP_RDSR: + cycle = HSFSTS_CYCLE_RD_STATUS; + break; + case SPINOR_OP_WRDI: + return 0; /* ignore */ + case SPINOR_OP_BE_4K: + cycle = HSFSTS_CYCLE_4K_ERASE; + while (len) { + uint xfer_len = 0x1000; + + ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); + if (ret) + return ret; + offset += xfer_len; + len -= xfer_len; + } + return 0; + default: + debug("Unknown cycle %x\n", op->cmd.opcode); + return -EINVAL; + }; + + out = op->data.dir == SPI_MEM_DATA_OUT; + buf = out ? (u8 *)op->data.buf.out : op->data.buf.in; + page_size = flash->page_size ? : 256; + + while (len) { + uint xfer_len = get_xfer_len(offset, len, page_size); + + if (out) + fill_xfer_fifo(regs, buf, xfer_len); + + ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len); + if (ret) + return ret; + + if (!out) + drain_xfer_fifo(regs, buf, xfer_len); + + offset += xfer_len; + buf += xfer_len; + len -= xfer_len; + } + + return 0; +} + +static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + struct udevice *bus = dev_get_parent(slave->dev); + struct ich_spi_platdata *plat = dev_get_platdata(bus); + int ret; + + bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi"); + if (plat->hwseq) + ret = ich_spi_exec_op_hwseq(slave, op); + else + ret = ich_spi_exec_op_swseq(slave, op); + bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI); + + return ret; +} + static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) { unsigned int page_offset; @@ -583,9 +778,11 @@ static int ich_spi_child_pre_probe(struct udevice *dev) /* * Yes this controller can only write a small number of bytes at - * once! The limit is typically 64 bytes. + * once! The limit is typically 64 bytes. For hardware sequencing a + * a loop is used to get around this. */ - slave->max_write_size = priv->databytes; + if (!plat->hwseq) + slave->max_write_size = priv->databytes; /* * ICH 7 SPI controller only supports array read command * and byte program command for SST flash @@ -611,10 +808,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); pch_get_spi_base(priv->pch, &plat->mmio_base); + plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0); #else plat->ich_version = ICHV_APL; plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); + plat->hwseq = plat->dtplat.intel_hardware_seq; #endif debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base); diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 623b2c547a..c7cf37b932 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -163,6 +163,45 @@ struct spi_trans { #define ICH_BOUNDARY 0x1000 +#define HSFSTS_FDBC_SHIFT 24 +#define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT) +#define HSFSTS_WET BIT(21) +#define HSFSTS_FCYCLE_SHIFT 17 +#define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT) + +/* Supported flash cycle types */ +enum hsfsts_cycle_t { + HSFSTS_CYCLE_READ = 0, + HSFSTS_CYCLE_WRITE = 2, + HSFSTS_CYCLE_4K_ERASE, + HSFSTS_CYCLE_64K_ERASE, + HSFSTS_CYCLE_RDSFDP, + HSFSTS_CYCLE_RDID, + HSFSTS_CYCLE_WR_STATUS, + HSFSTS_CYCLE_RD_STATUS, +}; + +#define HSFSTS_FGO BIT(16) +#define HSFSTS_FLOCKDN BIT(15) +#define HSFSTS_FDV BIT(14) +#define HSFSTS_FDOPSS BIT(13) +#define HSFSTS_WRSDIS BIT(11) +#define HSFSTS_SAF_CE BIT(8) +#define HSFSTS_SAF_ACTIVE BIT(7) +#define HSFSTS_SAF_LE BIT(6) +#define HSFSTS_SCIP BIT(5) +#define HSFSTS_SAF_DLE BIT(4) +#define HSFSTS_SAF_ERROR BIT(3) +#define HSFSTS_AEL BIT(2) +#define HSFSTS_FCERR BIT(1) +#define HSFSTS_FDONE BIT(0) +#define HSFSTS_W1C_BITS 0xff + +/* Maximum bytes of data that can fit in FDATAn (0x10) registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000 + enum ich_version { ICHV_7, ICHV_9, From patchwork Fri Nov 22 04:18:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199250 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Simon Glass --- Changes in v4: - Use the new pci_ofplat_get_devfn() function Changes in v3: None Changes in v2: None drivers/spi/ich.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 32d7ebce57..ebf369f215 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -611,6 +611,37 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; } +static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep, + uint *map_sizep, uint *offsetp) +{ + pci_dev_t spi_bdf; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct pci_child_platdata *pplat = dev_get_parent_platdata(bus); + + spi_bdf = pplat->devfn; +#else + struct ich_spi_platdata *plat = dev_get_platdata(bus); + + /* + * We cannot rely on plat->bdf being set up yet since this method can + * be called before the device is probed. Use the of-platdata directly + * instead. + */ + spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + + return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp); +} + +static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, + uint *offsetp) +{ + struct udevice *bus = dev_get_parent(dev); + + return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp); +} + static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) { unsigned int page_offset; @@ -831,6 +862,7 @@ static const struct dm_spi_ops ich_spi_ops = { .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, + .get_mmap = ich_get_mmap, /* * cs_info is not needed, since we require all chip selects to be * in the device tree explicitly From patchwork Fri Nov 22 04:18:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199262 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="gv73zkvO"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K40F3HvTz9s7T for ; Fri, 22 Nov 2019 15:56:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 13184C22046; Fri, 22 Nov 2019 04:42:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5E97AC22049; Fri, 22 Nov 2019 04:28:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 35856C22063; Fri, 22 Nov 2019 04:22:27 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id 9D0EEC220A1 for ; Fri, 22 Nov 2019 04:22:23 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id q1so5556206ile.13 for ; Thu, 21 Nov 2019 20:22:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ULX1Wxyc5eaOBzcdUSo5h5HUl3m8IDTyViMloSO5fJA=; b=gv73zkvOcIvDfIE0CLXdWtfzNA860z9PzbOslRRDW0Ag8NNLKP5KzM9w+3P2bZu3VX fsJQOPAR+3xQK5ziTDlakv3rDptYWx9/4MloS9HDgPjTRBHZ8kdg4G/IM98b7RKlgIYQ ZX2pWYdy64+pECQVwWvAs6zKe9mzJXAPJHmcg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ULX1Wxyc5eaOBzcdUSo5h5HUl3m8IDTyViMloSO5fJA=; b=GIhQi94XJq+mQzQEYx8EGrAfnTuWq7S2990Apg/SsTXyPoLOV9fuN1Fy9loZw37mpc NhMGtsI5lr+tfOFeJaviMY15zRd+a58W8jeAxmvQJX4zzkBhNWReso8+qTJwMxM1sqiX +AJThz7Ef18ucBTDdMfr/Yb1tbJ9CM+TQqoaJQi2E3zLBk5mCQX8DRQGiCfzvq4N0COz yGBDl7stRwQdl6W7R4jnvM1xgGMtrRf0BT84NVnSTBu+m03ArqFhugEzmDQfkglgdSI2 E23ovHRIeSLrWTsBb4EgVRgEKppkZChshgQLZJ2C9hORfCMUXi82F7pHx3L0UpBTMScn mdrQ== X-Gm-Message-State: APjAAAWq9EzRnlsPDF9GjuJ17Lvv3DSMeijHYKbcs0wCsKViewwWoR40 cLLV9cf3bsG24MsqosUzlkGk7CZk8tE= X-Google-Smtp-Source: APXvYqws/hSJAkNDxs8642fGXn2X3Gr7PNcW/v1c7g0pN58AKz/u46+rlqkv6aE7SsfbnS8XiKfRZQ== X-Received: by 2002:a92:6609:: with SMTP id a9mr14824935ilc.131.1574396542475; Thu, 21 Nov 2019 20:22:22 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:22 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:40 -0700 Message-Id: <20191122041905.224686-55-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 075/100] spi: ich: Add TPL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/ich.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index ebf369f215..02601e9125 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -19,8 +19,10 @@ #include #include #include +#include #include #include +#include #include "ich.h" @@ -115,6 +117,8 @@ static bool ich9_can_do_33mhz(struct udevice *dev) struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; + if (!CONFIG_IS_ENABLED(PCI)) + return false; /* Observe SPI Descriptor Component Section 0 */ dm_pci_write_config32(priv->pch, 0xb0, 0x1000); @@ -706,6 +710,15 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { + if (spl_phase() == PHASE_TPL) { + struct ich_spi_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = fast_spi_early_init(plat->bdf, plat->mmio_base); + if (ret) + return ret; + } + ctlr->base = (void *)plat->mmio_base; if (plat->ich_version == ICHV_7) { struct ich7_spi_regs *ich7_spi = ctlr->base; @@ -754,6 +767,25 @@ static int ich_init_controller(struct udevice *dev, return 0; } +static int ich_cache_bios_region(struct udevice *dev) +{ + ulong map_base; + uint map_size; + uint offset; + ulong base; + int ret; + + ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset); + if (ret) + return ret; + + base = (4ULL << 30) - map_size; + mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size); + log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size); + + return 0; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -764,10 +796,16 @@ static int ich_spi_probe(struct udevice *dev) if (ret) return ret; - ret = ich_protect_lockdown(dev); - if (ret) - return ret; - + if (spl_phase() == PHASE_TPL) { + /* Cache the BIOS to speed things up */ + ret = ich_cache_bios_region(dev); + if (ret) + return ret; + } else { + ret = ich_protect_lockdown(dev); + if (ret) + return ret; + } priv->cur_speed = priv->max_speed; return 0; From patchwork Fri Nov 22 04:18:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199286 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="oDdFk8RJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4GS6P7dz9sPW for ; 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Thu, 21 Nov 2019 20:22:24 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:23 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:41 -0700 Message-Id: <20191122041905.224686-56-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 076/100] spi: ich: Add Apollo Lake support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: None Changes in v2: None drivers/spi/ich.c | 19 ++++++++++++++----- drivers/spi/ich.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 02601e9125..52a75167b1 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -105,10 +105,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; - minaddr &= bbar_mask; - ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + if (ctlr->bbar) { + minaddr &= bbar_mask; + ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + } } /* @return 1 if the SPI flash supports the 33MHz speed */ @@ -749,6 +751,7 @@ static int ich_init_controller(struct udevice *dev, ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; + } else if (plat->ich_version == ICHV_APL) { } else { debug("ICH SPI: Unrecognised ICH version %d\n", plat->ich_version); @@ -876,7 +879,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); + if (plat->ich_version == ICHV_APL) { + plat->mmio_base = dm_pci_read_bar32(dev, 0); + } else { + /* SBASE is similar */ + pch_get_spi_base(priv->pch, &plat->mmio_base); + } plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0); #else plat->ich_version = ICHV_APL; @@ -910,6 +918,7 @@ static const struct dm_spi_ops ich_spi_ops = { static const struct udevice_id ich_spi_ids[] = { { .compatible = "intel,ich7-spi", ICHV_7 }, { .compatible = "intel,ich9-spi", ICHV_9 }, + { .compatible = "intel,fast-spi", ICHV_APL }, { } }; diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index c7cf37b932..d7f1ffdf37 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -205,6 +205,7 @@ enum hsfsts_cycle_t { enum ich_version { ICHV_7, ICHV_9, + ICHV_APL, }; struct ich_spi_priv { From patchwork Fri Nov 22 04:18:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199290 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XFhcQORz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4HT6HsHz9sPW for ; Fri, 22 Nov 2019 16:09:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 9E531C221D5; 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Thu, 21 Nov 2019 20:22:26 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:25 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:42 -0700 Message-Id: <20191122041905.224686-57-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Cc: Jagannadha Sutradharudu Teki Subject: [U-Boot] [PATCH v4 077/100] mtd: spi: Export spi_flash_std_probe() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With of-platdata we need to create drivers for particular chips, or at least drivers that are separate from the standard code, since C structures are created by dtoc which are private to that driver. To avoid duplicating the probing code, export this probe function for use by these drivers. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/mtd/spi/sf_probe.c | 2 +- include/spi_flash.h | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index f051e473ff..72b6ee702d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -137,7 +137,7 @@ static int spi_flash_std_get_sw_write_prot(struct udevice *dev) return spi_flash_cmd_get_sw_write_prot(flash); } -static int spi_flash_std_probe(struct udevice *dev) +int spi_flash_std_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); diff --git a/include/spi_flash.h b/include/spi_flash.h index 55b4721813..0b23f57a71 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -102,6 +102,18 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len); */ int spl_flash_get_sw_write_prot(struct udevice *dev); +/** + * spi_flash_std_probe() - Probe a SPI flash device + * + * This is the standard internal method for probing a SPI flash device to + * determine its type. It can be used in chip-specific drivers which need to + * do this, typically with of-platdata + * + * @dev: SPI-flash device to probe + * @return 0 if OK, -ve on error + */ +int spi_flash_std_probe(struct udevice *dev); + int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode, struct udevice **devp); From patchwork Fri Nov 22 04:18:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199257 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XHBUnzq4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3z971Htz9sPJ for ; Fri, 22 Nov 2019 15:55:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8A960C220EA; Fri, 22 Nov 2019 04:45:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2F897C22093; Fri, 22 Nov 2019 04:37:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8978CC22104; Fri, 22 Nov 2019 04:22:33 +0000 (UTC) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by lists.denx.de (Postfix) with ESMTPS id 71282C21FD1 for ; Fri, 22 Nov 2019 04:22:29 +0000 (UTC) Received: by mail-io1-f65.google.com with SMTP id z26so2878159iot.8 for ; Thu, 21 Nov 2019 20:22:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t1YXUzqGALVJ462p5NbJZcsvxK+hRaRmGq7TyCfkKAQ=; b=XHBUnzq4K98ivedH8VqPwuMHCGWOEglwS4eASILriE89BhCvvuI8uTu/YQQMyo56lG 9FjD5vLpcMzfm0Skf5aFj2s5FOG96SFj1QxzEXHeAlDb8NjpTFxKGbPrSfgs2+ZHfwlN t36M6+17U+a3vBLJBjkw3AL387P7Rr/Px8nfQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t1YXUzqGALVJ462p5NbJZcsvxK+hRaRmGq7TyCfkKAQ=; b=IR+G+HTiQvtn7ul3A+PpEbnHM0XWTAGvXMu357+DVj8olQCBc7xaWviW1x+R5UlMl4 eFtn2RlSWuIMNWQ+YnKJ/t5GGFYYA/Pr8JvO6rUVbozeV+qya0VPct9NRUhF96UEdlTJ vDc1o97Jt1zqjfvxsSVKBJ5MD1kd1ARR9ha2tBGdYEHogIgt75eBYOiwNgh8/izPe0pW A5QooROnr3iLuVCOyNsgFuYjSV7YPhXcRHNA5Ysx6rRxG3VwiOE0XCcCJZ+aAkOSs9Gj nhwrwKhPmeHOINaw+oKtYWNxFvBR6MoDYv4S6kb9yyl/nwWL/VMh8Cr+TrTH2V2t3f97 AUMw== X-Gm-Message-State: APjAAAWahO6u19Daa6RG1215HEAdMX7RmehfpeuMOqPtGSabo6qZ4/Oj XdvfCW4hlCo2zQZ6BT7l9CKlp2h7Vac= X-Google-Smtp-Source: APXvYqz8BjdaQ5heqKvEfzYIkEQ2Il3qIuaGObqU9+0NUACeObbB0Ko5NPqExl7QKj53u00nrvyhCA== X-Received: by 2002:a02:3085:: with SMTP id q127mr11587461jaq.140.1574396548116; Thu, 21 Nov 2019 20:22:28 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:27 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:43 -0700 Message-Id: <20191122041905.224686-58-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 078/100] x86: Enable pinctrl in SPL and TPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If these phases are used we typically want to enable pinctrl in then, so that pad setup and GPIO access are possible. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None arch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index 54de91afb3..ae9c93ed7b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -193,6 +193,7 @@ config X86 imply SPL_OF_LIBFDT imply SPL_DRIVERS_MISC_SUPPORT imply SPL_GPIO_SUPPORT + imply SPL_PINCTRL imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT imply SPL_SERIAL_SUPPORT @@ -206,6 +207,7 @@ config X86 imply TPL_DM imply TPL_DRIVERS_MISC_SUPPORT imply TPL_GPIO_SUPPORT + imply TPL_PINCTRL imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SERIAL_SUPPORT From patchwork Fri Nov 22 04:18:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199297 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="lT4hZSZ7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Mx3BwTz9sPc for ; Fri, 22 Nov 2019 16:13:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 19975C2222D; Fri, 22 Nov 2019 04:51:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CAF15C22035; Fri, 22 Nov 2019 04:51:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A9AB0C220BB; Fri, 22 Nov 2019 04:22:34 +0000 (UTC) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by lists.denx.de (Postfix) with ESMTPS id 4EBF3C220B2 for ; Fri, 22 Nov 2019 04:22:31 +0000 (UTC) Received: by mail-io1-f66.google.com with SMTP id 1so6427663iou.4 for ; Thu, 21 Nov 2019 20:22:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E1+v1Bc3VWh7/+sfTVISjfRQjBvC5FN7iwH/BTxZP+Y=; b=lT4hZSZ7Iirfpt5TiVqqLKrJ7ImBYxJWV+nKXpyKbP3hblpq77v171NWe/l6wYxZ8l T9xc4o8fh3KDuqBIbfd9aMetmUX5POaSrxf7fomISc9fqfqTQCpEhZr/+hXRhb3D7MMV lavGGv5RENCfEEsBM7v37xnHY9Gc0cPFAFSp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E1+v1Bc3VWh7/+sfTVISjfRQjBvC5FN7iwH/BTxZP+Y=; b=QCLNoaFvukklPQwk4VVKP9uKOCRwKiVtJMpXixOYsyE4S4xRvnMp6NzrXm1ux7PcaY VMyHtWEJyw/8AOiwW14mHcZlk8K/N8djb9fCobeuWNQdwdJ0kFkhlaiEeGgPlRFJviKS /V//dRtOTV8N1qRB5n6J88YKqzYGchQWvm5sdB/oCXXvFOMbCQ24HWSWUDNBisgLf5Eg jug3KSo8BU0ysnw/jNq5DARyk5B2y7+4nd6+EXCRcAYoUHUhfZxb9ZLue8/SrmO8ePT5 GuAI/wigyNv1vx7Iv31drEXKBNxRDITvhoK0Gx9n7g9JRgqi/+wdvriuVkHjJqIXj7AK 6Amw== X-Gm-Message-State: APjAAAULlYiThdmntVh8Y/euRK6b0CwKcuXIjstOMNqE19vBwLMDd2uV 0xk9QuUJJqs/W6+FjFZV5siQReUktVo= X-Google-Smtp-Source: APXvYqwnaN3V/PJry6BOBz9XjiTMvta4MUDxeku5OavxvdPc+uf+tIY16ZgAWI5dFUBFNJZ7cJkWwA== X-Received: by 2002:a5d:8501:: with SMTP id q1mr5916073ion.268.1574396550129; Thu, 21 Nov 2019 20:22:30 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:29 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:44 -0700 Message-Id: <20191122041905.224686-59-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 079/100] x86: Add low-power subsystem (lpss) support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass --- Changes in v4: - Add support for updating power state - Move this to intel_common Changes in v3: None Changes in v2: None arch/x86/cpu/intel_common/Makefile | 1 + arch/x86/cpu/intel_common/lpss.c | 44 ++++++++++++++++++++++++++++++ arch/x86/include/asm/lpss.h | 36 ++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 arch/x86/cpu/intel_common/lpss.c create mode 100644 arch/x86/include/asm/lpss.h diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 09212cee04..cc4e1c962b 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -19,6 +19,7 @@ endif obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o +obj-y += lpss.o ifndef CONFIG_TARGET_EFI_APP obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/intel_common/lpss.c b/arch/x86/cpu/intel_common/lpss.c new file mode 100644 index 0000000000..26a2d2d1e3 --- /dev/null +++ b/arch/x86/cpu/intel_common/lpss.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Special driver to handle of-platdata + * + * Copyright 2019 Google LLC + * + * Some code from coreboot lpss.c + */ + +#include +#include +#include +#include +#include + +enum { + LPSS_RESET_CTL_REG = 0x204, + + /* + * Bit 1:0 controls LPSS controller reset. + * + * 00 ->LPSS Host Controller is in reset (Reset Asserted) + * 01/10 ->Reserved + * 11 ->LPSS Host Controller is NOT at reset (Reset Released) + */ + LPSS_CNT_RST_RELEASE = 3, + + /* Power management control and status register */ + PME_CTRL_STATUS = 0x84, + + /* Bit 1:0 Powerstate, controls D0 and D3 state */ + POWER_STATE_MASK = 3, +}; + +/* Take controller out of reset */ +void lpss_reset_release(void *regs) +{ + writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG); +} + +void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state) +{ + dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state); +} diff --git a/arch/x86/include/asm/lpss.h b/arch/x86/include/asm/lpss.h new file mode 100644 index 0000000000..7814872688 --- /dev/null +++ b/arch/x86/include/asm/lpss.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_LPSS_H +#define __ASM_LPSS_H + +struct udevice; + +/* D0 and D3 enable config */ +enum lpss_pwr_state { + STATE_D0 = 0, + STATE_D3 = 3 +}; + +/** + * lpss_reset_release() - Release device from reset + * + * This is used for devices which have LPSS support. + * + * @regs: Pointer to device registers + */ +void lpss_reset_release(void *regs); + +/** + * lpss_set_power_state() - Change power state of a device + * + * This is used for devices which have LPSS support. + * + * @dev: Device to update + * @state: New power state to set + */ +void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state); + +#endif From patchwork Fri Nov 22 04:18:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199276 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="hivHofKJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K49M6fmcz9s7T for ; Fri, 22 Nov 2019 16:04:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A296EC2217C; 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Thu, 21 Nov 2019 20:22:32 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:31 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:45 -0700 Message-Id: <20191122041905.224686-60-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 080/100] x86: Add a generic Intel pinctrl driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass --- Changes in v4: - Add a binding file - Split out GPIO code from the pinctrl driver - Switch over to use pinctrl for pad init/config Changes in v3: None Changes in v2: None arch/x86/include/asm/intel_pinctrl.h | 293 +++++++++ arch/x86/include/asm/intel_pinctrl_defs.h | 386 +++++++++++ .../pinctrl/intel,apl-pinctrl.txt | 39 ++ drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/intel/Kconfig | 7 + drivers/pinctrl/intel/Makefile | 5 + drivers/pinctrl/intel/pinctrl.c | 615 ++++++++++++++++++ 8 files changed, 1355 insertions(+) create mode 100644 arch/x86/include/asm/intel_pinctrl.h create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt create mode 100644 drivers/pinctrl/intel/Kconfig create mode 100644 drivers/pinctrl/intel/Makefile create mode 100644 drivers/pinctrl/intel/pinctrl.c diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h new file mode 100644 index 0000000000..6e727b584e --- /dev/null +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Copyright 2019 Google LLC + * + * Modified from coreboot gpio.h + */ + +#ifndef __ASM_INTEL_PINCTRL_H +#define __ASM_INTEL_PINCTRL_H + +#include + +/** + * struct pad_config - config for a pad + * @pad: offset of pad within community + * @pad_config: Pad config data corresponding to DW0, DW1, etc. + */ +struct pad_config { + int pad; + u32 pad_config[4]; +}; + +#include + +/* GPIO community IOSF sideband clock gating */ +#define MISCCFG_GPSIDEDPCGEN BIT(5) +/* GPIO community RCOMP clock gating */ +#define MISCCFG_GPRCOMPCDLCGEN BIT(4) +/* GPIO community RTC clock gating */ +#define MISCCFG_GPRTCDLCGEN BIT(3) +/* GFX controller clock gating */ +#define MISCCFG_GSXSLCGEN BIT(2) +/* GPIO community partition clock gating */ +#define MISCCFG_GPDPCGEN BIT(1) +/* GPIO community local clock gating */ +#define MISCCFG_GPDLCGEN BIT(0) +/* Enable GPIO community power management configuration */ +#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ + | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + +/* + * GPIO numbers may not be contiguous and instead will have a different + * starting pin number for each pad group. + */ +#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + group_pad_base) \ + { \ + .first_pad = (start_of_group) - (first_of_community), \ + .size = (end_of_group) - (start_of_group) + 1, \ + .acpi_pad_base = (group_pad_base), \ + } + +/* + * A pad base of -1 indicates that this group uses contiguous numbering + * and a pad base should not be used for this group. + */ +#define PAD_BASE_NONE -1 + +/* The common/default group numbering is contiguous */ +#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ + INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + PAD_BASE_NONE) + +/** + * struct reset_mapping - logical to actual value for PADRSTCFG in DW0 + * + * Note that the values are expected to be within the field placement of the + * register itself. i.e. if the reset field is at 31:30 then the values within + * logical and chipset should occupy 31:30. + */ +struct reset_mapping { + u32 logical; + u32 chipset; +}; + +/** + * struct pad_group - describes the groups within each community + * + * @first_pad: offset of first pad of the group relative to the community + * @size: size of the group + * @acpi_pad_base: starting pin number for the pads in this group when they are + * used in ACPI. This is only needed if the pins are not contiguous across + * groups. Most groups will have this set to PAD_BASE_NONE and use + * contiguous numbering for ACPI. + */ +struct pad_group { + int first_pad; + uint size; + int acpi_pad_base; +}; + +/** + * struct pad_community - community of pads + * + * This describes a community, or each group within a community when multiple + * groups exist inside a community + * + * @name: Community name + * @acpi_path: ACPI path + * @num_gpi_regs: number of gpi registers in community + * @max_pads_per_group: number of pads in each group; number of pads bit-mapped + * in each GPI status/en and Host Own Reg + * @first_pad: first pad in community + * @last_pad: last pad in community + * @host_own_reg_0: offset to Host Ownership Reg 0 + * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0 + * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0 + * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0 + * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0 + * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg + * @gpi_status_offset: specifies offset in struct gpi_status + * @port: PCR Port ID + * @reset_map: PADRSTCFG logical to chipset mapping + * @num_reset_vals: number of values in @reset_map + * @groups; list of groups for this community + * @num_groups: number of groups + */ +struct pad_community { + const char *name; + const char *acpi_path; + size_t num_gpi_regs; + size_t max_pads_per_group; + uint first_pad; + uint last_pad; + u16 host_own_reg_0; + u16 gpi_int_sts_reg_0; + u16 gpi_int_en_reg_0; + u16 gpi_smi_sts_reg_0; + u16 gpi_smi_en_reg_0; + u16 pad_cfg_base; + u8 gpi_status_offset; + u8 port; + const struct reset_mapping *reset_map; + size_t num_reset_vals; + const struct pad_group *groups; + size_t num_groups; +}; + +/** + * struct intel_pinctrl_priv - private data for each pinctrl device + * + * @comm: Pad community for this device + * @num_cfgs: Number of configuration words for each pad + * @itss: ITSS device (for interrupt handling) + * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register + * Each bit represents IRQx Active High Polarity Disable configuration: + * when set to 1, the interrupt polarity associated with IRQx is inverted + * to appear as Active Low to IOAPIC and vice versa + */ +struct intel_pinctrl_priv { + const struct pad_community *comm; + int num_cfgs; + struct udevice *itss; + bool itss_pol_cfg; +}; + +/* Exported common operations for the pinctrl driver */ +extern const struct pinctrl_ops intel_pinctrl_ops; + +/* Exported common probe function for the pinctrl driver */ +int intel_pinctrl_probe(struct udevice *dev); + +/** + * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup + * + * @dev: Pinctrl device + * @comm: Pad community for this device + * @num_cfgs: Number of configuration words for each pad + * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error + */ +int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, + const struct pad_community *comm, + int num_cfgs); + +/** + * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks + * + * The values from PMC register GPE_CFG are passed which is then mapped to + * proper groups for MISCCFG. This basically sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + * + * @dev: ITSS device + * @gpe0b: Value for GPE0B + * @gpe0c: Value for GPE0C + * @gpe0d: Value for GPE0D + * @return 0 if OK, -ve on error + */ +int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d); + +/** + * pinctrl_config_pads() - Configure a list of pads + * + * Configures multiple pads using the provided data from the device tree. + * + * @dev: pinctrl device (any will do) + * @pads: Pad data, consisting of a pad number followed by num_cfgs entries + * containing the data for that pad (num_cfgs is set by the pinctrl device) + * @pads_count: Number of pads to configure + * @return 0 if OK, -ve on error + */ +int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count); + +/** + * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use + * + * This enables the interrupt inputs and clears the status register bits + * + * @return 0 if OK, -ve on error + */ +int pinctrl_gpi_clear_int_cfg(void); + +/** + * pinctrl_config_pads_for_node() - Configure pads + * + * Set up the pads using the data in a given node + * + * @dev: pinctrl device (any will do) + * @node: Node containing the 'pads' property with the data in it + * @return 0 if OK, -ve on error + */ +int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node); + +/** + * pinctrl_read_pads() - Read pad data from a node + * + * @dev: pinctrl device (any will do, it is just used to get config) + * @node: Node to read pad data from + * @prop: Property name to use (e.g. "pads") + * @padsp: Returns a pointer to an allocated array of pad data, in the format: + * + * + * + * ... + * + * The number of pad config values is set by the pinctrl controller. + * The caller must free this array. + * @pad_countp: Returns the number of pads read + * @ereturn 0 if OK, -ve on error + */ +int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop, + u32 **padsp, int *pad_countp); + +/** + * pinctrl_count_pads() - Count the number of pads in a pad array + * + * This used used with of-platdata where the array may be smaller than its + * maximum size. This function searches for the last pad in the array by finding + * the first 'zero' record + * + * This works out the number of records in the array. Each record has one word + * for the pad and num_cfgs words for the config. + * + * @dev: pinctrl device (any will do) + * @pads: Array of pad data + * @size: Size of pad data in bytes + * @return number of pads represented by the data + */ +int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size); + +/** + * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers + * + * @dev: Pinctrl device + * @offset: GPIO offset within this device + * @return register offset within the GPIO p2sb region + */ +u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset); + +/** + * intel_pinctrl_get_config_reg() - Get the value of a GPIO register + * + * @dev: Pinctrl device + * @offset: GPIO offset within this device + * @return register value within the GPIO p2sb region + */ +u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset); + +/** + * intel_pinctrl_get_pad() - Get pad information for a pad + * + * This is used by the GPIO controller to find the pinctrl used by a pad. + * + * @pad: Pad to check + * @devp: Returns pinctrl device containing that pad + * @offsetp: Returns offset of pad within that pinctrl device + */ +int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp); + +#endif diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h new file mode 100644 index 0000000000..edffe7d1ea --- /dev/null +++ b/arch/x86/include/asm/intel_pinctrl_defs.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright 2019 Google LLC + * + * Modified from coreboot gpio_defs.h + */ + +#ifndef _ASM_INTEL_PINCTRL_DEFS_H_ +#define _ASM_INTEL_PINCTRL_DEFS_H_ + +/* This file is included by device trees, so avoid BIT() macros */ + +#define PAD_CFG0_TX_STATE_BIT 0 +#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) +#define PAD_CFG0_RX_STATE_BIT 1 +#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) +#define PAD_CFG0_TX_DISABLE (1 << 8) +#define PAD_CFG0_RX_DISABLE (1 << 9) + +#define PAD_CFG0_MODE_SHIFT 10 +#define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT) + +#define PAD_CFG0_ROUTE_MASK (0xf << 17) +#define PAD_CFG0_ROUTE_NMI (1 << 17) +#define PAD_CFG0_ROUTE_SMI (1 << 18) +#define PAD_CFG0_ROUTE_SCI (1 << 19) +#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_RXTENCFG_MASK (3 << 21) +#define PAD_CFG0_RXINV_MASK (1 << 23) +#define PAD_CFG0_RX_POL_INVERT (1 << 23) +#define PAD_CFG0_RX_POL_NONE (0 << 23) +#define PAD_CFG0_PREGFRXSEL (1 << 24) +#define PAD_CFG0_TRIG_MASK (3 << 25) +#define PAD_CFG0_TRIG_LEVEL (0 << 25) +#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ +#define PAD_CFG0_TRIG_OFF (2 << 25) +#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_RXRAW1_MASK (1 << 28) +#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) +#define PAD_CFG0_RESET_MASK (3 << 30) +#define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30) +#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) +#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) +#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) + +/* + * Use the fourth bit in IntSel field to indicate gpio ownership. This field is + * RO and hence not used during gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) +#define PAD_CFG1_IRQ_MASK (0xff << 0) +#define PAD_CFG1_IOSTERM_MASK (0x3 << 8) +#define PAD_CFG1_IOSTERM_SAME (0x0 << 8) +#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) +#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) +#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) +#define PAD_CFG1_PULL_MASK (0xf << 10) +#define PAD_CFG1_PULL_NONE (0x0 << 10) +#define PAD_CFG1_PULL_DN_5K (0x2 << 10) +#define PAD_CFG1_PULL_DN_20K (0x4 << 10) +#define PAD_CFG1_PULL_UP_1K (0x9 << 10) +#define PAD_CFG1_PULL_UP_5K (0xa << 10) +#define PAD_CFG1_PULL_UP_2K (0xb << 10) +#define PAD_CFG1_PULL_UP_20K (0xc << 10) +#define PAD_CFG1_PULL_UP_667 (0xd << 10) +#define PAD_CFG1_PULL_NATIVE (0xf << 10) + +/* Tx enabled driving last value driven, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14) +/* + * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14) +/* + * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14) +/* + * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14) +/* + * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14) +/* Tx enabled driving 0, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14) +/* Tx enabled driving 1, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14) +/* Hi-Z, Rx driving 0 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14) +/* Hi-Z, Rx driving 1 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14) +/* Tx disabled, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14) +#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ +/* mask to extract Iostandby bits */ +#define PAD_CFG1_IOSSTATE_MASK (0xf << 14) +#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ + +#define PAD_CFG2_DEBEN 1 +/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ +#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) +#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) +#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) +#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) +#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) +#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) +#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) +#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) +#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) +#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) +#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) +#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) +#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) +#define PAD_CFG2_DEBOUNCE_MASK 0x1f + +/* voltage tolerance 0=3.3V default 1=1.8V tolerant */ +#if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY) +#define PAD_CFG1_TOL_MASK (0x1 << 25) +#define PAD_CFG1_TOL_1V8 (0x1 << 25) +#endif + +#define PAD_FUNC(value) PAD_CFG0_MODE_##value +#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_PULL(value) PAD_CFG1_PULL_##value + +#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value +#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value + +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_CFG0_ROUTE_##route | \ + PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_POL_##inv) + +#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) +#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ + (PAD_CFG0_ROUTE_##route1 | \ + PAD_CFG0_ROUTE_##route2 | \ + PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_POL_##inv) +#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ + +#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ + __pad(__config0) (__config1) + +#if GPIO_NUM_PAD_CFG_REGS > 2 +#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .pad_config[2] = __config2, \ + } +#else +#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ + _PAD_CFG_STRUCT(__pad, __config0, __config1) +#endif + +/* Native function configuration */ +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(TX_LAST_RXE)) + +#if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL) +/* + * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not + * applicable to all SOCs. Refer EDS. + */ +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ + PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8) +#endif + +/* Native function configuration for standby state */ +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate)) + +/* + * Native function configuration for standby state, also configuring iostandby + * as masked + */ +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(IGNORE)) + +/* + * Native function configuration for standby state, also configuring iosstate + * and iosterm + */ +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* General purpose output, no pullup/down */ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE)) + +/* General purpose output, with termination specified */ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE)) + +/* General purpose output, no pullup/down */ +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \ + PAD_CFG1_GPIO_DRIVER) + +/* General purpose output */ +#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + +/* General purpose input */ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to GPIO Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* GPIO Interrupt */ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +/* + * No Connect configuration for unused pad. + * Both TX and RX are disabled. RX disabling is done to avoid unnecessary + * setting of GPI_STS. + */ +#define PAD_NC(pad, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to APIC */ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to APIC - with IOStandby Config*/ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* + * The following APIC macros assume the APIC will handle the filtering + * on its own end. One just needs to pass an active high message into the + * ITSS. + */ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) + +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) + +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) + +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) + +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) + +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) + +/* General purpose input, routed to NMI */ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) +/* GPI, GPIO Driver, SCI interrupt */ +#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ + PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) + +#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ + +#endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */ diff --git a/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt b/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt new file mode 100644 index 0000000000..cd7f8a0ca3 --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt @@ -0,0 +1,39 @@ +* Intel Apollo Lake pin controller + +The Apollo Lake (APL) pin controller is used to select the function of a pin +and to configure it. + +Required properties: +- compatible: "intel,apl-pinctrl" +- intel,p2sb-port-id: Port ID number within the parent P2SB +- reg: PCI address of the controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Optional subnodes: + +GPIO nodes may be added as children of the pinctrl nodes. See intel,apl-gpio +for the binding. + + +Example: + +... +{ + p2sb: p2sb@d,0 { + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = ; + + n { + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = ; + gpio_n: gpio-n { + compatible = "intel,apl-gpio"; + #gpio-cells = <2>; + }; + }; + }; +}; +... diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 449f614eb2..83e39b9de3 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -177,6 +177,14 @@ config PINCTRL_AT91PIO4 This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC. +config PINCTRL_INTEL + bool "Standard Intel pin-control and pin-mux driver" + help + Recent Intel chips such as Apollo Lake (APL) use a common pin control + and GPIO scheme. The settings for this come from an SoC-specific + driver which must be separately enabled. The driver supports setting + pins on start-up and changing the GPIO attributes. + config PINCTRL_PIC32 bool "Microchip PIC32 pin-control and pin-mux driver" depends on DM && MACH_PIC32 @@ -280,6 +288,7 @@ endif source "drivers/pinctrl/broadcom/Kconfig" source "drivers/pinctrl/exynos/Kconfig" +source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mscc/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ce0879a2b7..4f662c4f6d 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,6 +9,7 @@ obj-y += nxp/ obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ +obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig new file mode 100644 index 0000000000..727b743431 --- /dev/null +++ b/drivers/pinctrl/intel/Kconfig @@ -0,0 +1,7 @@ +# +# Intel PINCTRL drivers +# + +if PINCTRL_INTEL + +endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile new file mode 100644 index 0000000000..bc1aad2c06 --- /dev/null +++ b/drivers/pinctrl/intel/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += pinctrl.o diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c new file mode 100644 index 0000000000..69402c713a --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corp. + * Copyright 2019 Google LLC + * + * Taken partly from coreboot gpio.c + * + * Pinctrl is modelled as a separate device-tree node and device for each + * 'community' (basically a set of GPIOs). The separate devices work together + * and many functions permit any PINCTRL device to be provided as a parameter, + * since the pad numbering is unique across all devices. + * + * Each pinctrl has a single child GPIO device to handle GPIO access and + * therefore there is a simple GPIO driver included in this file. + */ + +#define LOG_CATEGORY UCLASS_GPIO + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_DW_SIZE(x) (sizeof(u32) * (x)) +#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num)) +#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0) +#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1) + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + +#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \ + ((group) * sizeof(u32))) +#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ + ((group) * sizeof(u32))) +#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \ + ((group) * sizeof(uint32_t))) +#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \ + ((group) * sizeof(uint32_t))) + +/** + * relative_pad_in_comm() - Get the relative position of a GPIO + * + * This finds the position of a GPIO within a community + * + * @comm: Community to search + * @gpio: Pad number to look up (assumed to be valid) + * @return offset, 0 for first GPIO in community + */ +static size_t relative_pad_in_comm(const struct pad_community *comm, + uint gpio) +{ + return gpio - comm->first_pad; +} + +/** + * pinctrl_group_index() - Find group for a a pad + * + * Find the group within the community that the pad is a part of + * + * @comm: Community to search + * @relative_pad: Pad to look up + * @return group number if found (see community_n_groups, etc.), or + * -ESPIPE if no groups, or -ENOENT if not found + */ +static int pinctrl_group_index(const struct pad_community *comm, + uint relative_pad) +{ + int i; + + if (!comm->groups) + return -ESPIPE; + + /* find the base pad number for this pad's group */ + for (i = 0; i < comm->num_groups; i++) { + if (relative_pad >= comm->groups[i].first_pad && + relative_pad < comm->groups[i].first_pad + + comm->groups[i].size) + return i; + } + + return -ENOENT; +} + +static int pinctrl_group_index_scaled(const struct pad_community *comm, + uint relative_pad, size_t scale) +{ + int ret; + + ret = pinctrl_group_index(comm, relative_pad); + if (ret < 0) + return ret; + + return ret * scale; +} + +static int pinctrl_within_group(const struct pad_community *comm, + uint relative_pad) +{ + int ret; + + ret = pinctrl_group_index(comm, relative_pad); + if (ret < 0) + return ret; + + return relative_pad - comm->groups[ret].first_pad; +} + +static u32 pinctrl_bitmask_within_group(const struct pad_community *comm, + uint relative_pad) +{ + return 1U << pinctrl_within_group(comm, relative_pad); +} + +/** + * pinctrl_get_device() - Find the device for a particular pad + * + * Each pinctr, device is attached to one community and this supports a number + * of pads. This function finds the device which controls a particular pad. + * + * @pad: Pad to check + * @devp: Returns the device for that pad + * @return 0 if OK, -ENOTBLK if no device was found for the given pin + */ +static int pinctrl_get_device(uint pad, struct udevice **devp) +{ + struct udevice *dev; + + /* + * We have to probe each one of these since the community link is only + * attached in intel_pinctrl_ofdata_to_platdata(). + */ + uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) { + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + + if (pad >= comm->first_pad && pad <= comm->last_pad) { + *devp = dev; + return 0; + } + } + printf("pad %d not found\n", pad); + + return -ENOTBLK; +} + +int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp) +{ + const struct pad_community *comm; + struct intel_pinctrl_priv *priv; + struct udevice *dev; + int ret; + + ret = pinctrl_get_device(pad, &dev); + if (ret) + return log_msg_ret("pad", ret); + priv = dev_get_priv(dev); + comm = priv->comm; + *devp = dev; + *offsetp = relative_pad_in_comm(comm, pad); + + return 0; +} + +static int pinctrl_configure_owner(struct udevice *dev, + const struct pad_config *cfg, + const struct pad_community *comm) +{ + u32 hostsw_own; + u16 hostsw_own_offset; + int pin; + int ret; + + pin = relative_pad_in_comm(comm, cfg->pad); + + /* + * Based on the gpio pin number configure the corresponding bit in + * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. + */ + hostsw_own_offset = comm->host_own_reg_0; + ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32)); + if (ret < 0) + return ret; + hostsw_own_offset += ret; + + hostsw_own = pcr_read32(dev, hostsw_own_offset); + + /* + *The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. Set the bit if GPIO driver ownership + * requested, otherwise clear the bit. + */ + if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + hostsw_own |= pinctrl_bitmask_within_group(comm, pin); + else + hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin); + + pcr_write32(dev, hostsw_own_offset, hostsw_own); + + return 0; +} + +static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg, + const struct pad_community *comm) +{ + u32 value; + u16 sts_reg; + u16 en_reg; + int group; + int pin; + int ret; + + if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) + return 0; + + pin = relative_pad_in_comm(comm, cfg->pad); + ret = pinctrl_group_index(comm, pin); + if (ret < 0) + return ret; + group = ret; + + sts_reg = GPI_SMI_STS_OFFSET(comm, group); + value = pcr_read32(dev, sts_reg); + /* Write back 1 to reset the sts bits */ + pcr_write32(dev, sts_reg, value); + + /* Set enable bits */ + en_reg = GPI_SMI_EN_OFFSET(comm, group); + pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin)); + + return 0; +} + +static int pinctrl_configure_itss(struct udevice *dev, + const struct pad_config *cfg, + uint pad_cfg_offset) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->itss_pol_cfg) + return -ENOSYS; + + int irq; + + /* + * Set up ITSS polarity if pad is routed to APIC. + * + * The ITSS takes only active high interrupt signals. Therefore, + * if the pad configuration indicates an inversion assume the + * intent is for the ITSS polarity. Before forwarding on the + * request to the APIC there's an inversion setting for how the + * signal is forwarded to the APIC. Honor the inversion setting + * in the GPIO pad configuration so that a hardware active low + * signal looks that way to the APIC (double inversion). + */ + if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) + return 0; + + irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset)); + irq &= PAD_CFG1_IRQ_MASK; + if (!irq) { + log_err("GPIO %u doesn't support APIC routing\n", cfg->pad); + + return -EPROTONOSUPPORT; + } + irq_set_polarity(priv->itss, irq, + cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT); + + return 0; +} + +/* Number of DWx config registers can be different for different SOCs */ +static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad) +{ + const struct pad_community *comm = priv->comm; + size_t offset; + + offset = relative_pad_in_comm(comm, pad); + offset *= GPIO_DW_SIZE(priv->num_cfgs); + + return offset + comm->pad_cfg_base; +} + +static int pinctrl_pad_reset_config_override(const struct pad_community *comm, + u32 config_value) +{ + const struct reset_mapping *rst_map = comm->reset_map; + int i; + + /* Logical reset values equal chipset values */ + if (!rst_map || !comm->num_reset_vals) + return config_value; + + for (i = 0; i < comm->num_reset_vals; i++, rst_map++) { + if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) { + config_value &= ~PAD_CFG0_RESET_MASK; + config_value |= rst_map->chipset; + + return config_value; + } + } + log_err("Logical-to-Chipset mapping not found\n"); + + return -ENOENT; +} + +static const int mask[4] = { + PAD_CFG0_TX_STATE | + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK | + PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | + PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | + PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK, + +#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY + PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK, +#else + PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK, +#endif + + PAD_CFG2_DEBOUNCE_MASK, + + 0, +}; + +/** + * pinctrl_configure_pad() - Configure a pad + * + * @dev: Pinctrl device containing the pad (see pinctrl_get_device()) + * @cfg: Configuration to apply + * @return 0 if OK, -ve on error + */ +static int pinctrl_configure_pad(struct udevice *dev, + const struct pad_config *cfg) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint config_offset; + u32 pad_conf, soc_pad_conf; + int ret; + int i; + + if (IS_ERR(comm)) + return PTR_ERR(comm); + config_offset = pad_config_offset(priv, cfg->pad); + for (i = 0; i < priv->num_cfgs; i++) { + pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i)); + + soc_pad_conf = cfg->pad_config[i]; + if (i == 0) { + ret = pinctrl_pad_reset_config_override(comm, + soc_pad_conf); + if (ret < 0) + return ret; + soc_pad_conf = ret; + } + soc_pad_conf &= mask[i]; + soc_pad_conf |= pad_conf & ~mask[i]; + + log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), i, + pad_conf,/* old value */ + /* value passed from pinctrl table */ + cfg->pad_config[i], + soc_pad_conf); /*new value*/ + pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i), + soc_pad_conf); + } + ret = pinctrl_configure_itss(dev, cfg, config_offset); + if (ret && ret != -ENOSYS) + return log_msg_ret("itss config failed", ret); + ret = pinctrl_configure_owner(dev, cfg, comm); + if (ret) + return ret; + ret = gpi_enable_smi(dev, cfg, comm); + if (ret) + return ret; + + return 0; +} + +u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint config_offset; + + assert(device_get_uclass_id(dev) == UCLASS_PINCTRL); + config_offset = comm->pad_cfg_base + offset * + GPIO_DW_SIZE(priv->num_cfgs); + + return config_offset; +} + +u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset) +{ + uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset); + + return pcr_read32(dev, config_offset); +} + +int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d) +{ + struct udevice *pinctrl_dev; + u32 misccfg_value; + u32 misccfg_clr; + int ret; + + /* + * Get the group here for community specific MISCCFG register. + * If any of these returns -1 then there is some error in devicetree + * where the group is probably hardcoded and does not comply with the + * PMC group defines. So we return from here and MISCFG is set to + * default. + */ + ret = irq_route_pmc_gpio_gpe(itss, gpe0b); + if (ret) + return ret; + gpe0b = ret; + + ret = irq_route_pmc_gpio_gpe(itss, gpe0c); + if (ret) + return ret; + gpe0c = ret; + + ret = irq_route_pmc_gpio_gpe(itss, gpe0d); + if (ret) + return ret; + gpe0d = ret; + + misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; + misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; + misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; + + /* Program GPIO_MISCCFG */ + misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK; + + log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr, + misccfg_value); + uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) { + pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr, + misccfg_value); + } + + return 0; +} + +int pinctrl_gpi_clear_int_cfg(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_PINCTRL, &uc); + if (ret) + return log_msg_ret("pinctrl uc", ret); + uclass_foreach_dev(dev, uc) { + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint sts_value; + int group; + + for (group = 0; group < comm->num_gpi_regs; group++) { + /* Clear the enable register */ + pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0); + + /* Read and clear the set status register bits*/ + sts_value = pcr_read32(dev, + GPI_IS_OFFSET(comm, group)); + pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value); + } + } + + return 0; +} + +int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const u32 *ptr; + int i; + + log_debug("%s: pads_count=%d\n", __func__, pads_count); + for (ptr = pads, i = 0; i < pads_count; + ptr += 1 + priv->num_cfgs, i++) { + struct udevice *pad_dev = NULL; + struct pad_config *cfg; + int ret; + + cfg = (struct pad_config *)ptr; + ret = pinctrl_get_device(cfg->pad, &pad_dev); + if (ret) + return ret; + ret = pinctrl_configure_pad(pad_dev, cfg); + if (ret) + return ret; + } + + return 0; +} + +int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop, + u32 **padsp, int *pad_countp) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + u32 *pads; + int size; + int ret; + + *padsp = NULL; + *pad_countp = 0; + size = ofnode_read_size(node, prop); + if (size < 0) + return 0; + + pads = malloc(size); + if (!pads) + return -ENOMEM; + size /= sizeof(fdt32_t); + ret = ofnode_read_u32_array(node, prop, pads, size); + if (ret) { + free(pads); + return ret; + } + *pad_countp = size / (1 + priv->num_cfgs); + *padsp = pads; + + return 0; +} + +int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int count = 0; + int i; + + for (i = 0; i < size;) { + u32 val; + int j; + + for (val = j = 0; j < priv->num_cfgs + 1; j++) + val |= pads[i + j]; + if (!val) + break; + count++; + i += priv->num_cfgs + 1; + } + + return count; +} + +int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node) +{ + int pads_count; + u32 *pads; + int ret; + + if (device_get_uclass_id(dev) != UCLASS_PINCTRL) + return log_msg_ret("uclass", -EPROTONOSUPPORT); + ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count); + if (ret) + return log_msg_ret("no pads", ret); + ret = pinctrl_config_pads(dev, pads, pads_count); + free(pads); + if (ret) + return log_msg_ret("pad config", ret); + + return 0; +} + +int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, + const struct pad_community *comm, + int num_cfgs) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int ret; + + if (!comm) { + log_err("Cannot find community for pid %d\n", pplat->pid); + return -EDOM; + } + ret = uclass_first_device_err(UCLASS_IRQ, &priv->itss); + if (ret) + return log_msg_ret("Cannot find ITSS", ret); + priv->comm = comm; + priv->num_cfgs = num_cfgs; + + return 0; +} + +int intel_pinctrl_probe(struct udevice *dev) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + + priv->itss_pol_cfg = true; + + return 0; +} + +const struct pinctrl_ops intel_pinctrl_ops = { +}; From patchwork Fri Nov 22 04:18:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199243 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="j7J4OeN2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3pF2Jqwz9sNx for ; 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Thu, 21 Nov 2019 20:22:34 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:33 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:46 -0700 Message-Id: <20191121211845.v4.81.I364be7c3fc47205b9e5f90030ae246c8e85cb9f1@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 081/100] x86: Add a generic Intel GPIO driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a GPIO driver which uses the pinctrl driver to access the pad information. This driver relies on the GPIO nodes being subnodes to the pinctrl device. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None Changes in v2: None .../gpio/intel,apl-gpio.txt | 55 ++++++ drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/intel_gpio.c | 161 ++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt create mode 100644 drivers/gpio/intel_gpio.c diff --git a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt new file mode 100644 index 0000000000..e34e7c3501 --- /dev/null +++ b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt @@ -0,0 +1,55 @@ +* Intel Apollo Lake GPIO controller + +The Apollo Lake (APL) GPIO controller is used to control GPIO functions of +the pins. + +Required properties: +- compatible: "intel,apl-gpio" +- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client + nodes should be the following with values derived from the SoC user manual. + <[phandle of the gpio controller node] + [pin number within the gpio controller] + [flags]> + + Values for gpio specifier: + - Pin number: is a GPIO pin number between 0 and 244 + - Flags: GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW + +- gpio-controller: Specifies that the node is a gpio controller. + +Example: + +... +{ + p2sb: p2sb@d,0 { + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = ; + + n { + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = ; + gpio_n: gpio-n { + compatible = "intel,apl-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + i2c_2: i2c2@16,2 { + compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; + reg = <0x0200b210 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + tpm@50 { + reg = <0x50>; + compatible = "google,cr50"; + u-boot,i2c-offset-len = <0>; + ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>; + }; + }; + +}; +... diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 447cf04578..1de6f5225e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -104,6 +104,15 @@ config INTEL_BROADWELL_GPIO driver from the common Intel ICH6 driver. It supports a total of 95 GPIOs which can be configured from the device tree. +config INTEL_GPIO + bool "Intel generic GPIO driver" + depends on DM_GPIO + help + Say yes here to select Intel generic GPIO driver. This controller + supports recent chips (e.g. Apollo Lake). It permits basic GPIO + control including setting pins to input/output. It makes use of its + parent pinctrl driver to actually effect changes. + config INTEL_ICH6_GPIO bool "Intel ICH6 compatible legacy GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3612e66786..449046b64c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c new file mode 100644 index 0000000000..eeff95de7b --- /dev/null +++ b/drivers/gpio/intel_gpio.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int intel_gpio_direction_input(struct udevice *dev, uint offset) +{ + struct udevice *pinctrl = dev_get_parent(dev); + uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + + pcr_clrsetbits32(pinctrl, config_offset, + PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE | + PAD_CFG0_RX_DISABLE, + PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE); + + return 0; +} + +static int intel_gpio_direction_output(struct udevice *dev, uint offset, + int value) +{ + struct udevice *pinctrl = dev_get_parent(dev); + uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + + pcr_clrsetbits32(dev, config_offset, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE | + PAD_CFG0_TX_DISABLE, + PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE | + (value ? PAD_CFG0_TX_STATE : 0)); + + return 0; +} + +static int intel_gpio_get_value(struct udevice *dev, uint offset) +{ + struct udevice *pinctrl = dev_get_parent(dev); + uint mode, rx_tx; + u32 reg; + + reg = intel_pinctrl_get_config_reg(pinctrl, offset); + mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT; + if (!mode) { + rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE); + if (rx_tx == PAD_CFG0_TX_DISABLE) + return mode & PAD_CFG0_RX_STATE_BIT ? 1 : 0; + else if (rx_tx == PAD_CFG0_RX_DISABLE) + return mode & PAD_CFG0_TX_STATE_BIT ? 1 : 0; + } + + return 0; +} + +static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value) +{ + struct udevice *pinctrl = dev_get_parent(dev); + uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + + pcr_clrsetbits32(dev, config_offset, PAD_CFG0_TX_STATE, + value ? PAD_CFG0_TX_STATE : 0); + + return 0; +} + +static int intel_gpio_get_function(struct udevice *dev, uint offset) +{ + struct udevice *pinctrl = dev_get_parent(dev); + uint mode, rx_tx; + u32 reg; + + reg = intel_pinctrl_get_config_reg(pinctrl, offset); + mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT; + if (!mode) { + rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE); + if (rx_tx == PAD_CFG0_TX_DISABLE) + return GPIOF_INPUT; + else if (rx_tx == PAD_CFG0_RX_DISABLE) + return GPIOF_OUTPUT; + } + + return GPIOF_FUNC; +} + +static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + struct udevice *pinctrl, *dev; + int gpio, ret; + + /* + * GPIO numbers are global in the device tree so it doesn't matter + * which hone is used + */ + gpio = args->args[0]; + ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset); + if (ret) + return log_msg_ret("bad", ret); + device_find_first_child(pinctrl, &dev); + if (!dev) + return log_msg_ret("no child", -ENOENT); + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + desc->dev = dev; + + return 0; +} + +static int intel_gpio_probe(struct udevice *dev) +{ + return 0; +} + +static int intel_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev); + struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent); + const struct pad_community *comm = pinctrl_priv->comm; + + upriv->gpio_count = comm->last_pad - comm->first_pad + 1; + upriv->bank_name = dev->name; + + return 0; +} + +static const struct dm_gpio_ops gpio_intel_ops = { + .direction_input = intel_gpio_direction_input, + .direction_output = intel_gpio_direction_output, + .get_value = intel_gpio_get_value, + .set_value = intel_gpio_set_value, + .get_function = intel_gpio_get_function, + .xlate = intel_gpio_xlate, +}; + +static const struct udevice_id intel_intel_gpio_ids[] = { + { .compatible = "intel,apl-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_intel) = { + .name = "gpio_intel", + .id = UCLASS_GPIO, + .of_match = intel_intel_gpio_ids, + .ops = &gpio_intel_ops, + .ofdata_to_platdata = intel_gpio_ofdata_to_platdata, + .probe = intel_gpio_probe, +}; From patchwork Fri Nov 22 04:18:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199278 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="WMt9u+Z6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4BF02CXz9s7T for ; Fri, 22 Nov 2019 16:05:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A2C53C22178; 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Thu, 21 Nov 2019 20:22:36 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:35 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:47 -0700 Message-Id: <20191122041905.224686-61-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 082/100] x86: apl: Add basic IO addresses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass --- Changes in v4: - Drop TCO_BASE_ADDRESS - Tidy up header guards Changes in v3: None Changes in v2: None arch/x86/include/asm/arch-apollolake/iomap.h | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h new file mode 100644 index 0000000000..d6be06fc01 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_IOMAP_H +#define _ASM_ARCH_IOMAP_H + +#define R_ACPI_PM1_TMR 0x8 + +/* Put p2sb at 0xd0000000 in TPL */ +#define IOMAP_P2SB_BAR 0xd0000000 + +#define IOMAP_SPI_BASE 0xfe010000 +/* + * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial + * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. + */ +#define PCH_DEV_UART PCI_BDF(0, 0x18, 2) + +#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) +#define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2) + +#endif From patchwork Fri Nov 22 04:18:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199277 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XczriUAu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K49V4T9hz9sPc for ; Fri, 22 Nov 2019 16:04:46 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 53C5EC22185; Fri, 22 Nov 2019 04:38:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 140B9C220D9; Fri, 22 Nov 2019 04:24:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 550C0C220F3; Fri, 22 Nov 2019 04:22:46 +0000 (UTC) Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by lists.denx.de (Postfix) with ESMTPS id 55E7AC22019 for ; Fri, 22 Nov 2019 04:22:39 +0000 (UTC) Received: by mail-io1-f45.google.com with SMTP id s3so6442255ioe.3 for ; Thu, 21 Nov 2019 20:22:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7ZtO4hoCxWlUiDyMEkkLOgW2tmSDZWUzvwkNKbh+aa4=; b=XczriUAuFQGXNVQ3ZtCnQvgTgLfAsjAdehPmZsYoaG3WcyPuA2YseEBegeC3cTgheF u+AfbRCixxwPTjuM6Cq3D39gzZlIXpRBtsTUJH2cflR1YzNMl2j2VHhm0Y2utWD/QdlK 6qzUs+pziCUnjvDTCp2fK0O0fJjHtvcqbOrq0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ZtO4hoCxWlUiDyMEkkLOgW2tmSDZWUzvwkNKbh+aa4=; b=tOIeTyOd9Q/4kjhkEqakc9PulCDLz4H1Z29Q+BQurDT2JCde5+HufvD6tYcDYwqtT9 VyHxNVuxlQk2w9BOtYvP9y6Onhg7ycNSdMQN60m/hbbBSNHdH886G88T08w6MKACaTGM L+PaSDufxVpnUE3tELl2WBIdkuBExAXhbRT2TBxHYYjjlexatFJWxD6hCZpHEwsppdJQ hmdgIl5qzQryIKvSl3MBgWYNpAXh2hoz4hEsxftsrnsEX/qs091UZJ/DM5okcqquVGjP I/IaCMIiINfyCkhPEKNPGplVWRw9TyjiKojI0V94QlQmjW2+TQOPfF2LdRg/XOR400J0 y4Xg== X-Gm-Message-State: APjAAAWXsYqjY7WQAw0pmFyp2dPE5vs5bNInbmsnLacCuHvUWj7l3y8x +kwA8TRhqkXyFEvgT4THzz4HnLNt9bs= X-Google-Smtp-Source: APXvYqwqIg2PTLaDgJSXVbpRq5IWfL2JNmGU/c+qqCvPPVc1IwKZjwWAJJNPIPTp16nESyyvqrHGzg== X-Received: by 2002:a5e:de08:: with SMTP id e8mr11035909iok.4.1574396557938; Thu, 21 Nov 2019 20:22:37 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:37 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:48 -0700 Message-Id: <20191122041905.224686-62-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 083/100] x86: apl: Add PMC driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass --- Changes in v4: - Fix Makefile copyright message - Fix incorrect mask check in pmc_gpe_init() - Switch over to use pinctrl for pad init/config - Tidy up header guards - Use pci_ofplat_get_devfn() - apollolake -> Apollo Lake Changes in v3: - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 5 + arch/x86/cpu/apollolake/pmc.c | 216 ++++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/pm.h | 19 ++ drivers/power/acpi_pmc/acpi-pmc-uclass.c | 56 ++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/x86/cpu/apollolake/Makefile create mode 100644 arch/x86/cpu/apollolake/pmc.c create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile new file mode 100644 index 0000000000..5e136b6515 --- /dev/null +++ b/arch/x86/cpu/apollolake/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += pmc.o diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c new file mode 100644 index 0000000000..683c6082f2 --- /dev/null +++ b/arch/x86/cpu/apollolake/pmc.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corporation. + * Copyright 2019 Google LLC + * + * Modified from coreboot pmclib.c, pmc.c and pmutil.c + */ + +#define LOG_CATEGORY UCLASS_ACPI_PMC + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_GPE_CFG 0x1050 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +#define COLD_BOOT_STS BIT(27) +#define COLD_RESET_STS BIT(26) +#define WARM_RESET_STS BIT(25) +#define GLOBAL_RESET_STS BIT(24) +#define SRS BIT(20) +#define MS4V BIT(18) +#define RPS BIT(2) +#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \ + WARM_RESET_STS | GLOBAL_RESET_STS | \ + SRS | MS4V) +#define GEN_PMCON2 0x1024 +#define GEN_PMCON3 0x1028 + +/* Offset of TCO registers from ACPI base I/O address */ +#define TCO_REG_OFFSET 0x60 +#define TCO1_STS 0x64 +#define DMISCI_STS BIT(9) +#define BOOT_STS BIT(18) +#define TCO2_STS 0x66 +#define TCO1_CNT 0x68 +#define TCO_LOCK BIT(12) +#define TCO2_CNT 0x6a + +enum { + ETR = 0x1048, + CF9_LOCK = 1UL << 31, + CF9_GLB_RST = 1 << 20, +}; + +struct apl_pmc_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_pmc dtplat; +#endif + pci_dev_t bdf; +}; + +static int apl_pmc_fill_power_state(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS); + upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS); + + upriv->prsts = readl(upriv->pmc_bar0 + PRSTS); + upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1); + upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2); + upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3); + + return 0; +} + +static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + /* WAK_STS bit will not be set when waking from G3 state */ + if (!(upriv->pm1_sts & WAK_STS) && + (upriv->gen_pmcon1 & COLD_BOOT_STS)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +static int apl_disable_tco(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET); + + return 0; +} + +static int apl_global_reset_set_enable(struct udevice *dev, bool enable) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + if (enable) + setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST); + else + clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST); + + return 0; +} + +int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct apl_pmc_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 base[6]; + int size; + int ret; + + ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + upriv->pmc_bar0 = (void *)base[0]; + upriv->pmc_bar2 = (void *)base[2]; + upriv->acpi_base = base[4]; + + /* Since PCI is not enabled, we must get the BDF manually */ + plat->bdf = pci_get_devfn(dev); + if (plat->bdf < 0) + return log_msg_ret("Cannot get PMC PCI address", plat->bdf); + + /* Get the dwX values for pmc gpe settings */ + size = dev_read_size(dev, "gpe0-dw"); + if (size < 0) + return log_msg_ret("Cannot read gpe0-dm", size); + upriv->gpe0_count = size / sizeof(u32); + ret = dev_read_u32_array(dev, "gpe0-dw", upriv->gpe0_dw, + upriv->gpe0_count); + if (ret) + return log_msg_ret("Bad gpe0-dw", ret); + + return pmc_ofdata_to_uc_platdata(dev); +#else + struct dtd_intel_apl_pmc *dtplat = &plat->dtplat; + + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + upriv->pmc_bar0 = (void *)dtplat->early_regs[0]; + upriv->pmc_bar2 = (void *)dtplat->early_regs[2]; + upriv->acpi_base = dtplat->early_regs[4]; + upriv->gpe0_dwx_mask = dtplat->gpe0_dwx_mask; + upriv->gpe0_dwx_shift_base = dtplat->gpe0_dwx_shift_base; + upriv->gpe0_sts_reg = dtplat->gpe0_sts; + upriv->gpe0_sts_reg += upriv->acpi_base; + upriv->gpe0_en_reg = dtplat->gpe0_en; + upriv->gpe0_en_reg += upriv->acpi_base; + upriv->gpe0_count = min((int)ARRAY_SIZE(dtplat->gpe0_dw), GPE0_REG_MAX); + memcpy(upriv->gpe0_dw, dtplat->gpe0_dw, sizeof(dtplat->gpe0_dw)); +#endif + upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG); + + return 0; +} + +static int enable_pmcbar(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct apl_pmc_platdata *priv = dev_get_platdata(dev); + pci_dev_t pmc = priv->bdf; + + /* + * Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit + * BARs. + */ + pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0, + PCI_SIZE_32); + pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); + pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2, + PCI_SIZE_32); + pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32); + pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base, + PCI_SIZE_16); + pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, + PCI_SIZE_16); + + return 0; +} + +static int apl_pmc_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return enable_pmcbar(dev); + + return 0; +} + +static struct acpi_pmc_ops apl_pmc_ops = { + .init = apl_pmc_fill_power_state, + .prev_sleep_state = apl_prev_sleep_state, + .disable_tco = apl_disable_tco, + .global_reset_set_enable = apl_global_reset_set_enable, +}; + +static const struct udevice_id apl_pmc_ids[] = { + { .compatible = "intel,apl-pmc" }, + { } +}; + +U_BOOT_DRIVER(apl_pmc) = { + .name = "intel_apl_pmc", + .id = UCLASS_ACPI_PMC, + .of_match = apl_pmc_ids, + .ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata, + .probe = apl_pmc_probe, + .ops = &apl_pmc_ops, + .platdata_auto_alloc_size = sizeof(struct apl_pmc_platdata), +}; diff --git a/arch/x86/include/asm/arch-apollolake/pm.h b/arch/x86/include/asm/arch-apollolake/pm.h new file mode 100644 index 0000000000..557fb9538e --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/pm.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Lance Zhao for Intel Corp.) + */ + +#ifndef _ASM_ARCH_PM_H +#define _ASM_ARCH_PM_H + +#define PMC_GPE_SW_31_0 0 +#define PMC_GPE_SW_63_32 1 +#define PMC_GPE_NW_31_0 3 +#define PMC_GPE_NW_63_32 4 +#define PMC_GPE_NW_95_64 5 +#define PMC_GPE_N_31_0 6 +#define PMC_GPE_N_63_32 7 +#define PMC_GPE_W_31_0 9 + +#endif diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c index 653c71b948..d43de87126 100644 --- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -9,6 +9,9 @@ #include #include #include +#ifdef CONFIG_X86 +#include +#endif #include #include @@ -34,6 +37,59 @@ enum { TCO1_CNT_HLT = 1 << 11, }; +#ifdef CONFIG_X86 +static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum) +{ + return upriv->gpe0_dwx_shift_base + regnum * 4; +} + +int pmc_gpe_init(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct udevice *itss; + u32 *dw; + u32 gpio_cfg_mask; + u32 gpio_cfg; + int ret, i; + u32 mask; + + if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC) + return log_msg_ret("uclass", -EPROTONOSUPPORT); + dw = upriv->gpe0_dw; + mask = upriv->gpe0_dwx_mask; + gpio_cfg_mask = 0; + for (i = 0; i < upriv->gpe0_count; i++) { + gpio_cfg_mask |= mask << gpe0_shift(upriv, i); + if (dw[i] & ~mask) + return log_msg_ret("Base GPE0 value", -EINVAL); + } + + /* + * Route the GPIOs to the GPE0 block. Determine that all values + * are different and if they aren't, use the reset values. + */ + if (dw[0] == dw[1] || dw[1] == dw[2]) { + log_info("PMC: Using default GPE route"); + gpio_cfg = readl(upriv->gpe_cfg); + for (i = 0; i < upriv->gpe0_count; i++) + dw[i] = gpio_cfg >> gpe0_shift(upriv, i); + } else { + gpio_cfg = 0; + for (i = 0; i < upriv->gpe0_count; i++) + gpio_cfg |= dw[i] << gpe0_shift(upriv, i); + clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg); + } + + /* Set the routes in the GPIO communities as well */ + ret = uclass_first_device_err(UCLASS_IRQ, &itss); + if (ret) + return log_msg_ret("Cannot find itss", ret); + pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]); + + return 0; +} +#endif /* CONFIG_X86 */ + static void pmc_fill_pm_reg_info(struct udevice *dev) { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); From patchwork Fri Nov 22 04:18:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199270 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="WN8LzTsm"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K45t4gTBz9s7T for ; Fri, 22 Nov 2019 16:01:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5E14BC2211D; Fri, 22 Nov 2019 04:44:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E1677C22095; Fri, 22 Nov 2019 04:34:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70C1BC22036; Fri, 22 Nov 2019 04:22:47 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id CDAB8C220B2 for ; Fri, 22 Nov 2019 04:22:41 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id x21so6437166ior.2 for ; Thu, 21 Nov 2019 20:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DmTKQ1CR2sy6JGZLbu+Pml/YUBMrF1YmtS53Xo+jsDM=; b=WN8LzTsmJhGbHmZE9K5+3o99TyuEBj2BGc3eGLmtqQ+j5Gwe416s7oEQGoJTn6NCxn 96qUhDLBrNa57r7SJRU5dr0o5ljmxK8WOUIAgCJa4NNbwVhcyjyRynmgryuY3vRVZv6b bvT8fJYaN29YrjlTbTQ1TbPsVQfVKqVmfKgXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DmTKQ1CR2sy6JGZLbu+Pml/YUBMrF1YmtS53Xo+jsDM=; b=VYLaYptPMpztR/9VFdagQ4VlFLkZgShTzlAOlKABwPLVNruzoi4tsoL16orEYSZQ7B L5LnG34c/hFN5WStzOTVR71Vb11B9PhlftcOrS2Su6daX2No8cb7qiGX58tuO6tbWrLx tEymAf4aPT9Ij4xvzq9MdWyXycaRzwHYCKv0V0Vx2GYSCWHxj6tiyaLwXc/TPIytzfaq OuCy3ubpbrAesKd7Sbs+IH3kcVAjKUCLDSlY8tnl+QuxalPwfIJxKgEQhY4dwieB0hIS ObH6qAzPeRzxFlk+sMsbl0dsUGp/QPjHqzjRR68s5KqeTUpXw3hJuD6DfHHkMsq4tcAJ sZdg== X-Gm-Message-State: APjAAAVG1j9mVXTuIZFs2x7Av76uSjhlLElfe0KWb0uAnTxB78JlSReT g1nLrvFG4mAdgdGhmgKvl1f/6yvfLec= X-Google-Smtp-Source: APXvYqzk+aRgvkX0UxCN1nUDE2mPIVGkEQxm0nh0+db6BnYR4/D0CKuJnC317vZwqUJ7GzmFAt+f+g== X-Received: by 2002:a6b:9254:: with SMTP id u81mr10639457iod.126.1574396559930; Thu, 21 Nov 2019 20:22:39 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:39 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:49 -0700 Message-Id: <20191122041905.224686-63-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 084/100] x86: apl: Add UART driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass --- Changes in v4: - Add an extra comment to apl_uart_init() - Tidy up header guards - apollolake -> Apollo Lake Changes in v3: - Use the LPSS code from a separate file Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/uart.c | 141 ++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/uart.h | 20 +++ 3 files changed, 162 insertions(+) create mode 100644 arch/x86/cpu/apollolake/uart.c create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 5e136b6515..fdda748ea3 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC obj-y += pmc.o +obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c new file mode 100644 index 0000000000..1dc4d33e52 --- /dev/null +++ b/arch/x86/cpu/apollolake/uart.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Special driver to handle of-platdata + * + * Copyright 2019 Google LLC + * + * Some code from coreboot lpss.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Low-power Subsystem (LPSS) clock register */ +enum { + LPSS_CLOCK_CTL_REG = 0x200, + LPSS_CNT_CLOCK_EN = 1, + LPSS_CNT_CLK_UPDATE = 1U << 31, + LPSS_CLOCK_DIV_N_SHIFT = 16, + LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT, + LPSS_CLOCK_DIV_M_SHIFT = 1, + LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT, + + /* These set the UART input clock speed */ + LPSS_UART_CLK_M_VAL = 0x25a, + LPSS_UART_CLK_N_VAL = 0x7fff, +}; + +static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val) +{ + u32 clk_sel; + + clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | + clk_m_val << LPSS_CLOCK_DIV_M_SHIFT; + clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; + + writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); +} + +static void uart_lpss_init(void *regs) +{ + /* Take UART out of reset */ + lpss_reset_release(regs); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL); +} + +void apl_uart_init(pci_dev_t bdf, ulong base) +{ + /* Set UART base address */ + pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32); + + /* Enable memory access and bus master */ + pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER, PCI_SIZE_32); + + uart_lpss_init((void *)base); +} + +/* + * This driver uses its own compatible string but almost everything else from + * the standard ns16550 driver. This allows us to provide an of-platdata + * implementation, since the platdata produced by of-platdata does not match + * struct ns16550_platdata. + * + * When running with of-platdata (generally TPL), the platdata is converted to + * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot + * proper), we use ns16550's ofdata_to_platdata routine. + */ + +static int apl_ns16550_probe(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + + if (!CONFIG_IS_ENABLED(PCI)) + apl_uart_init(plat->bdf, plat->base); + + return ns16550_serial_probe(dev); +} + +static int apl_ns16550_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev); + + /* + * Convert our platdata to the ns16550's platdata, so we can just use + * that driver + */ + plat = malloc(sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->base = dtplat->early_regs[0]; + plat->reg_width = 1; + plat->reg_shift = dtplat->reg_shift; + plat->reg_offset = 0; + plat->clock = dtplat->clock_frequency; + plat->fcr = UART_FCR_DEFVAL; + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + dev->platdata = plat; +#else + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + if (!CONFIG_IS_ENABLED(OF_TRANSLATE)) { + /* + * Without address translation we cannot get correct PCI + * address, so just read the BAR manually. + */ + plat = dev_get_platdata(dev); + plat->base = dm_pci_read_bar32(dev, 0); + } +#endif /* OF_PLATDATA */ + + return 0; +} + +static const struct udevice_id apl_ns16550_serial_ids[] = { + { .compatible = "intel,apl-ns16550" }, + { }, +}; + +U_BOOT_DRIVER(apl_ns16550) = { + .name = "intel_apl_ns16550", + .id = UCLASS_SERIAL, + .of_match = apl_ns16550_serial_ids, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .ops = &ns16550_serial_ops, + .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata, + .probe = apl_ns16550_probe, +}; diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h new file mode 100644 index 0000000000..71006ccc74 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/uart.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_UART_H +#define _ASM_ARCH_UART_H + +/** + * apl_uart_init() - Set up the APL UART device and clock + * + * This enables the PCI device, sets up the MMIO region and turns on the clock + * using LPSS. + * + * The UART won't actually work unless the GPIO settings are correct and the + * signals actually exit the SoC. See init_for_uart() for that. + */ +int apl_uart_init(pci_dev_t bdf, ulong base); + +#endif From patchwork Fri Nov 22 04:18:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199287 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ZREgwScu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4GV2tNYz9sPc for ; Fri, 22 Nov 2019 16:09:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1680EC221E4; Fri, 22 Nov 2019 04:46:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AE1A3C220B1; Fri, 22 Nov 2019 04:40:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1B29DC2208F; Fri, 22 Nov 2019 04:22:50 +0000 (UTC) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by lists.denx.de (Postfix) with ESMTPS id C7813C220BE for ; Fri, 22 Nov 2019 04:22:43 +0000 (UTC) Received: by mail-il1-f195.google.com with SMTP id m5so5625860ilq.0 for ; Thu, 21 Nov 2019 20:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xEWfWauzjE38Rtocm3uv+prK4yeFApHGeJT0mdOeB/8=; b=ZREgwScuE9aQgmtExUOw/fdZe3E6K4h/DR+WLNDMfwqeUJM7k1SWcRHWFed6QDIGmK xeuek+p65cGdz7+VpgbkN3Zx6kfrjUg+juzwu7lUt678IWPekvt5iygdPCMMbCW0xOG4 uDod/17ZYesZbJS3PXhbQJBAXYFGX/o7u/+G4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xEWfWauzjE38Rtocm3uv+prK4yeFApHGeJT0mdOeB/8=; b=YvKLqHHIPkzXY6/KpPNLjkVBLcyWwnV0DpmgpukH3Zt1HTRrdsvvEid9+Zg/2IhUa5 tl6HQf9uPGXaQbqKgPgErUzhMHYhll/58b5GfMbgIM0qKZKRRJDAB2rPvLpzVyQ8jnRP b2x00sG0ltTdFP0hFir/tLMQrXBFmQLqjBNKZR1qU4FpqkK9a56UO7eaJkzpZmfKoALb MEXEMa1AP9W9ysbleWEVyRiH+w9YyGVAwBJJZgarfWRn+SEyjEUeiGBlNXiyGXVly1Mg m3lvI7xQpIEGTd1kaDy90FJ/hBkgHnLhWF/AYkalMcZREgWniGcQMh5blDps5SKRiiJ2 ivWw== X-Gm-Message-State: APjAAAX0aDjRnFMKa+VD+BnEWONDZJr7h/fvxMrMnZqlyD0YDxlT1OuS tFB4HUhDLv+JMsgvFcIzGhrhy6b6ZwU= X-Google-Smtp-Source: APXvYqxxCMzJmyFDwcXK3obedrNUS2G5aS2i0O35s4DompRFkAAEJfSUZ++rlQ9Ll4AVQGFwmD+Pbg== X-Received: by 2002:a92:bbdd:: with SMTP id x90mr260829ilk.286.1574396562222; Thu, 21 Nov 2019 20:22:42 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:41 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:50 -0700 Message-Id: <20191122041905.224686-64-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 085/100] x86: apl: Add pinctrl driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass --- Changes in v4: - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Drop GPIO_NUM_PAD_CFG_REGS - Switch over to use pinctrl for pad init/config - Tidy up the header file a little - apollolake -> Apollo Lake Changes in v3: - Add various minor tidy-ups - Fix mixed case in GPIO defines - Rework how pads configuration is defined in TPL and SPL - Use the IRQ uclass instead of ITSS Changes in v2: None arch/x86/include/asm/arch-apollolake/gpio.h | 490 ++++++++++++++++++++ drivers/pinctrl/intel/Kconfig | 17 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++++++ 4 files changed, 700 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h new file mode 100644 index 0000000000..f33025d7c5 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpio.h @@ -0,0 +1,490 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Definitions for the GPIO subsystem on Apollolake + * + * Copyright (C) 2015 - 2017 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * Placed in a separate file since some of these definitions can be used from + * assembly code + * + * Taken from gpio_apl.h in coreboot + */ + +#ifndef _ASM_ARCH_GPIO_H_ +#define _ASM_ARCH_GPIO_H_ + +/* Port ids */ +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#define PID_GPIO_AUDIO 0xC9 +#define PID_GPIO_SCC 0xC8 +#else +#define PID_GPIO_SW 0xC0 +#define PID_GPIO_S 0xC2 +#define PID_GPIO_W 0xC7 +#endif +#define PID_GPIO_NW 0xC4 +#define PID_GPIO_N 0xC5 +#define PID_ITSS 0xD0 +#define PID_RTC 0xD1 + +/* + * Miscellaneous Configuration register(MISCCFG). These are community-specific + * registers and are meant to house miscellaneous configuration fields per + * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent) + */ +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ +#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */ +#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */ +#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */ +#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */ +#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */ +#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */ +#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */ +#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */ + +#define GPIO_MAX_NUM_PER_GROUP 32 + +/* + * Host Software Pad Ownership Register. + * The pins in the community are divided into 3 groups: + * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 + */ +#define HOSTSW_OWN_REG_0 0x80 + +#define PAD_CFG_BASE 0x500 + +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 + +#define GPI_SMI_STS_0 0x140 +#define GPI_SMI_EN_0 0x150 + +#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1) +#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1) +#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1) +#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1) + +#define NUM_N_GPI_REGS \ + (ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_NW_GPI_REGS \ + (ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_W_GPI_REGS \ + (ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SW_GPI_REGS \ + (ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +/* + * Total number of GPI status registers across all GPIO communities in the SOC + */ +#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ + + NUM_W_GPI_REGS + NUM_SW_GPI_REGS) + +/* North community pads */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_28 28 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_33 33 +#define GPIO_34 34 +#define GPIO_35 35 +#define GPIO_36 36 +#define GPIO_37 37 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_41 41 +#define GPIO_42 42 +#define GPIO_43 43 +#define GPIO_44 44 +#define GPIO_45 45 +#define GPIO_46 46 +#define GPIO_47 47 +#define GPIO_48 48 +#define GPIO_49 49 +#define GPIO_62 50 +#define GPIO_63 51 +#define GPIO_64 52 +#define GPIO_65 53 +#define GPIO_66 54 +#define GPIO_67 55 +#define GPIO_68 56 +#define GPIO_69 57 +#define GPIO_70 58 +#define GPIO_71 59 +#define GPIO_72 60 +#define GPIO_73 61 +#define JTAG_TCK 62 +#define JTAG_TRST_B 63 +#define JTAG_TMS 64 +#define JTAG_TDI 65 +#define JTAG_CX_PMODE 66 +#define JTAG_CX_PREQ_B 67 +#define JTAGX 68 +#define JTAG_CX_PRDY_B 69 +#define JTAG_TDO 70 +#define CNV_BRI_DT 71 +#define CNV_BRI_RSP 72 +#define CNV_RGI_DT 73 +#define CNV_RGI_RSP 74 +#define SVID0_ALERT_B 75 +#define SVID0_DATA 76 +#define SVID0_CLK 77 + +/* Northwest community pads */ +#define GPIO_187 78 +#define GPIO_188 79 +#define GPIO_189 80 +#define GPIO_190 81 +#define GPIO_191 82 +#define GPIO_192 83 +#define GPIO_193 84 +#define GPIO_194 85 +#define GPIO_195 86 +#define GPIO_196 87 +#define GPIO_197 88 +#define GPIO_198 89 +#define GPIO_199 90 +#define GPIO_200 91 +#define GPIO_201 92 +#define GPIO_202 93 +#define GPIO_203 94 +#define GPIO_204 95 +#define PMC_SPI_FS0 96 +#define PMC_SPI_FS1 97 +#define PMC_SPI_FS2 98 +#define PMC_SPI_RXD 99 +#define PMC_SPI_TXD 100 +#define PMC_SPI_CLK 101 +#define PMIC_PWRGOOD 102 +#define PMIC_RESET_B 103 +#define GPIO_213 104 +#define GPIO_214 105 +#define GPIO_215 106 +#define PMIC_THERMTRIP_B 107 +#define PMIC_STDBY 108 +#define PROCHOT_B 109 +#define PMIC_I2C_SCL 110 +#define PMIC_I2C_SDA 111 +#define GPIO_74 112 +#define GPIO_75 113 +#define GPIO_76 114 +#define GPIO_77 115 +#define GPIO_78 116 +#define GPIO_79 117 +#define GPIO_80 118 +#define GPIO_81 119 +#define GPIO_82 120 +#define GPIO_83 121 +#define GPIO_84 122 +#define GPIO_85 123 +#define GPIO_86 124 +#define GPIO_87 125 +#define GPIO_88 126 +#define GPIO_89 127 +#define GPIO_90 128 +#define GPIO_91 129 +#define GPIO_92 130 +#define GPIO_97 131 +#define GPIO_98 132 +#define GPIO_99 133 +#define GPIO_100 134 +#define GPIO_101 135 +#define GPIO_102 136 +#define GPIO_103 137 +#define FST_SPI_CLK_FB 138 +#define GPIO_104 139 +#define GPIO_105 140 +#define GPIO_106 141 +#define GPIO_109 142 +#define GPIO_110 143 +#define GPIO_111 144 +#define GPIO_112 145 +#define GPIO_113 146 +#define GPIO_116 147 +#define GPIO_117 148 +#define GPIO_118 149 +#define GPIO_119 150 +#define GPIO_120 151 +#define GPIO_121 152 +#define GPIO_122 153 +#define GPIO_123 154 + +/* West community pads */ +#define GPIO_124 155 +#define GPIO_125 156 +#define GPIO_126 157 +#define GPIO_127 158 +#define GPIO_128 159 +#define GPIO_129 160 +#define GPIO_130 161 +#define GPIO_131 162 +#define GPIO_132 163 +#define GPIO_133 164 +#define GPIO_134 165 +#define GPIO_135 166 +#define GPIO_136 167 +#define GPIO_137 168 +#define GPIO_138 169 +#define GPIO_139 170 +#define GPIO_146 171 +#define GPIO_147 172 +#define GPIO_148 173 +#define GPIO_149 174 +#define GPIO_150 175 +#define GPIO_151 176 +#define GPIO_152 177 +#define GPIO_153 178 +#define GPIO_154 179 +#define GPIO_155 180 +#define GPIO_209 181 +#define GPIO_210 182 +#define GPIO_211 183 +#define GPIO_212 184 +#define OSC_CLK_OUT_0 185 +#define OSC_CLK_OUT_1 186 +#define OSC_CLK_OUT_2 187 +#define OSC_CLK_OUT_3 188 +#define OSC_CLK_OUT_4 189 +#define PMU_AC_PRESENT 190 +#define PMU_BATLOW_B 191 +#define PMU_PLTRST_B 192 +#define PMU_PWRBTN_B 193 +#define PMU_RESETBUTTON_B 194 +#define PMU_SLP_S0_B 195 +#define PMU_SLP_S3_B 196 +#define PMU_SLP_S4_B 197 +#define PMU_SUSCLK 198 +#define PMU_WAKE_B 199 +#define SUS_STAT_B 200 +#define SUSPWRDNACK 201 + +/* Southwest community pads */ +#define GPIO_205 202 +#define GPIO_206 203 +#define GPIO_207 204 +#define GPIO_208 205 +#define GPIO_156 206 +#define GPIO_157 207 +#define GPIO_158 208 +#define GPIO_159 209 +#define GPIO_160 210 +#define GPIO_161 211 +#define GPIO_162 212 +#define GPIO_163 213 +#define GPIO_164 214 +#define GPIO_165 215 +#define GPIO_166 216 +#define GPIO_167 217 +#define GPIO_168 218 +#define GPIO_169 219 +#define GPIO_170 220 +#define GPIO_171 221 +#define GPIO_172 222 +#define GPIO_179 223 +#define GPIO_173 224 +#define GPIO_174 225 +#define GPIO_175 226 +#define GPIO_176 227 +#define GPIO_177 228 +#define GPIO_178 229 +#define GPIO_186 230 +#define GPIO_182 231 +#define GPIO_183 232 +#define SMB_ALERTB 233 +#define SMB_CLK 234 +#define SMB_DATA 235 +#define LPC_ILB_SERIRQ 236 +#define LPC_CLKOUT0 237 +#define LPC_CLKOUT1 238 +#define LPC_AD0 239 +#define LPC_AD1 240 +#define LPC_AD2 241 +#define LPC_AD3 242 +#define LPC_CLKRUNB 243 +#define LPC_FRAMEB 244 + +/* PERST_0 not defined */ +#define GPIO_PRT0_UDEF 0xFF + +#define TOTAL_PADS 245 +#define N_OFFSET GPIO_0 +#define NW_OFFSET GPIO_187 +#define W_OFFSET GPIO_124 +#define SW_OFFSET GPIO_205 + +/* Macros for translating a global pad offset to a local offset */ +#define PAD_N(pad) (pad - N_OFFSET) +#define PAD_NW(pad) (pad - NW_OFFSET) +#define PAD_W(pad) (pad - W_OFFSET) +#define PAD_SW(pad) (pad - SW_OFFSET) + +/* Linux names of the GPIO devices */ +#define GPIO_COMM_N_NAME "INT3452:00" +#define GPIO_COMM_NW_NAME "INT3452:01" +#define GPIO_COMM_W_NAME "INT3452:02" +#define GPIO_COMM_SW_NAME "INT3452:03" + +/* Following is used in gpio asl */ +#define GPIO_COMM_NAME "INT3452" +#define GPIO_COMM_0_DESC \ + "General Purpose Input/Output (GPIO) Controller - North" +#define GPIO_COMM_1_DESC \ + "General Purpose Input/Output (GPIO) Controller - Northwest" +#define GPIO_COMM_2_DESC \ + "General Purpose Input/Output (GPIO) Controller - West" +#define GPIO_COMM_3_DESC \ + "General Purpose Input/Output (GPIO) Controller - Southwest" + +#define GPIO_COMM0_PID PID_GPIO_N +#define GPIO_COMM1_PID PID_GPIO_NW +#define GPIO_COMM2_PID PID_GPIO_W +#define GPIO_COMM3_PID PID_GPIO_SW + +/* + * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use + * shared IRQ instead of direct IRQ, in case of overlapping, we can easily + * program one of the overlap to shared IRQ to avoid the conflict. + */ + +/* NorthWest community pads */ +#define PMIC_I2C_SDA_IRQ 0x32 +#define GPIO_74_IRQ 0x33 +#define GPIO_75_IRQ 0x34 +#define GPIO_76_IRQ 0x35 +#define GPIO_77_IRQ 0x36 +#define GPIO_78_IRQ 0x37 +#define GPIO_79_IRQ 0x38 +#define GPIO_80_IRQ 0x39 +#define GPIO_81_IRQ 0x3A +#define GPIO_82_IRQ 0x3B +#define GPIO_83_IRQ 0x3C +#define GPIO_84_IRQ 0x3D +#define GPIO_85_IRQ 0x3E +#define GPIO_86_IRQ 0x3F +#define GPIO_87_IRQ 0x40 +#define GPIO_88_IRQ 0x41 +#define GPIO_89_IRQ 0x42 +#define GPIO_90_IRQ 0x43 +#define GPIO_91_IRQ 0x44 +#define GPIO_97_IRQ 0x49 +#define GPIO_98_IRQ 0x4A +#define GPIO_99_IRQ 0x4B +#define GPIO_100_IRQ 0x4C +#define GPIO_101_IRQ 0x4D +#define GPIO_102_IRQ 0x4E +#define GPIO_103_IRQ 0x4F +#define GPIO_104_IRQ 0x50 +#define GPIO_105_IRQ 0x51 +#define GPIO_106_IRQ 0x52 +#define GPIO_109_IRQ 0x54 +#define GPIO_110_IRQ 0x55 +#define GPIO_111_IRQ 0x56 +#define GPIO_112_IRQ 0x57 +#define GPIO_113_IRQ 0x58 +#define GPIO_116_IRQ 0x5B +#define GPIO_117_IRQ 0x5C +#define GPIO_118_IRQ 0x5D +#define GPIO_119_IRQ 0x5E +#define GPIO_120_IRQ 0x5F +#define GPIO_121_IRQ 0x60 +#define GPIO_122_IRQ 0x61 +#define GPIO_123_IRQ 0x62 + +/* North community pads */ +#define GPIO_0_IRQ 0x63 +#define GPIO_1_IRQ 0x64 +#define GPIO_2_IRQ 0x65 +#define GPIO_3_IRQ 0x66 +#define GPIO_4_IRQ 0x67 +#define GPIO_5_IRQ 0x68 +#define GPIO_6_IRQ 0x69 +#define GPIO_7_IRQ 0x6A +#define GPIO_8_IRQ 0x6B +#define GPIO_9_IRQ 0x6C +#define GPIO_10_IRQ 0x6D +#define GPIO_11_IRQ 0x6E +#define GPIO_12_IRQ 0x6F +#define GPIO_13_IRQ 0x70 +#define GPIO_14_IRQ 0x71 +#define GPIO_15_IRQ 0x72 +#define GPIO_16_IRQ 0x73 +#define GPIO_17_IRQ 0x74 +#define GPIO_18_IRQ 0x75 +#define GPIO_19_IRQ 0x76 +#define GPIO_20_IRQ 0x77 +#define GPIO_21_IRQ 0x32 +#define GPIO_22_IRQ 0x33 +#define GPIO_23_IRQ 0x34 +#define GPIO_24_IRQ 0x35 +#define GPIO_25_IRQ 0x36 +#define GPIO_26_IRQ 0x37 +#define GPIO_27_IRQ 0x38 +#define GPIO_28_IRQ num_reset_vals0x39 +#define GPIO_29_IRQ 0x3A +#define GPIO_30_IRQ 0x3B +#define GPIO_31_IRQ 0x3C +#define GPIO_32_IRQ 0x3D +#define GPIO_33_IRQ 0x3E +#define GPIO_34_IRQ 0x3F +#define GPIO_35_IRQ 0x40 +#define GPIO_36_IRQ 0x41 +#define GPIO_37_IRQ 0x42 +#define GPIO_38_IRQ 0x43 +#define GPIO_39_IRQ 0x44 +#define GPIO_40_IRQ 0x45 +#define GPIO_41_IRQ 0x46 +#define GPIO_42_IRQ 0x47 +#define GPIO_43_IRQ 0x48 +#define GPIO_44_IRQ 0x49 +#define GPIO_45_IRQ 0x4A +#define GPIO_46_IRQ 0x4B +#define GPIO_47_IRQ 0x4C +#define GPIO_48_IRQ 0x4D +#define GPIO_49_IRQ 0x4E +#define GPIO_62_IRQ 0x5B +#define GPIO_63_IRQ 0x5C +#define GPIO_64_IRQ 0x5D +#define GPIO_65_IRQ 0x5E +#define GPIO_66_IRQ 0x5F +#define GPIO_67_IRQ 0x60 +#define GPIO_68_IRQ 0x61 +#define GPIO_69_IRQ 0x62 +#define GPIO_70_IRQ 0x63 +#define GPIO_71_IRQ 0x64 +#define GPIO_72_IRQ 0x65 +#define GPIO_73_IRQ 0x66 + +#endif /* _ASM_ARCH_GPIO_H_ */ diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 727b743431..daf34d23ba 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -4,4 +4,21 @@ if PINCTRL_INTEL +config PINCTRL_INTEL_APL + bool "Support Intel Apollo Lake (APL)" + help + Add support for Intel Apollo Lake pin-control and pin-mux settings. + These are mostly read from the device tree, with the early-pads + property in the host bridge and the pads property in the fsp-s + subnode of the host bridge. + +config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT + def_bool y + +config INTEL_PINCTRL_PADCFG_PADTOL + def_bool n + +config INTEL_PINCTRL_IOSTANDBY + def_bool y + endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index bc1aad2c06..3aed8e9663 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC obj-y += pinctrl.o +obj-$(CONFIG_PINCTRL_INTEL_APL) += pinctrl_apl.o diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c new file mode 100644 index 0000000000..bd80435ffa --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl_apl.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corp. + * Copyright 2019 Google LLC + * + * Taken partly from coreboot gpio.c + */ + +#define LOG_CATEGORY UCLASS_GPIO + +#include +#include +#include +#include +#include +#include +#include + +/** + * struct apl_gpio_platdata - platform data for each device + * + * @dtplat: of-platdata data from C struct + */ +struct apl_gpio_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_intel_apl_pinctrl dtplat; +#endif +}; + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +/* Groups for each community */ +static const struct pad_group apl_community_n_groups[] = { + INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */ + INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */ + INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */ +}; + +static const struct pad_group apl_community_w_groups[] = { + INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */ + INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */ +}; + +static const struct pad_group apl_community_sw_groups[] = { + INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */ + INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */ +}; + +static const struct pad_group apl_community_nw_groups[] = { + INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */ + INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */ + INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */ +}; + +/* TODO(sjg@chromium.org): Consider moving this to device tree */ +static const struct pad_community apl_gpio_communities[] = { + { + .port = PID_GPIO_N, + .first_pad = N_OFFSET, + .last_pad = SVID0_CLK, + .num_gpi_regs = NUM_N_GPI_REGS, + .gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS + + NUM_SW_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_N", + .acpi_path = "\\_SB.GPO0", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_n_groups, + .num_groups = ARRAY_SIZE(apl_community_n_groups), + }, { + .port = PID_GPIO_NW, + .first_pad = NW_OFFSET, + .last_pad = GPIO_123, + .num_gpi_regs = NUM_NW_GPI_REGS, + .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_NW", + .acpi_path = "\\_SB.GPO1", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_nw_groups, + .num_groups = ARRAY_SIZE(apl_community_nw_groups), + }, { + .port = PID_GPIO_W, + .first_pad = W_OFFSET, + .last_pad = SUSPWRDNACK, + .num_gpi_regs = NUM_W_GPI_REGS, + .gpi_status_offset = NUM_SW_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_W", + .acpi_path = "\\_SB.GPO2", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_w_groups, + .num_groups = ARRAY_SIZE(apl_community_w_groups), + }, { + .port = PID_GPIO_SW, + .first_pad = SW_OFFSET, + .last_pad = LPC_FRAMEB, + .num_gpi_regs = NUM_SW_GPI_REGS, + .gpi_status_offset = 0, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_SW", + .acpi_path = "\\_SB.GPO3", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_sw_groups, + .num_groups = ARRAY_SIZE(apl_community_sw_groups), + }, +}; + +static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev) +{ + struct p2sb_child_platdata *pplat; + const struct pad_community *comm = NULL; + int i; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct apl_gpio_platdata *plat = dev_get_platdata(dev); + int ret; + + /* + * It would be nice to do this in the bind() method, but with + * of-platdata binding happens in the order that DM finds things in the + * linker list (i.e. alphabetical order by driver name). So the GPIO + * device may well be bound before its parent (p2sb), and this call + * will fail if p2sb is not bound yet. + * + * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc + */ + ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id); + if (ret) + return log_msg_ret("Could not set port id", ret); +#endif + /* Attach this device to its community structure */ + pplat = dev_get_parent_platdata(dev); + for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) { + if (apl_gpio_communities[i].port == pplat->pid) + comm = &apl_gpio_communities[i]; + } + + return intel_pinctrl_ofdata_to_platdata(dev, comm, 2); +} + +static const struct udevice_id apl_gpio_ids[] = { + { .compatible = "intel,apl-pinctrl"}, + { } +}; + +U_BOOT_DRIVER(apl_pinctrl_drv) = { + .name = "intel_apl_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = apl_gpio_ids, + .probe = intel_pinctrl_probe, + .ops = &intel_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv), + .platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata), +}; From patchwork Fri Nov 22 04:18:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199264 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="bQN/8cNq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4335WqGz9s7T for ; Fri, 22 Nov 2019 15:59:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6A42FC22096; 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Thu, 21 Nov 2019 20:22:47 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:47 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:51 -0700 Message-Id: <20191122041905.224686-65-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 086/100] i2c: designware: Add Apollo Lake support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver. Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Add a weak function to avoid errors on other platforms Changes in v2: None drivers/i2c/designware_i2c_pci.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 2bf90eaa4b..5114883923 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -8,8 +8,14 @@ #include #include #include +#include #include "designware_i2c.h" +enum { + VANILLA = 0, + INTEL_APL, +}; + /* BayTrail HCNT/LCNT/SDA hold time */ static struct dw_scl_sda_cfg byt_config = { .ss_hcnt = 0x200, @@ -62,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev) static int designware_i2c_pci_probe(struct udevice *dev) { + struct dw_i2c *priv = dev_get_priv(dev); + + if (dev_get_driver_data(dev) == INTEL_APL) { + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + + lpss_reset_release(priv->regs); + } + return designware_i2c_probe(dev); } @@ -91,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev) static const struct udevice_id designware_i2c_pci_ids[] = { { .compatible = "snps,designware-i2c-pci" }, + { .compatible = "intel,apl-i2c", INTEL_APL }, { } }; @@ -116,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = { { PCI_VDEVICE(INTEL, 0x0f45) }, { PCI_VDEVICE(INTEL, 0x0f46) }, { PCI_VDEVICE(INTEL, 0x0f47) }, + { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL }, {}, }; From patchwork Fri Nov 22 04:18:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199237 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Simon Glass --- Changes in v4: - Add a comment for enable_bios_reset_cpl() - Tidy up header guards - use GENMASK() for VTBAR_MASK Changes in v3: None Changes in v2: None arch/x86/cpu/apollolake/Makefile | 2 + arch/x86/cpu/apollolake/systemagent.c | 19 ++++++++++ .../include/asm/arch-apollolake/systemagent.h | 37 +++++++++++++++++++ 3 files changed, 58 insertions(+) create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index fdda748ea3..3a8c2f66a3 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,5 +2,7 @@ # # Copyright 2019 Google LLC +obj-$(CONFIG_SPL_BUILD) += systemagent.o + obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c new file mode 100644 index 0000000000..3a41b329c3 --- /dev/null +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#include +#include +#include +#include + +void enable_bios_reset_cpl(void) +{ + /* + * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialised memory and power management + */ + setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); +} diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h new file mode 100644 index 0000000000..206d8903fa --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/systemagent.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_SYSTEMAGENT_H +#define _ASM_ARCH_SYSTEMAGENT_H + +/* Device 0:0.0 PCI configuration space */ +#define MCHBAR 0x48 + +/* RAPL Package Power Limit register under MCHBAR */ +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 +#define BIOS_RESET_CPL 0x7078 +#define PCODE_INIT_DONE BIT(8) +#define MCHBAR_RAPL_PPL 0x70A8 +#define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE BIT(23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK GENMASK_ULL(39, 12) +#define VTBAR_SIZE 0x1000 + +/** + * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready + * + * This should be called when U-Boot has set up the memory and power + * management. + */ +void enable_bios_reset_cpl(void); + +#endif From patchwork Fri Nov 22 04:18:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199293 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Ri46Bki9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4Kx1CFwz9sPW for ; Fri, 22 Nov 2019 16:12:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C1CACC221B7; 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Thu, 21 Nov 2019 20:22:51 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:53 -0700 Message-Id: <20191122041905.224686-67-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 088/100] x86: apl: Add hostbridge driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass --- Changes in v4: - Avoid needing to know internals of pinctrl in this driver - Move code to pinctrl driver - Switch over to use pinctrl for pad init/config Changes in v3: - Move pad programming into the hostbridge to reduce TPL device-tree size - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/hostbridge.c | 179 +++++++++++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 arch/x86/cpu/apollolake/hostbridge.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 3a8c2f66a3..4d3c08f84e 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o +obj-y += hostbridge.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c new file mode 100644 index 0000000000..25fb51dd9a --- /dev/null +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct apl_hostbridge_platdata - platform data for hostbridge + * + * @num_cfgs: Number of configuration words for each pad + * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1) + * @early_pads_count: Number of pads to process + * @pciex_region_size: BAR length in bytes + * @bdf: Bus/device/function of hostbridge + */ +struct apl_hostbridge_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_hostbridge dtplat; +#endif + u32 *early_pads; + int early_pads_count; + uint pciex_region_size; + pci_dev_t bdf; +}; + +enum { + PCIEXBAR = 0x60, + PCIEXBAR_LENGTH_256MB = 0, + PCIEXBAR_LENGTH_128MB, + PCIEXBAR_LENGTH_64MB, + + PCIEXBAR_PCIEXBAREN = 1 << 0, + + TSEG = 0xb8, /* TSEG base */ +}; + +static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge pinctrl", ret); + + return pinctrl_config_pads(pinctrl, plat->early_pads, + plat->early_pads_count); +} + +static int apl_hostbridge_early_init(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + u32 region_size; + ulong base; + u32 reg; + int ret; + + /* Set up the MCHBAR */ + pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32); + base = MCH_BASE_ADDRESS; + pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32); + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB + */ + pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); + + switch (plat->pciex_region_size >> 20) { + default: + case 256: + region_size = PCIEXBAR_LENGTH_256MB; + break; + case 128: + region_size = PCIEXBAR_LENGTH_128MB; + break; + case 64: + region_size = PCIEXBAR_LENGTH_64MB; + break; + } + + reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1) + | PCIEXBAR_PCIEXBAREN; + pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32); + + ret = apl_hostbridge_early_init_pinctrl(dev); + if (ret) + return log_msg_ret("pinctrl", ret); + + return 0; +} + +static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + /* + * The host bridge holds the early pad data needed to get through TPL. + * This is a small amount of data, enough to fit in TPL, so we keep it + * separate from the full pad data, stored in the fsp-s subnode. That + * subnode is not present in TPL, to save space. + */ + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge PINCTRL", ret); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int root; + + /* Get length of PCI Express Region */ + plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size", + 256 << 20); + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads", + &plat->early_pads, &plat->early_pads_count); + if (ret) + return log_msg_ret("early-pads", ret); +#else + struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat; + int size; + + plat->pciex_region_size = dtplat->pciex_region_size; + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + + /* Assume that if everything is 0, it is empty */ + plat->early_pads = dtplat->early_pads; + size = ARRAY_SIZE(dtplat->early_pads); + plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads, + size); + +#endif + + return 0; +} + +static int apl_hostbridge_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_hostbridge_early_init(dev); + + return 0; +} + +static const struct udevice_id apl_hostbridge_ids[] = { + { .compatible = "intel,apl-hostbridge" }, + { } +}; + +U_BOOT_DRIVER(apl_hostbridge_drv) = { + .name = "intel_apl_hostbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = apl_hostbridge_ids, + .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, + .probe = apl_hostbridge_probe, + .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), +}; From patchwork Fri Nov 22 04:18:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199256 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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Thu, 21 Nov 2019 20:22:53 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:53 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:54 -0700 Message-Id: <20191122041905.224686-68-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 089/100] x86: apl: Add ITSS driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass --- Changes in v4: - Tidy up header guards Changes in v3: - Add snapshot/restore for IRQs - Use the IRQ uclass instead of ITSS Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/itss.c | 214 ++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/itss.h | 43 ++++ 3 files changed, 258 insertions(+) create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 4d3c08f84e..2d78368150 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += hostbridge.o +obj-y += itss.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/apollolake/itss.c new file mode 100644 index 0000000000..8789f8e6bb --- /dev/null +++ b/arch/x86/cpu/apollolake/itss.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Something to do with Interrupts, but I don't know what ITSS stands for + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017 Siemens AG + * Copyright 2019 Google LLC + * + * Taken from coreboot itss.c + */ + +#include +#include +#include +#include +#include +#include +#include + +struct apl_itss_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* Put this first since driver model will copy the data here */ + struct dtd_intel_apl_itss dtplat; +#endif +}; + +/* struct pmc_route - Routing for PMC to GPIO */ +struct pmc_route { + u32 pmc; + u32 gpio; +}; + +struct apl_itss_priv { + struct pmc_route *route; + uint route_count; + u32 irq_snapshot[NUM_IPC_REGS]; +}; + +static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low) +{ + u32 mask; + uint reg; + + if (irq > ITSS_MAX_IRQ) + return -EINVAL; + + reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC); + mask = 1 << (irq % IRQS_PER_IPC); + + pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0); + + return 0; +} + +#ifndef CONFIG_TPL_BUILD +static int apl_snapshot_polarities(struct udevice *dev) +{ + struct apl_itss_priv *priv = dev_get_priv(dev); + const int start = GPIO_IRQ_START; + const int end = GPIO_IRQ_END; + int reg_start; + int reg_end; + int i; + + reg_start = start / IRQS_PER_IPC; + reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + + for (i = reg_start; i < reg_end; i++) { + uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + + priv->irq_snapshot[i] = pcr_read32(dev, reg); + } + + return 0; +} + +static void show_polarities(struct udevice *dev, const char *msg) +{ + int i; + + log_info("ITSS IRQ Polarities %s:\n", msg); + for (i = 0; i < NUM_IPC_REGS; i++) { + uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + + log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg)); + } +} + +static int apl_restore_polarities(struct udevice *dev) +{ + struct apl_itss_priv *priv = dev_get_priv(dev); + const int start = GPIO_IRQ_START; + const int end = GPIO_IRQ_END; + int reg_start; + int reg_end; + int i; + + show_polarities(dev, "Before"); + + reg_start = start / IRQS_PER_IPC; + reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + + for (i = reg_start; i < reg_end; i++) { + u32 mask; + u16 reg; + int irq_start; + int irq_end; + + irq_start = i * IRQS_PER_IPC; + irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ); + + if (start > irq_end) + continue; + if (end < irq_start) + break; + + /* Track bits within the bounds of of the register */ + irq_start = max(start, irq_start) % IRQS_PER_IPC; + irq_end = min(end, irq_end) % IRQS_PER_IPC; + + /* Create bitmask of the inclusive range of start and end */ + mask = (((1U << irq_end) - 1) | (1U << irq_end)); + mask &= ~((1U << irq_start) - 1); + + reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]); + } + + show_polarities(dev, "After"); + + return 0; +} +#endif + +static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +{ + struct apl_itss_priv *priv = dev_get_priv(dev); + struct pmc_route *route; + int i; + + for (i = 0, route = priv->route; i < priv->route_count; i++, route++) { + if (pmc_gpe_num == route->pmc) + return route->gpio; + } + + return -ENOENT; +} + +static int apl_itss_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_itss_priv *priv = dev_get_priv(dev); + int ret; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct apl_itss_platdata *plat = dev_get_platdata(dev); + struct dtd_intel_apl_itss *dtplat = &plat->dtplat; + + /* + * It would be nice to do this in the bind() method, but with + * of-platdata binding happens in the order that DM finds things in the + * linker list (i.e. alphabetical order by driver name). So the GPIO + * device may well be bound before its parent (p2sb), and this call + * will fail if p2sb is not bound yet. + * + * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc + */ + ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id); + if (ret) + return log_msg_ret("Could not set port id", ret); + priv->route = (struct pmc_route *)dtplat->intel_pmc_routes; + priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) / + sizeof(struct pmc_route); +#else + int size; + + size = dev_read_size(dev, "intel,pmc-routes"); + if (size < 0) + return size; + priv->route = malloc(size); + if (!priv->route) + return -ENOMEM; + ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route, + size / sizeof(fdt32_t)); + if (ret) + return log_msg_ret("Cannot read pmc-routes", ret); + priv->route_count = size / sizeof(struct pmc_route); +#endif + + return 0; +} + +static const struct irq_ops apl_itss_ops = { + .route_pmc_gpio_gpe = apl_route_pmc_gpio_gpe, + .set_polarity = apl_set_polarity, +#ifndef CONFIG_TPL_BUILD + .snapshot_polarities = apl_snapshot_polarities, + .restore_polarities = apl_restore_polarities, +#endif +}; + +static const struct udevice_id apl_itss_ids[] = { + { .compatible = "intel,apl-itss"}, + { } +}; + +U_BOOT_DRIVER(apl_itss_drv) = { + .name = "intel_apl_itss", + .id = UCLASS_IRQ, + .of_match = apl_itss_ids, + .ops = &apl_itss_ops, + .ofdata_to_platdata = apl_itss_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct apl_itss_platdata), + .priv_auto_alloc_size = sizeof(struct apl_itss_priv), +}; diff --git a/arch/x86/include/asm/arch-apollolake/itss.h b/arch/x86/include/asm/arch-apollolake/itss.h new file mode 100644 index 0000000000..1e29503974 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/itss.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Copyright 2019 Google LLC + * + * Modified from coreboot itss.h + */ + +#ifndef _ASM_ARCH_ITSS_H +#define _ASM_ARCH_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC) + +/* Max PXRC registers in ITSS */ +#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) + +/* PIRQA Routing Control Register */ +#define PCR_ITSS_PIRQA_ROUT 0x3100 +/* PIRQB Routing Control Register */ +#define PCR_ITSS_PIRQB_ROUT 0x3101 +/* PIRQC Routing Control Register */ +#define PCR_ITSS_PIRQC_ROUT 0x3102 +/* PIRQD Routing Control Register */ +#define PCR_ITSS_PIRQD_ROUT 0x3103 +/* PIRQE Routing Control Register */ +#define PCR_ITSS_PIRQE_ROUT 0x3104 +/* PIRQF Routing Control Register */ +#define PCR_ITSS_PIRQF_ROUT 0x3105 +/* PIRQG Routing Control Register */ +#define PCR_ITSS_PIRQG_ROUT 0x3106 +/* PIRQH Routing Control Register */ +#define PCR_ITSS_PIRQH_ROUT 0x3107 +/* ITSS Interrupt polarity control */ +#define PCR_ITSS_IPC0_CONF 0x3200 +/* ITSS Power reduction control */ +#define PCR_ITSS_ITSSPRC 0x3300 + +#endif /* _ASM_ARCH_ITSS_H */ From patchwork Fri Nov 22 04:18:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199298 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="e5t10/aU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4N13Kghz9sPW for ; Fri, 22 Nov 2019 16:13:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0FBB8C221A3; Fri, 22 Nov 2019 04:41:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EDF61C22086; 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bh=GchbZUGmlZO/WvrHApt8CYzU74Bi9Ipd3YJFTpEdE3c=; b=XEeMc4EghxDO0UZs/pItGR4UgRYEtQzjowAr547qXSzeANyxKH6BSw/xyxr9OPfEXD olsURw5cUFEVqwfScHTq9WorGD5QM6sjyqTq9XlcuOfxwoz8vC9a3E0ob5w1gNOGsfqv uCTgjLka8tPVetdUck1RzUYy+B+Bv2u6+2iLlGDR1nWGs08wYuhR6irftBhf+BaAqE+M n4z3CNIM5BaE+BDeJmrX7b7szpRC/E/vMCoGqzyV2SKS1BOXP9mV7IT5dXeRfYV+S+Fw Onid4H1Itjh55rnuk0LjG6Sl1bGQwR2AZ6aWiFc1HWhSdaE77X0Vy498DmyZKKwRSYal LN4w== X-Gm-Message-State: APjAAAXLTC1IlIwohEGdzekzGB3Z0uS8Ecn0Zo3tx5MhUhWHYw6p99YO JjFYP8eHu1TcsdWDU0df6sl0rHZ9okE= X-Google-Smtp-Source: APXvYqyiQQr+gjaJ4CLFDhpsec6Jy2JBrzft4vO37gFQn329HiU/8XU+lanT+pdaR9zRuypSE3NqIg== X-Received: by 2002:a05:6638:2b1:: with SMTP id d17mr12056954jaq.3.1574396575703; Thu, 21 Nov 2019 20:22:55 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:55 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:55 -0700 Message-Id: <20191122041905.224686-69-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 090/100] x86: apl: Add LPC driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass --- Changes in v4: - Add comments for exported functions - Tidy up header guards - Use 'Apollo Lake' - Use BIT() macro a bit more - Use tabs instead of spaces Changes in v3: - Drop unused code in lpc_configure_pads() - Fix value of LPC_BC_LE Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/lpc.c | 141 +++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 2d78368150..31045a03c1 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += hostbridge.o obj-y += itss.o +obj-y += lpc.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c new file mode 100644 index 0000000000..b14eed6508 --- /dev/null +++ b/arch/x86/cpu/apollolake/lpc.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + * + * From coreboot Apollo Lake support lpc.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void lpc_configure_pads(void) +{ + /* All pads are configured by the hostbridge */ +} + +void lpc_enable_fixed_io_ranges(uint io_enables) +{ + pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables, + PCI_SIZE_16); +} + +/* + * Find the first unused IO window. + * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... + */ +static int find_unused_pmio_window(void) +{ + int i; + ulong lgir; + + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), + &lgir, PCI_SIZE_32); + + if (!(lgir & LPC_LGIR_EN)) + return i; + } + + return -1; +} + +int lpc_open_pmio_window(uint base, uint size) +{ + int i, lgir_reg_num; + u32 lgir_reg_offset, lgir, window_size, alignment; + ulong bridged_size, bridge_base; + ulong reg; + + log_debug("LPC: Trying to open IO window from %x size %x\n", base, + size); + + bridged_size = 0; + bridge_base = base; + + while (bridged_size < size) { + /* Each IO range register can only open a 256-byte window */ + window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE); + + /* Window size must be a power of two for the AMASK to work */ + alignment = 1UL << (order_base_2(window_size)); + window_size = ALIGN(window_size, alignment); + + /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */ + lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN; + lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; + + /* Skip programming if same range already programmed */ + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + pci_x86_read_config(PCH_DEV_LPC, + LPC_GENERIC_IO_RANGE(i), ®, + PCI_SIZE_32); + if (lgir == reg) + return -EALREADY; + } + + lgir_reg_num = find_unused_pmio_window(); + if (lgir_reg_num < 0) { + log_err("LPC: Cannot open IO window: %lx size %lx\n", + bridge_base, size - bridged_size); + log_err("No more IO windows\n"); + + return -ENOSPC; + } + lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); + + pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir, + PCI_SIZE_32); + + log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n", + lgir_reg_num, bridge_base, window_size); + + bridged_size += window_size; + bridge_base += window_size; + } + + return 0; +} + +void lpc_io_setup_comm_a_b(void) +{ + /* ComA Range 3F8h-3FFh [2:0] */ + u16 com_ranges = LPC_IOD_COMA_RANGE; + u16 com_enable = LPC_IOE_COMA_EN; + + /* ComB Range 2F8h-2FFh [6:4] */ + if (0) { + com_ranges |= LPC_IOD_COMB_RANGE; + com_enable |= LPC_IOE_COMB_EN; + } + + /* Setup I/O Decode Range Register for LPC */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges); + /* Enable ComA and ComB Port */ + lpc_enable_fixed_io_ranges(com_enable); +} + +static int apl_lpc_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + lpc_configure_pads(); + + return 0; +} + +static const struct udevice_id apl_lpc_ids[] = { + { .compatible = "intel,apl-lpc" }, + { } +}; + +U_BOOT_DRIVER(apl_lpc_drv) = { + .name = "intel_apl_lpc", + .id = UCLASS_LPC, + .of_match = apl_lpc_ids, + .probe = apl_lpc_probe, +}; diff --git a/arch/x86/include/asm/arch-apollolake/lpc.h b/arch/x86/include/asm/arch-apollolake/lpc.h new file mode 100644 index 0000000000..5d2adad319 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/lpc.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_LPC_H +#define _ASM_ARCH_LPC_H + +#define LPC_SERIRQ_CTL 0x64 +#define LPC_SCNT_EN BIT(7) +#define LPC_SCNT_MODE BIT(6) +#define LPC_IO_DECODE 0x80 +#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/ +#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/ +/* + * Use IO__ style macros defined in lpc_lib.h + * to enable decoding of I/O locations for a peripheral + */ +#define LPC_IO_ENABLES 0x82 +#define LPC_GENERIC_IO_RANGE(n) ((((n) & 0x3) * 4) + 0x84) +#define LPC_LGIR_AMASK_MASK (0xfc << 16) +#define LPC_LGIR_ADDR_MASK 0xfffc +#define LPC_LGIR_EN BIT(0) +#define LPC_LGIR_MAX_WINDOW_SIZE 256 +#define LPC_GENERIC_MEM_RANGE 0x98 +#define LPC_LGMR_ADDR_MASK 0xffff0000 +#define LPC_LGMR_EN BIT(0) +#define LPC_LGMR_WINDOW_SIZE (64 * KiB) +#define LPC_BIOS_CNTL 0xdc +#define LPC_BC_BILD BIT(7) +#define LPC_BC_LE BIT(1) +#define LPC_BC_EISS BIT(5) +#define LPC_PCCTL 0xE0 /* PCI Clock Control */ +#define LPC_PCCTL_CLKRUN_EN BIT(0) + +/* + * IO decode enable macros are in the format IO__. + * For example, to open ports 0x60, 0x64 for the keyboard controller, + * use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range, + * the port range is selectable via the IO decodes register. + */ +#define LPC_IOE_EC_4E_4F BIT(13) +#define LPC_IOE_SUPERIO_2E_2F BIT(12) +#define LPC_IOE_EC_62_66 BIT(11) +#define LPC_IOE_KBC_60_64 BIT(10) +#define LPC_IOE_HGE_208 BIT(9) +#define LPC_IOE_LGE_200 BIT(8) +#define LPC_IOE_FDD_EN BIT(3) +#define LPC_IOE_LPT_EN BIT(2) +#define LPC_IOE_COMB_EN BIT(1) +#define LPC_IOE_COMA_EN BIT(0) +#define LPC_NUM_GENERIC_IO_RANGES 4 + +#define LPC_IO_ENABLES 0x82 + +/** + * lpc_enable_fixed_io_ranges() - enable the fixed I/O ranges + * + * @io_enables: Mask of things to enable (LPC_IOE_.) + */ +void lpc_enable_fixed_io_ranges(uint io_enables); + +/** + * lpc_open_pmio_window() - Open an IO port range + * + * @base: Base I/O address (e.g. 0x800) + * @size: Size of window (e.g. 0x100) + * @return 0 if OK, -ENOSPC if there are no more windows available, -EALREADY + * if already set up + */ +int lpc_open_pmio_window(uint base, uint size); + +/** + * lpc_io_setup_comm_a_b() - Set up basic serial UARTs + * + * Set up the LPC to handle I/O to the COMA/COMB serial UART addresses + * 2f8-2ff and 3f8-3ff. + */ +void lpc_io_setup_comm_a_b(void); + +#endif From patchwork Fri Nov 22 04:18:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199274 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="AEh9BJY+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K47f0Pjyz9s7T for ; Fri, 22 Nov 2019 16:03:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8CB28C220F5; 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Thu, 21 Nov 2019 20:22:57 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:22:57 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:56 -0700 Message-Id: <20191122041905.224686-70-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 091/100] x86: apl: Add PCH driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass --- Changes in v4: - Tidy up header guards - Update SPI flash protection only in SPL - apollolake -> Apollo Lake Changes in v3: None Changes in v2: - Drop probe() function - Implement set_spi_protect() arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/pch.c | 36 ++++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/pch.h | 9 ++++++ 3 files changed, 46 insertions(+) create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 31045a03c1..36eefcbad7 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o obj-y += hostbridge.o obj-y += itss.o obj-y += lpc.o +obj-y += pch.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c new file mode 100644 index 0000000000..1a5a985221 --- /dev/null +++ b/arch/x86/cpu/apollolake/pch.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +#define BIOS_CTRL 0xdc + +static int apl_set_spi_protect(struct udevice *dev, bool protect) +{ + if (spl_phase() == PHASE_SPL) + return lpc_set_spi_protect(dev, BIOS_CTRL, protect); + + return 0; +} + +static const struct pch_ops apl_pch_ops = { + .set_spi_protect = apl_set_spi_protect, +}; + +static const struct udevice_id apl_pch_ids[] = { + { .compatible = "intel,apl-pch" }, + { } +}; + +U_BOOT_DRIVER(apl_pch) = { + .name = "apl_pch", + .id = UCLASS_PCH, + .of_match = apl_pch_ids, + .ops = &apl_pch_ops, +}; diff --git a/arch/x86/include/asm/arch-apollolake/pch.h b/arch/x86/include/asm/arch-apollolake/pch.h new file mode 100644 index 0000000000..bf3e1670d2 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/pch.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_PCH_H +#define _ASM_ARCH_PCH_H + +#endif /* _ASM_ARCH_PCH_H */ From patchwork Fri Nov 22 04:18:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199260 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="K8HMypOs"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K40846cDz9s7T for ; Fri, 22 Nov 2019 15:56:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4E02DC22094; Fri, 22 Nov 2019 04:51:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 06229C220AF; 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bh=iKRTQ7OovE/9SJoKL/xLTB8TqwwTWcKZUQQnYGTuahU=; b=TshRr4kmjmKJXAty5GtWgGxcsFqwEt3zqkNieJHU5mg1ucRX8uSGFMh7agGigoOE51 Za9LwEnXTf9htzQEP2hfvhTGzqvtEN0hOyUqsdKKQULWPo03ndKfTwqP756avikbRhCl sL5wqU1jPvb0seV5GegPW9rUKvGmC2FlhutjCKrPFmtKssB1r1aszxwR/aQV70WAKrIF KhYjPR66FE/lkoj6A4dsqf0g3K6YSrRGloo2o+Vq8f9ZC0Qb54o+L0HyOqcgX1hyHYA5 shhBhY7um4/WsctHw0ClDbpvt4vKmItHSc1r7DE9E+MPUVspjYKYvqFWjaQz179y3yZR xfcg== X-Gm-Message-State: APjAAAWNYxpEC9/v/iroOoDy9asOYb60OKm4sfDn5MJwWtYTscXeEbF7 2dRvhYIVBuR8GcNGwSRnQouypv89uOg= X-Google-Smtp-Source: APXvYqxfabyQHe8JJmBtkKnKCoP3apj2DwZsDYK8S1BreosVJxxRiZpUbwk4LMrsj3s2MhtUFNfmwA== X-Received: by 2002:a92:8c49:: with SMTP id o70mr14692579ild.72.1574396600502; Thu, 21 Nov 2019 20:23:20 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:20 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:57 -0700 Message-Id: <20191122041905.224686-71-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 092/100] x86: apl: Add PUNIT driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass --- Changes in v4: - Name this P-Unit instead of power unit, in the commit message - apollolake -> Apollo Lake Changes in v3: - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 3 + arch/x86/cpu/apollolake/punit.c | 121 +++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/x86/cpu/apollolake/punit.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 36eefcbad7..875d454157 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,9 @@ # Copyright 2019 Google LLC obj-$(CONFIG_SPL_BUILD) += systemagent.o +ifndef CONFIG_TPL_BUILD +obj-y += punit.o +endif obj-y += hostbridge.o obj-y += itss.o diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c new file mode 100644 index 0000000000..3bef4686eb --- /dev/null +++ b/arch/x86/cpu/apollolake/punit.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct apl_punit_platdata - platform data for punit + * + * @pciex_region_size: BAR length in bytes + */ +struct apl_punit_platdata { + pci_dev_t bdf; +}; + +/* + * Punit Initialization code. This all isn't documented, but + * this is the recipe. + */ +static int punit_init(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + struct udevice *cpu; + u32 reg; + ulong start; + int ret; + + /* Thermal throttle activation offset */ + ret = uclass_first_device_err(UCLASS_CPU, &cpu); + if (ret) + return log_msg_ret("Cannot find CPU", ret); + cpu_configure_thermal_target(cpu); + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). + * Enable all cores here. + */ + writel(0, MCHBAR_REG(CORE_DISABLE_MASK)); + + /* P-Unit bring up */ + reg = readl(MCHBAR_REG(BIOS_RESET_CPL)); + if (reg == 0xffffffff) { + /* P-unit not found */ + debug("Punit MMIO not available\n"); + return -ENOENT; + } + + /* Set Punit interrupt pin IPIN offset 3D */ + pci_x86_write_config(plat->bdf, PCI_INTERRUPT_PIN, 0x2, PCI_SIZE_8); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK, + MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ)); + + if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + clrsetbits_le32(MCHBAR_REG(0x7818), 0x1fe0, 0x220); + + /* Stage0 BIOS Reset Complete (RST_CPL) */ + enable_bios_reset_cpl(); + + /* + * Poll for bit 8 to check if PCODE has completed its action in response + * to BIOS Reset complete. We wait here till 1 ms for the bit to get + * set. + */ + start = get_timer(0); + while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) { + if (get_timer(start) > 1) { + debug("PCODE Init Done timeout\n"); + return -ETIMEDOUT; + } + udelay(100); + } + debug("PUNIT init complete\n"); + + return 0; +} + +static int apl_punit_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_SPL) + return punit_init(dev); + + return 0; +} + +static int apl_punit_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + int root; + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + return 0; +} + +static const struct udevice_id apl_syscon_ids[] = { + { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT }, + { } +}; + +U_BOOT_DRIVER(syscon_intel_punit) = { + .name = "intel_punit_syscon", + .id = UCLASS_SYSCON, + .of_match = apl_syscon_ids, + .ofdata_to_platdata = apl_punit_ofdata_to_platdata, + .probe = apl_punit_probe, +}; From patchwork Fri Nov 22 04:18:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199288 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="apW7+/Lx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4H00h99z9sPW for ; Fri, 22 Nov 2019 16:09:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B0851C221D5; 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Thu, 21 Nov 2019 20:23:22 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:22 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:58 -0700 Message-Id: <20191122041905.224686-72-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 093/100] x86: apl: Add SPL loaders X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: - Add a driver for APL SPI for TPL (using of-platdata) - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support bootstage timing Changes in v2: None arch/x86/cpu/apollolake/Makefile | 2 + arch/x86/cpu/apollolake/spl.c | 202 +++++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 arch/x86/cpu/apollolake/spl.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 875d454157..1fde400d77 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,7 +2,9 @@ # # Copyright 2019 Google LLC +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o + ifndef CONFIG_TPL_BUILD obj-y += punit.o endif diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c new file mode 100644 index 0000000000..a12379e312 --- /dev/null +++ b/arch/x86/cpu/apollolake/spl.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * We need to read well past the end of the region in order for execution from + * the loaded data to work. It is not clear why. + */ +#define SAFETY_MARGIN 0x4000 + +binman_sym_declare(ulong, u_boot_spl, image_pos); +binman_sym_declare(ulong, u_boot_spl, size); +/* U-Boot image_pos is declared by common/spl/spl.c */ +binman_sym_declare(ulong, u_boot_any, size); + +static ulong get_image_pos(void) +{ + return spl_phase() == PHASE_TPL ? + binman_sym(ulong, u_boot_spl, image_pos) : + binman_sym(ulong, u_boot_any, image_pos); +} + +static ulong get_image_size(void) +{ + return spl_phase() == PHASE_TPL ? + binman_sym(ulong, u_boot_spl, size) : + binman_sym(ulong, u_boot_any, size); +} + +/* This reads the next phase from mapped SPI flash */ +static int rom_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + ulong spl_pos = get_image_pos(); + ulong spl_size = get_image_size(); + struct udevice *dev; + ulong map_base; + size_t map_size; + uint offset; + int ret; + + spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ + spl_image->entry_point = spl_phase() == PHASE_TPL ? + CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = spl_image->entry_point; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size); + + if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) { + ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("spi_flash", ret); + if (!dev) + return log_msg_ret("spi_flash dev", -ENODEV); + ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset); + if (ret) + return log_msg_ret("mmap", ret); + } else { + ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size, + &offset); + if (ret) + return ret; + } + spl_pos += map_base & ~0xff000000; + debug(", base %lx, pos %lx\n", map_base, spl_pos); + bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); + memcpy((void *)spl_image->load_addr, (void *)spl_pos, + spl_size + SAFETY_MARGIN); + bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image); + +#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT) + +static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len, + void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + struct mtd_info *mtd = &flash->mtd; + size_t retlen; + + return log_ret(mtd->_read(mtd, offset, len, &retlen, buf)); +} + +static int apl_flash_probe(struct udevice *dev) +{ + return spi_flash_std_probe(dev); +} + +/* + * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also + * need to allocate the parent_platdata since by the time this function is + * called device_bind() has already gone past that step. + */ +static int apl_flash_bind(struct udevice *dev) +{ + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + struct dm_spi_slave_platdata *plat; + struct udevice *spi; + int ret; + + ret = uclass_first_device_err(UCLASS_SPI, &spi); + if (ret) + return ret; + dev->parent = spi; + + plat = calloc(sizeof(*plat), 1); + if (!plat) + return -ENOMEM; + dev->parent_platdata = plat; + } + + return 0; +} + +static const struct dm_spi_flash_ops apl_flash_ops = { + .read = apl_flash_std_read, +}; + +static const struct udevice_id apl_flash_ids[] = { + { .compatible = "jedec,spi-nor" }, + { } +}; + +U_BOOT_DRIVER(winbond_w25q128fw) = { + .name = "winbond_w25q128fw", + .id = UCLASS_SPI_FLASH, + .of_match = apl_flash_ids, + .bind = apl_flash_bind, + .probe = apl_flash_probe, + .priv_auto_alloc_size = sizeof(struct spi_flash), + .ops = &apl_flash_ops, +}; + +/* This uses a SPI flash device to read the next phase */ +static int spl_fast_spi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + ulong spl_pos = get_image_pos(); + ulong spl_size = get_image_size(); + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return ret; + + spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ + spl_image->entry_point = spl_phase() == PHASE_TPL ? + CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = spl_image->entry_point; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + spl_pos &= ~0xff000000; + debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size); + ret = spi_flash_read_dm(dev, spl_pos, spl_size + SAFETY_MARGIN, + (void *)spl_image->load_addr); + if (ret) + return ret; + + return 0; +} +SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI, + spl_fast_spi_load_image); + +void board_boot_order(u32 *spl_boot_list) +{ + bool use_spi_flash = BOOT_FROM_FAST_SPI_FLASH; + + if (use_spi_flash) { + spl_boot_list[0] = BOOT_DEVICE_FAST_SPI; + spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP; + } else { + spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP; + spl_boot_list[1] = BOOT_DEVICE_FAST_SPI; + } +} + +#else + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP; +} +#endif From patchwork Fri Nov 22 04:18:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199273 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Gy7QxDR6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K47P0lwnz9s7T for ; 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Thu, 21 Nov 2019 20:23:24 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:24 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:18:59 -0700 Message-Id: <20191122041905.224686-73-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 094/100] x86: apl: Add a CPU driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass --- Changes in v4: - Change apollolake to apl - Tidy up header guards Changes in v3: - Add two more defines for the CPU driver - Expand comments for BOOT_FROM_FAST_SPI_FLASH Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/cpu.c | 51 ++++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 27 ++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1fde400d77..274d44e859 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o ifndef CONFIG_TPL_BUILD +obj-y += cpu.o obj-y += punit.o endif diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c new file mode 100644 index 0000000000..089923e85a --- /dev/null +++ b/arch/x86/cpu/apollolake/cpu.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include + +struct cpu_apl_priv { +}; + +static int apl_get_info(struct udevice *dev, struct cpu_info *info) +{ + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); +} + +static int apl_get_count(struct udevice *dev) +{ + return 4; +} + +static int cpu_x86_apl_probe(struct udevice *dev) +{ + return 0; +} + +static const struct cpu_ops cpu_x86_apl_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = apl_get_info, + .get_count = apl_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_apl_ids[] = { + { .compatible = "intel,apl-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_apl_drv) = { + .name = "cpu_x86_apl", + .id = UCLASS_CPU, + .of_match = cpu_x86_apl_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_apl_probe, + .ops = &cpu_x86_apl_ops, + .priv_auto_alloc_size = sizeof(struct cpu_apl_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h b/arch/x86/include/asm/arch-apollolake/cpu.h new file mode 100644 index 0000000000..ab712b0810 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/cpu.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +/* Common Timer Copy (CTC) frequency - 19.2MHz */ +#define CTC_FREQ 19200000 + +/* + * Set to true to use the fast SPI driver to boot, instead of mapped SPI. + * You also need to enable CONFIG_APL_SPI_FLASH_BOOT. + */ +#define BOOT_FROM_FAST_SPI_FLASH false + +/* + * We need to read well past the end of the region in order for execution from + * the loaded data to work. It is not clear why. + */ +#define SAFETY_MARGIN 0x4000 + +#define MAX_PCIE_PORTS 6 +#define CLKREQ_DISABLED 0xf + +#endif /* _ASM_ARCH_CPU_H */ From patchwork Fri Nov 22 04:19:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199292 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Zr0VDVJR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K4KQ1t7qz9sPW for ; Fri, 22 Nov 2019 16:11:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DC709C22201; Fri, 22 Nov 2019 04:49:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C96EC220AF; Fri, 22 Nov 2019 04:49:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DC3ECC22083; Fri, 22 Nov 2019 04:23:34 +0000 (UTC) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by lists.denx.de (Postfix) with ESMTPS id A02DCC2202B for ; Fri, 22 Nov 2019 04:23:28 +0000 (UTC) Received: by mail-io1-f67.google.com with SMTP id k1so6406741ioj.6 for ; Thu, 21 Nov 2019 20:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hYIQn0hqBjEVU6F2Gboi+FMzZJzWPfo8f5yu3cl1d6Q=; b=Zr0VDVJRqo9zev1svWvyxjX5gu/W8IQwcORIMh0OLucUKPWE22QMe6taiqNor6xEsp zqBaQ+5YylWElR6IueMEAB6hHRCJ999ZWkgouszDtQmO48ld8jAPvyqKv+UQvNVsFAnF Hk93Bf2cYK6VDXkbnELiOFTc+I0ENUEjr3Wks= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hYIQn0hqBjEVU6F2Gboi+FMzZJzWPfo8f5yu3cl1d6Q=; b=XqJIipWKaRvOHFnOSLvG4My6efifsjfDNwuImszRdgiYA9CEpO6dNQqI5DVuTWOK9F TQESJnSDga1QTugxOgJNaSFhpgjj2Lg43sr/l7PqWDhPDYcPw2HEqBPa1nayK4mSkMcJ 1gqQTljNXrgrLaL/ZXUDIHIZeQFp9RRIOVydjzJQjC7S9jTZwx0EXCP/lycHVJCBA3bs 6ScNdd3ccl61TrttgphCk/kXhy8+hqcs6nSsPSQ7FrVWPsZ9BaDQRuIA1EhIIEpe4aOW +mbksTODAJjuPQog1tnikwEdQlBjVJ2J0GUfz0iLQmzevMZEdvj35bu4Pr+r/a+23D9r +yYw== X-Gm-Message-State: APjAAAVccH6CI7SiMKu/sA43Yi4GxXyr1O48PI6AO47xLYmECC9qgEkf 1VhvviCvgc24zK6BGRX3TzHUGWAPo3U= X-Google-Smtp-Source: APXvYqzd9oY9RbTnGSGTdzBkFDf+h0RsAczqJ13rJPU6/jX9MHlBeDtGf+wAvOKFrYbzdSr8VIhnsA== X-Received: by 2002:a6b:6909:: with SMTP id e9mr10339453ioc.124.1574396607307; Thu, 21 Nov 2019 20:23:27 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:27 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:00 -0700 Message-Id: <20191122041905.224686-74-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 095/100] x86: apl: Add SPL/TPL init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass --- Changes in v4: - Switch over to use pinctrl for pad init/config Changes in v3: - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Fix build error when debug UART is disabled - Init the p2sb before the northbridge since the latter so it can use GPIOs - Move location of fast_spi.h header file - Shorten log_msg_ret() calls since the function name is always printed - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/cpu_spl.c | 274 ++++++++++++++++++++++++++++++ 2 files changed, 275 insertions(+) create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 274d44e859..eabb542f71 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,6 +2,7 @@ # # Copyright 2019 Google LLC +obj-$(CONFIG_SPL_BUILD) += cpu_spl.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c new file mode 100644 index 0000000000..3298448352 --- /dev/null +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + * + * Portions taken from coreboot + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Define this here to avoid referencing any drivers for the debug UART 1 */ +#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0) + +static void pch_uart_init(void) +{ + /* + * Set up the pinmux so that the UART rx/tx signals are connected + * outside the SoC. + * + * There are about 500 lines of code required to program the GPIO + * configuration for the UARTs. But it boils down to four writes, and + * for the debug UART we want the minimum possible amount of code before + * the UART is running. So just add the magic writes here. See + * apl_gpio_early_init() for the full horror. + */ + if (PCI_FUNC(PCH_DEV_UART) == 1) { + writel(0x40000402, 0xd0c50650); + writel(0x3c47, 0xd0c50654); + writel(0x40000400, 0xd0c50658); + writel(0x3c48, 0xd0c5065c); + } else { /* UART2 */ + writel(0x40000402, 0xd0c50670); + writel(0x3c4b, 0xd0c50674); + writel(0x40000400, 0xd0c50678); + writel(0x3c4c, 0xd0c5067c); + } + +#ifdef CONFIG_DEBUG_UART + apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE); +#endif +} + +static void p2sb_enable_bar(ulong bar) +{ + /* Enable PCR Base address in PCH */ + pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar, + PCI_SIZE_32); + pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); + + /* Enable P2SB MSE */ + pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY, + PCI_SIZE_8); +} + +/* + * init_for_uart() - Init the debug UART ready for use + * + * This is the minimum init needed to get the UART running. It avoids any + * drivers or complex code, so that the UART is running as soon as possible. + */ +static void init_for_uart(void) +{ + p2sb_enable_bar(IOMAP_P2SB_BAR); + pch_uart_init(); +} + +static int fast_spi_cache_bios_region(void) +{ + uint map_size, offset; + ulong map_base, base; + int ret; + + ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE); + if (ret) + return log_msg_ret("early_init", ret); + + ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size, + &offset); + if (ret) + return log_msg_ret("get_mmap", ret); + + base = (4ULL << 30) - map_size; + mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size); + log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size); + + return 0; +} + +static void enable_pm_timer_emulation(struct udevice *pmc) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc); + msr_t msr; + + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * + * Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is + * used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + + /* Set PM1 timer IO port and enable */ + msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR); + debug("PM timer %x %x\n", msr.hi, msr.lo); + msr_write(MSR_EMULATE_PM_TIMER, msr); +} + +static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep) +{ + uint base; + uint size; + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) { + base = MEC_EMI_BASE; + size = MEC_EMI_SIZE; + } else { + base = EC_HOST_CMD_REGION0; + size = 2 * EC_HOST_CMD_REGION_SIZE; + /* Make sure MEMMAP region follows host cmd region */ + assert(base + size == EC_LPC_ADDR_MEMMAP); + size += EC_MEMMAP_SIZE; + } + + *out_basep = base; + *out_sizep = size; +} + +static void early_ec_init(void) +{ + uint base, size; + + /* + * Set up LPC decoding for the Chrome OS EC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - Chrome OS EC communication I/O ports + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 | + LPC_IOE_LGE_200); + google_chromeec_ioport_range(&base, &size); + lpc_open_pmio_window(base, size); +} + +static int arch_cpu_init_tpl(void) +{ + struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); + if (ret) + return log_msg_ret("PMC", ret); + + /* Clear global reset promotion bit */ + ret = pmc_global_reset_set_enable(pmc, false); + if (ret) + return log_msg_ret("disable global reset", ret); + + enable_pm_timer_emulation(pmc); + + ret = uclass_first_device_err(UCLASS_P2SB, &p2sb); + if (ret) + return log_msg_ret("p2sb", ret); + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa); + if (ret) + return log_msg_ret("northbridge", ret); + gd->baudrate = CONFIG_BAUDRATE; + ret = uclass_first_device_err(UCLASS_SERIAL, &serial); + if (ret) + return log_msg_ret("serial", ret); + if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) { + ret = uclass_first_device_err(UCLASS_SPI, &spi); + if (ret) + return log_msg_ret("SPI", ret); + } else { + /* Alternative code if we don't have SPI in TPL */ + if (BOOT_FROM_FAST_SPI_FLASH) + printf("Warning: Enable APL_SPI_FLASHBOOT to use SPI-flash driver in TPL"); + ret = fast_spi_cache_bios_region(); + if (ret) + return log_msg_ret("BIOS cache", ret); + } + ret = pmc_disable_tco(pmc); + if (ret) + return log_msg_ret("disable TCO", ret); + ret = pmc_gpe_init(pmc); + if (ret) + return log_msg_ret("pmc_gpe", ret); + ret = uclass_first_device_err(UCLASS_LPC, &lpc); + if (ret) + return log_msg_ret("lpc", ret); + + early_ec_init(); + + return 0; +} + +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static int arch_cpu_init_spl(void) +{ + struct udevice *pmc, *p2sb; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); + if (ret) + return log_msg_ret("Could not probe PMC", ret); + ret = uclass_first_device_err(UCLASS_P2SB, &p2sb); + if (ret) + return log_msg_ret("Cannot set up p2sb", ret); + + lpc_io_setup_comm_a_b(); + /* enable_rtc_upper_bank(); */ + + ret = pmc_init(pmc); + if (ret < 0) + return log_msg_ret("Could not init PMC", ret); +#ifdef CONFIG_HAVE_ACPI_RESUME + ret = pmc_prev_sleep_state(pmc); + if (ret < 0) + return log_msg_ret("Could not get PMC sleep state", ret); + gd->arch.prev_sleep_state = ret; +#endif + + return 0; +} + +int arch_cpu_init(void) +{ + int ret = 0; + + if (spl_phase() == PHASE_TPL) + ret = arch_cpu_init_tpl(); + else if (spl_phase() == PHASE_SPL) + ret = arch_cpu_init_spl(); + if (ret) + printf("%s: Error %d\n", __func__, ret); + + return ret; +} + +void board_debug_uart_init(void) +{ + init_for_uart(); +} From patchwork Fri Nov 22 04:19:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199291 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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Thu, 21 Nov 2019 20:23:29 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:29 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:01 -0700 Message-Id: <20191122041905.224686-75-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 096/100] x86: apl: Add P2SB driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass --- Changes in v4: - Detect zero mmio address - Use BIT() macro bit more - apollolake -> Apollo Lake Changes in v3: - Use pci_get_devfn() Changes in v2: None arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/p2sb.c | 167 +++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 arch/x86/cpu/apollolake/p2sb.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index eabb542f71..1cce759124 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -14,6 +14,7 @@ endif obj-y += hostbridge.o obj-y += itss.o obj-y += lpc.o +obj-y += p2sb.o obj-y += pch.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c new file mode 100644 index 0000000000..0a5deaf4a0 --- /dev/null +++ b/arch/x86/cpu/apollolake/p2sb.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Primary-to-Sideband Bridge + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_P2SB + +#include +#include +#include +#include +#include +#include + +struct p2sb_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_p2sb dtplat; +#endif + ulong mmio_base; + pci_dev_t bdf; +}; + +/* PCI config space registers */ +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT BIT(7) + +/* High Performance Event Timer Configuration */ +#define P2SB_HPTC 0x60 +#define P2SB_HPTC_ADDRESS_ENABLE BIT(7) + +/* + * ADDRESS_SELECT ENCODING_RANGE + * 0 0xfed0 0000 - 0xfed0 03ff + * 1 0xfed0 1000 - 0xfed0 13ff + * 2 0xfed0 2000 - 0xfed0 23ff + * 3 0xfed0 3000 - 0xfed0 33ff + */ +#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) + +/* + * apl_p2sb_early_init() - Enable decoding for HPET range + * + * This is needed for FspMemoryInit to store and retrieve a global data + * pointer + * + * @dev: P2SB device + * @return 0 if OK, -ve on error + */ +static int apl_p2sb_early_init(struct udevice *dev) +{ + struct p2sb_platdata *plat = dev_get_platdata(dev); + pci_dev_t pdev = plat->bdf; + + /* + * Enable decoding for HPET memory address range. + * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode + * the High Performance Timer memory address range + * selected by bits 1:0 + */ + pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT, + PCI_SIZE_8); + + /* Enable PCR Base address in PCH */ + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base, + PCI_SIZE_32); + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); + + /* Enable P2SB MSE */ + pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY, PCI_SIZE_8); + + return 0; +} + +static int apl_p2sb_spl_init(struct udevice *dev) +{ + /* Enable decoding for HPET. Needed for FSP global pointer storage */ + dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | + P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8); + + return 0; +} + +int apl_p2sb_ofdata_to_platdata(struct udevice *dev) +{ + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); + struct p2sb_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int ret; + + if (spl_phase() == PHASE_TPL) { + u32 base[2]; + + /* TPL sets up the initial BAR */ + ret = dev_read_u32_array(dev, "early-regs", base, + ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + plat->bdf = pci_get_devfn(dev); + if (plat->bdf < 0) + return log_msg_ret("Cannot get p2sb PCI address", + plat->bdf); + } else { + plat->mmio_base = dev_read_addr_pci(dev); + /* Don't set BDF since it should not be used */ + if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) + return -EINVAL; + } +#else + plat->mmio_base = plat->dtplat.early_regs[0]; + plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + upriv->mmio_base = plat->mmio_base; + debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); + + return 0; +} + +static int apl_p2sb_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_p2sb_early_init(dev); + else if (spl_phase() == PHASE_SPL) + return apl_p2sb_spl_init(dev); + + return 0; +} + +static int p2sb_child_post_bind(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; +#endif + + return 0; +} + +static const struct udevice_id apl_p2sb_ids[] = { + { .compatible = "intel,apl-p2sb" }, + { } +}; + +U_BOOT_DRIVER(apl_p2sb_drv) = { + .name = "intel_apl_p2sb", + .id = UCLASS_P2SB, + .of_match = apl_p2sb_ids, + .probe = apl_p2sb_probe, + .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), + .per_child_platdata_auto_alloc_size = + sizeof(struct p2sb_child_platdata), + .child_post_bind = p2sb_child_post_bind, +}; From patchwork Fri Nov 22 04:19:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199253 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="F9N9MF5Y"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3vP0yz1z9sPJ for ; Fri, 22 Nov 2019 15:52:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BC416C220C6; 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Thu, 21 Nov 2019 20:23:31 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:31 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:02 -0700 Message-Id: <20191121211845.v4.97.I4e81b308a4f32d13eaf045072fd913dbbf3fc816@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 097/100] x86: apl: Add Kconfig and Makefile X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass --- Changes in v4: - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Switch over to use pinctrl for pad init/config - Use existing VBT Kconfig option - apollolake -> Apollo Lake Changes in v3: - Add MMC, video, USB configs - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Fix the incorrect value of CPU_ADDR_BITS Changes in v2: None arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/apollolake/Kconfig | 86 +++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) create mode 100644 arch/x86/cpu/apollolake/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ae96e69f86..54ad934172 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -106,6 +106,7 @@ source "board/google/Kconfig" source "board/intel/Kconfig" # platform-specific options below +source "arch/x86/cpu/apollolake/Kconfig" source "arch/x86/cpu/baytrail/Kconfig" source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index b6a010ea32..4c151f8c94 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -41,6 +41,7 @@ extra-y += call32.o endif obj-y += intel_common/ +obj-$(CONFIG_INTEL_APOLLOLAKE) += apollolake/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig new file mode 100644 index 0000000000..5b923ba0ef --- /dev/null +++ b/arch/x86/cpu/apollolake/Kconfig @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2019 Google LLC +# + +config INTEL_APOLLOLAKE + bool + select FSP_VERSION2 + select HAVE_FSP + select ARCH_MISC_INIT + select USE_CAR + select INTEL_PMC + select TPL_X86_TSC_TIMER_NATIVE + select SPL_PCH_SUPPORT + select TPL_PCH_SUPPORT + select PCH_SUPPORT + select P2SB + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply SCSI + imply SCSI_AHCI + imply SPI_FLASH + imply USB + imply USB_EHCI_HCD + imply TPL + imply SPL + imply TPL_X86_16BIT_INIT + imply TPL_OF_PLATDATA + imply ACPI_PMC + imply MMC + imply DM_MMC + imply MMC_PCI + imply MMC_SDHCI + imply CMD_MMC + imply VIDEO_FSP + imply PINCTRL_INTEL + imply PINCTRL_INTEL_APL + imply HAVE_VBT + imply HAVE_X86_FIT + imply INTEL_GPIO + +if INTEL_APOLLOLAKE + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0xc0000 + +config DCACHE_RAM_MRC_VAR_SIZE + default 0xb0000 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config TPL_SIZE_LIMIT + default 0x7800 + +config CPU_ADDR_BITS + default 39 + +config APL_SPI_FLASH_BOOT + bool "Support booting with SPI-flash driver instead memory-mapped SPI" + select TPL_SPI_FLASH_SUPPORT + select TPL_SPI_SUPPORT + help + If you want to set BOOT_FROM_FAST_SPI_FLASH to true, enable this + option. It enables SPI and SPI flash in TPL. Without the this only + available boot method is to use memory-mapped SPI. Since this is + actually fast and produces a TPL which is 7KB smaller, it is the + default. + +config VBT_ADDR + default 0xff3f1000 + +endif From patchwork Fri Nov 22 04:19:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199244 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="E44nfqxz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K3pN5JV8z9sPf for ; Fri, 22 Nov 2019 15:48:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 51811C22085; Fri, 22 Nov 2019 04:44:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9F071C2200D; Fri, 22 Nov 2019 04:34:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 61CC2C22090; Fri, 22 Nov 2019 04:23:38 +0000 (UTC) Received: from mail-il1-f194.google.com (mail-il1-f194.google.com [209.85.166.194]) by lists.denx.de (Postfix) with ESMTPS id DA3AAC2202B for ; Fri, 22 Nov 2019 04:23:34 +0000 (UTC) Received: by mail-il1-f194.google.com with SMTP id s75so5625831ilc.3 for ; Thu, 21 Nov 2019 20:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cCOSA4KSRMIqN68RD9lW1ZON2pl081fXW5Gv06CWtIs=; b=E44nfqxzANFcOOXKUzUhXEcAa2zZrrSb2+nQ7XfZR96OBnEhxrKxvZLiLf9aIUUmg+ oSPMEeuNGQ05ZErJ3lG2DfNCslTfCoiO68OfCURHnPdzDBHZhzv36qzovky4HPelpsL2 H/T9XgZcgAmIO3NOngwV/kGX1vItZZ+1M1scs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cCOSA4KSRMIqN68RD9lW1ZON2pl081fXW5Gv06CWtIs=; b=ZmiLi0bL/57ToSNAyhxgFAuKDs3sE0vyQMOyvh6X2CefY0Z/tl4r+YW/63clvfMSb2 SsqnwL9dGmixKfwUMNaEsuTpBZW7rXkj8dt+JXwnbzatfhj8oy6PkiHvCanHSDwX5o29 884EbAyJ9/VJp3l0OoxYMjV+I4PkWCCNXMVxZPzW0Q5uguVOScTQrBw1NX33Xva4vIag ekpAPAEAEzG+lx4tq9Ut/86FVGanASHl3cKuKKDu7RK6atNVtuq6jKdG9DsQrYThiN6o 4pOuun1MeOVwNe5MZj5VrIMEB6mnZMe+IZh78Ptks5S6OrQQr/0/BlEKrZR/2GWdnRLu hEug== X-Gm-Message-State: APjAAAXBSLmkGerAslWyKH+8YZEgJAnenSv39h5muFbl+j8ght+13Phh wasJu6jhuWAJf/H2XRpAGDrEmpZLaj0= X-Google-Smtp-Source: APXvYqws23JW7qEhE5mwkQKuT1YIbPBOitk21u28NCzFMC1hHWnn5dfpFJYMzSWsRRsP331Tojm7Sw== X-Received: by 2002:a92:5cce:: with SMTP id d75mr14464320ilg.299.1574396613488; Thu, 21 Nov 2019 20:23:33 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:33 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:03 -0700 Message-Id: <20191122041905.224686-76-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 098/100] x86: apl: Add FSP structures X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass --- Changes in v4: - apollolake -> Apollo Lake Changes in v3: - Add VBT signature - Add structures for FSP-S also - Drop struct fsp_usp_header as it is now in the API file Changes in v2: None .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 ++++++++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++++++++++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + 4 files changed, 440 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h new file mode 100644 index 0000000000..9185d94b2b --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#define VBT_SIGNATURE 0x54425624 + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h new file mode 100644 index 0000000000..e673fa9966 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_ARCH_FSP_M_UDP_H +#define __ASM_ARCH_FSP_M_UDP_H + +#include + +#define FSP_DRAM_CHANNELS 4 + +struct __packed fspm_arch_upd { + u8 revision; + u8 reserved[3]; + void *nvs_buffer_ptr; + void *stack_base; + u32 stack_size; + u32 boot_loader_tolum_size; + u32 boot_mode; + u8 reserved1[8]; +}; + +struct __packed fsp_ram_channel { + u8 rank_enable; + u8 device_width; + u8 dram_density; + u8 option; + u8 odt_config; + u8 tristate_clk1; + u8 mode2_n; + u8 odt_levels; +}; + +struct __packed fsp_m_config { + u32 serial_debug_port_address; + u8 serial_debug_port_type; + u8 serial_debug_port_device; + u8 serial_debug_port_stride_size; + u8 mrc_fast_boot; + u8 igd; + u8 igd_dvmt50_pre_alloc; + u8 igd_aperture_size; + u8 gtt_size; + u8 primary_video_adaptor; + u8 package; + u8 profile; + u8 memory_down; + + u8 ddr3_l_page_size; + u8 ddr3_lasr; + u8 scrambler_support; + u8 interleaved_mode; + u16 channel_hash_mask; + u16 slice_hash_mask; + u8 channels_slices_enable; + u8 min_ref_rate2x_enable; + u8 dual_rank_support_enable; + u8 rmt_mode; + u16 memory_size_limit; + u16 low_memory_max_value; + + u16 high_memory_max_value; + u8 disable_fast_boot; + u8 dimm0_spd_address; + u8 dimm1_spd_address; + struct fsp_ram_channel chan[FSP_DRAM_CHANNELS]; + u8 rmt_check_run; + u16 rmt_margin_check_scale_high_threshold; + u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32]; + u32 msg_level_mask; + u8 unused_upd_space0[4]; + + u8 pre_mem_gpio_table_pin_num[4]; + u32 pre_mem_gpio_table_ptr; + u8 pre_mem_gpio_table_entry_num; + u8 enhance_port8xh_decoding; + u8 spd_write_enable; + u8 mrc_data_saving; + u32 oem_loading_base; + + u8 oem_file_name[16]; + + void *mrc_boot_data_ptr; + u8 e_mmc_trace_len; + u8 skip_cse_rbp; + u8 npk_en; + u8 fw_trace_en; + u8 fw_trace_destination; + u8 recover_dump; + u8 msc0_wrap; + u8 msc1_wrap; + u32 msc0_size; + + u32 msc1_size; + u8 pti_mode; + u8 pti_training; + u8 pti_speed; + u8 punit_mlvl; + + u8 pmc_mlvl; + u8 sw_trace_en; + u8 periodic_retraining_disable; + u8 enable_reset_system; + + u8 enable_s3_heci2; + u8 unused_upd_space1[3]; + + void *variable_nvs_buffer_ptr; + u8 reserved_fspm_upd[12]; +}; + +/** Fsp M UPD Configuration */ +struct __packed fspm_upd { + struct fsp_upd_header header; + struct fspm_arch_upd arch; + struct fsp_m_config config; + u8 unused_upd_space2[158]; + u16 upd_terminator; +}; + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h new file mode 100644 index 0000000000..ef908906b8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (c) 2016, Intel Corporation. All rights reserved. + * Copyright 2019 Google LLC + */ +#ifndef __ASM_ARCH_FSP_S_UDP_H +#define __ASM_ARCH_FSP_S_UDP_H + +#include + +struct __packed fsp_s_config { + u8 active_processor_cores; + u8 disable_core1; + u8 disable_core2; + u8 disable_core3; + u8 vmx_enable; + u8 proc_trace_mem_size; + u8 proc_trace_enable; + u8 eist; + u8 boot_p_state; + u8 enable_cx; + u8 c1e; + u8 bi_proc_hot; + u8 pkg_c_state_limit; + u8 c_state_auto_demotion; + u8 c_state_un_demotion; + u8 max_core_c_state; + u8 pkg_c_state_demotion; + u8 pkg_c_state_un_demotion; + u8 turbo_mode; + u8 hda_verb_table_entry_num; + u32 hda_verb_table_ptr; + u8 p2sb_unhide; + u8 ipu_en; + u8 ipu_acpi_mode; + u8 force_wake; + u32 gtt_mm_adr; + u32 gm_adr; + u8 pavp_lock; + u8 graphics_freq_modify; + u8 graphics_freq_req; + u8 graphics_video_freq; + u8 pm_lock; + u8 dop_clock_gating; + u8 unsolicited_attack_override; + u8 wopcm_support; + u8 wopcm_size; + u8 power_gating; + u8 unit_level_clock_gating; + u8 fast_boot; + u8 dyn_sr; + u8 sa_ipu_enable; + u8 pm_support; + u8 enable_render_standby; + u32 logo_size; + u32 logo_ptr; + u32 graphics_config_ptr; + u8 pavp_enable; + u8 pavp_pr3; + u8 cd_clock; + u8 pei_graphics_peim_init; + u8 write_protection_enable[5]; + u8 read_protection_enable[5]; + u16 protected_range_limit[5]; + u16 protected_range_base[5]; + u8 gmm; + u8 clk_gating_pgcb_clk_trunk; + u8 clk_gating_sb; + u8 clk_gating_sb_clk_trunk; + u8 clk_gating_sb_clk_partition; + u8 clk_gating_core; + u8 clk_gating_dma; + u8 clk_gating_reg_access; + u8 clk_gating_host; + u8 clk_gating_partition; + u8 clk_gating_trunk; + u8 hda_enable; + u8 dsp_enable; + u8 pme; + u8 hd_audio_io_buffer_ownership; + u8 hd_audio_io_buffer_voltage; + u8 hd_audio_vc_type; + u8 hd_audio_link_frequency; + u8 hd_audio_i_disp_link_frequency; + u8 hd_audio_i_disp_link_tmode; + u8 dsp_endpoint_dmic; + u8 dsp_endpoint_bluetooth; + u8 dsp_endpoint_i2s_skp; + u8 dsp_endpoint_i2s_hp; + u8 audio_ctl_pwr_gate; + u8 audio_dsp_pwr_gate; + u8 mmt; + u8 hmt; + u8 hd_audio_pwr_gate; + u8 hd_audio_clk_gate; + u32 dsp_feature_mask; + u32 dsp_pp_module_mask; + u8 bios_cfg_lock_down; + u8 hpet; + u8 hpet_bdf_valid; + u8 hpet_bus_number; + u8 hpet_device_number; + u8 hpet_function_number; + u8 io_apic_bdf_valid; + u8 io_apic_bus_number; + u8 io_apic_device_number; + u8 io_apic_function_number; + u8 io_apic_entry24_119; + u8 io_apic_id; + u8 io_apic_range_select; + u8 ish_enable; + u8 bios_interface; + u8 bios_lock; + u8 spi_eiss; + u8 bios_lock_sw_smi_number; + u8 lpss_s0ix_enable; + u8 unused_upd_space0[1]; + u8 i2c_clk_gate_cfg[8]; + u8 hsuart_clk_gate_cfg[4]; + u8 spi_clk_gate_cfg[3]; + u8 i2c0_enable; + u8 i2c1_enable; + u8 i2c2_enable; + u8 i2c3_enable; + u8 i2c4_enable; + u8 i2c5_enable; + u8 i2c6_enable; + u8 i2c7_enable; + u8 hsuart0_enable; + u8 hsuart1_enable; + u8 hsuart2_enable; + u8 hsuart3_enable; + u8 spi0_enable; + u8 spi1_enable; + u8 spi2_enable; + u8 os_dbg_enable; + u8 dci_en; + u32 uart2_kernel_debug_base_address; + u8 pcie_clock_gating_disabled; + u8 pcie_root_port8xh_decode; + u8 pcie8xh_decode_port_index; + u8 pcie_root_port_peer_memory_write_enable; + u8 pcie_aspm_sw_smi_number; + u8 unused_upd_space1[1]; + u8 pcie_root_port_en[6]; + u8 pcie_rp_hide[6]; + u8 pcie_rp_slot_implemented[6]; + u8 pcie_rp_hot_plug[6]; + u8 pcie_rp_pm_sci[6]; + u8 pcie_rp_ext_sync[6]; + u8 pcie_rp_transmitter_half_swing[6]; + u8 pcie_rp_acs_enabled[6]; + u8 pcie_rp_clk_req_supported[6]; + u8 pcie_rp_clk_req_number[6]; + u8 pcie_rp_clk_req_detect[6]; + u8 advanced_error_reporting[6]; + u8 pme_interrupt[6]; + u8 unsupported_request_report[6]; + u8 fatal_error_report[6]; + u8 no_fatal_error_report[6]; + u8 correctable_error_report[6]; + u8 system_error_on_fatal_error[6]; + u8 system_error_on_non_fatal_error[6]; + u8 system_error_on_correctable_error[6]; + u8 pcie_rp_speed[6]; + u8 physical_slot_number[6]; + u8 pcie_rp_completion_timeout[6]; + u8 ptm_enable[6]; + u8 pcie_rp_aspm[6]; + u8 pcie_rp_l1_substates[6]; + u8 pcie_rp_ltr_enable[6]; + u8 pcie_rp_ltr_config_lock[6]; + u8 pme_b0_s5_dis; + u8 pci_clock_run; + u8 timer8254_clk_setting; + u8 enable_sata; + u8 sata_mode; + u8 sata_salp_support; + u8 sata_pwr_opt_enable; + u8 e_sata_speed_limit; + u8 speed_limit; + u8 unused_upd_space2[1]; + u8 sata_ports_enable[2]; + u8 sata_ports_dev_slp[2]; + u8 sata_ports_hot_plug[2]; + u8 sata_ports_interlock_sw[2]; + u8 sata_ports_external[2]; + u8 sata_ports_spin_up[2]; + u8 sata_ports_solid_state_drive[2]; + u8 sata_ports_enable_dito_config[2]; + u8 sata_ports_dm_val[2]; + u8 unused_upd_space3[2]; + u16 sata_ports_dito_val[2]; + u16 sub_system_vendor_id; + u16 sub_system_id; + u8 crid_settings; + u8 reset_select; + u8 sdcard_enabled; + u8 e_mmc_enabled; + u8 e_mmc_host_max_speed; + u8 ufs_enabled; + u8 sdio_enabled; + u8 gpp_lock; + u8 sirq_enable; + u8 sirq_mode; + u8 start_frame_pulse; + u8 smbus_enable; + u8 arp_enable; + u8 unused_upd_space4; + u16 num_rsvd_smbus_addresses; + u8 rsvd_smbus_address_table[128]; + u8 disable_compliance_mode; + u8 usb_per_port_ctl; + u8 usb30_mode; + u8 unused_upd_space5[1]; + u8 port_usb20_enable[8]; + u8 port_us20b_over_current_pin[8]; + u8 usb_otg; + u8 hsic_support_enable; + u8 port_usb30_enable[6]; + u8 port_us30b_over_current_pin[6]; + u8 ssic_port_enable[2]; + u16 dlane_pwr_gating; + u8 vtd_enable; + u8 lock_down_global_smi; + u16 reset_wait_timer; + u8 rtc_lock; + u8 sata_test_mode; + u8 ssic_rate[2]; + u16 dynamic_power_gating; + u16 pcie_rp_ltr_max_snoop_latency[6]; + u8 pcie_rp_snoop_latency_override_mode[6]; + u8 unused_upd_space6[2]; + u16 pcie_rp_snoop_latency_override_value[6]; + u8 pcie_rp_snoop_latency_override_multiplier[6]; + u8 skip_mp_init; + u8 dci_auto_detect; + u16 pcie_rp_ltr_max_non_snoop_latency[6]; + u8 pcie_rp_non_snoop_latency_override_mode[6]; + u8 tco_timer_halt_lock; + u8 pwr_btn_override_period; + u16 pcie_rp_non_snoop_latency_override_value[6]; + u8 pcie_rp_non_snoop_latency_override_multiplier[6]; + u8 pcie_rp_slot_power_limit_scale[6]; + u8 pcie_rp_slot_power_limit_value[6]; + u8 disable_native_power_button; + u8 power_butter_debounce_mode; + u32 sdio_tx_cmd_cntl; + u32 sdio_tx_data_cntl1; + u32 sdio_tx_data_cntl2; + u32 sdio_rx_cmd_data_cntl1; + u32 sdio_rx_cmd_data_cntl2; + u32 sdcard_tx_cmd_cntl; + u32 sdcard_tx_data_cntl1; + u32 sdcard_tx_data_cntl2; + u32 sdcard_rx_cmd_data_cntl1; + u32 sdcard_rx_strobe_cntl; + u32 sdcard_rx_cmd_data_cntl2; + u32 emmc_tx_cmd_cntl; + u32 emmc_tx_data_cntl1; + u32 emmc_tx_data_cntl2; + u32 emmc_rx_cmd_data_cntl1; + u32 emmc_rx_strobe_cntl; + u32 emmc_rx_cmd_data_cntl2; + u32 emmc_master_sw_cntl; + u8 pcie_rp_selectable_deemphasis[6]; + u8 monitor_mwait_enable; + u8 hd_audio_dsp_uaa_compliance; + u32 ipc[4]; + u8 sata_ports_disable_dynamic_pg[2]; + u8 init_s3_cpu; + u8 skip_punit_init; + u8 unused_upd_space7[4]; + u8 port_usb20_per_port_tx_pe_half[8]; + u8 port_usb20_per_port_pe_txi_set[8]; + u8 port_usb20_per_port_txi_set[8]; + u8 port_usb20_hs_skew_sel[8]; + u8 port_usb20_i_usb_tx_emphasis_en[8]; + u8 port_usb20_per_port_rxi_set[8]; + u8 port_usb20_hs_npre_drv_sel[8]; + u8 reserved_fsps_upd[16]; +}; + +/** struct fsps_upd - FSP S Configuration */ +struct __packed fsps_upd { + struct fsp_upd_header header; + struct fsp_s_config config; + u8 unused_upd_space2[46]; + u16 upd_terminator; +}; + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h new file mode 100644 index 0000000000..b14f28b236 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __FSP_VPD_H +#define __FSP_VPD_H + +/* Nothing to declare here for FSP2 */ + +#endif From patchwork Fri Nov 22 04:19:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199300 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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bh=ru80Og8c4uJmO1dzWC5BLTm/KpIDDOO+L4Go9oTLrKM=; b=QkUaF7ovL4AKiqH1+Msg63+KtUk/BvLcaHeAEjfpX4avNf74Rpp9SZfGJ3DQpWYPlE uhkmkOWP2guYZ7kVbpBrsDHpBYv00AOP1E0n7+Z0aiagJVaJr0kEQlLB1DVGp6+8fnB8 3uRHB6jE7nmtfaFzOqkGM26FWzw3QyyTnd68i0CkVz6QUeIkuFNXA6tUGj7peynr750f Yr4SHReub5a0uLP3pToSlg0lktitv/Os2dFUXMLwdyO4ze6uj2YRIDEO8vlRgjryn6xf 6ju5SEgBmFh8LEvlMcuruKW0vBtFl5NEXz8+5xVvf3OWczqvEIEA7v3XYFB3BM+a1Zr1 GmHQ== X-Gm-Message-State: APjAAAW/rIecREhQF024N4PG2nTxXpJTkKXu4k9zQXKSzVOTDqUrKKID RVQVWQ72up4quANE3sxO+zOSBGnR32E= X-Google-Smtp-Source: APXvYqx8OW5ltdVpdWCSEPGqjc7BNje4g39W8pYTX8JD6sw74pSjjwkc4y+a7SiMda+ERwGMlLGGKg== X-Received: by 2002:a92:ce92:: with SMTP id r18mr14584777ilo.265.1574396615492; Thu, 21 Nov 2019 20:23:35 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:35 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:04 -0700 Message-Id: <20191122041905.224686-77-sjg@chromium.org> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 099/100] x86: apl: Add FSP support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass --- Changes in v4: - Adjust the comment for struct dw_i2c_speed_config - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Switch over to use pinctrl for pad init/config - Tidy up mixed case in FSP code - apollolake -> Apollo Lake Changes in v3: - Add bootstage timing for reading vbt - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Set boot_loader_tolum_size to 0 - Use the IRQ uclass instead of ITSS Changes in v2: None arch/x86/cpu/apollolake/Makefile | 6 + arch/x86/cpu/apollolake/fsp_m.c | 210 ++++++++++ arch/x86/cpu/apollolake/fsp_s.c | 664 +++++++++++++++++++++++++++++++ 3 files changed, 880 insertions(+) create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1cce759124..4377c6d021 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -9,6 +9,12 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o ifndef CONFIG_TPL_BUILD obj-y += cpu.o obj-y += punit.o +ifdef CONFIG_SPL_BUILD +obj-y += fsp_m.o +endif +endif +ifndef CONFIG_SPL_BUILD +obj-y += fsp_s.o endif obj-y += hostbridge.o diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c new file mode 100644 index 0000000000..39cda7c49b --- /dev/null +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * ODT settings: + * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B, + * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A + * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW. + * + * Note that the enum values correspond to the interpreted UPD fields + * within Ch[3:0]_OdtConfig parameters. + */ +enum { + ODT_A_B_HIGH_LOW = 0 << 1, + ODT_A_B_HIGH_HIGH = 1 << 1, + N_WR_24 = 1 << 5, +}; + +/* + * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. + * There are four physical LPDDR4 channels, each 32-bits wide. There are two + * logical channels using two physical channels together to form a 64-bit + * interface to memory for each logical channel. + */ + +enum { + LP4_PHYS_CH0A, + LP4_PHYS_CH0B, + LP4_PHYS_CH1A, + LP4_PHYS_CH1B, + + LP4_NUM_PHYS_CHANNELS, +}; + +/* + * The DQs within a physical channel can be bit-swizzled within each byte. + * Within a channel the bytes can be swapped, but the DQs need to be routed + * with the corresponding DQS (strobe). + */ +enum { + LP4_DQS0, + LP4_DQS1, + LP4_DQS2, + LP4_DQS3, + + LP4_NUM_BYTE_LANES, + DQ_BITS_PER_DQS = 8, +}; + +/* Provide bit swizzling per DQS and byte swapping within a channel */ +struct lpddr4_chan_swizzle_cfg { + u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; +}; + +struct lpddr4_swizzle_cfg { + struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; +}; + +static void setup_sdram(struct fsp_m_config *cfg, + const struct lpddr4_swizzle_cfg *swizzle_cfg) +{ + const struct lpddr4_chan_swizzle_cfg *sch; + /* Number of bytes to copy per DQS */ + const size_t sz = DQ_BITS_PER_DQS; + int chan; + + cfg->memory_down = 1; + cfg->scrambler_support = 1; + cfg->channel_hash_mask = 0x36; + cfg->slice_hash_mask = 9; + cfg->interleaved_mode = 2; + cfg->channels_slices_enable = 0; + cfg->min_ref_rate2x_enable = 0; + cfg->dual_rank_support_enable = 1; + + /* LPDDR4 is memory down so no SPD addresses */ + cfg->dimm0_spd_address = 0; + cfg->dimm1_spd_address = 0; + + for (chan = 0; chan < 4; chan++) { + struct fsp_ram_channel *ch = &cfg->chan[chan]; + + ch->rank_enable = 1; + ch->device_width = 1; + ch->dram_density = 2; + ch->option = 3; + ch->odt_config = ODT_A_B_HIGH_HIGH; + } + + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; + memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); + + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; + memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); + + sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; + memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); + + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; + memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); +} + +int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) +{ + struct fsp_m_config *cfg = &upd->config; + struct fspm_arch_upd *arch = &upd->arch; + + arch->nvs_buffer_ptr = NULL; + prepare_mrc_cache(upd); + arch->stack_base = (void *)0xfef96000; + arch->boot_loader_tolum_size = 0; + + arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; + cfg->serial_debug_port_type = 2; + cfg->serial_debug_port_device = 2; + cfg->serial_debug_port_stride_size = 2; + cfg->serial_debug_port_address = 0; + + cfg->package = 1; + /* Don't enforce a memory size limit */ + cfg->memory_size_limit = 0; + cfg->low_memory_max_value = 2048; /* 2 GB */ + /* No restrictions on memory above 4GiB */ + cfg->high_memory_max_value = 0; + + /* Always default to attempt to use saved training data */ + cfg->disable_fast_boot = 0; + + const u8 *swizzle_data; + + swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle", + LP4_NUM_BYTE_LANES * + DQ_BITS_PER_DQS * + LP4_NUM_PHYS_CHANNELS); + if (!swizzle_data) + return log_msg_ret("Cannot read swizzel data", -EINVAL); + + setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data); + + cfg->pre_mem_gpio_table_ptr = 0; + + cfg->profile = 0xb; + cfg->msg_level_mask = 0; + + /* other */ + cfg->skip_cse_rbp = 1; + cfg->periodic_retraining_disable = 0; + cfg->enable_s3_heci2 = 0; + + return 0; +} + +/* + * The FSP-M binary appears to break the SPI controller. It can be fixed by + * writing the BAR again, so do that here + */ +int fspm_done(struct udevice *dev) +{ + struct udevice *spi; + int ret; + + /* Don't probe the device, since that reads the BAR */ + ret = uclass_find_first_device(UCLASS_SPI, &spi); + if (ret) + return log_msg_ret("SPI", ret); + if (!spi) + return log_msg_ret("SPI2", -ENODEV); + + dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0, + IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY); + + return 0; +} diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c new file mode 100644 index 0000000000..a8a6050f20 --- /dev/null +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCH_P2SB_E0 0xe0 +#define HIDE_BIT BIT(0) + +#define INTEL_GSPI_MAX 3 +#define INTEL_I2C_DEV_MAX 8 +#define APOLLOLAKE_USB2_PORT_MAX 8 + +enum { + CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ + CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ +}; + +enum i2c_speed { + I2C_SPEED_STANDARD = 100000, + I2C_SPEED_FAST = 400000, + I2C_SPEED_FAST_PLUS = 1000000, + I2C_SPEED_HIGH = 3400000, + I2C_SPEED_FAST_ULTRA = 5000000, +}; + +/* + * Timing values are in units of clock period, with the clock speed + * provided by the SOC + * + * TODO(sjg@chromium.org): Connect this up to the I2C driver + */ +struct dw_i2c_speed_config { + enum i2c_speed speed; + /* SCL high and low period count */ + u16 scl_lcnt; + u16 scl_hcnt; + /* + * SDA hold time should be 300ns in standard and fast modes + * and long enough for deterministic logic level change in + * fast-plus and high speed modes. + * + * [15:0] SDA TX Hold Time + * [23:16] SDA RX Hold Time + */ + u32 sda_hold; +}; + +/* Serial IRQ control. SERIRQ_QUIET is the default (0) */ +enum serirq_mode { + SERIRQ_QUIET, + SERIRQ_CONTINUOUS, + SERIRQ_OFF, +}; + +/* + * This I2C controller has support for 3 independent speed configs but can + * support both FAST_PLUS and HIGH speeds through the same set of speed + * config registers. These are treated separately so the speed config values + * can be provided via ACPI to the OS. + */ +#define DW_I2C_SPEED_CONFIG_COUNT 4 + +struct dw_i2c_bus_config { + /* Bus should be enabled prior to ramstage with temporary base */ + int early_init; + /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ + enum i2c_speed speed; + /* + * If rise_time_ns is non-zero the calculations for lcnt and hcnt + * registers take into account the times of the bus. However, if + * there is a match in speed_config those register values take + * precedence + */ + int rise_time_ns; + int fall_time_ns; + int data_hold_time_ns; + /* Specific bus speed configuration */ + struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT]; +}; + +struct gspi_cfg { + /* Bus speed in MHz */ + u32 speed_mhz; + /* Bus should be enabled prior to ramstage with temporary base */ + u8 early_init; +}; + +/* + * This structure will hold data required by common blocks. + * These are soc specific configurations which will be filled by soc. + * We'll fill this structure once during init and use the data in common block. + */ +struct soc_intel_common_config { + int chipset_lockdown; + struct gspi_cfg gspi[INTEL_GSPI_MAX]; + struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX]; +}; + +enum pnp_settings { + PNP_PERF, + PNP_POWER, + PNP_PERF_POWER, +}; + +struct usb2_eye_per_port { + u8 per_port_tx_pe_half; + u8 per_port_pe_txi_set; + u8 per_port_txi_set; + u8 hs_skew_sel; + u8 usb_tx_emphasis_en; + u8 per_port_rxi_set; + u8 hs_npre_drv_sel; + u8 override_en; +}; + +struct apl_config { + /* Common structure containing soc config data required by common code*/ + struct soc_intel_common_config common_soc_config; + + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; + + /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */ + u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; + + /* De-emphasis enable configuration for each PCIe root port */ + u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; + + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR mode Number of dealy elements.Each = 125pSec. + */ + u32 emmc_tx_cmd_cntl; + + /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. + */ + u32 emmc_tx_data_cntl1; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements. + * Each = 125pSec. + */ + u32 emmc_tx_data_cntl2; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements. + * Each = 125pSec. + */ + u32 emmc_rx_cmd_data_cntl1; + + /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. + * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. + */ + u32 emmc_rx_strobe_cntl; + + /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. + */ + u32 emmc_rx_cmd_data_cntl2; + + /* Select the eMMC max speed allowed */ + u32 emmc_host_max_speed; + + /* Specifies on which IRQ the SCI will internally appear */ + u32 sci_irq; + + /* Configure serial IRQ (SERIRQ) line */ + enum serirq_mode serirq_mode; + + /* Configure LPSS S0ix Enable */ + bool lpss_s0ix_enable; + + /* Enable DPTF support */ + bool dptf_enable; + + /* TCC activation offset value in degrees Celsius */ + int tcc_offset; + + /* Configure Audio clk gate and power gate + * IOSF-SB port ID 92 offset 0x530 [5] and [3] + */ + bool hdaudio_clk_gate_enable; + bool hdaudio_pwr_gate_enable; + bool hdaudio_bios_config_lockdown; + + /* SLP S3 minimum assertion width */ + int slp_s3_assertion_width_usecs; + + /* GPIO pin for PERST_0 */ + u32 prt0_gpio; + + /* USB2 eye diagram settings per port */ + struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; + + /* GPIO SD card detect pin */ + unsigned int sdcard_cd_gpio; + + /* + * PRMRR size setting with three options + * 0x02000000 - 32MiB + * 0x04000000 - 64MiB + * 0x08000000 - 128MiB + */ + u32 PrmrrSize; + + /* + * Enable SGX feature. + * Enabling SGX feature is 2 step process, + * (1) set sgx_enable = 1 + * (2) set PrmrrSize to supported size + */ + bool sgx_enable; + + /* + * Select PNP Settings. + * (0) Performance, + * (1) Power + * (2) Power & Performance + */ + enum pnp_settings pnp_settings; + + /* + * PMIC PCH_PWROK delay configuration - IPC Configuration + * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address + * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) + */ + u32 PmicPmcIpcCtrl; + + /* + * Options to disable XHCI Link Compliance Mode. Default is FALSE to not + * disable Compliance Mode. Set TRUE to disable Compliance Mode. + * 0:FALSE(Default), 1:True. + */ + bool DisableComplianceMode; + + /* + * Options to change USB3 ModPhy setting for the Integrated Filter (IF) + * value. Default is 0 to not changing default IF value (0x12). Set + * value with the range from 0x01 to 0xff to change IF value. + */ + u32 ModPhyIfValue; + + /* + * Options to bump USB3 LDO voltage. Default is FALSE to not increasing + * LDO voltage. Set TRUE to increase LDO voltage with 40mV. + * 0:FALSE (default), 1:True. + */ + bool ModPhyVoltageBump; + + /* + * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting + * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage + * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) + * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: + * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). + */ + u32 PmicVdd2Voltage; + + /* + * Option to enable VTD feature. Default is 0 which disables VTD + * capability in FSP. Setting this option to 1 in devicetree will enable + * the Upd parameter VtdEnable. + */ + bool enable_vtd; +}; + +static int get_config(struct udevice *dev, struct apl_config *apl) +{ + const u8 *ptr; + ofnode node; + u32 emmc[4]; + int ret; + + memset(apl, '\0', sizeof(*apl)); + + node = dev_read_subnode(dev, "fsp-s"); + if (!ofnode_valid(node)) + return log_msg_ret("fsp-s settings", -ENOENT); + + ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin", + MAX_PCIE_PORTS); + if (!ptr) + return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL); + memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS); + + ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio); + if (ret) + return log_msg_ret("prt0-gpio", ret); + ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio); + if (ret) + return log_msg_ret("sdcard-cd-gpio", ret); + + ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc)); + if (ret) + return log_msg_ret("emmc", ret); + apl->emmc_tx_data_cntl1 = emmc[0]; + apl->emmc_tx_data_cntl2 = emmc[1]; + apl->emmc_rx_cmd_data_cntl1 = emmc[2]; + apl->emmc_rx_cmd_data_cntl2 = emmc[3]; + + apl->dptf_enable = ofnode_read_bool(node, "dptf-enable"); + + apl->hdaudio_clk_gate_enable = ofnode_read_bool(node, + "hdaudio-clk-gate-enable"); + apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node, + "hdaudio-pwr-gate-enable"); + apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node, + "hdaudio-bios-config-lockdown"); + apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable"); + + /* Santa */ + apl->usb2eye[1].per_port_pe_txi_set = 7; + apl->usb2eye[1].per_port_txi_set = 2; + + return 0; +} + +static void apl_fsp_silicon_init_params_cb(struct apl_config *apl, + struct fsp_s_config *cfg) +{ + u8 port; + + for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { + if (apl->usb2eye[port].per_port_tx_pe_half) + cfg->port_usb20_per_port_tx_pe_half[port] = + apl->usb2eye[port].per_port_tx_pe_half; + + if (apl->usb2eye[port].per_port_pe_txi_set) + cfg->port_usb20_per_port_pe_txi_set[port] = + apl->usb2eye[port].per_port_pe_txi_set; + + if (apl->usb2eye[port].per_port_txi_set) + cfg->port_usb20_per_port_txi_set[port] = + apl->usb2eye[port].per_port_txi_set; + + if (apl->usb2eye[port].hs_skew_sel) + cfg->port_usb20_hs_skew_sel[port] = + apl->usb2eye[port].hs_skew_sel; + + if (apl->usb2eye[port].usb_tx_emphasis_en) + cfg->port_usb20_i_usb_tx_emphasis_en[port] = + apl->usb2eye[port].usb_tx_emphasis_en; + + if (apl->usb2eye[port].per_port_rxi_set) + cfg->port_usb20_per_port_rxi_set[port] = + apl->usb2eye[port].per_port_rxi_set; + + if (apl->usb2eye[port].hs_npre_drv_sel) + cfg->port_usb20_hs_npre_drv_sel[port] = + apl->usb2eye[port].hs_npre_drv_sel; + } +} + +int fsps_update_config(struct udevice *dev, ulong rom_offset, + struct fsps_upd *upd) +{ + struct fsp_s_config *cfg = &upd->config; + struct apl_config apl_cfg, *apl = &apl_cfg; + struct binman_entry vbt; + void *buf; + int ret; + + ret = binman_entry_find("intel-vbt", &vbt); + if (ret) + return log_msg_ret("Cannot find VBT", ret); + vbt.image_pos += rom_offset; + buf = malloc(vbt.size); + if (!buf) + return log_msg_ret("Alloc VBT", -ENOMEM); + + /* + * Load VBT before devicetree-specific config. This only supports + * memory-mapped SPI at present. + */ + bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); + memcpy(buf, (void *)vbt.image_pos, vbt.size); + bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); + if (*(u32 *)buf != VBT_SIGNATURE) + return log_msg_ret("VBT signature", -EINVAL); + cfg->graphics_config_ptr = (ulong)buf; + + get_config(dev, apl); + + cfg->ish_enable = 0; + cfg->enable_sata = 0; + cfg->pcie_root_port_en[2] = 0; + cfg->pcie_rp_hot_plug[2] = 0; + cfg->pcie_root_port_en[3] = 0; + cfg->pcie_rp_hot_plug[3] = 0; + cfg->pcie_root_port_en[4] = 0; + cfg->pcie_rp_hot_plug[4] = 0; + cfg->pcie_root_port_en[5] = 0; + cfg->pcie_rp_hot_plug[5] = 0; + cfg->pcie_root_port_en[1] = 0; + cfg->pcie_rp_hot_plug[1] = 0; + cfg->usb_otg = 0; + cfg->i2c6_enable = 0; + cfg->i2c7_enable = 0; + cfg->hsuart3_enable = 0; + cfg->spi1_enable = 0; + cfg->spi2_enable = 0; + cfg->sdio_enabled = 0; + + memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin, + sizeof(cfg->pcie_rp_clk_req_number)); + + memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable, + sizeof(cfg->pcie_rp_hot_plug)); + + switch (apl->serirq_mode) { + case SERIRQ_QUIET: + cfg->sirq_enable = 1; + cfg->sirq_mode = 0; + break; + case SERIRQ_CONTINUOUS: + cfg->sirq_enable = 1; + cfg->sirq_mode = 1; + break; + case SERIRQ_OFF: + default: + cfg->sirq_enable = 0; + break; + } + + if (apl->emmc_tx_cmd_cntl) + cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl; + if (apl->emmc_tx_data_cntl1) + cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1; + if (apl->emmc_tx_data_cntl2) + cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2; + if (apl->emmc_rx_cmd_data_cntl1) + cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1; + if (apl->emmc_rx_strobe_cntl) + cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl; + if (apl->emmc_rx_cmd_data_cntl2) + cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2; + if (apl->emmc_host_max_speed) + cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed; + + cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable; + + /* + * Disable monitor mwait since it is broken due to a hardware bug + * without a fix. Specific to Apollo Lake. + */ + if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + cfg->monitor_mwait_enable = 0; + + cfg->skip_mp_init = true; + + /* Disable setting of EISS bit in FSP */ + cfg->spi_eiss = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + cfg->rtc_lock = 0; + + /* Enable Audio clk gate and power gate */ + cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable; + cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable; + /* Bios config lockdown Audio clk and power gate */ + cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown; + apl_fsp_silicon_init_params_cb(apl, cfg); + + cfg->usb_otg = true; + + /* Set VTD feature according to devicetree */ + cfg->vtd_enable = apl->enable_vtd; + + return 0; +} + +static void p2sb_set_hide_bit(pci_dev_t dev, int hide) +{ + pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT, + hide ? HIDE_BIT : 0, PCI_SIZE_8); +} + +/* Configure package power limits */ +static int set_power_limits(struct udevice *dev) +{ + msr_t rapl_msr_reg, limit; + u32 power_unit; + u32 tdp, min_power, max_power; + u32 pl2_val; + u32 override_tdp[2]; + int ret; + + /* Get units */ + rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (rapl_msr_reg.lo & 0xf); + + /* Get power defaults for this SKU */ + rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU); + tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; + pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; + max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp, + ARRAY_SIZE(override_tdp)); + if (ret) + return log_msg_ret("tdp-pl-override-mw", ret); + + /* Set PL1 override value */ + if (override_tdp[0]) + tdp = override_tdp[0] * power_unit / 1000; + + /* Set PL2 override value */ + if (override_tdp[1]) + pl2_val = override_tdp[1] * power_unit / 1000; + + /* Set long term power limit to TDP */ + limit.lo = tdp & PKG_POWER_LIMIT_MASK; + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & + PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit PL2 */ + limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Program package power limits in RAPL MSR */ + msr_write(MSR_PKG_POWER_LIMIT, limit); + log_info("RAPL PL1 %d.%dW\n", tdp / power_unit, + 100 * (tdp % power_unit) / power_unit); + log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit, + 100 * (pl2_val % power_unit) / power_unit); + + /* + * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR + * instead of MMIO, so disable LIMIT_EN bit for MMIO + */ + writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL)); + writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4)); + + return 0; +} + +int p2sb_unhide(void) +{ + pci_dev_t dev = PCI_BDF(0, 0xd, 0); + ulong val; + + p2sb_set_hide_bit(dev, 0); + + pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16); + + if (val != PCI_VENDOR_ID_INTEL) + return log_msg_ret("p2sb unhide", -EIO); + + return 0; +} + +/* Overwrites the SCI IRQ if another IRQ number is given by device tree */ +static void set_sci_irq(void) +{ + /* Skip this for now */ +} + +int arch_fsps_preinit(void) +{ + struct udevice *itss; + int ret; + + ret = uclass_first_device_err(UCLASS_IRQ, &itss); + if (ret) + return log_msg_ret("no itss", ret); + /* + * Snapshot the current GPIO IRQ polarities. FSP is setting a default + * policy that doesn't honour boards' requirements + */ + irq_snapshot_polarities(itss); + + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + ret = pinctrl_gpi_clear_int_cfg(); + if (ret) + return log_msg_ret("gpi_clear", ret); + + return 0; +} + +int arch_fsp_init_r(void) +{ +#ifdef CONFIG_HAVE_ACPI_RESUME + bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; +#else + bool s3wake = false; +#endif + struct udevice *dev, *itss; + int ret; + + /* + * This must be called before any devices are probed. Put any probing + * into arch_fsps_preinit() above. + * + * We don't use BOOT_FROM_FAST_SPI_FLASH here since it will force PCI + * to be probed. + */ + ret = fsp_silicon_init(s3wake, false); + if (ret) + return ret; + + ret = uclass_first_device_err(UCLASS_IRQ, &itss); + if (ret) + return log_msg_ret("no itss", ret); + /* Restore GPIO IRQ polarities back to previous settings */ + irq_restore_polarities(itss); + + /* soc_init() */ + ret = p2sb_unhide(); + if (ret) + return log_msg_ret("unhide p2sb", ret); + + /* Set RAPL MSR for Package power limits*/ + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return log_msg_ret("Cannot get northbridge", ret); + set_power_limits(dev); + + /* + * FSP-S routes SCI to IRQ 9. With the help of this function you can + * select another IRQ for SCI. + */ + set_sci_irq(); + + return 0; +} From patchwork Fri Nov 22 04:19:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1199272 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="HoP1J5Ty"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47K46R3ZWWz9s7T for ; Fri, 22 Nov 2019 16:02:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 30D91C22046; Fri, 22 Nov 2019 04:40:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 61625C220F7; Fri, 22 Nov 2019 04:26:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 03C5DC2204C; Fri, 22 Nov 2019 04:23:43 +0000 (UTC) Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) by lists.denx.de (Postfix) with ESMTPS id 0BF37C2204B for ; Fri, 22 Nov 2019 04:23:40 +0000 (UTC) Received: by mail-io1-f50.google.com with SMTP id 1so6429987iou.4 for ; Thu, 21 Nov 2019 20:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q0eFoQrmXsDK2aIL5EMEjuBeenAvEOwbMpQ1jgAq5Ww=; b=HoP1J5TyClSwyahJWgZjINKU5NHxhMwBsq9TrYvvm9/qrDykdb9/1N8HZuMCuBEkFX +nK6OBHBPB4HNlv65KJMEHE358Stc8hB+0fB7TvRGN3dw/4J3htJiS3gsOpFOGSRSJ0a WdhI2dvaD3ih3ExTFNN8vdH9V7cCSote5qFnw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q0eFoQrmXsDK2aIL5EMEjuBeenAvEOwbMpQ1jgAq5Ww=; b=mhNS4lnx5LlO+IN8nfJUSgIp2oq21s2TUqaln2roe9tmlfbqt8bFHpVjcbeyOAjSr/ ACQJB4z2cAZuNLknI5IWn1rXIVNa94fJJRKWAiYQt+DsmJZ9RLu5ljEjY2YiRyQGtDG3 XUoeY89Zh91KjX1cFR54LqZkph2hzrNfaATN0tukhFSJ01hX8Frgg1KK1N0rqc+3uy8J r0stTI4x5o3a3yEUwIFCvjAQzhYWeXOMM8RbF1xDsj70qo7tt54crdzMCEVmRi18iEiv tC2sN+NHeqvi8xOQ3Kw5CJTT5UwDWfyDjd7sM5pKNsUvJowCe8ElVYcZasmmntwyE1yC NPJw== X-Gm-Message-State: APjAAAVsF41ueChAnx9s26ULyqOR7KpLnv073McTeIy5ybcBByJ0molM gsE046VsBNhCgPrD16w5tkE4iezBuxI= X-Google-Smtp-Source: APXvYqx5QKcjpiPz/cJkJJH94VHK43nZw+sEWBRnFY3vYV0uuBiaW/D7cnJaSG43ooEoCcNISS57YA== X-Received: by 2002:a02:a50b:: with SMTP id e11mr11991125jam.67.1574396617616; Thu, 21 Nov 2019 20:23:37 -0800 (PST) Received: from kiwi.bld.corp.google.com ([2620:15c:183:0:8223:87c:a681:66aa]) by smtp.gmail.com with ESMTPSA id s18sm2195879ilo.21.2019.11.21.20.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 20:23:37 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 21 Nov 2019 21:19:05 -0700 Message-Id: <20191121211845.v4.100.Ied9423f679557f95a4714a72bd7aa11fdd4445ac@changeid> X-Mailer: git-send-email 2.24.0.432.g9d3f5f5b63-goog In-Reply-To: <20191122041905.224686-1-sjg@chromium.org> References: <20191122041905.224686-1-sjg@chromium.org> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 100/100] x86: Add chromebook_coral X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass --- Changes in v4: - Add u-boot,skip-auto-config-until-reloc property to PCI - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - New GPIO driver binding - Set up LPC pads early - Switch over to use pinctrl for pad init/config - Update documentation with more detailed memory map - Use hyphen for device-tree properties - apollolake -> Apollo Lake Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add a proper SPI node and make the SPI flash node a child - Add bootstage support - Add more documentation - Add spi alias in device tree - Disable the bootcommand since it does nothing useful on coral - Don't enable SPI flash in TPL by default - Drop CONFIG_SPL_NET_SUPPORT - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Enable video and USB3 - Reduce amount of early-pad data in TPL - Tidy up the pad settings in the device tree - Use a zero-based tsc timer Changes in v2: None arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 823 ++++++++++++++++++++++ board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 ++ board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 18 + configs/chromebook_coral_defconfig | 102 +++ doc/board/google/chromebook_coral.rst | 241 +++++++ include/configs/chromebook_coral.h | 32 + 10 files changed, 1286 insertions(+) create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 include/configs/chromebook_coral.h diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index d4bdf62be6..be209aaaf8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -2,6 +2,7 @@ dtb-y += bayleybay.dtb \ cherryhill.dtb \ + chromebook_coral.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts new file mode 100644 index 0000000000..daf35cb29c --- /dev/null +++ b/arch/x86/dts/chromebook_coral.dts @@ -0,0 +1,823 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/dts-v1/; + +#include + +/include/ "skeleton.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +#ifdef CONFIG_CHROMEOS +#include "chromeos-x86.dtsi" +#include "flashmap-x86-ro.dtsi" +#include "flashmap-16mb-rw.dtsi" +#endif + +#include +#include +#include +#include +#include + +/ { + model = "Google Coral"; + compatible = "google,coral", "intel,apollolake"; + + aliases { + cros-ec0 = &cros_ec; + fsp = &fsp_s; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = &serial; + }; + + cpus { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + + keyboard { + intel,duplicate-por; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + u-boot,skip-auto-config-until-reloc; + + host_bridge: host-bridge@0,0 { + u-boot,dm-pre-reloc; + reg = <0x00000000 0 0 0 0>; + compatible = "intel,apl-hostbridge"; + pciex-region-size = <0x10000000>; + /* + * Parameters used by the FSP-S binary blob. This is + * really unfortunate since these parameters mostly + * relate to drivers but we need them in one place. We + * could put them in the driver nodes easily, but then + * would have to scan each node to find them. So just + * dump them here for now. + */ + fsp_s: fsp-s { + }; + }; + + punit@0,1 { + u-boot,dm-pre-reloc; + reg = <0x00000800 0 0 0 0>; + compatible = "intel,apl-punit"; + }; + + p2sb: p2sb@d,0 { + u-boot,dm-pre-reloc; + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = ; + + n { + compatible = "intel,apl-pinctrl"; + u-boot,dm-pre-reloc; + intel,p2sb-port-id = ; + gpio_n: gpio-n { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + nw { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = ; + #gpio-cells = <2>; + gpio_nw: gpio-nw { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + w { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = ; + #gpio-cells = <2>; + gpio_w: gpio-w { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + sw { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = ; + #gpio-cells = <2>; + gpio_sw: gpio-sw { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + itss { + u-boot,dm-pre-reloc; + compatible = "intel,apl-itss"; + intel,p2sb-port-id = ; + intel,pmc-routes = < + PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 + PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32 + PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0 + PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32 + PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64 + PMC_GPE_N_31_0 GPIO_GPE_N_31_0 + PMC_GPE_N_63_32 GPIO_GPE_N_63_32 + PMC_GPE_W_31_0 GPIO_GPE_W_31_0>; + }; + }; + + pmc@d,1 { + u-boot,dm-pre-reloc; + reg = <0x6900 0 0 0 0>; + + /* + * Values for BAR0, BAR2 and ACPI_BASE for when PCI + * auto-configure is not available + */ + early-regs = <0xfe042000 0x2000 + 0xfe044000 0x2000 + 0x400 0x100>; + compatible = "intel,apl-pmc"; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + + /* + * GPE configuration + * Note that GPE events called out in ASL code rely on + * this route, i.e., if this route changes then the + * affected GPE * offset bits also need to be changed. + * This sets the PMC register GPE_CFG fields. + */ + gpe0-dw = ; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; + + spi: fast-spi@d,2 { + u-boot,dm-pre-reloc; + reg = <0x02006a10 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,fast-spi"; + early-regs = ; + intel,hardware-seq = <1>; + + fwstore_spi: spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + u-boot,dm-pre-reloc; + reg = <0>; + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x008e0000 0x00010000>; + u-boot,dm-pre-reloc; + }; + rw-var-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x008f0000 0x0001000>; + u-boot,dm-pre-reloc; + }; + }; + }; + + serial: serial@18,2 { + reg = <0x0200c210 0 0 0 0>; + u-boot,dm-pre-reloc; + compatible = "intel,apl-ns16550"; + early-regs = <0xde000000 0x20>; + reg-shift = <2>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pch: pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,apl-pch"; + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + lpc { + compatible = "intel,apl-lpc"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + cros_ec: cros-ec { + u-boot,dm-pre-reloc; + compatible = "google,cros-ec-lpc"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* + * Describes the flash memory within + * the EC + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; + }; + }; + }; + }; + +}; + +&host_bridge { + /* + * PL1 override 12000 mW: the energy calculation is wrong with the + * current VR solution. Experiments show that SoC TDP max (6W) can be + * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W. + */ + tdp-pl-override-mw = <12000 15000>; + + early-pads = < + /* These two are for the debug UART */ + GPIO_46 /* UART2 RX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + GPIO_47 /* UART2 TX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + GPIO_75 /* I2S1_BCLK -- PCH_WP */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE) + + /* I2C2 - TPM */ + GPIO_128 /* LPSS_I2C2_SDA */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + GPIO_129 /* LPSS_I2C2_SCL */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + GPIO_28 /* TPM IRQ */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) + + /* + * WLAN_PE_RST - default to deasserted just in case FSP + * misbehaves + */ + GPIO_122 /* SIO_SPI_2_RXD */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_RX_DISABLE | 0) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + >; + + lpddr4-swizzle = /bits/ 8 < + /* LP4_PHYS_CH0A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 6 7 5 4 3 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 12 10 11 13 14 8 9 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 16 22 23 20 18 17 19 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 30 28 29 25 24 26 27 31 + + /* LP4_PHYS_CH0B */ + /* DQA[0:7] pins of LPDDR4 module */ + 7 3 5 2 6 0 1 4 + /* DQA[8:15] pins of LPDDR4 module */ + 9 14 12 13 10 11 8 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 22 23 16 19 17 18 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 28 24 26 27 29 30 31 25 + + /* LP4_PHYS_CH1A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 2 1 6 7 5 4 3 0 + /* DQA[8:15] pins of LPDDR4 module */ + 11 10 8 9 12 15 13 14 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 17 23 19 16 21 22 20 18 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 31 29 26 25 28 27 24 30 + + /* LP4_PHYS_CH1B */ + + /* DQA[0:7] pins of LPDDR4 module */ + 4 3 7 5 6 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 15 9 8 11 14 13 12 10 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 23 22 21 18 19 16 17 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 25 28 30 31 26 27 24 29>; +}; + +&fsp_s { + u-boot,dm-pre-proper; + + /* Disable unused clkreq of PCIe root ports */ + pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */ + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED>; + + /* + * GPIO for PERST_0 + * If the Board has PERST_0 signal, assign the GPIO + * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + */ + prt0-gpio = ; + /* GPIO for SD card detect */ + sdcard-cd-gpio = ; + + /* + * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2, + * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2 + * + * EMMC TX DATA Delay 1 + * Refer to EDS-Vol2-22.3 + * [14:8] steps of delay for HS400, each 125ps + * [6:0] steps of delay for SDR104/HS200, each 125ps + + /* + * EMMC TX DATA Delay 2 + * Refer to EDS-Vol2-22.3. + * [30:24] steps of delay for SDR50, each 125ps + * [22:16] steps of delay for DDR50, each 125ps + * [14:8] steps of delay for SDR25/HS50, each 125ps + * [6:0] steps of delay for SDR12, each 125ps + */ + + /* + * EMMC RX CMD/DATA Delay 1 + * Refer to EDS-Vol2-22.3. + * [30:24] steps of delay for SDR50, each 125ps + * [22:16] steps of delay for DDR50, each 125ps + * [14:8] steps of delay for SDR25/HS50, each 125ps + * [6:0] steps of delay for SDR12, each 125ps + */ + + /* + * EMMC RX CMD/DATA Delay 2 + * Refer to EDS-Vol2-22.3. + * [17:16] stands for Rx Clock before Output Buffer + * [14:8] steps of delay for Auto Tuning Mode, each 125ps + * [6:0] steps of delay for HS200, each 125ps + */ + emmc = <0x0c16 0x28162828 0x00181717 0x10008>; + + /* Enable DPTF */ + dptf-enable; + + /* Enable Audio Clock and Power gating */ + hdaudio-clk-gate-enable; + hdaudio-pwr-gate-enable; + hdaudio-bios-config-lockdown; + + /* Enable lpss s0ix */ + lpss-s0ix-enable; + + /* + * TODO(sjg@chromium.org): Move this to the I2C nodes + * Intel Common SoC Config + *+-------------------+---------------------------+ + *| Field | Value | + *+-------------------+---------------------------+ + *| I2C0 | Audio | + *| I2C2 | TPM | + *| I2C3 | Touchscreen | + *| I2C4 | Trackpad | + *| I2C5 | Digitizer | + *+-------------------+---------------------------+ + * + common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 104, + .fall-time-ns = 52, + }, + .i2c[2] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise-time-ns = 57, + .fall-time-ns = 28, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 76, + .fall-time-ns = 164, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 114, + .fall-time-ns = 164, + .data_hold_time_ns = 350, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 152, + .fall-time-ns = 30, + }, + }" + */ + + /* Minimum SLP S3 assertion width 28ms */ + slp-s3-assertion-width-usecs = <28000>; + + pads = < + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */ + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */ + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */ + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */ + + /* EMMC interface */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */ + PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */ + + /* SMBus -- unused */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */ + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */ + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + + /* I2C0 - Audio */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */ + + /* I2C1 - NFC with external pulls */ + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */ + + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */ + + /* I2C3 - touch */ + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */ + + /* I2C4 - trackpad */ + /* LPSS_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1) + /* LPSS_I2C4_SCL */ + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1) + + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */ + + /* Audio Amp - I2S6 */ + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */ + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */ + + /* NFC Reset */ + PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */ + + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */ + + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */ + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */ + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */ + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */ + + /* OSC_CLK_OUT_[0:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP) + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */ + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */ + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */ + + /* Panel 0 control */ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */ + + /* Hot plug detect */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */ + + /* USB overcurrent pins */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP) + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP) + + /* PMIC Signals Unused signals related to an old PMIC interface */ + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */ + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */ + + /* I2S1 -- largely unused */ + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */ + PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */ + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */ + PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */ + + /* DMIC or I2S4 */ + /* AVS_DMIC_CLK_A1 */ + PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE) + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */ + + /* I2S2 -- Headset amp */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */ + + /* I2S3 -- largely unused */ + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */ + PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */ + + /* Fast SPI */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */ + + /* SIO_SPI_0 - Used for FP */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */ + + /* SIO_SPI_1 -- largely unused */ + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */ + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */ + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */ + /* Headset interrupt */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */ + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */ + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */ + /* WLAN_PE_RST - default to deasserted */ + PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */ + + /* Debug tracing */ + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP) + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */ + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP) + + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */ + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */ + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */ + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */ + PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */ + PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */ + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */ + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */ + PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */ + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ + /* Next 2 are straps */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */ + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */ + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */ + + /* Camera interface -- completely unused */ + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ + >; +}; diff --git a/board/google/Kconfig b/board/google/Kconfig index 679a0f1023..0593833fd2 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -60,8 +60,23 @@ config TARGET_CHROMEBOOK_SAMUS_TPL between different A/B versions of SPL/U-Boot, to allow upgrading of almost all U-Boot code in the field. +config TARGET_CHROMEBOOK_CORAL + bool "Chromebook coral" + help + This is a range of Intel-based laptops released in 2018. They use an + Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of + LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB), + up two cameras (front-facing 720p and another 5MP option), USB SD + reader, microphone and speakers. It also includes two USB 3 Type A and + two Type C ports. The latter are used as power input and can also + charge external devices as well as a 4K external display. There is a + Chrome OS EC connected on LPC, a Cr50 secure chip from Google and + various display options. OEMs products include Acer Chromebook 11 + (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e). + endchoice +source "board/google/chromebook_coral/Kconfig" source "board/google/chromebook_link/Kconfig" source "board/google/chromebox_panther/Kconfig" source "board/google/chromebook_samus/Kconfig" diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig new file mode 100644 index 0000000000..940bee89b0 --- /dev/null +++ b/board/google/chromebook_coral/Kconfig @@ -0,0 +1,43 @@ +if TARGET_CHROMEBOOK_CORAL + +config SYS_BOARD + default "chromebook_coral" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "apollolake" + +config SYS_CONFIG_NAME + default "chromebook_coral" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + help + Allow post codes to be sent to the Chroem OS EC early during boot, + to enable monitoring of the boot and debugging when things go wrong. + With this option enabled, the EC console can be used to watch post + codes the first part of boot. + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0xc0000 + +endif diff --git a/board/google/chromebook_coral/MAINTAINERS b/board/google/chromebook_coral/MAINTAINERS new file mode 100644 index 0000000000..904227e2e2 --- /dev/null +++ b/board/google/chromebook_coral/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK_CORAL_BOARD +M: Simon Glass +S: Maintained +F: board/google/chromebook_coral/ +F: include/configs/chromebook_coral.h +F: configs/chromebook_coral_defconfig diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile new file mode 100644 index 0000000000..6a27ce3da1 --- /dev/null +++ b/board/google/chromebook_coral/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += coral.o diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c new file mode 100644 index 0000000000..dfe0fa484a --- /dev/null +++ b/board/google/chromebook_coral/coral.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#include + +int arch_misc_init(void) +{ + return 0; +} + +int board_run_command(const char *cmdline) +{ + printf("No command line\n"); + + return 0; +} diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig new file mode 100644 index 0000000000..566d47d22f --- /dev/null +++ b/configs/chromebook_coral_defconfig @@ -0,0 +1,102 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1110000 +CONFIG_SYS_MALLOC_F_LEN=0x3d00 +CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xde000000 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_CORAL=y +CONFIG_DEBUG_UART=y +CONFIG_FSP_VERSION2=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_INTEL_CAR_CQOS=y +CONFIG_X86_OFFSET_U_BOOT=0xffe00000 +CONFIG_X86_OFFSET_SPL=0xffe80000 +CONFIG_SPL_TEXT_BASE=0xfef10000 +CONFIG_BOOTSTAGE=y +CONFIG_SPL_BOOTSTAGE=y +CONFIG_TPL_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 +CONFIG_BOOTSTAGE_STASH=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set +CONFIG_BLOBLIST_ADDR=0x100000 +CONFIG_HANDOFF=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CPU_SUPPORT=y +CONFIG_SPL_PCI=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_PMC=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_X86_PCH7 is not set +# CONFIG_X86_PCH9 is not set +CONFIG_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_SOUND_RT5677=y +CONFIG_SPI=y +CONFIG_ICH_SPI=y +CONFIG_TPL_SYSRESET=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_FS_CBFS=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_TPL_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_TPM=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst new file mode 100644 index 0000000000..515fd06d76 --- /dev/null +++ b/doc/board/google/chromebook_coral.rst @@ -0,0 +1,241 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass + +Chromebook Coral +================ + +Coral is a Chromebook (or really about 20 different Chromebooks) which use the +Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so +should also work. Some later ones based on Glacier Lake (GLK) need various +changes in GPIOs, etc. but are very similar. + +It is hoped that this port can enable ports to embedded APL boards which are +starting to appear. + +Note that booting U-Boot on APL is already supported by coreboot and +Slim Bootloader. This documentation refers to a 'bare metal' port. + + +Boot flow - TPL +--------------- + +Apollo Lake boots via an IFWI (Integrated Firmware Image). TPL is placed in +this, in the IBBL entry. + +On boot, an on-chip microcontroller called the CSE (Converged Security Engine) +sets up some SDRAM at ffff8000 and loads the TPL image to that address. The +SRAM extends up to the top of 32-bit address space, but the last 2KB is the +start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE +must be ffff8000. Actually the start16 region is small and it could probably +move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so +there is no need to change it at present. The size limit is enforced by +CONFIG_TPL_SIZE_LIMIT to avoid producing images that won't boot. + +TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides +larger area of RAM for use while booting. CAR is mapped at CONFIG_SYS_CAR_ADDR +(fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB +of this space (i.e. below fef10000). This means that the stack and early +malloc() region in TPL can be 64KB at most. + +TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the +x86-specific functions pci_x86_write_config(), etc. SPL creates a simple-bus +device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl() +is called to early init on various devices. This includes placing PCI devices +at hard-coded addresses in the memory map. PCI auto-config is not used. + +Most of the 16KB ROM is mapped into the very top of memory, except for the +Intel descriptor (first 4KB) and the space for SRAM as above. + +TPL does not set up a bloblist since at present it does not have anything to +pass to SPL. + +Once TPL is done it loads SPL from ROM using either the memory-mapped SPI or by +using the Intel fast SPI driver. SPL is loaded into CAR, at the address given +by CONFIG_SPL_TEXT_BASE, which is normally fef10000. + +Note that booting using the SPI driver results in an TPL image that is about +26KB in size instead of 19KB. Also boot speed is worse by about 340ms. If you +really want to use the driver, enable CONFIG_APL_SPI_FLASH_BOOT and set +BOOT_FROM_FAST_SPI_FLASH to true[2]. + + +Boot flow - SPL +--------------- + +SPL (running from start_from_tpl.S) continues to use the same stack as TPL. +It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads +the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the +output 'HOB' list (Hand-off-block) is stored into gd->arch.hob_list for parsing. +There is a 2GB chunk of SDRAM starting at 0 and the rest is at 4GB. + +PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so +proper PCI access is available and normal dm_pci_read_config() calls can be +used. However PCI auto-config is not used so the same static memory mapping set +up by TPL is still active. + +SPL on x86 always runs with CONFIG_SPL_SEPARATE_BSS=y and BSS is at 120000 +(see u-boot-spl.lds). This works because SPL doesn't access BSS until after +board_init_r(), as per the rules, and DRAM is available then. + +SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper. +This includes a pointer to the HOB list as well as DRAM information. See +struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR, +normally 100000. + +SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent +boots. Be warned that SPL can take 30 seconds without this cache! This is a +known issue with Intel SoCs with modern DRAM and apparently cannot be improved. +The MRC caches are used to work around this. + +Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which +is normally 1110000. Note that CAR is still active. + + +Boot flow - U-Boot pre-relocation +--------------------------------- + +U-Boot (running from start_from_spl.S) starts running in RAM and uses the same +stack as SPL. It does various init activities before relocation. Notably +arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table +in the device tree. + +PCI auto-config is not used before relocation, but CONFIG_PCI of course is +defined, so proper PCI access is available. The same static memory mapping set +up by TPL is still active until relocation. + +As per usual, U-Boot allocates memory at the top of available RAM (a bit below +2GB in this case) and copies things there ready to relocate itself. Notably +reserve_arch() does not reserve space for the HOB list returned by FSP-M since +this is already located in RAM. + +U-Boot then shuts down CAR and jumps to its relocated version. + + +Boot flow - U-Boot post-relocation +--------------------------------- + +U-Boot starts up normally, running near the top of RAM. After driver model is +running, arch_fsp_init_r() is called which loads and runs the FSP-S binary. +This updates the HOB list to include graphics information, used by the fsp_video +driver. + +PCI autoconfig is done and a few devices are probed to complete init. Most +others are started only when they are used. + +Note that FSP-S is supposed to run after CAR has been shut down, which happens +immediately before U-Boot starts up in its relocated position. Therefore we +cannot run FSP-S before relocation. On the other hand we must run it before +PCI auto-config is done, since FSP-S may show or hide devices. The first device +that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S +must run before that. A corollary is that loading FSP-S must be done without +using the SPI driver, to avoid probing PCI and causing an autoconfig, so +memory-mapped reading is always used for FSP-S. + +It would be possible to tear down CAR in SPL instead of U-Boot. The SPL handoff +information could make sure it does not include any pointers into CAR (in fact +it doesn't). But tearing down CAR in U-Boot allows the initial state used by TPL +and SPL to be read by U-Boot, which seems useful. It also matches how older +platforms start up (those that don't use SPL). + + +Performance +----------- + +Bootstage is used through all phases of U-Boot to keep accurate timimgs for +boot. Use 'bootstage report' in U-Boot to see the report, e.g.: + +Timer summary in microseconds (16 records): + Mark Elapsed Stage + 0 0 reset + 155,325 155,325 TPL + 204,014 48,689 end TPL + 204,385 371 SPL + 738,633 534,248 end SPL + 739,161 528 board_init_f + 842,764 103,603 board_init_r + 1,166,233 323,469 main_loop + 1,166,283 50 id=175 + +Accumulated time: + 62 fast_spi + 202 dm_r + 7,779 dm_spl + 15,555 dm_f + 208,357 fsp-m + 239,847 fsp-s + 292,143 mmap_spi + +CPU performance is about 3500 DMIPS: + +=> dhry +1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS + + +Partial memory map +------------------ + +ffffffff Top of ROM (and last byte of 32-bit address space) +ffff8000 TPL loaded here (from IFWI) +ff000000 Bottom of ROM +fefc000 Top of CAR region +fef96000 Stack for FSP-M +fef40000 59000 FSP-M +fef11000 SPL loaded here +fef10000 CONFIG_BLOBLIST_ADDR +fef10000 Stack top in TPL, SPL and U-Boot before relocation +fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR +fef00000 Base of CAR region + + f0000 CONFIG_ROM_TABLE_ADDR + 120000 BSS (defined in u-boot-spl.lds) + 200000 FSP-S (which is run after U-Boot is relocated) + 1110000 CONFIG_SYS_TEXT_BASE + + +Supported peripherals +--------------------- + +- UART +- SPI flash +- Video +- MMC (dev 0) and micro-SD (dev 1) +- Chrome OS EC +- Keyboard +- USB + + +To do +----- + +- Finish peripherals + - left-side USB + - USB-C + - Cr50 (security chip: a basic driver is running but not included here) + - I2C (driver exists but not enabled in device tree) + - Sound (Intel I2S support exists, but need da7219 driver) + - RTC (driver exists but not enabled in device tree) + - Various minor features supported by LPC, etc. +- Booting Chrome OS, e.g. with verified boot +- Integrate with Chrome OS vboot +- Improvements to booting from coreboot (i.e. as a coreboot target) +- Use FSP-T binary instead of our own CAR implementation +- Use the official FSP package instead of the coreboot one +- Enable all CPU cores +- Suspend / resume +- ACPI + + +Credits +------- + +This is a spare-time project conducted slowly over a long period of time. + +Much of the code for this port came from Coreboot, an open-source firmware +project similar to U-Boot's SPL in terms of features. + +Also see [2] for information about the boot flow used by coreboot. It is +similar, but has an extra postcar stage. U-Boot doesn't need this since it +supports relocating itself in memory. + + +[2] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h new file mode 100644 index 0000000000..a63c3c9eea --- /dev/null +++ b/include/configs/chromebook_coral.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +/* + * board/config.h - configuration options, board-specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 1:c 1000000 syslinux/vmlinuz.A; zboot 1000000" + +#include +#include + +#undef CONFIG_STD_DEVICES_SETTINGS +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_TPL_TEXT_BASE 0xffff8000 + +#define CONFIG_SYS_NS16550_MEM32 +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#endif /* __CONFIG_H */