From patchwork Tue Nov 19 17:53:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bx22B959"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYMr6lvzz9sPK for ; Wed, 20 Nov 2019 04:53:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727014AbfKSRx1 (ORCPT ); Tue, 19 Nov 2019 12:53:27 -0500 Received: from mail-wr1-f48.google.com ([209.85.221.48]:40339 "EHLO mail-wr1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726939AbfKSRx1 (ORCPT ); Tue, 19 Nov 2019 12:53:27 -0500 Received: by mail-wr1-f48.google.com with SMTP id q15so12144089wrw.7; Tue, 19 Nov 2019 09:53:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KpxeRwM+qEoa4VAc9BPhZpNvjuA7mG+/4K8rmEaY6mQ=; b=bx22B9591gBTbNsaJPnRIhrdB/HobDRSuf8N/+RQ9vfgk//8OYwdPjFEWXeCbw2el7 OtR8xn3BePNX7Aa1zV/8zUU2IU8jcimexfTHG1xPtdoHp4pTcd11hdJZbNeiKX23TKcI opTob0wiEguEjhHWaxkF8u7gvO7xeD+kMS6mSGyN4Ul//IuNFsWSM1b0ktJ9i6HcAA8L fQcG2ljYoL/j0baD5omgDh3BD4BKgLIVlOfuwDbqyP7Gyx7xSOlwlUDv/EVI0S85hoS/ NvKqjMIxsZUU2mF4uszX1Y4515VQ+C/T4q7+pKYVBWXUM5YUXVhjbeKFoUOJ+DFMD3C3 ZxFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KpxeRwM+qEoa4VAc9BPhZpNvjuA7mG+/4K8rmEaY6mQ=; b=R2BRyWluUEde9QItUF30/s+qX4j1eGAuFhwllQSOCl7J9cg8eDX8LemSuXlSYyiCLe bZ/HH7+3F+mbLRymZKkkeYCeiXgHZCZW9PSO77gnLlxK98l7E3PqjGB+q7KsijTjrVX4 mHf1MtgvFbfrkc2p2qqMCho9LRs/3NZQ8uJdGKQnyRZU+U0fYJXF4nzjWzKMoGRl7izd x11mpMg41Pe57OGvNyBaK1+jR/F7MDC89K1baLoMMsNp8/VLcUIqMkpLZjJxL9MRbenD 1Yz28vWjaZJrVHRc68imrEG0fDRRt3oSegzq4raeKHP1fS71GpczfIGvp9dggcEuuUH7 EQXQ== X-Gm-Message-State: APjAAAVFjq0CZ4KdgHm76MjwZV9vXzHCyCPrEwdpaf+7HsuaHE/1Hasl stANazjefI7gc17bOzfLeKM= X-Google-Smtp-Source: APXvYqzRPud+LGIWs0JP7TgLZFqPoXTmaPDi4j3Bz5kBu2ryyj8/BvNdjOcJSRbKl1ehPz/aD1c7ng== X-Received: by 2002:a5d:51c8:: with SMTP id n8mr38156093wrv.302.1574186005316; Tue, 19 Nov 2019 09:53:25 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:24 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , Rob Herring , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 1/8] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Tue, 19 Nov 2019 18:53:12 +0100 Message-Id: <20191119175319.16561-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Reviewed-by: Rob Herring Signed-off-by: Clément Péron --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..a7dc19fc347a 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,51 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + items: + - description: Module Clock + - description: Bus Clock + + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clock-names: true + + resets: maxItems: 1 +if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + +then: + properties: + clocks: + maxItems: 2 + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + +else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +92,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Tue Nov 19 17:53:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YtWcSQnI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYNN2DZkz9sPT for ; Wed, 20 Nov 2019 04:53:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727545AbfKSRxa (ORCPT ); Tue, 19 Nov 2019 12:53:30 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:34612 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727007AbfKSRx3 (ORCPT ); Tue, 19 Nov 2019 12:53:29 -0500 Received: by mail-wr1-f68.google.com with SMTP id e6so24992321wrw.1; Tue, 19 Nov 2019 09:53:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=YtWcSQnI6pXUARGVokPA5sc6sJqKiwcAGEZYpo6ywyxt4+5YqjDAlaXPKMFD1vYyag 2Mr/4CjKk7dJLtfCfn/QxO/0Qp/+/jUChWLRiMIjnGhg2bO7rysomkyJljQpsv5c/ZED vJ0eSh5q+6TZ1bWgnNXb3ldlRHd8f1I4ULlY6AAcSjAfyDrt5+HTLEypkypaceRlBXdj PzU+UHw29mV9PTRk/0BgEYQ+0oVwf8ch0WxeEoaGkeXhWPXW22DBh2taXEolCS7wvFiv ykBZjmTbEG1/A545uNLv8wOsLRq09Ptr0G9uZ+oApPys4ZXJTlzRX2OSOOxBO+618u06 DFQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=hMuA1t0sa3RcTVMvtlOEmlO+4VYe83GrUr6ENo5rxyM8sP3o8pRAaQ8KGOIPMBSWsq t+qSDHpBPikp2q7LR3EG6khJ0iz38fPCclPkcGX095XzV9YPmpEqKsMEGDgkRDvcRbnr 6V8cRVfFmDGeNSXoMG8MdE7ZU8lqgzBk3Ia0PzLaZbHp06vkPo11NtzskRlPpOpEbbIs LLIYJ1LYQ/BhOMxEQNDBSl0Arf7DZ6s0lyQ1pud3Q87Ec4F2QH3CUGNTbEBInTu+6eTO qR0byAQVN3rA3Kko2fPmpiceyt050x6+tzc4jhqYyBxrQm6WGuPW5NWYFUjMp+5fCXKg P/UA== X-Gm-Message-State: APjAAAWCTQjCQU011qmzQTXMh1p+6GHCKdjttUjp0DxelgEjAjxomqig kd/5LAqWaVZ0K8IZhVuQd8Y= X-Google-Smtp-Source: APXvYqzTJFqhXrrlq0ftpNdro0ODeqnvh2+LUQyS9Y4HxRGQJ38Jh0DSAqFFjpPJR3D9IFQyvA8rpA== X-Received: by 2002:adf:efcb:: with SMTP id i11mr17605497wrp.229.1574186005947; Tue, 19 Nov 2019 09:53:25 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:25 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 2/8] pwm: sun4i: Add an optional probe for reset line Date: Tue, 19 Nov 2019 18:53:13 +0100 Message-Id: <20191119175319.16561-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Reviewed-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 581d23287333..c17935805690 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get reset failed %pe\n", + pwm->rst); + return PTR_ERR(pwm->rst); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Tue Nov 19 17:53:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HrqbTpU4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYNP01lKz9sPv for ; Wed, 20 Nov 2019 04:53:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726985AbfKSRxz (ORCPT ); Tue, 19 Nov 2019 12:53:55 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:39012 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726939AbfKSRxa (ORCPT ); Tue, 19 Nov 2019 12:53:30 -0500 Received: by mail-wm1-f67.google.com with SMTP id t26so4788796wmi.4; Tue, 19 Nov 2019 09:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+uPwPfx0oQerpYTv3rMNbZ1we4qpdrwsuG2bGFowiTE=; b=HrqbTpU48LtXXGhuT1jSoBXlW4dQYaVuKNPJ6cUTawNnHjXEbsNb2n+BtrFaIT0nxg jO0U2HrzGfy4kyXtUC/suSyd8YuQ1lB28fbgBv/rNCKapu5Q0EmVKEVIeNLjdTj+1lOB UfcojpSGvn4mY8QWbvlzHdDWCtJPBuPB9aRRGscQUs79XtKLnDCvPNkkJ19xsPlJBdRB y76yrpvQEmgaIa9po8DcKV70OOJk2lfCDp6KoT6W+wAsBJRwe9Etn5OH4Eik9P+qn+dh ib0klC/9sl7FbGu3gDtebUHe43V/2zVto6ZKc3hNx/Np+vi+obLmAZ4D+qav/uAGE0tb utQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+uPwPfx0oQerpYTv3rMNbZ1we4qpdrwsuG2bGFowiTE=; b=FdXWzeoFYPw7BQebqhZba3fohGGcw2LDRBkT4yIJLewRwS/EGoR7dNl1ujAaHVrvUs zWF8t1SXW4rvTxVrPL/ELbpih6Yfac+GolYION0FXZ4Cv3TV4Zi9Ic9YvM+GDABapLDX lDxMPrluYE+/jLsps+Np6x+6YXCyjVXNkZHG6WRxFu9KYUIlmRkLozzPc5NkH3nGfxiG k2Z2bKqVDIiMRaFrGpwWIajwnFSZv5TfAy37CuJJWXg5kluII51MURh0Xde5PjfpEgkz 9Ez3q+fmhtNORYid/C7/LzEI1D9lInzHkScRzEn1MTkPLzb9Se4jHHBvVf8DYKSD5aij TNWg== X-Gm-Message-State: APjAAAV3vdwBapWBaTGuoImhBASC3e5DPE36p4QmgmVr6AswCupCKseg XLdQx7Ppke2ewWFLJfWdajI= X-Google-Smtp-Source: APXvYqxoIbx/qLj+H9mdcAmhEdkBaM+WWALtgFxviLoGVxHH9Lkd0YrjTBQkL8yEBwpAShppBEu69w== X-Received: by 2002:a7b:c392:: with SMTP id s18mr6609135wmj.61.1574186006521; Tue, 19 Nov 2019 09:53:26 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:26 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 3/8] pwm: sun4i: Prefer "mod" clock to unnamed Date: Tue, 19 Nov 2019 18:53:14 +0100 Message-Id: <20191119175319.16561-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org New device tree bindings called the source clock of the module "mod" when several clocks are defined. Try to get a clock called "mod" if nothing is found try to get an unnamed clock. Signed-off-by: Clément Péron Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index c17935805690..6d97fef4ed43 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->base)) return PTR_ERR(pwm->base); - pwm->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) + /* + * All hardware variants need a source clock that is divided and + * then feeds the counter that defines the output wave form. In the + * device tree this clock is either unnamed or called "mod". + * Some variants (e.g. H6) need another clock to access the + * hardware registers; this is called "bus". + * So we request "mod" first (and ignore the corner case that a + * parent provides a "mod" clock while the right one would be the + * unnamed one of the PWM device) and if this is not found we fall + * back to the first clock of the PWM. + */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get mod clock failed %pe\n", + pwm->clk); return PTR_ERR(pwm->clk); + } + + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get unnamed clock failed %pe\n", + pwm->clk); + return PTR_ERR(pwm->clk); + } + } pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { From patchwork Tue Nov 19 17:53:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cBidvaue"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYNM0LNpz9sPv for ; Wed, 20 Nov 2019 04:53:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727566AbfKSRxa (ORCPT ); Tue, 19 Nov 2019 12:53:30 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37772 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727117AbfKSRx3 (ORCPT ); Tue, 19 Nov 2019 12:53:29 -0500 Received: by mail-wr1-f66.google.com with SMTP id t1so24949087wrv.4; Tue, 19 Nov 2019 09:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jsifq8PTX0er46e43pUZkmCyPNqnaTwpRAxn8YySges=; b=cBidvaueQsZTh/Frc70oKIqbOXFsI31ZCgK+cvPz7uDUQVgnrF8XXl/ND9nEuJgu7Y eOSIlc4pHu2jvj6YIEeg3+4CVutsG5r6Dv+JWjMmDauVIf2l44hRPkf7tzTXIC6/mvyd ZD2vZGtnImp5VjL1vI66KiUnPnC/ULh0VmfNSD5vQ7LeN61CBFQxkiIyaRKEvbrihFRB pTpBauPOy8hWr3AXRaNINzrHmCEnvUBIh5xi0M9JOboR8IoYrYloNKVjBmAaptZNdUCO ORORJsOIGnMOXObKAFQml63ayUqG8j1zjagW+F8qHYN13h9DPYuKgYEAMXU9u6/MnvWn DC0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jsifq8PTX0er46e43pUZkmCyPNqnaTwpRAxn8YySges=; b=AVOioiavEPjj0dnXus94GdlU5RxFgxxu/zcsOjCojfa8D5XVo/IGAqCyGZMEnubA/z ZXGJS93L/bENRTWVTvZ1CaI2iT1ZquTfKufYdvvLeLmbMQfXLnBCpeSkymNrOO0ypD1j CpXfXATTc7MPhTgw+Y12fDCMQFPZDIniYvQCmY111uksFtU185tYid6qcA8BhfxtxYS3 AnCI2N4C7V4Bc9HrfIbqmac5ygFm7PFdLmfST4gTAsEbtnlP7dHUtadt5pTesV7n7IMH HjG5stWQhyaimzmBVuGZuDYDZLy23A+pSeNlpxGZOo/oJyqY/7MYS05U3gC0pFRASwm/ S1CA== X-Gm-Message-State: APjAAAVHXVKFeluOb1mM3NrF1SqpakFeGq3T659EUd/21C9zQBnxlRHa B/dIOkmu20AbMXoyN7JPKYM= X-Google-Smtp-Source: APXvYqxLWxt/WyrFLqrGFY1V0vJ+g8vbDOhRT6OpisfVcWiUoWWKXZb1BiJK06DNDICYviBRXNyOjQ== X-Received: by 2002:a5d:4810:: with SMTP id l16mr5347849wrq.127.1574186007205; Tue, 19 Nov 2019 09:53:27 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:26 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 4/8] pwm: sun4i: Add an optional probe for bus clock Date: Tue, 19 Nov 2019 18:53:15 +0100 Message-Id: <20191119175319.16561-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6d97fef4ed43..ce83d479ba0e 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) } } + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get bus clock failed %pe\n", + pwm->bus_clk); + return PTR_ERR(pwm->bus_clk); + } + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) @@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* + * We're keeping the bus clock on for the sake of simplicity. + * Actually it only needs to be on for hardware register accesses. + */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -426,6 +445,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -440,6 +461,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Tue Nov 19 17:53:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197570 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KU6LloSb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYNJ5FHZz9sPv for ; Wed, 20 Nov 2019 04:53:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727171AbfKSRxs (ORCPT ); Tue, 19 Nov 2019 12:53:48 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35486 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727289AbfKSRxb (ORCPT ); Tue, 19 Nov 2019 12:53:31 -0500 Received: by mail-wr1-f65.google.com with SMTP id s5so24972733wrw.2; Tue, 19 Nov 2019 09:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ftjDb5WxJHIC5enFSHC7KF6MbGREBXU1Fw5+H0zCqjU=; b=KU6LloSbgJbhjYz8glUYl+Sy4m+gnNNcLyWGIcxK70P9GMiRFSBG8ekzID6NeIA/zq BPEyrJnMqsuHoJvReby6/m6gUR2AH6GVpJoeY1R7ZSfGxZKHaqwEgVFnUqjv1RMm/Ki0 nk2hE+4JO6vtQIjkKECkPC8dHsxlqKp+rjfgxJX4fA0XPmR/xrBlgi67Hc3X8xap4Vyz ZYyEXCa2UifXtDSvSIvvMqarH9tK0/T+Vc9ZWJUVAGjjY2r8UDLhDahH9Bc9BhSWVcEI o3i2u0zIBMx4C+W27D/hU/TJnCTHl9ONEEp+GEwJzYgmm5cCCifpiL+Hnx9mmDstu29e 36Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ftjDb5WxJHIC5enFSHC7KF6MbGREBXU1Fw5+H0zCqjU=; b=NI459muNzshju6EXOrMZmIQJzBwZX7BV3yLVkDHDxOzDGb8nH8qWl//xhoskXCPiSu SPC6W/fC93+A8sofdD25t2+pf+d+CFE7MeLEJAxSfGsVm2qhELnhbRaoYOv7pOZl03cS iSp6XFm4DwweXcaQiKGYwd94KmryRhuIsNhbynNNJINWsKFRf3PHdKkewXZ7Dq7iHkh2 lvQSQBdPGpEZaWARgAEHxnXos0/3wREmugSxikJzGCJnS4P5oLIxbB4qRJ1ifWzSjn7G Dx/SlKM6hLXvCeJwquzvjoPmN6PimD62zKLX5MYxRyDrYnjNn7RGeOScCuVNUId9xdcA A5wQ== X-Gm-Message-State: APjAAAXGJPA9iG4RDeS9Tchy0rn8rXbqjkojL/TKva3mEtACW5mXmubP Ch8lyVG+/VtFR/txgjUEK404xCXM66Pe6Q== X-Google-Smtp-Source: APXvYqz5E/Oxsl405HgiJg967Yp2OBUbbajWimUnFeUuLd8q6rxo8ERPQ3nx320aCcWVxgS0R2dCmQ== X-Received: by 2002:a5d:4381:: with SMTP id i1mr3842117wrq.292.1574186007899; Tue, 19 Nov 2019 09:53:27 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:27 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 5/8] pwm: sun4i: Add support to output source clock directly Date: Tue, 19 Nov 2019 18:53:16 +0100 Message-Id: <20191119175319.16561-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++------------- 1 file changed, 64 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index ce83d479ba0e..a1d8851b18f0 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, const struct pwm_state *state, - u32 *dty, u32 *prd, unsigned int *prsclr) + u32 *dty, u32 *prd, unsigned int *prsclr, + bool *bypass) { u64 clk_rate, div = 0; unsigned int pval, prescaler = 0; clk_rate = clk_get_rate(sun4i_pwm->clk); + *bypass = state->enabled && + (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + + /* Skip calculation of other parameters if we bypass them */ + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) + return 0; + if (sun4i_pwm->data->has_prescaler_bypass) { /* First, test without any prescaler when available */ prescaler = PWM_PRESCAL_MASK; @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, period, duty, val; int ret; - unsigned int delay_us; + unsigned int delay_us, prescaler; unsigned long now; + bool bypass; pwm_get_state(pwm, &cstate); @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - if ((cstate.period != state->period) || - (cstate.duty_cycle != state->duty_cycle)) { - u32 period, duty, val; - unsigned int prescaler; + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, + &bypass); + if (ret) { + dev_err(chip->dev, "period exceeds the maximum value\n"); + spin_unlock(&sun4i_pwm->ctrl_lock); + if (!cstate.enabled) + clk_disable_unprepare(sun4i_pwm->clk); + return ret; + } - ret = sun4i_pwm_calculate(sun4i_pwm, state, - &duty, &period, &prescaler); - if (ret) { - dev_err(chip->dev, "period exceeds the maximum value\n"); - spin_unlock(&sun4i_pwm->ctrl_lock); - if (!cstate.enabled) - clk_disable_unprepare(sun4i_pwm->clk); - return ret; + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) { + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + /* We can skip apply of other parameters */ + goto bypass_mode; + } else { + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); } + } - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { - /* Prescaler changed, the clock has to be gated */ - ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - - ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); - ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } + if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { + /* Prescaler changed, the clock has to be gated */ + ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - val = (duty & PWM_DTY_MASK) | PWM_PRD(period); - sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); - sun4i_pwm->next_period[pwm->hwpwm] = jiffies + - usecs_to_jiffies(cstate.period / 1000 + 1); - sun4i_pwm->needs_delay[pwm->hwpwm] = true; + ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); + ctrl |= BIT_CH(prescaler, pwm->hwpwm); } + val = (duty & PWM_DTY_MASK) | PWM_PRD(period); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); + sun4i_pwm->next_period[pwm->hwpwm] = jiffies + + usecs_to_jiffies(cstate.period / 1000 + 1); + sun4i_pwm->needs_delay[pwm->hwpwm] = true; + if (state->polarity != PWM_POLARITY_NORMAL) ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); else ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -264,6 +299,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Tue Nov 19 17:53:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DPEzAa9d"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYNB450Xz9sPc for ; Wed, 20 Nov 2019 04:53:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727677AbfKSRxl (ORCPT ); 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[82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:28 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 6/8] pwm: sun4i: Add support for H6 PWM Date: Tue, 19 Nov 2019 18:53:17 +0100 Message-Id: <20191119175319.16561-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Acked-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index a1d8851b18f0..640f6349e36f 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -358,6 +358,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -374,6 +380,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Tue Nov 19 17:53:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kX2xzYkO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYN21wllz9sPc for ; Wed, 20 Nov 2019 04:53:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727628AbfKSRxc (ORCPT ); Tue, 19 Nov 2019 12:53:32 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33234 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727534AbfKSRxc (ORCPT ); Tue, 19 Nov 2019 12:53:32 -0500 Received: by mail-wr1-f67.google.com with SMTP id w9so24968370wrr.0; Tue, 19 Nov 2019 09:53:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=kX2xzYkOJcey0IukBXgQckcOBqFfeKMPv7YciY4a3L0doXl5qmk0A2usdXyKAJIgZ0 7eNa0NiVdsNwe5PsQcg/JLjb7hMqUj+611GewB5jwT9ULmoA8Bdl/5D+O3BXxlXGnOFj WO3IHhcSyZMcNGYYF1kcr1czchvuFfF8Xh6GsBkkCTrtyyBQMqCkTdcQuXtF7DACJkvq 4/Q5Tn0uOlIETPi6UJ1atg6uty8SQhHJxAH1+9Howsr7fRttG/ri4mdKX8xrSWq249S8 Da8kOFKoOLLvRgnOnTJkmvhgDWXuvqNP0o/UoHtROWRKubHpL79tewAs2qJhmr12mSQz GORw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=n/92RMOrtW/hJ/BSgIUBk85smNZUCKgfbAIwwqDcM9kUevIL96f6qJMxjdUGyLls68 +ucV3oIYih+UOr5stnnMzqurvAETwGP+cxlqPGo2F5ZsQieoc3PX7xxIVhrVkKKxfR8e VFuX2cVmXvuf6kjCPz+K5CNICqoeXxKXGPD2+WSRv3r+CCBzcrmV8TOQy7y2p5smqioZ G6AMHiCnv4MwlMznCLTQhZr/zTg0Ihu1HRPafMcaVsMEcpjVjlK2XOuJlHpWYglrBh1c 0g2YAeCqzHHLwvZ01bc5uccJm3aBm+U88o0ciHE/oqv34RQKxOF6PMAEDpjsuFXPkEqK 8djg== X-Gm-Message-State: APjAAAXi3tUQO9rlquOEE+PKuY1encV4X8KWGrqQL00s7YjDK9Z2chq4 shOgEa8wCt1ketMYEuLEXLs= X-Google-Smtp-Source: APXvYqzFlw39pjo+DqL/WXfkMNWpQBCjd95PTn5lbA4E2SEiaWGk7919C/2iTa87tf1G8RE9zuXazg== X-Received: by 2002:a5d:5227:: with SMTP id i7mr38288820wra.277.1574186009397; Tue, 19 Nov 2019 09:53:29 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:28 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 7/8] arm64: dts: allwinner: h6: Add PWM node Date: Tue, 19 Nov 2019 18:53:18 +0100 Message-Id: <20191119175319.16561-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 29824081b43b..6d4bde488f15 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -245,6 +245,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Tue Nov 19 17:53:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1197568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Fc13efBM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47HYN26DKrz9sR5 for ; Wed, 20 Nov 2019 04:53:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727534AbfKSRxg (ORCPT ); Tue, 19 Nov 2019 12:53:36 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46164 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727585AbfKSRxc (ORCPT ); Tue, 19 Nov 2019 12:53:32 -0500 Received: by mail-wr1-f68.google.com with SMTP id b3so24943417wrs.13; Tue, 19 Nov 2019 09:53:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=Fc13efBMJJjOXeqjH+ZH/G7w0cMsQNvHOnfUpMSgYCkHs+tF+L3ULQ25t7ZQBQutNE T+VProISjfu37CsMUc0z10Y3ljPZiXievptG17p1rtrrFzKesy+AvID1JSBuZ2TrUV/r EndFAJzzb1E1x4+NirNRghaeVYsxqn0t605JjeWRIt164/KHhNVTZP7w3zBfxksXUt63 +UhoILSnlqiFCFsiF8OCJlyr7S+dDFExinST2zBeqUJZJC0/ck3zs25sGr/fPjVZF7Qk 1xs+9jnhqfg+Mrx/fIX2faWX5k0tDgUj7dZ05hQ2763TpIWLsQCuGsM3L+xoJKcnIoQX Dgow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=cLn1N17Ztn+jFABlYj+N/1q2Kt9veze3scJKnG/12LG8IiZ4s90GlIAC/FmpPC57Tw jUZccoprThXiiLBlsKp4ZiNJhO0c3/RJmHLIH/dQ2DnFis3blB43Vd9kZJp7IXEYASoQ Fyj1wI0eqOnltc+OczAQUFkogyGas+G72nD65lxbEIY590fSePJ5AU0O1yGB0K3AnrDO gxvyYiYympaGc5ZOb0QuEWUj1zKpmMOUL+VT7lqhDj9DPgkKJFX7uXsMSIHF8ptMx3Wo Q9uZ36qpQCzN6pUBGvjUV2FOrMA7Pz5ACaTfYhxoysVriuIjHmnrO4kvrHhFQSfVBiqj SN5A== X-Gm-Message-State: APjAAAUPXeEI7Ms0AWZTZO0FGpgmnvCBVosFQF4OjKe5v/OWgEq64dCQ x8mUju+pSGSrR5R25qScdGtP9GGHl6O/1w== X-Google-Smtp-Source: APXvYqyrBcqNH9t86bk+axnFrVx1ZfsuKnxRbES8aE/F8d/qm8q7ETQ/uOkWuTpa8cWqpKUFPKW04A== X-Received: by 2002:adf:e78c:: with SMTP id n12mr36004693wrm.94.1574186010055; Tue, 19 Nov 2019 09:53:30 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id l13sm3772618wmh.12.2019.11.19.09.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 09:53:29 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v7 8/8] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Tue, 19 Nov 2019 18:53:19 +0100 Message-Id: <20191119175319.16561-9-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191119175319.16561-1-peron.clem@gmail.com> References: <20191119175319.16561-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index f335f7482a73..cf684bc7374d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -136,6 +136,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";