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Fri, 15 Nov 2019 12:31:07 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iVacf-0000ly-BX; Fri, 15 Nov 2019 04:22:45 -0800 Received: from [127.0.0.1] (helo=xsj-smtp-dlp2.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iVaca-00086u-6r; Fri, 15 Nov 2019 04:22:40 -0800 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xAFCMdu6020507; Fri, 15 Nov 2019 04:22:39 -0800 Received: from [10.140.6.59] (helo=xhdshubhraj40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iVacY-00086f-RP; Fri, 15 Nov 2019 04:22:39 -0800 From: shubhrajyoti.datta@gmail.com To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, shubhrajyoti.datta@gmail.com, Shubhrajyoti Datta Subject: [PATCHv2 2/2] dt-bindings: add documentation of xilinx clocking wizard Date: Fri, 15 Nov 2019 17:52:32 +0530 Message-Id: <1573820552-21164-2-git-send-email-shubhrajyoti.datta@gmail.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1573820552-21164-1-git-send-email-shubhrajyoti.datta@gmail.com> References: <1573820552-21164-1-git-send-email-shubhrajyoti.datta@gmail.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--9.223-7.0-31-1 X-imss-scan-details: No--9.223-7.0-31-1;No--9.223-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-Matching-Connectors: 132182946675093049; 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X-Forefront-PRVS: 02229A4115 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aTekPEpOxvNZr9/QqfPbPZhDjVFW/c586kQZOFSIIsUAhkQvW0v7+d8bLqX6FFMxBM1sSmB+KxJ+e6+8c2k/XS35RSh2tppffoeRlMuYMfUDc0lQbCO9vrycvjJD1eYU/VEIYYh1UtY7WLQ7ZhcJF8EEOJm1Z9BxXrSdBJGfao50IOCrOSpwkxQajwcKtpk2QM6ATM6WMZpUkFqFSijerqI2YCBpmxucVr7zZLJL9+LAR+pTHwr+Egoohfza/93g76F8oJ5+51MFYfhHCoUdVnTLGSczTdpszzRf/b2vVv7lCcEGM7SX4i3uXANEsLMzrePbWU/ulHODsznTB0UR++mXsduMHLTMOmxH63X83r1QZy1XamBOUBKmqWYUQ+n3Tb6fAax1gNAL7tQYdjJq4AqA0uepDXIAvFN3v5j/BF/NVdZzUHu/BO7II4dg5q022Z5AhmDRTtFyCDWYUFGtHC3iU7zro+/6xu5eujIjoOU= X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2019 12:31:07.3461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17226a15-63cb-457a-95f9-08d769c7b060 X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4699 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shubhrajyoti Datta Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta --- moving from drivers/staging/clocking-wizard/dt-binding.txt .../bindings/clock/xlnx,clocking-wizard.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt new file mode 100644 index 0000000..aedac84 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt @@ -0,0 +1,32 @@ +Binding for Xilinx Clocking Wizard IP Core + +This binding uses the common clock binding[1]. Details about the devices can be +found in the product guide[2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Clocking Wizard Product Guide +http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf + +Required properties: + - compatible: Must be 'xlnx,clocking-wizard' + - #clock-cells: Number of cells in a clock specifier. Should be 1 + - reg: Base and size of the cores register space + - clocks: Handle to input clock + - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' + - clock-output-names: Names for the output clocks + +Optional properties: + - speed-grade: Speed grade of the device (valid values are 1..3) + +Example: + clock-generator@40040000 { + #clock-cells = <1>; + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out0", "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + };