From patchwork Mon Nov 20 03:24:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="E6uV8UAg"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDd46kb1z9s7c for ; Mon, 20 Nov 2017 14:25:44 +1100 (AEDT) Received: from localhost ([::1]:55189 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGciM-0001gL-US for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:25:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGchU-0001df-55 for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGchT-0006R3-5U for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:48 -0500 Received: from mail-io0-x244.google.com ([2607:f8b0:4001:c06::244]:44955) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGchO-0006OX-QL; Sun, 19 Nov 2017 22:24:42 -0500 Received: by mail-io0-x244.google.com with SMTP id w127so14301860iow.11; Sun, 19 Nov 2017 19:24:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XcwkVsaCLxQPr05Qj1Y5/fQm3uLY1/vIUl/p7wGaITk=; b=E6uV8UAgxYRFfMhzy2Uo7718vX9J9uYAwtJzU7XuZPnAVntBBJA1aVivXkFlYx1FDo Nk0Bd3rNWU4yNsw4JQcuaLSLNOP1R7D22QNuHy6L0v+Ko/PZBJxBTr4tcsLGorXmxnXt wizQSQOAKHFsDPOJboqRfg7HsxHaUcoMqY0WE3jWa4bxyJwBhOT6uuZGhfW4CXnOuSTV qL1uyK0GXGlqzxrmUVZ+AKu7c4oWEwTfIcUohh6IHZHOORcF4b/s0zXrE63LLH6vHNJY yoYFoPBzrSXsw9b2oKHrXesx/KabmvDiiD04+31fYoWjYAfknIzaxlSOYoBkQPPbWJ7o f4zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XcwkVsaCLxQPr05Qj1Y5/fQm3uLY1/vIUl/p7wGaITk=; b=SpQJkXznnj2GLFHpoxN0uwDC/Q4W68q9lRibBvqKMLlFDnMQUdMg6b55ySEzJYKcIJ QHQ7dzeDg1/h18RTpNycicRppESCrWCzgKkaq1gnBJF/uVy924jdPmpprwRdQ/dG+Ld4 IQC6H2o2irDPAIk0XI4UIU1PoUoDJ7JH2wfujShbWiK/JzztUVWLSNg00bitOcHtrdf8 BF4F0cSju4Z890RBA/Qfsx3b2vnn5ONpD1xrtN0WJpnNun6df2wM7fwgXPX/ouIMaZpc +RAWWmi6tjYZG41Gtk2fjmkZs044D391a4VZ//1bIuWoXUvrQPVxYpiP58G3dSez2QUX 0P4w== X-Gm-Message-State: AJaThX4/NGgI3lIFhxez5yeHazcSGAd+tzTZlcqESiQR+n8pbdZd7uNe uwVLAzx4ZJa01yDGX6C4FCM= X-Google-Smtp-Source: AGs4zMbfPzr3BouC1lp6EkG7Ta9ORqLMHr7vikKBtqYvNqxnSkXDWoZ14+9OUGFpbrgOOKrnHKwjKQ== X-Received: by 10.107.132.19 with SMTP id g19mr11440578iod.47.1511148281926; Sun, 19 Nov 2017 19:24:41 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:41 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:09 -0600 Message-Id: <20171120032420.9134-2-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: [Qemu-devel] [PATCH 01/12] e500: add board config options X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" allow board code to skip common NIC and guest image setup and configure decrementor frequency. Existing boards unchanged. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 8 ++++++-- hw/ppc/e500.h | 3 +++ hw/ppc/e500plat.c | 1 + hw/ppc/mpc8544ds.c | 1 + 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 5cf0dabef3..9e7e1b29c4 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -826,7 +826,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) env->mpic_iack = params->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; - ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); + ppc_booke_timers_init(cpu, params->decrementor_freq, PPC_TIMER_E500); /* Register reset handler */ if (!i) { @@ -899,7 +899,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - if (pci_bus) { + if (pci_bus && !params->tsec_nic) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); @@ -948,6 +948,10 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) sysbus_mmio_get_region(s, 0)); } + if (params->skip_load) { + return; + } + /* Load kernel. */ if (machine->kernel_filename) { kernel_base = cur_base; diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 70ba1d8f4f..40f72f2de2 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -22,6 +22,9 @@ typedef struct PPCE500Params { hwaddr pci_mmio_base; hwaddr pci_mmio_bus_base; hwaddr spin_base; + uint32_t decrementor_freq; /* in Hz */ + bool skip_load; + bool tsec_nic; } PPCE500Params; void ppce500_init(MachineState *machine, PPCE500Params *params); diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index e59e80fb9e..3d07987bd1 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -47,6 +47,7 @@ static void e500plat_init(MachineState *machine) .pci_mmio_base = 0xC00000000ULL, .pci_mmio_bus_base = 0xE0000000ULL, .spin_base = 0xFEF000000ULL, + .decrementor_freq = 400000000, }; /* Older KVM versions don't support EPR which breaks guests when we announce diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index 1717953ec7..6d9931c475 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -40,6 +40,7 @@ static void mpc8544ds_init(MachineState *machine) .pci_mmio_bus_base = 0xC0000000ULL, .pci_pio_base = 0xE1000000ULL, .spin_base = 0xEF000000ULL, + .decrementor_freq = 400000000, }; if (machine->ram_size > 0xc0000000) { From patchwork Mon Nov 20 03:24:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839397 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TvraAVKl"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDgW6GhPz9s7M for ; Mon, 20 Nov 2017 14:27:51 +1100 (AEDT) Received: from localhost ([::1]:55210 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGckQ-0003dm-0U for incoming@patchwork.ozlabs.org; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:44 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:11 -0600 Message-Id: <20171120032420.9134-4-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 03/12] e500: note possible bug with host bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/pci-host/ppce500.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index f2d108bc8a..0e2833bd98 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -424,6 +424,9 @@ static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) MemoryRegion *ccsr_mr = sysbus_mmio_get_region(ccsr, 0); pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); + /* BUG? identifies as PCI_HEADER_TYPE_BRIDGE but uses + * standard device config read/write + */ d->config[PCI_HEADER_TYPE] = (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | PCI_HEADER_TYPE_BRIDGE; From patchwork Mon Nov 20 03:24:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839398 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SZqRTxxc"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDhL3hdTz9s7M for ; Mon, 20 Nov 2017 14:28:34 +1100 (AEDT) Received: from localhost ([::1]:55213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcl6-0004D2-Fk for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:28:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGchX-0001gN-QJ for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGchW-0006Td-Dl for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:51 -0500 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]:44956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGchT-0006Qy-Ao; Sun, 19 Nov 2017 22:24:47 -0500 Received: by mail-io0-x242.google.com with SMTP id w127so14301993iow.11; Sun, 19 Nov 2017 19:24:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SQsAYat02HsS4BhtEP9JcbnS+ovKclidv1z5s2WqpKM=; b=SZqRTxxcRQiqth/DLwLG/NX2/6IFm/caJpF3XBVizRA6qyI1tfLdkKjYu8g6IlJq2q XRE2cYN7/Z5l13RkiLZqHOgOW4ziZAFGTlr8ixgZsX5ZjdJUJZJPVU/G6bBiSP7i9+FT sfhirsSMEV8MS6trNP6eMLd8ELASyGpNQRHLp693op61h7eefurGlS9NhMRDUOKh1b/z OJOYZf12/erbJkjqfVpy7Gy66h24zXHcX0pwZGFYjz8/AbPtQD9RWGcONpX0qCYTrjLx Qytzb+BEvCXIYkOcVscIJYV8TW/BJotXjxEPo3yMii9HcUz8deXfh3x4rzp/LOxxfrDr 1LsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SQsAYat02HsS4BhtEP9JcbnS+ovKclidv1z5s2WqpKM=; b=rvO57d9KmkNMS1/unfQAzkX7gJ3k9cuNp1fmbAZVuurxUOYCXk2S3Bp4rkijdApPDS nMwW4d4n6JrRM0+VCjgD4DWSWo6nDl6B/pT+MlNk9YHnl/nZ0W5XFU4tEUcQi4b17TUP WEiO9YqEB8UzQy3drS2huoUVakhOnT3lk/gEpFv2nYD/dIPuecY6LNFq6x04MlEr5i8e VESp9iug/d85AJgTofu9N1B3omdaf0K8O0LWG16VZYRFqli0WherBnU7Jn8vhAwp7v5p iSlUDdvxhliT4rG75dPWmKogOzjGVmc7wHx82YH+6zlZWJy3gCctDHkVFv+GbUJ0BnlP zbWA== X-Gm-Message-State: AJaThX7UR0iLwViSF94A75XDkHcuLtmpsvdo+6cKgjehqQ6V4gUVOf+9 2wE+C4ouLDf59+wF44i0a8ayAQ== X-Google-Smtp-Source: AGs4zMaaCbJzCv23mvZK5i0DODIl5SXPv/NAKhJd0yXMLCjymOTT2hQpBMeNkwqIGzXnGChDPDSzRA== X-Received: by 10.107.114.10 with SMTP id n10mr12435107ioc.240.1511148286748; Sun, 19 Nov 2017 19:24:46 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:45 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:12 -0600 Message-Id: <20171120032420.9134-5-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 04/12] e500: additional CCSR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add CCSRBAR to allow CCSR region to be relocated. Guest memory size introspection. Dummy RAM error controls. Guest clock introspection. Signed-off-by: Michael Davidsaver Reviewed-by: David Gibson --- hw/ppc/e500.c | 2 ++ hw/ppc/e500.h | 1 + hw/ppc/e500_ccsr.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- hw/ppc/e500plat.c | 1 + hw/ppc/mpc8544ds.c | 1 + 5 files changed, 75 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 474a46a985..057be1751b 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -853,7 +853,9 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) dev = qdev_create(NULL, "e500-ccsr"); object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); + qdev_prop_set_uint32(dev, "porpllsr", params->porpllsr); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); + qdev_prop_set_uint32(dev, "ram-size", ram_size); qdev_init_nofail(dev); ccsr_addr_space = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 40f72f2de2..1f39095dfa 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -22,6 +22,7 @@ typedef struct PPCE500Params { hwaddr pci_mmio_base; hwaddr pci_mmio_bus_base; hwaddr spin_base; + uint32_t porpllsr; /* value of PORPLLSR register */ uint32_t decrementor_freq; /* in Hz */ bool skip_load; bool tsec_nic; diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index 1b586c3f42..c58b17f06b 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -31,6 +31,16 @@ /* E500_ denotes registers common to all */ +#define E500_CCSRBAR (0) + +#define E500_CS0_BNDS (0x2000) + +#define E500_CS0_CONFIG (0x2080) + +#define E500_ERR_DETECT (0x2e40) +#define E500_ERR_DISABLE (0x2e44) + +#define E500_PORPLLSR (0xE0000) #define E500_PVR (0xE00A0) #define E500_SVR (0xE00A4) @@ -44,7 +54,11 @@ typedef struct { MemoryRegion iomem; - uint32_t defbase; + uint32_t defbase, base; + uint32_t ram_size; + uint32_t merrd; + + uint32_t porpllsr; } CCSRState; #define TYPE_E500_CCSR "e500-ccsr" @@ -53,10 +67,28 @@ typedef struct { static uint64_t e500_ccsr_read(void *opaque, hwaddr addr, unsigned size) { + CCSRState *ccsr = opaque; PowerPCCPU *cpu = POWERPC_CPU(current_cpu); CPUPPCState *env = &cpu->env; switch (addr) { + case E500_CCSRBAR: + return ccsr->base >> 12; + case E500_CS0_BNDS: + /* we model all RAM in a single chip with addresses [0, ram_size) */ + return (ccsr->ram_size - 1) >> 24; + case E500_CS0_CONFIG: + return 1 << 31; + case E500_ERR_DETECT: + return 0; /* (errors not modeled) */ + case E500_ERR_DISABLE: + return ccsr->merrd; + case E500_PORPLLSR: + if (!ccsr->porpllsr) { + qemu_log_mask(LOG_UNIMP, + "Machine does not provide valid PORPLLSR\n"); + } + return ccsr->porpllsr; case E500_PVR: return env->spr[SPR_PVR]; case E500_SVR: @@ -72,10 +104,22 @@ static uint64_t e500_ccsr_read(void *opaque, hwaddr addr, static void e500_ccsr_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { + CCSRState *ccsr = opaque; PowerPCCPU *cpu = POWERPC_CPU(current_cpu); CPUPPCState *env = &cpu->env; uint32_t svr = env->spr[SPR_E500_SVR] >> 16; + switch (addr) { + case E500_CCSRBAR: + value &= 0x000fff00; + ccsr->base = value << 12; + sysbus_mmio_map(SYS_BUS_DEVICE(ccsr), 0, ccsr->base); + return; + case E500_ERR_DISABLE: + ccsr->merrd = value & 0xd; + return; + } + switch (svr) { case 0: /* generic. assumed to be mpc8544ds or e500plat board */ case 0x8034: /* mpc8544 */ @@ -104,11 +148,20 @@ static const MemoryRegionOps e500_ccsr_ops = { } }; +static int e500_ccsr_post_load(void *opaque, int version_id) +{ + CCSRState *ccsr = opaque; + + sysbus_mmio_map(SYS_BUS_DEVICE(ccsr), 0, ccsr->base); + return 0; +} + static void e500_ccsr_reset(DeviceState *dev) { CCSRState *ccsr = E500_CCSR(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ccsr->defbase); + ccsr->base = ccsr->defbase; + e500_ccsr_post_load(ccsr, 1); } static void e500_ccsr_initfn(Object *obj) @@ -123,15 +176,30 @@ static void e500_ccsr_initfn(Object *obj) static Property e500_ccsr_props[] = { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), + DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), + DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), DEFINE_PROP_END_OF_LIST() }; +static const VMStateDescription vmstate_e500_ccsr = { + .name = TYPE_E500_CCSR, + .version_id = 1, + .minimum_version_id = 1, + .post_load = e500_ccsr_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(base, CCSRState), + VMSTATE_UINT32(merrd, CCSRState), + VMSTATE_END_OF_LIST() + } +}; + static void e500_ccsr_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->props = e500_ccsr_props; + dc->vmsd = &vmstate_e500_ccsr; dc->reset = e500_ccsr_reset; } diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 3d07987bd1..4e763d9c09 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -47,6 +47,7 @@ static void e500plat_init(MachineState *machine) .pci_mmio_base = 0xC00000000ULL, .pci_mmio_bus_base = 0xE0000000ULL, .spin_base = 0xFEF000000ULL, + .porpllsr = 0, /* TODO missing valid value */ .decrementor_freq = 400000000, }; diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index 6d9931c475..f5e0042245 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -40,6 +40,7 @@ static void mpc8544ds_init(MachineState *machine) .pci_mmio_bus_base = 0xC0000000ULL, .pci_pio_base = 0xE1000000ULL, .spin_base = 0xEF000000ULL, + .porpllsr = 0, /* TODO missing valid value */ .decrementor_freq = 400000000, }; From patchwork Mon Nov 20 03:24:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Dd9wfa8s"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDkn1vMtz9s7M for ; Mon, 20 Nov 2017 14:30:41 +1100 (AEDT) Received: from localhost ([::1]:55224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcn9-0005py-AH for incoming@patchwork.ozlabs.org; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:47 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:13 -0600 Message-Id: <20171120032420.9134-6-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 05/12] e500: name openpic and pci host bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 057be1751b..6f77844303 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -685,6 +685,8 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, int i, j, k; dev = qdev_create(NULL, TYPE_OPENPIC); + object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev), + &error_fatal); qdev_prop_set_uint32(dev, "model", params->mpic_version); qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); @@ -876,6 +878,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) /* PCI */ dev = qdev_create(NULL, "e500-pcihost"); + object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), + &error_abort); qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); qdev_init_nofail(dev); From patchwork Mon Nov 20 03:24:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lTzqnGi6"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDhk1ZQKz9s7M for ; Mon, 20 Nov 2017 14:28:54 +1100 (AEDT) Received: from localhost ([::1]:55215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGclQ-0004Rw-8y for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:28:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGchc-0001kc-3t for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGcha-0006Vd-Ms for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:56 -0500 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:43233) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGchW-0006T7-4K; Sun, 19 Nov 2017 22:24:50 -0500 Received: by mail-it0-x241.google.com with SMTP id m191so10358027itg.2; Sun, 19 Nov 2017 19:24:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5pcD2SFAm3ugwva4NgpuYIne5DVrNotg0hMRX00jO6Y=; b=lTzqnGi6DkZD0c+4KTpFyohzriPF7f1VE5w+riCJovsiVUYM0QBVFNah6Akbs6JKrl F60Zu6V4tGxiNgaPj1w42ho4vcIScOuilvDcVXJ0xScPk/udoI+fdwIBtnUF/Vyaq+yh sIeDxfB8U6gD4PWOmyXRNV2AEuI4aSevLAThLSNuzQuo/RJWcEdjEUFK50QPfj5GyIx8 bktBrFCMhfqfKWiUg+SSdxPk0/v7dV1IwtyZDPWTspOxJTCxePUmx2JbFxXQaAnAQCCe JgHdM0hBrjBXLUWWhiAx7wyjpI8hH/RbsP0CI8nMcFyxlZjCLI3GWqlB1fsekvEu7ZvX mKzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5pcD2SFAm3ugwva4NgpuYIne5DVrNotg0hMRX00jO6Y=; b=jL9jdfFxC8/kbBhJn/AsyFqp3yCGYJyWkIa7ZDcv/Uv5NaGOka0Inoqvq0xGZP9BzK xk7Sf6E3W/C91UZCAiM6jIbygwv/JM7dy0Ojd5ViyKQeJnqQeDC3MEtXEviUDOgPqSK9 MJCXefmkPZNddDfoxHOaJew9ldLUuTgo5wYsOPDlFhLe01I39iQ/uxdAokRkwP5CPqye 9yvuo3btefdyEtHCcMTOD7aPtXYSSJBld8lGkAphfgG5dxeZVH+tBS3LbR2BsPpbUt/j At9QzeBkOvhA3eHhJTen5BJqabbSROaCcdrLcLHTB2+MkaDhMEaD/WmE1hiZWTnBfKUf 8rrg== X-Gm-Message-State: AJaThX5vE0GkOQP0JJNZP4Nva/rU3OQEWQc2mekVg0tBZWDq7BIZE/L7 8bAcS6fgQi/wmdTJPA7LtmCckA== X-Google-Smtp-Source: AGs4zMYV9MZFwLDkVJpaFZtZvvh+mooLHbU40cy/A0adoY5OeFN42d21qvf/Eg/YuiOWcaMGOEMMbw== X-Received: by 10.36.147.198 with SMTP id y189mr16881696itd.6.1511148289397; Sun, 19 Nov 2017 19:24:49 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:48 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:14 -0600 Message-Id: <20171120032420.9134-7-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 06/12] i2c: add mpc8540 i2c controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/i2c/Makefile.objs | 1 + hw/i2c/mpc8540_i2c.c | 287 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 288 insertions(+) create mode 100644 hw/i2c/mpc8540_i2c.c diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs index 0594dea3ae..79af1dd901 100644 --- a/hw/i2c/Makefile.objs +++ b/hw/i2c/Makefile.objs @@ -9,3 +9,4 @@ common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_i2c.o obj-$(CONFIG_OMAP) += omap_i2c.o obj-$(CONFIG_PPC4XX) += ppc4xx_i2c.o +obj-$(CONFIG_E500) += mpc8540_i2c.o diff --git a/hw/i2c/mpc8540_i2c.c b/hw/i2c/mpc8540_i2c.c new file mode 100644 index 0000000000..884052cc9b --- /dev/null +++ b/hw/i2c/mpc8540_i2c.c @@ -0,0 +1,287 @@ +/* + * MPC8540 I2C bus interface + * As described in + * MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 + * Part 2 chapter 11 + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/i2c/i2c.h" +#include "hw/sysbus.h" + +/* #define DEBUG_LVL 0 */ + +#ifdef DEBUG_LVL +#define DPRINTK(LVL, FMT, ...) do { if ((LVL) <= DEBUG_LVL) { \ + printf(TYPE_MPC8540_I2C " : " FMT, ## __VA_ARGS__); } } while (0) +#else +#define DPRINTK(LVL, FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_MPC8540_I2C \ + " : " FMT, ## __VA_ARGS__) + +#define TYPE_MPC8540_I2C "mpc8540-i2c" +#define MPC8540_I2C(obj) OBJECT_CHECK(I2CState, (obj), TYPE_MPC8540_I2C) + +/* offsets relative to CCSR offset 0x3000 */ +#define R_I2CADR (0) +#define R_I2CFDR (4) +#define R_I2CCR (8) +#define R_I2CSR (0xc) +#define R_I2CDR (0x10) +#define R_I2CDFSRR (0x14) + +FIELD(I2CCR, MEN, 7, 1) +FIELD(I2CCR, MIEN, 6, 1) +FIELD(I2CCR, MSTA, 5, 1) +FIELD(I2CCR, MTX, 4, 1) +FIELD(I2CCR, TXAK, 3, 1) +FIELD(I2CCR, RSTA, 2, 1) +FIELD(I2CCR, BCST, 0, 1) + +FIELD(I2CSR, MCF, 7, 1) +FIELD(I2CSR, MAAS, 6, 1) +FIELD(I2CSR, MBB, 5, 1) +FIELD(I2CSR, MAL, 4, 1) +FIELD(I2CSR, BCSTM, 3, 1) +FIELD(I2CSR, SRW, 2, 1) +FIELD(I2CSR, MIF, 1, 1) +FIELD(I2CSR, RXAK, 0, 1) + +typedef struct I2CState { + SysBusDevice parent_obj; + + I2CBus *bus; + + uint8_t ctrl, sts; + uint8_t freq, filt; + /* Reads are pipelined, this is the next data value */ + uint8_t dbuf; + + qemu_irq irq; + + MemoryRegion mmio; +} I2CState; + +#define I2CCR(BIT) FIELD_EX32(i2c->ctrl, I2CCR, BIT) +#define I2CSR(BIT) FIELD_EX32(i2c->sts, I2CSR, BIT) + +#define I2CSR_SET(BIT, VAL) do {\ + i2c->sts = FIELD_DP32(i2c->sts, I2CSR, BIT, VAL);\ + } while (0) + +static +void mpc8540_update_irq(I2CState *i2c) +{ + int ena = i2c->ctrl & 0x40, + sts = i2c->sts & 0x02, + act = !!(ena && sts); + + DPRINTK(1, "IRQ %c ena %c sts %c\n", + act ? 'X' : '_', + ena ? 'X' : '_', + sts ? 'X' : '_'); + + qemu_set_irq(i2c->irq, act); +} + +static +uint64_t mpc8540_i2c_read(void *opaque, hwaddr addr, unsigned size) +{ + I2CState *i2c = opaque; + uint32_t val, offset = addr; + + switch (offset) { + case R_I2CADR: /* ADDR */ + val = 0; + break; + case R_I2CFDR: /* Freq Div. */ + val = i2c->freq; + break; + case R_I2CCR: /* CONTROL */ + val = i2c->ctrl & ~0x06; + break; + case R_I2CSR: /* STATUS */ + val = i2c->sts; + break; + case R_I2CDR: /* DATA */ + /* Reads are "pipelined" and so return the previous value of the + * register + */ + val = i2c->dbuf; + if (I2CCR(MEN) && I2CSR(MBB)) { /* enabled and busy */ + if (!i2c_bus_busy(i2c->bus) || I2CCR(MTX)) { + LOG(LOG_GUEST_ERROR, "Read during addr or tx\n"); + i2c->dbuf = 0xff; + } else { + int ret = i2c_recv(i2c->bus); + i2c->dbuf = (uint8_t)ret; + DPRINTK(0, "READ %02x ('%c')\n", i2c->dbuf, (char)i2c->dbuf); + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + mpc8540_update_irq(i2c); + } + } else { + i2c->dbuf = 0xff; + LOG(LOG_GUEST_ERROR, "Read when not enabled or busy\n"); + } + break; + case R_I2CDFSRR: /* FILTER */ + val = i2c->filt; + break; + default: + val = 0xff; + } + + DPRINTK(offset == 0xc ? 2 : 1, " read %08x -> %08x\n", + (unsigned)offset, (unsigned)val); + return val; +} + +static +void mpc8540_i2c_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + I2CState *i2c = opaque; + uint32_t offset = addr; + + DPRINTK(1, " write %08x <- %08x\n", (unsigned)offset, (unsigned)val); + + switch (offset) { + case R_I2CADR: /* ADDR */ + break; + case R_I2CFDR: /* Freq Div. */ + i2c->freq = val & 0x3f; + break; + case R_I2CCR: /* CONTROL CCR */ + if (!FIELD_EX32(val, I2CCR, MEN)) { + DPRINTK(0, "Not Enabled\n"); + + } else if (!I2CCR(MSTA) && FIELD_EX32(val, I2CCR, MSTA)) { + /* MSTA 0 -> 1 is START */ + + I2CSR_SET(MBB, 1); + DPRINTK(0, "START\n"); + i2c_end_transfer(i2c->bus); /* paranoia */ + + } else if (I2CCR(MSTA) && !FIELD_EX32(val, I2CCR, MSTA)) { + /* MSTA 1 -> 0 is STOP */ + + I2CSR_SET(MBB, 0); + DPRINTK(0, "STOP\n"); + i2c_end_transfer(i2c->bus); + + } else if (I2CCR(MSTA) && FIELD_EX32(val, I2CCR, RSTA)) { + i2c_end_transfer(i2c->bus); + I2CSR_SET(MBB, 1); + DPRINTK(0, "REP START\n"); + + } + /* RSTA always reads zero, bit 1 unusd */ + val &= 0xf9; + i2c->ctrl = val; + mpc8540_update_irq(i2c); + break; + case R_I2CSR: /* STATUS CSR */ + /* only MAL and MIF are writable */ + val &= 0x12; + i2c->sts &= ~0x12; + i2c->sts |= val; + mpc8540_update_irq(i2c); + break; + case R_I2CDR: /* DATA CDR */ + if (I2CCR(MEN) && I2CSR(MBB)) { /* enabled and busy */ + if (!i2c_bus_busy(i2c->bus)) { + if (i2c_start_transfer(i2c->bus, val >> 1, val & 1)) { + LOG(LOG_GUEST_ERROR, "I2C no device %02x\n", + (unsigned)(val & 0xfe)); + } else { + DPRINTK(0, "ADDR %02x\n", (unsigned)(val & 0xfe)); + } + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + + } else if (I2CCR(MTX)) { + DPRINTK(0, "WRITE %02x\n", (unsigned)val); + i2c_send(i2c->bus, val); + I2CSR_SET(MIF, 1); + I2CSR_SET(RXAK, 0); + } else { + LOG(LOG_GUEST_ERROR, "I2CDR Write during read\n"); + } + mpc8540_update_irq(i2c); + } else { + LOG(LOG_GUEST_ERROR, "I2CDR Write when not enabled or busy\n"); + } + break; + case R_I2CDFSRR: /* FILTER */ + val &= 0x3f; + i2c->filt = val; + break; + } + + DPRINTK(1, "I2CCR = %02x I2SCR = %02x\n", i2c->ctrl, i2c->sts); +} + +static const MemoryRegionOps i2c_ops = { + .read = mpc8540_i2c_read, + .write = mpc8540_i2c_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static +void mpc8540_i2c_reset(DeviceState *dev) +{ + I2CState *i2c = MPC8540_I2C(dev); + + i2c->sts = 0x81; /* transfer complete and ack received */ +} + +static int mpc8540_i2c_inst_init(SysBusDevice *dev) +{ + I2CState *i2c = MPC8540_I2C(dev); + + i2c->bus = i2c_init_bus(&dev->parent_obj, "bus"); + + memory_region_init_io(&i2c->mmio, &dev->parent_obj.parent_obj, + &i2c_ops, i2c, TYPE_MPC8540_I2C, 0x18); + + sysbus_init_mmio(dev, &i2c->mmio); + sysbus_init_irq(dev, &i2c->irq); + return 0; +} + +static void mpc8540_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = &mpc8540_i2c_inst_init; + dc->reset = &mpc8540_i2c_reset; +} + +static const TypeInfo mpc8540_i2c_type = { + .name = TYPE_MPC8540_I2C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(I2CState), + .class_size = sizeof(SysBusDeviceClass), + .class_init = mpc8540_i2c_class_init, +}; + +static void mpc8540_i2c_register(void) +{ + type_register_static(&mpc8540_i2c_type); +} + +type_init(mpc8540_i2c_register) From patchwork Mon Nov 20 03:24:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:49 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:15 -0600 Message-Id: <20171120032420.9134-8-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::242 Subject: [Qemu-devel] [PATCH 07/12] qtest: add e500_i2c_create() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add interface for testing i2c devices with PPC e500. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 1 + tests/libqos/i2c-e500.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/libqos/i2c.h | 3 +++ 3 files changed, 70 insertions(+) create mode 100644 tests/libqos/i2c-e500.c diff --git a/tests/Makefile.include b/tests/Makefile.include index c002352134..ad1c219423 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -721,6 +721,7 @@ libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o libqos-pc-obj-y += tests/libqos/ahci.o libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-e500-obj-y = $(libqos-obj-y) tests/libqos/i2c-e500.o libqos-usb-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/usb.o libqos-virtio-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o diff --git a/tests/libqos/i2c-e500.c b/tests/libqos/i2c-e500.c new file mode 100644 index 0000000000..4272ada0a5 --- /dev/null +++ b/tests/libqos/i2c-e500.c @@ -0,0 +1,66 @@ +/* + * QTest I2C driver + * + * Copyright (c) 2016 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "libqos/i2c.h" + + +#include "qemu/bswap.h" +#include "libqtest.h" + +typedef struct E500I2C { + I2CAdapter parent; + + uint64_t addr; +} E500I2C; + +static void e500_i2c_send(I2CAdapter *i2c, uint8_t addr, + const uint8_t *buf, uint16_t len) +{ + E500I2C *s = (E500I2C *)i2c; + + writeb(s->addr + 0x8, 0xb0); /* Enable and START a write */ + writeb(s->addr + 0x10, addr & 0xfe); /* Send address for write */ + + while (len--) { + writeb(s->addr + 0x10, *buf++); + } + + writeb(s->addr + 0x8, 0x80); /* STOP but leave enabled */ +} + +static void e500_i2c_recv(I2CAdapter *i2c, uint8_t addr, + uint8_t *buf, uint16_t len) +{ + E500I2C *s = (E500I2C *)i2c; + + writeb(s->addr + 0x8, 0xa0); /* Enable and START a read */ + writeb(s->addr + 0x10, addr | 1); /* Send address for read */ + + /* reads are "pipelined" so the initial value is junk */ + readb(s->addr + 0x10); + + while (len--) { + *buf++ = readb(s->addr + 0x10); + } + + writeb(s->addr + 0x8, 0x80); /* STOP but leave enabled */ +} + +I2CAdapter *e500_i2c_create(uint64_t ccsr_base) +{ + E500I2C *s = g_malloc0(sizeof(*s)); + I2CAdapter *i2c = (I2CAdapter *)s; + + s->addr = ccsr_base + 0x3000; + + i2c->send = e500_i2c_send; + i2c->recv = e500_i2c_recv; + + return i2c; +} diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h index 6e648f922a..40c59a7997 100644 --- a/tests/libqos/i2c.h +++ b/tests/libqos/i2c.h @@ -29,4 +29,7 @@ I2CAdapter *omap_i2c_create(uint64_t addr); /* libi2c-imx.c */ I2CAdapter *imx_i2c_create(uint64_t addr); +/* i2c-e500.c */ +I2CAdapter *e500_i2c_create(uint64_t ccsr_base); + #endif From patchwork Mon Nov 20 03:24:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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X-Received-From: 2607:f8b0:4001:c0b::242 Subject: [Qemu-devel] [PATCH 08/12] e500: add mpc8540 i2c controller to ccsr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 6f77844303..bef7d313d4 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -861,6 +861,14 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) qdev_init_nofail(dev); ccsr_addr_space = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + dev = qdev_create(NULL, "mpc8540-i2c"); + object_property_add_child(qdev_get_machine(), "i2c[*]", + OBJECT(dev), NULL); + qdev_init_nofail(dev); + s = SYS_BUS_DEVICE(dev); + memory_region_add_subregion(ccsr_addr_space, 0x3000, + sysbus_mmio_get_region(s, 0)); + mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); /* Serial */ From patchwork Mon Nov 20 03:24:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839405 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="o4x6uG5X"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDp4151Kz9s7c for ; Mon, 20 Nov 2017 14:33:32 +1100 (AEDT) Received: from localhost ([::1]:55242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcpu-00082r-6h for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:33:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGche-0001nQ-9E for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGchd-0006XE-1J for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:24:58 -0500 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:40724) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGcha-0006V9-2f; Sun, 19 Nov 2017 22:24:54 -0500 Received: by mail-it0-x243.google.com with SMTP id 72so10202904itl.5; Sun, 19 Nov 2017 19:24:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0UGdw9kJrL6TFz2BJj1RPJUGY8ZWUQKRhBYwAOSvVZ8=; b=o4x6uG5XPl/0SAZ2QEvxdR4FuC3vH+RCLSscY179jDwGo07FFKaM1iZQYri9XjT5uz kNHafzHKH7gva7wzi1beMHr0/YFvJ/3+aURvmAol0orTssufd6fYzBYyn052h1gXQSPj F2ocII6DkNIR9OhmTzDDAeSOEJAgH17JDZkRwxWM9/w9E3hfe1TE9zmb7I+G7LKg8Oe+ cXyBCXFE+kkneAeCxpdr8lScyfhdj8bexJ1oiObOSV7RxIkinU557paZs5ETxJOQPq4O GTBlMTGGGDqltx6NZCcORhKgvwv6s41069umcEqxEHGddGJnjVLkWM0TfemLtXiKEcbt WOlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0UGdw9kJrL6TFz2BJj1RPJUGY8ZWUQKRhBYwAOSvVZ8=; b=KEOerDZVV5GlO+InU8ltCQS6QOHnyrjQYY/xyqbo3LefIHBoRx6NwuI8Rb15RaMd/s VxUvTqdfaxVJ+3KnrcdHwZoTKe49U611Wl15mOlNnvHRKJy87jYh49nsvWFvdb9jpkRT 1cK/fIi1kFPbyWV7DkyGHbgARm7WRIAB+MNikipssxalgd4UULJ6FgEkyFc071zlUGCu pi/2j9mbivOCsO7oVA15No1xf13GPjIWuftF9pU7SROELpA6S+Cbg967hEAq948wJx/6 CLA8op3oqVlT+54lOqtPeSeAOzoWPxuXA0QRTwJpu0pgJoxFh0i3j3nQnNHiyjt/QUwh em5A== X-Gm-Message-State: AJaThX71gbPxh6KfltrMWFl48JqdvnrOAHZFn68KGmgl7EIJWlUuzGUZ z3qyeY9Ikq55VC77JOggpqFPtQ== X-Google-Smtp-Source: AGs4zMac2Znp+WJKbChOVAMxSRWTEcxXkMKVUHjNNDEBYqn6TU6FqUp4Cz73O1wrGvJHaWxmOJoyNA== X-Received: by 10.36.254.71 with SMTP id w68mr16472557ith.24.1511148293492; Sun, 19 Nov 2017 19:24:53 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:52 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:17 -0600 Message-Id: <20171120032420.9134-10-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 09/12] nvram: add AT24Cx i2c eeprom X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/nvram/Makefile.objs | 1 + hw/nvram/eeprom_at24c.c | 205 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) create mode 100644 hw/nvram/eeprom_at24c.c diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index c018f6b2ff..0f4ee71dcb 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -1,5 +1,6 @@ common-obj-$(CONFIG_DS1225Y) += ds1225y.o common-obj-y += eeprom93xx.o +common-obj-y += eeprom_at24c.o common-obj-y += fw_cfg.o common-obj-y += chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c new file mode 100644 index 0000000000..efa3621ac6 --- /dev/null +++ b/hw/nvram/eeprom_at24c.c @@ -0,0 +1,205 @@ +/* + * *AT24C* series I2C EEPROM + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + */ + +#include + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/i2c/i2c.h" +#include "sysemu/block-backend.h" + +/* #define DEBUG_AT24C */ + +#ifdef DEBUG_AT24C +#define DPRINTK(FMT, ...) printf(TYPE_AT24C_EE " : " FMT, ## __VA_ARGS__) +#else +#define DPRINTK(FMT, ...) do {} while (0) +#endif + +#define ERR(FMT, ...) fprintf(stderr, TYPE_AT24C_EE " : " FMT, \ + ## __VA_ARGS__) + +#define TYPE_AT24C_EE "at24c-eeprom" +#define AT24C_EE(obj) OBJECT_CHECK(EEPROMState, (obj), TYPE_AT24C_EE) + +typedef struct EEPROMState { + I2CSlave parent_obj; + + /* address counter */ + uint16_t cur; + /* total size in bytes */ + uint32_t rsize; + bool writable; + /* cells changed since last START? */ + bool changed; + /* during WRITE, # of address bytes transfered */ + uint8_t haveaddr; + + uint8_t *mem; + + BlockBackend *blk; +} EEPROMState; + +static +int at24c_eeprom_event(I2CSlave *s, enum i2c_event event) +{ + EEPROMState *ee = container_of(s, EEPROMState, parent_obj); + + switch (event) { + case I2C_START_SEND: + case I2C_START_RECV: + case I2C_FINISH: + ee->haveaddr = 0; + DPRINTK("clear\n"); + if (ee->blk && ee->changed) { + int len = blk_pwrite(ee->blk, 0, ee->mem, ee->rsize, 0); + if (len != ee->rsize) { + ERR(TYPE_AT24C_EE + " : failed to write backing file\n"); + } + DPRINTK("Wrote to backing file\n"); + } + ee->changed = false; + break; + case I2C_NACK: + break; + } + return 0; +} + +static +int at24c_eeprom_recv(I2CSlave *s) +{ + EEPROMState *ee = AT24C_EE(s); + int ret; + + ret = ee->mem[ee->cur]; + + ee->cur = (ee->cur + 1u) % ee->rsize; + DPRINTK("Recv %02x %c\n", ret, ret); + + return ret; +} + +static +int at24c_eeprom_send(I2CSlave *s, uint8_t data) +{ + EEPROMState *ee = AT24C_EE(s); + + if (ee->haveaddr < 2) { + ee->cur <<= 8; + ee->cur |= data; + ee->haveaddr++; + if (ee->haveaddr == 2) { + ee->cur %= ee->rsize; + DPRINTK("Set pointer %04x\n", ee->cur); + } + + } else { + if (ee->writable) { + DPRINTK("Send %02x\n", data); + ee->mem[ee->cur] = data; + ee->changed = true; + } else { + DPRINTK("Send error %02x read-only\n", data); + } + ee->cur = (ee->cur + 1u) % ee->rsize; + + } + + return 0; +} + +static +int at24c_eeprom_init(I2CSlave *i2c) +{ + EEPROMState *ee = AT24C_EE(i2c); + + ee->mem = g_malloc0(ee->rsize); + + if (ee->blk) { + int64_t len = blk_getlength(ee->blk); + + if (len != ee->rsize) { + ERR(TYPE_AT24C_EE " : Backing file size %lu != %u\n", + (unsigned long)len, (unsigned)ee->rsize); + exit(1); + } + + if (blk_set_perm(ee->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, + BLK_PERM_ALL, &error_fatal) < 0) + { + ERR(TYPE_AT24C_EE + " : Backing file incorrect permission\n"); + exit(1); + } + } + return 0; +} + +static +void at24c_eeprom_reset(DeviceState *state) +{ + EEPROMState *ee = AT24C_EE(state); + + ee->changed = false; + ee->cur = 0; + ee->haveaddr = 0; + + memset(ee->mem, 0, ee->rsize); + + if (ee->blk) { + int len = blk_pread(ee->blk, 0, ee->mem, ee->rsize); + + if (len != ee->rsize) { + ERR(TYPE_AT24C_EE + " : Failed initial sync with backing file\n"); + } + DPRINTK("Reset read backing file\n"); + } +} + +static Property at24c_eeprom_props[] = { + DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0), + DEFINE_PROP_BOOL("writable", EEPROMState, writable, true), + DEFINE_PROP_DRIVE("drive", EEPROMState, blk), + DEFINE_PROP_END_OF_LIST() +}; + +static +void at24c_eeprom_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + + k->init = &at24c_eeprom_init; + k->event = &at24c_eeprom_event; + k->recv = &at24c_eeprom_recv; + k->send = &at24c_eeprom_send; + + dc->props = at24c_eeprom_props; + dc->reset = at24c_eeprom_reset; +} + +static +const TypeInfo at24c_eeprom_type = { + .name = TYPE_AT24C_EE, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(EEPROMState), + .class_size = sizeof(I2CSlaveClass), + .class_init = at24c_eeprom_class_init, +}; + +static void at24c_eeprom_register(void) +{ + type_register_static(&at24c_eeprom_type); +} + +type_init(at24c_eeprom_register) From patchwork Mon Nov 20 03:24:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839408 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="g1Qy50hw"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDrp4tQtz9s7M for ; Mon, 20 Nov 2017 14:35:54 +1100 (AEDT) Received: from localhost ([::1]:55258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcsC-0001VQ-Li for incoming@patchwork.ozlabs.org; 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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:54 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:18 -0600 Message-Id: <20171120032420.9134-11-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 10/12] timer: add ds1375 RTC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" only basic functionality implemented (read time and sram). no set time or alarms. Signed-off-by: Michael Davidsaver --- default-configs/ppc-softmmu.mak | 1 + hw/timer/Makefile.objs | 1 + hw/timer/ds1375-i2c.c | 293 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 hw/timer/ds1375-i2c.c diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index bb225c6e46..04bfa79154 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -52,3 +52,4 @@ CONFIG_SERIAL_ISA=y CONFIG_MC146818RTC=y CONFIG_ISA_TESTDEV=y CONFIG_RS6000_MC=y +CONFIG_DS1375=y diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 8c19eac3b6..6521d47367 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -4,6 +4,7 @@ common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o common-obj-$(CONFIG_CADENCE) += cadence_ttc.o common-obj-$(CONFIG_DS1338) += ds1338.o +common-obj-$(CONFIG_DS1375) += ds1375-i2c.o common-obj-$(CONFIG_HPET) += hpet.o common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o common-obj-$(CONFIG_M48T59) += m48t59.o diff --git a/hw/timer/ds1375-i2c.c b/hw/timer/ds1375-i2c.c new file mode 100644 index 0000000000..dba9cc05c4 --- /dev/null +++ b/hw/timer/ds1375-i2c.c @@ -0,0 +1,293 @@ +/* + * Dallas/Maxim ds1375 I2C RTC w/ SRAM + * + * Copyright (c) 2017 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * Only basic functionality is modeled (time and user SRAM). + * Alarms not modeled. + */ +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "qemu/bcd.h" +#include "hw/hw.h" +#include "hw/registerfields.h" +#include "hw/i2c/i2c.h" + +#define DEBUG_DS1375 + +#ifdef DEBUG_DS1375 +#define DPRINTK(FMT, ...) printf(TYPE_DS1375 " : " FMT, ## __VA_ARGS__) +#else +#define DPRINTK(FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_DS1375 " : " FMT, \ + ## __VA_ARGS__) + +#define TYPE_DS1375 "ds1375" +#define DS1375(obj) OBJECT_CHECK(DS1375State, (obj), TYPE_DS1375) + +#define DS1375_REGSIZE 0x20 + +#define R_SEC (0x0) +#define R_MIN (0x1) +#define R_HOUR (0x2) +#define R_WDAY (0x3) +#define R_DATE (0x4) +#define R_MONTH (0x5) +#define R_YEAR (0x6) +#define R_A1SEC (0x7) +#define R_A1MIN (0x8) +#define R_A1HOUR (0x9) +#define R_A1DAY (0xa) +#define R_A2SEC (0xb) +#define R_A2MIN (0xc) +#define R_A2HOUR (0xd) +#define R_CTRL (0xe) +#define R_STS (0xf) + +FIELD(HOUR, SET12, 6, 1) +FIELD(HOUR, HOUR24, 0, 6) +FIELD(HOUR, AMPM, 5, 1) +FIELD(HOUR, HOUR12, 0, 5) + +FIELD(MONTH, MONTH, 0, 5) +FIELD(MONTH, CENTURY, 7, 1) + +FIELD(CTRL, ECLK, 7, 1) +FIELD(CTRL, CLKSEL, 5, 2) +FIELD(CTRL, RS, 3, 2) +FIELD(CTRL, INTCN, 2, 1) +FIELD(CTRL, A2IE, 1, 1) +FIELD(CTRL, A1IE, 0, 1) + +typedef struct DS1375State { + I2CSlave parent_obj; + + /* register address counter */ + uint8_t addr; + /* when writing, whether the address has been sent */ + bool addrd; + + int time_offset; + + uint8_t regs[DS1375_REGSIZE]; +} DS1375State; + +/* update current time register if clock enabled */ +static +void ds1375_latch(DS1375State *ds) +{ + struct tm now; + + if (!ARRAY_FIELD_EX32(ds->regs, CTRL, ECLK)) { + return; + } + + qemu_get_timedate(&now, ds->time_offset); + + DPRINTK("Current Time %3u/%2u/%u %2u:%2u:%2u (wday %u)\n", + now.tm_year, now.tm_mon, now.tm_mday, + now.tm_hour, now.tm_min, now.tm_sec, + now.tm_wday); + + /* ensure unused bits are zero */ + memset(ds->regs, 0, R_YEAR + 1); + + ds->regs[R_SEC] = to_bcd(now.tm_sec); + ds->regs[R_MIN] = to_bcd(now.tm_min); + + if (ARRAY_FIELD_EX32(ds->regs, HOUR, SET12) == 0) { + /* 24 hour */ + ARRAY_FIELD_DP32(ds->regs, HOUR, HOUR24, to_bcd(now.tm_hour)); + } else { + /* 12 hour am/pm */ + ARRAY_FIELD_DP32(ds->regs, HOUR, AMPM, now.tm_hour >= 12); + ARRAY_FIELD_DP32(ds->regs, HOUR, HOUR12, to_bcd(now.tm_hour % 12u)); + } + + ds->regs[R_WDAY] = now.tm_wday; /* day of the week */ + ds->regs[R_DATE] = to_bcd(now.tm_mday); + + ARRAY_FIELD_DP32(ds->regs, MONTH, MONTH, to_bcd(now.tm_mon + 1)); + ARRAY_FIELD_DP32(ds->regs, MONTH, CENTURY, now.tm_year > 99); + + ds->regs[R_YEAR] = to_bcd(now.tm_year % 100u); + + DPRINTK("Latched time\n"); +} + +static +void ds1375_update(DS1375State *ds) +{ + struct tm now; + + now.tm_sec = from_bcd(ds->regs[R_SEC]); + now.tm_min = from_bcd(ds->regs[R_MIN]); + + if (ARRAY_FIELD_EX32(ds->regs, HOUR, SET12)) { + now.tm_hour = from_bcd(ARRAY_FIELD_EX32(ds->regs, HOUR, HOUR12)); + if (ARRAY_FIELD_EX32(ds->regs, HOUR, AMPM)) { + now.tm_hour += 12; + } + + } else { + now.tm_hour = from_bcd(ARRAY_FIELD_EX32(ds->regs, HOUR, HOUR24)); + } + + now.tm_wday = from_bcd(ds->regs[R_WDAY]); + now.tm_mday = from_bcd(ds->regs[R_DATE]); + now.tm_mon = from_bcd(ARRAY_FIELD_EX32(ds->regs, MONTH, MONTH)) - 1; + + now.tm_year = from_bcd(ds->regs[R_YEAR]) % 100u; + if (ARRAY_FIELD_EX32(ds->regs, MONTH, CENTURY)) { + now.tm_year += 100; + } + + DPRINTK("New Time %3u/%2u/%u %2u:%2u:%2u (wday %u)\n", + now.tm_year, now.tm_mon, now.tm_mday, + now.tm_hour, now.tm_min, now.tm_sec, + now.tm_wday); + + ds->time_offset = qemu_timedate_diff(&now); + DPRINTK("Update offset = %d\n", ds->time_offset); +} + +static +int ds1375_event(I2CSlave *s, enum i2c_event event) +{ + DS1375State *ds = container_of(s, DS1375State, parent_obj); + + switch (event) { + case I2C_START_SEND: + ds->addrd = false; + case I2C_START_RECV: + ds1375_latch(ds); + case I2C_FINISH: + DPRINTK("Event %d\n", (int)event); + case I2C_NACK: + break; + } + return 0; +} + +static +int ds1375_recv(I2CSlave *s) +{ + DS1375State *ds = container_of(s, DS1375State, parent_obj); + int ret = 0; + + switch (ds->addr) { + case R_SEC ... R_YEAR: + case R_CTRL: + case R_STS: + case 0x10 ... 0x1f: + ret = ds->regs[ds->addr]; + break; + default: + LOG(LOG_UNIMP, "Read from unimplemented (%02x) %02x\n", ds->addr, ret); + } + + DPRINTK("Recv (%02x) %02x\n", ds->addr, ret); + + ds->addr++; + ds->addr &= 0x1f; + if (ds->addr == 0) { + ds1375_latch(ds); + } + + return ret; +} + +static +int ds1375_send(I2CSlave *s, uint8_t data) +{ + DS1375State *ds = container_of(s, DS1375State, parent_obj); + + if (!ds->addrd) { + data &= 0x1f; + ds->addr = data; + DPRINTK("Set address pointer %02x\n", data); + ds->addrd = true; + return 0; + + } else { + DPRINTK("Send (%02x) %02x\n", ds->addr, data); + switch (ds->addr) { + case R_SEC ... R_YEAR: + ds->regs[ds->addr] = data; + ds1375_update(ds); + break; + case R_CTRL: + if (data & 0x7) { + LOG(LOG_UNIMP, "Alarm interrupt/output not modeled\n"); + } + ds->regs[ds->addr] = data; + break; + case 0x10 ... 0x1f: + ds->regs[ds->addr] = data; + break; + default: + LOG(LOG_UNIMP, "Write to unimplemented (%02x) %02x\n", + ds->addr, data); + } + + ds->addr++; + ds->addr &= 0x1f; + if (ds->addr == 0) { + ds1375_latch(ds); + } + + return 0; + } +} + +static +void ds1375_reset(DeviceState *device) +{ + DS1375State *ds = DS1375(device); + + memset(ds->regs, 0, sizeof(ds->regs)); + /* TODO: not clear SRAM? */ + + /* Default to 12-hour mode */ + ARRAY_FIELD_DP32(ds->regs, CTRL, ECLK, 1); + + ds->addr = 0; + + /* do not re-zero time offset */ +} + +static +void ds1375_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + + k->event = &ds1375_event; + k->recv = &ds1375_recv; + k->send = &ds1375_send; + + dc->reset = &ds1375_reset; +} + +static +const TypeInfo ds1375_type = { + .name = TYPE_DS1375, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(DS1375State), + .class_size = sizeof(I2CSlaveClass), + .class_init = ds1375_class_init, +}; + +static void ds1375_register(void) +{ + type_register_static(&ds1375_type); +} + +type_init(ds1375_register) From patchwork Mon Nov 20 03:24:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qIncVAvx"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDrb59s1z9s7M for ; Mon, 20 Nov 2017 14:35:43 +1100 (AEDT) Received: from localhost ([::1]:55253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcs1-0001In-Qc for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:35:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGchm-0001vR-Oh for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:25:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGchj-0006bC-Tc for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:25:06 -0500 Received: from mail-it0-x236.google.com ([2607:f8b0:4001:c0b::236]:46060) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGchd-0006XK-GR; Sun, 19 Nov 2017 22:24:57 -0500 Received: by mail-it0-x236.google.com with SMTP id x13so1895702iti.4; Sun, 19 Nov 2017 19:24:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+7EYrFciNt+DEfZ9Tu1+6qjHO0ORYbA9xrWO6RXbGAU=; b=qIncVAvxE0ZRP8mwrlZRWrB2HJEpzY/nE2alwAIcnscxSMLh0/J3TZ7Fx2y3Rtu5It uQQffEttB5lRfdh913vfWdJVj/8KQyDiRwkMO7pWZJP4//cSQBeboX4KGQ6qKCR1xB70 8rQ2ii6LlcTQGt0Eo/jz5g9zb5nBIQh3HnXE34tt822ZikvvBpCDtmTxknXvQlyQrPVp 3Z5p1U63Df5gy6+Ga17Tm7c+/sBC38M3ICatwOIQGb1Uf+ROUIy1hvC/gpuIzP3pI/rl vvsVo/S5zyJOhe5bN6LKDO00wG1+4sC+CKQsb7fyM4sJQ1XdmajkDkaR1E/l0sgRJxDq inAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+7EYrFciNt+DEfZ9Tu1+6qjHO0ORYbA9xrWO6RXbGAU=; b=RDVrYPSf4eiAuhUZkv6V+WsiRILfwnui0VxwOKshR43EB9Np1/Ez3WuU0Ok+9pDsZi G5220iOfcVgYLhgAUi2IcoqympdWkCPe1khXntxcdrqwY8/0Fyy8kjAeZu+76KgAq2PF j7gYTGJQ0IcvTzDiaZKPIrrKIdJ4k6/xfKOd08Avw+lhyO6ieIndSuVoZ2RrxdETVzV7 NzcnEvdh2jg1yQ4kK+5igAQ/bW2MWjuRX+Uz7mj40OvZbWmGxjYZQYrJV0GVwdnoJnrx DnDzbK1eN8UsXX/GmBm4YFeQBVACU8XRXJl8vjzJk2KXwjYiEZpSgYQ4/xh3IPx9BOOz n0JQ== X-Gm-Message-State: AJaThX66Ts7Rq7NahFMIrkZDyQKx93WXOAhPUjALq/1JFLpfAwlJVb+h e6n+zuyVlcaT48Ltb6KmEyU= X-Google-Smtp-Source: AGs4zMYyF1QeoL7gzfz36xL4JWWQc3tjE0yIqKj9UU/Wu1dWy4+WHcDEfTzP050RGEPeu6vKlHWQNg== X-Received: by 10.36.31.80 with SMTP id d77mr6520109itd.65.1511148296358; Sun, 19 Nov 2017 19:24:56 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:55 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:19 -0600 Message-Id: <20171120032420.9134-12-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::236 Subject: [Qemu-devel] [PATCH 11/12] ppc: add mvme3100 machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Davidsaver --- hw/ppc/Makefile.objs | 1 + hw/ppc/mvme3100.c | 688 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/mvme3100_cpld.c | 192 ++++++++++++++ 3 files changed, 881 insertions(+) create mode 100644 hw/ppc/mvme3100.c create mode 100644 hw/ppc/mvme3100_cpld.c diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index c1a63d0c39..c1118aaa42 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -26,5 +26,6 @@ obj-$(CONFIG_MAC) += mac_newworld.o obj-$(CONFIG_E500) += e500.o mpc8544ds.o e500plat.o obj-$(CONFIG_E500) += ppce500_spin.o obj-$(CONFIG_E500) += e500_ccsr.o +obj-$(CONFIG_E500) += mvme3100.o mvme3100_cpld.o # PowerPC 440 Xilinx ML507 reference board. obj-$(CONFIG_XILINX) += virtex_ml507.o diff --git a/hw/ppc/mvme3100.c b/hw/ppc/mvme3100.c new file mode 100644 index 0000000000..2e6d428533 --- /dev/null +++ b/hw/ppc/mvme3100.c @@ -0,0 +1,688 @@ +/* + * MVME3100 board emulation + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * This model was developed according to the + * MVME3100 Single Board Computer Programmer's Reference + * P/N: 6806800G37B + * July 2014 + * + * mvme3100-1152 + * 677MHz core, 256MB ram, 64MB flash + * mvme3100-1263 + * 833MHz core, 512MB ram, 128MB flash + * + * MOTLoad on mvme3100-1152 says: + * MPU-Type =MPC8540 + * MPU-Int Clock Speed =666MHz + * MPU-CCB Clock Speed =333MHz + * MPU-DDR Clock Speed =166MHz + * MPU-PCI Clock Speed =66MHz, PCI, 64-bit + * MPU-Int Cache(L2) Enabled, 256KB, L2CTL =A8000300 + * Reset/Boot Vector =Flash0 + * Local Memory Found =10000000 (&268435456) + * + * MOTLoad on mvme3100-1263 says: + * MPU-Type =MPC8540 + * MPU-Int Clock Speed =833MHz + * MPU-CCB Clock Speed =333MHz + * MPU-DDR Clock Speed =166MHz + * MPU-PCI Clock Speed =66MHz, PCI, 64-bit + * MPU-Int Cache(L2) Enabled, 256KB, L2CTL =A8000300 + * Reset/Boot Vector =Flash0 + * Local Memory Found =20000000 (&536870912) + * + * Clock ratios + * CCB/PCI -> 5/1 + * core/CCB -> 2/1 (-1152) + * -> 5/2 (-1263) + * + * The overall memory map is determined by the Local Address Windows. + * We do not model the LAWs explicitly. + * + * MOTLoad configures as follows (a super set of table 1-4) + * (MOTLoad RTOS Version 2.0, PAL Version 1.2 RM04) + * LAW 0, 7 - disabled + * LAW 1 - 0x00000000 -> 0x7fffffff - RAM 2G + * LAW 2 - 0x80000000 -> 0xbfffffff - PCI 1G + * LAW 3 - 0xc0000000 -> 0xdfffffff - PCI 512MB + * LAW 4 - 0xe0000000 -> 0xe0ffffff - PCI 16MB + * gap - 0xe1000000 -> 0xbfffffff - CCSR @ 0xe1000000 + * LAW 5 - 0xe2000000 -> 0xe2ffffff - LBC 16MB + * gap - 0xe3000000 -> 0xefffffff + * LAW 6 - 0xf0000000 -> 0xffffffff - LBC 256MB + * + * And validated against the RTEMS 4.9.6 mvme3100 BSP + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "e500.h" +#include "cpu.h" +#include "qemu-common.h" +#include "cpu-qom.h" +#include "sysemu/sysemu.h" +#include "sysemu/dma.h" +#include "sysemu/block-backend.h" +#include "hw/loader.h" +#include "hw/pci/pci.h" +#include "hw/boards.h" +#include "hw/ppc/ppc.h" +#include "hw/net/fsl_etsec/etsec.h" +#include "sysemu/device_tree.h" +#include "sysemu/qtest.h" +#include "hw/ppc/openpic.h" +#include "qemu/error-report.h" + +/* Same as prep.c and other PPC boards */ +#define CFG_ADDR 0xf0000510 + +#define TYPE_MVME3100 MACHINE_TYPE_NAME("mvme3100") +#define MVME3100(obj) OBJECT_CHECK(MVME3100State, (obj), TYPE_MVME3100) +#define MVME3100_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MVME3100Class, (obj), TYPE_MVME3100) +#define MVME3100_CLASS(klass) \ + OBJECT_CLASS_CHECK(MVME3100Class, (klass), TYPE_MVME3100) + + +typedef struct mvme3100_info { + const char *desc; + uint32_t cpu_freq; + uint32_t porpllsr; + uint32_t ram_size; +} mvme3100_info; + +typedef struct MVME3100Class { + /*< private >*/ + MachineClass parent_class; + /*< public >*/ + + const mvme3100_info *info; +} MVME3100Class; + +typedef struct MVME3100State { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ + + uint32_t load_address, + entry_address; +} MVME3100State; + + +/* motload "global environment" variables */ +static +const char *gev[] = { + /* TODO: somehow snoop in slirp_instances to pick up IP config? */ + "mot-/dev/enet0-cipa=10.0.2.15", + "mot-/dev/enet0-gipa=10.0.2.2", + "mot-/dev/enet0-snma=255.255.255.0", + "mot-/dev/enet0-sipa=10.0.2.2", + /* RTEMS specific names for things motload doesn't have */ + "rtems-dns-server=10.0.2.3", + "rtems-client-name=qemu", + NULL, +}; + +/* Prepare Motorola Vital Product Data eeprom image. + * Provided to bootloader for use as a default. + * + * Begins with constant "MOTLOAD" followed by variable length records + * with a two byte header (ID code then body length in bytes). + * + * | ID | Length | body .... | repeated until ID=0xFF + * + * ID Codes: + * 1 - Product ID (string) + * 2 - Assembly # (string) + * 3 - Serial # (string) + * 5 - CPU Speed (Hz, 4 byte integer + 1 nil) + * 6 - Bus Speed (Hz, 4 byte integer + 1 nil) + * 8 - Ethernet MAC (6 bytes + 1 nil) + * 9 - CPU type + * A - VPD CRC (4 bytes) + * B - Flash Config (??) + * E - L2 Cache Config (??) + * F - VPD Version (4 bytes) + * 19 - L3 Cache Config (??) + * FF - End of VPD (size zero) + * + * Repeat entries for repeated units. eg. two ID=0x8 for two NICs + * + * MOTLoad uses the same eeprom to hold it's user configuration + * Global Environment Variable (GEV) list. + */ +typedef struct vpdeeprom { + char * const base; + char *cur; + size_t total; +} vpdeeprom; + +static +void append_gev_vpd(vpdeeprom *vpd, const char *str) +{ + const size_t remaining = vpd->total - (vpd->cur - vpd->base), + len = strlen(str); + + if ((len == 0 && remaining < 1) + || (remaining < len + 2)) + { + fprintf(stderr, "VPD GEV overflow\n"); + return; + } + + memcpy(vpd->cur, str, len + 1); + + vpd->cur += len + 1; +} + +static +void append_vpd(vpdeeprom *vpd, uint8_t id, size_t cnt, const void *val) +{ + const size_t remaining = vpd->total - (vpd->cur - vpd->base); + + /* must have enough space for this entry and final ID=0xff */ + if ((id == 0xff && remaining < 2) + || (remaining + 4 < cnt || cnt > 255)) + { + fprintf(stderr, "VPD overflow\n"); + return; + } + + vpd->cur[0] = id; + vpd->cur[1] = cnt; + memcpy(vpd->cur + 2, val, cnt); + + vpd->cur += 2 + cnt; +} + +static +void append_string_vpd(vpdeeprom *vpd, uint8_t id, const char *str) +{ + /* include trailing nil */ + append_vpd(vpd, id, strlen(str) + 1, str); +} + +static +void append_mac_vpd(vpdeeprom *vpd, uint8_t id, const MACAddr *addr) +{ + char buf[7]; + memcpy(buf, addr->a, 6); + buf[6] = 0; + + append_vpd(vpd, id, 7, buf); +} + +static +void append_u32_vpd(vpdeeprom *vpd, uint8_t id, uint32_t val) +{ + union { + uint32_t ival; + char bytes[5]; /* include trailing nil */ + } buf; + buf.ival = cpu_to_be32(val); + buf.bytes[4] = 0; + + append_vpd(vpd, id, 5, buf.bytes); +} + +static +void build_vpd(const mvme3100_info *info, char *buf, size_t cnt, + const char *extra) +{ + vpdeeprom vpd = {buf, buf, cnt}; + size_t i; + + memset(buf, 0, cnt); + + strcpy(buf, "MOTOROLA"); + vpd.cur += 8; + + /* Product ID (eg. "MVME3100-1152") */ + append_string_vpd(&vpd, 1, info->desc); + + /* serial number */ + append_string_vpd(&vpd, 3, "E0120000"); + + /* CPU Freq. */ + append_u32_vpd(&vpd, 5, info->cpu_freq); + + /* PCI Bus Freq. */ + append_u32_vpd(&vpd, 6, 66666666); + + for (i = 0; i < MAX_NICS; i++) { + if (nd_table[i].used) { + append_mac_vpd(&vpd, 8, &nd_table[i].macaddr); + } + } + + append_vpd(&vpd, 0xff, 0, NULL); + + if (vpd.cur - vpd.base > 0x10f8) { + fprintf(stderr, "VPD overflows GEV area.\n"); + return; + } + + /* MOTLOAD's Global Environment Variables + * start at offset 0x10f8. + * This is a set of nil terminated strings of the form "name=value" + * with a zero length string signaling the end. + */ + vpd.cur = vpd.base + 0x10f8; + + for (i = 0; gev[i]; i++) { + append_gev_vpd(&vpd, gev[i]); + } + + if (extra) { + char *E = g_strdup(extra); + char **opts = g_strsplit(E, " ", 0); + size_t i; + + g_free(E); + + for (i = 0; opts[i]; i++) { + char *opt = g_strstrip(opts[i]); + size_t olen = strlen(opt); + + if (olen == 0) { + continue; + } else if (!strchr(opt, '=')) { + fprintf(stderr, "Missing '=' in -append %s\n", extra); + continue; + } + + append_gev_vpd(&vpd, opt); + } + + g_strfreev(opts); + } + + /* zero length string signals end */ + append_gev_vpd(&vpd, ""); +} + +static void mvme3100_fixup_devtree(PPCE500Params *params, void *fdt) +{ + (void)params; + (void)fdt; +} + +static +void set_map(CPUPPCState *env, unsigned way, + target_ulong va, hwaddr pa, + unsigned size) +{ + ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, way); + + tlb->mas1 = MAS1_VALID | (size << MAS1_TSIZE_SHIFT); + tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_I | MAS2_G; + tlb->mas7_3 = (pa & TARGET_PAGE_MASK) | MAS3_SR | MAS3_SW | MAS3_SX; +} + +static +void remap_tlb_bare(CPUPPCState *env) +{ + /* The MPC8540 ref. manual says only the upper 4KB (ROM) + * is mapped, but doesn't say exactly how this mapping + * is setup. So we arbitrarily decide to use TLB1 entry 0. + */ + set_map(env, 0, 0xfffff000, 0xfffff000, 0x02); + + env->tlb_dirty = true; +} + +/* runs after ppce500_cpu_reset() */ +static void mvme3100_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + + /* We don't model HID0 functions. + * HID0[EMCP] (32) and HID0[TBEN] (TBEN) set + */ + env->spr[SPR_HID0] = 0x80004000; + + remap_tlb_bare(&cpu->env); + env->nip = 0xfffffffc; +} + +/* PCI config from a real mvme3100 as configured by motload + * + * BUS:SLOT:FUN VENDOR-DEV_ID: COMMAND STATUS BASE_ADDR0 BASE_ADDR1 IRQ_PIN -> IRQ_LINE + * 0:0x00:0 0x1057-0x0008: 0x0006 0x20B0 0x80000000 0x00000000 0 -> 0 (=0x00) + * 0:0x11:0 0x10E3-0x0148: 0x0146 0x02B0 0x80100004 0x00000000 1 -> 0 (=0x00) + * 0:0x12:0 0x10B5-0x6520: 0x0147 0x02B0 0x00000000 0x00000000 0 -> 0 (=0x00) + * 0:0x13:0 0x10B5-0x6520: 0x0147 0x02B0 0x00000000 0x00000000 0 -> 0 (=0x00) + * 0:0x14:0 0x8086-0x3200: 0x0145 0x02B0 0x00012001 0x00013001 1 -> 2 (=0x02) + * 2:0x00:0 0x1033-0x0035: 0x0146 0x0210 0x80300000 0x00000000 1 -> 4 (=0x04) + * 2:0x00:1 0x1033-0x0035: 0x0146 0x0210 0x80301000 0x00000000 2 -> 5 (=0x05) + * + * The modeled PCI host bridge differs. + * + * We don't model: + * # The SATA controller GD31244 (0x8086-0x3200) + * # The USB (OHCI) controller uPD740101 (0x1033-0x0035) + * + * (Note that the SATA controller found on newer boards is different) + */ + +static void mvme3100_init(MachineState *machine) +{ + /* Config based on system state from MOTLoad, not power on */ + static + PPCE500Params params = { + .pci_first_slot = 0, + .pci_nr_slots = 5, + .fixup_devtree = mvme3100_fixup_devtree, + .mpic_version = OPENPIC_MODEL_FSL_MPIC_20, + .ccsrbar_base = 0xff700000ULL, + .pci_mmio_base = 0x80000000ULL, + .pci_mmio_bus_base = 0x80000000ULL, + .pci_pio_base = 0xE0000000ULL, + .spin_base = 0xE3000000ULL, /* not used */ + .skip_load = 1, + .tsec_nic = true, + /* .porpllsr set from mvme3100_info */ + /* Decrementor frequency actually controlled by HID0[SEL_TBCLK] + * or disabled by HID0[TBEN]. + * We don't model and assume always enabled with CCB/8 + */ + .decrementor_freq = 41666666, + }; + MVME3100State *mvme3100 = MVME3100(machine); + const mvme3100_info *info; + DeviceState *dev; + BusState *i2c; + SysBusDevice *cpld, *ccsr, *pic; + FWCfgState *fwinfo; + DriveInfo *drvinfo; + + { + MVME3100Class *klass = MVME3100_GET_CLASS(machine); + info = klass->info; + } + params.porpllsr = info->porpllsr; + + /* Setup CPU */ + ppce500_init(machine, ¶ms); + + qemu_register_reset(mvme3100_cpu_reset, POWERPC_CPU(first_cpu)); + + pic = SYS_BUS_DEVICE(object_resolve_path("/machine/pic", NULL)); + ccsr = SYS_BUS_DEVICE(object_resolve_path("/machine/e500-ccsr", NULL)); + + /* Setup mvme3100 specific CPLD device */ + cpld = SYS_BUS_DEVICE(qdev_create(NULL, "mvme3100-cpld")); + object_property_add_child(qdev_get_machine(), "cpld", + OBJECT(cpld), &error_fatal); + qdev_init_nofail(DEVICE(cpld)); + + memory_region_add_subregion(get_system_memory(), + 0xe2000000, + sysbus_mmio_get_region(cpld, 0)); + + fwinfo = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); + fw_cfg_add_i16(fwinfo, FW_CFG_NB_CPUS, 1); + fw_cfg_add_i16(fwinfo, FW_CFG_MAX_CPUS, 1); + fw_cfg_add_i64(fwinfo, FW_CFG_RAM_SIZE, machine->ram_size); + + /* I2C Controller */ + dev = DEVICE(object_resolve_path("/machine/i2c[0]", NULL)); + assert(dev); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(DEVICE(pic), 16 + 27)); + i2c = qdev_get_child_bus(dev, "bus"); + assert(i2c); + + dev = DEVICE(object_resolve_path("/machine/pci-host", NULL)); + assert(dev); + /*TODO: add pci-to-pci bridge and fix host bridge IRQ mappings + * to start from IRQ4 + */ + + /* NIC */ + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], "eTSEC"); + + dev = etsec_create(0x24000, + sysbus_mmio_get_region(ccsr, 0), + &nd_table[0], + qdev_get_gpio_in(DEVICE(pic), 16 + 13), + qdev_get_gpio_in(DEVICE(pic), 16 + 14), + qdev_get_gpio_in(DEVICE(pic), 16 + 18)); + + } else if (nd_table[1].used) { + qemu_check_nic_model(&nd_table[1], "eTSEC"); + + dev = etsec_create(0x25000, + sysbus_mmio_get_region(ccsr, 0), + &nd_table[1], + sysbus_get_connected_irq(pic, 16 + 19), + sysbus_get_connected_irq(pic, 16 + 20), + sysbus_get_connected_irq(pic, 16 + 23)); + } + + /* VPD EEPROM */ + dev = qdev_create(i2c, "at24c-eeprom"); + object_property_add_child(qdev_get_machine(), "vpd", OBJECT(dev), + &error_fatal); + qdev_prop_set_uint8(dev, "address", 0xa8 >> 1); + qdev_prop_set_uint32(dev, "rom-size", 8192 * 8); + + drvinfo = drive_get(IF_PFLASH, 0, 0); + if (drvinfo) { + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(drvinfo), + &error_fatal); + } + + qdev_init_nofail(dev); + + { + char *buf; + + buf = g_malloc0(8192 * 8); + + build_vpd(info, buf, 8192 * 8, machine->kernel_cmdline); + + fw_cfg_add_file(fwinfo, "tomload/vpd", buf, 8192 * 8); + } + + /* DS1375 RTC */ + dev = qdev_create(i2c, "ds1375"); + object_property_add_child(qdev_get_machine(), "rtc", OBJECT(dev), + &error_fatal); + qdev_prop_set_uint8(dev, "address", 0xd0 >> 1); + qdev_init_nofail(dev); + + /* TODO: unmodeled i2c devices. + * 0x90 - ds1621 temperature sensor + * 0xa0 - 256*8 byte DDR SPD (???) + * 0xa4 - 64k*8 byte eeprom for "user" configuration + * 0xa6 - 64k*8 byte eeprom for "user" configuration + * 0xaa - 8k*8 byte eeprom for VPD of rear expansion card + */ + + if (!bios_name) { + bios_name = "tomload.bin"; + } + + if (!qtest_enabled()) { + MemoryRegion *rom = g_malloc0(sizeof(*rom)); + char *fullname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + + if (!fullname) { + fprintf(stderr, "qemu: could not find bios file '%s'\n", + bios_name); + exit(1); + } + + memory_region_init_ram(rom, OBJECT(cpld), "rom", + 0x800000, &error_fatal); + + memory_region_add_subregion(get_system_memory(), + 0xff800000, rom); + + /* BIOS == image in rom (last 8MB of address space). + * Execution starts with the final word 0xfffffffc + */ + int bsize = get_image_size(fullname); + if (bsize != 8 * 1024 * 1024 || + -1 == load_image_targphys(fullname, + 0xff800000, 8 * 1024 * 1024)) + { + fprintf(stderr, "qemu: could not load bios file '%s'" + " (%u bytes, requires 8MB)\n", + fullname, (unsigned)bsize); + exit(1); + } + + memory_region_set_readonly(rom, true); + + g_free(fullname); + } + + { + hwaddr image_addr = mvme3100->load_address; + + int image_size = load_image_targphys(machine->kernel_filename, + image_addr, 0x01000000); + if (machine->kernel_filename && + -1 == image_size) + { + fprintf(stderr, "qemu: could not load file '%s'\n", + machine->kernel_filename); + exit(1); + + } else if (mvme3100->entry_address == 0) { + mvme3100->entry_address = image_addr; + + } else if (mvme3100->entry_address < image_addr + || mvme3100->entry_address >= image_addr + image_size) + { + fprintf(stderr, "qemu: entry-address out of range\n"); + exit(1); + } + + if (machine->kernel_cmdline) { + fw_cfg_add_i32(fwinfo, FW_CFG_CMDLINE_SIZE, + strlen(machine->kernel_cmdline) + 1); + fw_cfg_add_string(fwinfo, FW_CFG_CMDLINE_DATA, + machine->kernel_cmdline); + } + + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_ADDR, image_addr); + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_ENTRY, mvme3100->entry_address); + fw_cfg_add_i32(fwinfo, FW_CFG_KERNEL_SIZE, image_size); + } +} + +static void mvme3100_inst_init(Object *obj) +{ + MVME3100State *mvme3100 = MVME3100(obj); + mvme3100->load_address = 0x10000; + mvme3100->entry_address = 0; +} + +static void mvme3100_visit_addr(Object *obj, + Visitor *v, + const char *name, + void *opaque, + Error **errp) +{ + MVME3100State *mvme3100 = MVME3100(obj); + uint32_t *ptr; + + if (strcmp(name, "load-address") == 0) { + ptr = &mvme3100->load_address; + } else if (strcmp(name, "entry-address") == 0) { + ptr = &mvme3100->entry_address; + } else { + fprintf(stderr, "logic error: mvme3100 has no prop '%s'\n", name); + exit(1); + } + + visit_type_uint32(v, name, ptr, errp); +} + +static void ppce500_machine_class_init(ObjectClass *klass, void *raw) +{ + mvme3100_info *info = raw; + MachineClass *mc = MACHINE_CLASS(klass); + MVME3100Class *m3c = MVME3100_CLASS(klass); + + m3c->info = info; + + mc->desc = info->desc; + mc->init = mvme3100_init; + mc->max_cpus = 1; + mc->default_ram_size = info->ram_size; + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("mpc8540_v21"); + + object_class_property_add(OBJECT_CLASS(mc), "load-address", "uint32", + &mvme3100_visit_addr, &mvme3100_visit_addr, NULL, + NULL, &error_fatal); + object_class_property_add(OBJECT_CLASS(mc), "entry-address", "uint32", + &mvme3100_visit_addr, &mvme3100_visit_addr, NULL, + NULL, &error_fatal); +} + +static const TypeInfo mvme3100_type = { + .abstract = true, + .name = TYPE_MVME3100, + .parent = TYPE_MACHINE, + .instance_size = sizeof(MVME3100State), + .instance_init = mvme3100_inst_init, + .class_size = sizeof(MVME3100Class), +}; + +static mvme3100_info mvme3100_1152 = { + .desc = "MVME3100-1152", + .cpu_freq = 666666666u, + /* CCB/PCI -> 5/1 + * core/CCB -> 2/1 + * + * plat ratio = 5 -> 5:1 CCB:PCI + * e500 ratio = 4 -> 4:1 e500:CCB + */ + .porpllsr = 0x0004000a, + .ram_size = 256 * (1 << 20), +}; + +static const TypeInfo mvme3100_1152_type = { + .name = MACHINE_TYPE_NAME("mvme3100-1152"), + .parent = TYPE_MVME3100, + .class_init = ppce500_machine_class_init, + .class_data = &mvme3100_1152, +}; + +static mvme3100_info mvme3100_1263 = { + .desc = "MVME3100-1263", + .cpu_freq = 833333333u, + /* CCB/PCI -> 5/1 + * core/CCB -> 5/2 + */ + .porpllsr = 0x0005000a, + .ram_size = 512 * (1 << 20), +}; + +static const TypeInfo mvme3100_1263_type = { + .name = MACHINE_TYPE_NAME("mvme3100-1263"), + .parent = TYPE_MVME3100, + .class_init = ppce500_machine_class_init, + .class_data = &mvme3100_1263, +}; + +static void mvme3100_machine_init(void) +{ + type_register_static(&mvme3100_type); + type_register_static(&mvme3100_1152_type); + type_register_static(&mvme3100_1263_type); +} + +type_init(mvme3100_machine_init) diff --git a/hw/ppc/mvme3100_cpld.c b/hw/ppc/mvme3100_cpld.c new file mode 100644 index 0000000000..41024566ce --- /dev/null +++ b/hw/ppc/mvme3100_cpld.c @@ -0,0 +1,192 @@ +/* + * MVME3100 board CPLD (local logic) + * + * Copyright (c) 2015 Michael Davidsaver + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the LICENSE file in the top-level directory. + * + * This model was developed according to the + * MVME3100 Single Board Computer Programmer's Reference + * P/N: 6806800G37B + * July 2014 + * + * And validated against the RTEMS 4.9.6 mvme3100 BSP + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "exec/address-spaces.h" +#include "qemu-common.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" + +/* #define DEBUG_3100CPLD */ + +#define TYPE_CPLD "mvme3100-cpld" + +#define CPLD(obj) OBJECT_CHECK(MVMECPLD, (obj), TYPE_CPLD) + +#ifdef DEBUG_3100CPLD +#define DPRINTK(FMT, ...) printf(TYPE_CPLD " : " FMT, ## __VA_ARGS__) +#else +#define DPRINTK(FMT, ...) do {} while (0) +#endif + +#define LOG(MSK, FMT, ...) qemu_log_mask(MSK, TYPE_CPLD " : " FMT, \ + ## __VA_ARGS__) + +#define CPLD_SIZE 0x20 + +typedef struct { + SysBusDevice parent_obj; + + uint8_t mem[0x10]; + uint32_t test; + + MemoryRegion mmio; +} MVMECPLD; + +static +uint64_t cpld_read(void *opaque, hwaddr addr, unsigned size) +{ + MVMECPLD *self = opaque; + uint32_t offset = addr; + uint32_t val, A; + + switch (offset) { + case 1 ... 0xf: + val = 0; + A = offset; + while (size--) { + val <<= 8; + val |= self->mem[A++]; + } + break; + case 0x10: + val = self->test; + break; + case 0x14: + val = ~self->test; + break; + default: + LOG(LOG_UNIMP, "read from unimplimented register %08x\n", + (unsigned)offset); + val = 0; + } + + DPRINTK("read %08x -> %08x\n", (unsigned)offset, (unsigned)val); + + return val; +} + +static +void cpld_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + MVMECPLD *self = opaque; + uint32_t offset = addr; + + DPRINTK("write %08x <- %08x\n", (unsigned)offset, (unsigned)val); + + switch (offset) { + case 0: + break; + case 1: + /* TODO: TSTAT_MASK and EEPROM_WPEEPROM */ + if ((val & 0xe0) == 0xa0) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } + self->mem[offset >> 2] = val & 0x3; + break; + case 2: + self->mem[offset >> 2] = val & 0xf; + break; + case 3: + self->mem[offset >> 2] = val & 0x18; + break; + case 4 ... 9: + break; + case 10 ... 13: + /* TODO: allow date to be changed? */ + break; + case 0x10: + self->test = val; + break; + case 0x11: + self->test = ~val; + break; + default: + LOG(LOG_UNIMP, "write to unimplimented register %08x\n", + (unsigned)offset); + break; + } +} + +static const MemoryRegionOps cpld_ops = { + .read = cpld_read, + .write = cpld_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; +static +void mvme3100_cpld_realize(DeviceState *dev, Error **errp) +{ + MVMECPLD *self = CPLD(dev); + + memory_region_init_io(&self->mmio, OBJECT(self), &cpld_ops, self, + TYPE_CPLD, CPLD_SIZE); + + sysbus_init_mmio(&self->parent_obj, &self->mmio); +} + +static Property mvme3100_cpld_props[] = { + DEFINE_PROP_END_OF_LIST() +}; + +static +void mvme3100_cpld_reset(DeviceState *dev) +{ + MVMECPLD *self = CPLD(dev); + + self->mem[0] = 0; /* Type VME SBC, SAFE_START==0 */ + self->mem[1] = 3; + self->mem[2] = 1; + self->mem[3] = 9; + self->mem[4] = 9; + self->mem[5] = 0xa9; + self->mem[6] = 1; + self->mem[7] = 0xe0; /* TODO, TSEC phy irq status */ + self->mem[8] = 1; /* TODO: PMC presence ...? */ + self->mem[9] = 1; /* TODO: real rev. # */ + self->mem[10] = 15; /* TODO: real date code */ + self->mem[11] = 11; + self->mem[12] = 14; + self->mem[13] = 1; + self->test = 0; +} + +static +void mvme3100_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = &mvme3100_cpld_realize; + dc->reset = &mvme3100_cpld_reset; + dc->desc = "mvme3100 CPLD logic"; + dc->props = mvme3100_cpld_props; +} + +static const TypeInfo mvme3100_cpld_info = { + .name = TYPE_CPLD, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MVMECPLD), + .class_size = sizeof(SysBusDeviceClass), + .class_init = mvme3100_class_init, +}; + +static +void mvme3100_cpld_register(void) +{ + type_register_static(&mvme3100_cpld_info); +} + +type_init(mvme3100_cpld_register) From patchwork Mon Nov 20 03:24:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 839404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="X52f05ZQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygDnp6KGlz9s7M for ; Mon, 20 Nov 2017 14:33:18 +1100 (AEDT) Received: from localhost ([::1]:55241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGcph-0007rD-0r for incoming@patchwork.ozlabs.org; Sun, 19 Nov 2017 22:33:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGchj-0001rx-Ok for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:25:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGchg-0006a4-Kq for qemu-devel@nongnu.org; Sun, 19 Nov 2017 22:25:03 -0500 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]:42757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eGche-0006Xi-5f; Sun, 19 Nov 2017 22:24:58 -0500 Received: by mail-io0-x242.google.com with SMTP id u42so14308230ioi.9; Sun, 19 Nov 2017 19:24:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4dZp8lHWlpNCTEQZ9tT4sRvjuDMrX2abFCZm1Yvlqz8=; b=X52f05ZQw0Xs3fDiV6t3asiQ5DWRPJyBEriZXJTgaG7rBpuosw55ll8N6+pKAuwDxk hysDKE+7K3gVDBtsGljdf7UZe5ufLUKLtFn6Ye3gcIhfVx+ow33toqzA70Bb7+MUWXP4 jN/GSxit8eQiGPsqpefRVvbQR9FucHA3G+7/v0UaGbhJNq5T2CG9k+PXwfvnIVVRP3d3 f2YugQMy45CJuwZY0iPH8tdv9icLSRqdBi4f7ziC85j3UmZ7fj5ru58NdpJxnyQfmpc8 X4TvVV6SL6KVvKajVOPYh95Vsqj9P9sRQOraN8f1EomitvnXOnChbqqKMv/4O948uhuu iftA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4dZp8lHWlpNCTEQZ9tT4sRvjuDMrX2abFCZm1Yvlqz8=; b=a9/oF0a7QTF/r4JeGy45L+gj0iR7U500XeYlQ8XQo0aeluPVs9YZ2+b5UGnSKRoij/ aGekmSdbxqZE734JDOA8DRrAqast4ur9JlIH5ngzJfcRVAw38znRTDQq7mxKgP0D0Vx3 Gz0q6T5KNuEB9D7iz7RLsF75tdh12SHUPdrL6vBLfGQubJPvhdxEv8SwpGX+58jf5S4Y 7miWqo6CdsjCyc22FdEBRRuL30gj4o/I8ajLT/Di5SpR2eUrskoYJNL4sBNPYPwK47eM 2+3a0FAx/GH1h7c3tf3mPt/RBHJFKA5ryIHqHsGmzQPbYwaWId8/tU4SQzUSqA66mA20 gd4w== X-Gm-Message-State: AJaThX4CuodPZvXSYkG7iKFxjzxe2mpXg8iBdI0n9aDQdW3SD09eAw4b vCAI1anOzfcM1vstcXyDEqUxoQ== X-Google-Smtp-Source: AGs4zMb64e1bCJsq1Nbc7Y9wkTzazpEbgs1IJ3XgOn9eMDQbkYWGQKfCfJs9kpH6oBb4nvoP9aIEtw== X-Received: by 10.107.139.12 with SMTP id n12mr12681869iod.1.1511148297595; Sun, 19 Nov 2017 19:24:57 -0800 (PST) Received: from localhost.localdomain (173-29-146-33.client.mchsi.com. [173.29.146.33]) by smtp.gmail.com with ESMTPSA id o207sm4476119itc.27.2017.11.19.19.24.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Nov 2017 19:24:56 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson , qemu-ppc@nongnu.org Date: Sun, 19 Nov 2017 21:24:20 -0600 Message-Id: <20171120032420.9134-13-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171120032420.9134-1-mdavidsaver@gmail.com> References: <20171120032420.9134-1-mdavidsaver@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::242 Subject: [Qemu-devel] [PATCH 12/12] tests: add mvme3100-test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Exercise some features of the mvme3100 CPLD logic and read from the eeprom w/ VPD. Signed-off-by: Michael Davidsaver --- tests/Makefile.include | 3 ++ tests/mvme3100-test.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 tests/mvme3100-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index ad1c219423..7ea041a885 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -372,6 +372,8 @@ check-qtest-s390x-y += tests/virtio-balloon-test$(EXESUF) check-qtest-s390x-y += tests/virtio-console-test$(EXESUF) check-qtest-s390x-y += tests/virtio-serial-test$(EXESUF) +check-qtest-ppc-$(CONFIG_E500) += tests/mvme3100-test$(EXESUF) + check-qtest-generic-y += tests/qom-test$(EXESUF) check-qtest-generic-y += tests/test-hmp$(EXESUF) @@ -781,6 +783,7 @@ tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o tests/ac97-test$(EXESUF): tests/ac97-test.o tests/es1370-test$(EXESUF): tests/es1370-test.o tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/mvme3100-test$(EXESUF): tests/mvme3100-test.o $(libqos-e500-obj-y) tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y) tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y) diff --git a/tests/mvme3100-test.c b/tests/mvme3100-test.c new file mode 100644 index 0000000000..6dde8d1d29 --- /dev/null +++ b/tests/mvme3100-test.c @@ -0,0 +1,79 @@ +#include + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqos/libqos.h" +#include "libqos/i2c.h" + +#define assert_equal(A, B) g_assert_cmphex((A), ==, (B)) + +static +I2CAdapter *i2c; + +static +void test_ccsr(void) +{ + /* CCSRBAR is self referential */ + assert_equal(readl(0xff700000), 0x000ff700); + + /* introspect memory size */ + assert_equal(readl(0xff702080), 0x80000000); + /* value is (ram_size-1)>>24 */ + assert_equal(readl(0xff702000), 15); +} + +static +void test_cpld(void) +{ + /* read/write to test register */ + assert_equal(readl(0xe2000010), 0x00000000); + assert_equal(readl(0xe2000014), 0xffffffff); + + writel(0xe2000010, 0x12345678); + + assert_equal(readl(0xe2000010), 0x12345678); + assert_equal(readl(0xe2000014), 0x12345678 ^ 0xffffffff); +} + +static +void test_eeprom(void) +{ + char buf[] = "\x00\x00MOTOROLA"; + + /* 1. zero address pointer + * 2. write 8 bytes, + * 3. re-zero address pointer + */ + i2c_send(i2c, 0xa8, (uint8_t *)buf, 10); + i2c_send(i2c, 0xa8, (uint8_t *)buf, 2); + + /* read 8 bytes */ + i2c_recv(i2c, 0xa8, (uint8_t *)buf, 8); + buf[8] = '\0'; + + /* Read header for Motorola VPD info */ + g_assert_cmpstr(buf, ==, "MOTOROLA"); +} + +int main(int argc, char *argv[]) +{ + int ret; + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mvme3100-1152"); + + i2c = e500_i2c_create(0xff700000); + + qtest_add_func("/mvme3100/ccsr", test_ccsr); + qtest_add_func("/mvme3100/cpld", test_cpld); + qtest_add_func("/mvme3100/eeprom", test_eeprom); + + ret = g_test_run(); + + printf("Tests done\n"); + + qtest_end(); + printf("Tests end\n"); + + return ret; +}