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Thu, 14 Nov 2019 19:13:18 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][1/5x]: MVE store intrinsics. Date: Thu, 14 Nov 2019 19:13:18 +0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:20;OLM:20; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:DBBPR08MB4807; H:DBBPR08MB4775.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: AkvURI1d7eShzEGXz5t2AS8RKQTMtAWCqslIoNnmm5jjIRQzmfHFMXBovRjqtjS4u6zIqCysP3qT/HnwwWBnd2WszvZ1JuJQs3GX/1bKNkUpTkFyTWce8CttLZEnQbSCvRtCXbN4e8X9aUtJvhj+DHREeYzTJ+Cj3SQNGjw1appCz6hYn7N4pFQ7x0UebdsYrVULtMtQm3xoqg1dtGSXSz6xby+Py68DAWaDk+yZAsw3uwT+jmpQrDK6uscQL3U/dDH/dHNnlPhDZAyHIFqybicx/jVJOwOjSWvI/46W58aEYTyvTG1JsaI0QTXcjHwxT/CDPSjINPWuYWOe9Mm+pMVEr1gFTuBWBTiznWU5nSwB22gqImErIPhIW/J6yDIMcES/EB/x4hZR00qO8oafVf/5P8REaUlz82NIQhNIxAhhOmhwkaMWwfAmAwcCxrd5FrKN2fSYt//0xWLH+ujR5/r01+vKPhF8M7gTRlcBCCA= MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT027.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 8cd5fdd0-7ad3-4132-f33d-08d76936b4d3 X-IsSubscribed: yes Hello, This patch supports the following MVE ACLE store intrinsics. vstrbq_scatter_offset_s8, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_u8, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u16, vstrbq_s8, vstrbq_s32, vstrbq_s16, vstrbq_u8, vstrbq_u32, vstrbq_u16, vstrwq_scatter_base_s32, vstrwq_scatter_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_s8): Define macro. (vstrbq_u8): Likewise. (vstrbq_u16): Likewise. (vstrbq_scatter_offset_s8): Likewise. (vstrbq_scatter_offset_u8): Likewise. (vstrbq_scatter_offset_u16): Likewise. (vstrbq_s16): Likewise. (vstrbq_u32): Likewise. (vstrbq_scatter_offset_s16): Likewise. (vstrbq_scatter_offset_u32): Likewise. (vstrbq_s32): Likewise. (vstrbq_scatter_offset_s32): Likewise. (vstrwq_scatter_base_s32): Likewise. (vstrwq_scatter_base_u32): Likewise. (__arm_vstrbq_scatter_offset_s8): Define intrinsic. (__arm_vstrbq_scatter_offset_s32): Likewise. (__arm_vstrbq_scatter_offset_s16): Likewise. (__arm_vstrbq_scatter_offset_u8): Likewise. (__arm_vstrbq_scatter_offset_u32): Likewise. (__arm_vstrbq_scatter_offset_u16): Likewise. (__arm_vstrbq_s8): Likewise. (__arm_vstrbq_s32): Likewise. (__arm_vstrbq_s16): Likewise. (__arm_vstrbq_u8): Likewise. (__arm_vstrbq_u32): Likewise. (__arm_vstrbq_u16): Likewise. (__arm_vstrwq_scatter_base_s32): Likewise. (__arm_vstrwq_scatter_base_u32): Likewise. (vstrbq): Define polymorphic variant. (vstrbq_scatter_offset): Likewise. (vstrwq_scatter_base): Likewise. * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. (VSTRWSBQ): Define iterators. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (mve_vstrbq_): Define RTL pattern. (mve_vstrbq_scatter_offset_): Likewise. (mve_vstrwq_scatter_base_v4si): Likewise. gcc/testsuite/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 6dffb36fe179357c62cb4f35d486513971e3487d..ec88199bb5e7e9c15a346061c70841f3086004ef 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -555,6 +555,39 @@ arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ (arm_quadop_unone_unone_unone_none_unone_qualifiers) +static enum arm_type_qualifiers +arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_none }; +#define STRS_QUALIFIERS (arm_strs_qualifiers) + +static enum arm_type_qualifiers +arm_stru_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned }; +#define STRU_QUALIFIERS (arm_stru_qualifiers) + +static enum arm_type_qualifiers +arm_strss_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_none}; +#define STRSS_QUALIFIERS (arm_strss_qualifiers) + +static enum arm_type_qualifiers +arm_strsu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define STRSU_QUALIFIERS (arm_strsu_qualifiers) + +static enum arm_type_qualifiers +arm_strsbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, qualifier_none}; +#define STRSBS_QUALIFIERS (arm_strsbs_qualifiers) + +static enum arm_type_qualifiers +arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 896410a843716376b576016a07bc9ece41f63e7d..3d64033dd23636b041cbd6ecb3eb18c3b9db3aed 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1702,6 +1702,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsubq_m_f16(__inactive, __a, __b, __p) __arm_vsubq_m_f16(__inactive, __a, __b, __p) #define vsubq_m_n_f32(__inactive, __a, __b, __p) __arm_vsubq_m_n_f32(__inactive, __a, __b, __p) #define vsubq_m_n_f16(__inactive, __a, __b, __p) __arm_vsubq_m_n_f16(__inactive, __a, __b, __p) +#define vstrbq_s8( __addr, __value) __arm_vstrbq_s8( __addr, __value) +#define vstrbq_u8( __addr, __value) __arm_vstrbq_u8( __addr, __value) +#define vstrbq_u16( __addr, __value) __arm_vstrbq_u16( __addr, __value) +#define vstrbq_scatter_offset_s8( __base, __offset, __value) __arm_vstrbq_scatter_offset_s8( __base, __offset, __value) +#define vstrbq_scatter_offset_u8( __base, __offset, __value) __arm_vstrbq_scatter_offset_u8( __base, __offset, __value) +#define vstrbq_scatter_offset_u16( __base, __offset, __value) __arm_vstrbq_scatter_offset_u16( __base, __offset, __value) +#define vstrbq_s16( __addr, __value) __arm_vstrbq_s16( __addr, __value) +#define vstrbq_u32( __addr, __value) __arm_vstrbq_u32( __addr, __value) +#define vstrbq_scatter_offset_s16( __base, __offset, __value) __arm_vstrbq_scatter_offset_s16( __base, __offset, __value) +#define vstrbq_scatter_offset_u32( __base, __offset, __value) __arm_vstrbq_scatter_offset_u32( __base, __offset, __value) +#define vstrbq_s32( __addr, __value) __arm_vstrbq_s32( __addr, __value) +#define vstrbq_scatter_offset_s32( __base, __offset, __value) __arm_vstrbq_scatter_offset_s32( __base, __offset, __value) +#define vstrwq_scatter_base_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_s32(__addr, __offset, __value) +#define vstrwq_scatter_base_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_u32(__addr, __offset, __value) #endif __extension__ extern __inline void @@ -10995,6 +11009,103 @@ __arm_vshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred return __builtin_mve_vshrntq_m_n_uv8hi (__a, __b, __imm, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s8 (int8_t * __base, uint8x16_t __offset, int8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s32 (int8_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s16 (int8_t * __base, uint16x8_t __offset, int16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u8 (uint8_t * __base, uint8x16_t __offset, uint8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u32 (uint8_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u16 (uint8_t * __base, uint16x8_t __offset, uint16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s8 (int8_t * __addr, int8x16_t __value) +{ + __builtin_mve_vstrbq_sv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s32 (int8_t * __addr, int32x4_t __value) +{ + __builtin_mve_vstrbq_sv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s16 (int8_t * __addr, int16x8_t __value) +{ + __builtin_mve_vstrbq_sv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u8 (uint8_t * __addr, uint8x16_t __value) +{ + __builtin_mve_vstrbq_uv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u32 (uint8_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vstrbq_uv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u16 (uint8_t * __addr, uint16x8_t __value) +{ + __builtin_mve_vstrbq_uv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_s32 (uint32x4_t __addr, const int __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_sv4si (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_u32 (uint32x4_t __addr, const int __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -17542,6 +17653,35 @@ extern void *__ARM_undef; #define vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) #define __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p_s32(p0,p1,p2,p3) +#define vstrbq(p0,p1) __arm_vstrbq(p0,p1) +#define __arm_vstrbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrbq_scatter_offset(p0,p1,p2) __arm_vstrbq_scatter_offset(p0,p1,p2) +#define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_base(p0,p1,p2) __arm_vstrwq_scatter_base(p0,p1,p2) +#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index a18b9b3f433ead3c5d9e73afa3c2d94ae87765f7..149c4115b6167e3f2f0eb43fbdeaa8708ba5d723 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -685,3 +685,9 @@ VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) +VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si) +VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si) +VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) +VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si) +VAR1 (STRSBS, vstrwq_scatter_base_s, v4si) +VAR1 (STRSBU, vstrwq_scatter_base_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 741c1e84e7d2379d22cf6239649019453b037bc2..eb365166e934f32f7695e5354258151202f378c0 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -191,7 +191,8 @@ VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F - VMINNMQ_M_F VSUBQ_M_F]) + VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -342,7 +343,9 @@ (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") - (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")]) + (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") + (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -359,6 +362,7 @@ (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) +(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -562,6 +566,9 @@ (define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) +(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) +(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) +(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w") @@ -7933,3 +7940,65 @@ "vpst\;vsubt.f%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) + +;; +;; [vstrbq_s vstrbq_u] +;; +(define_insn "mve_vstrbq_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w")] + VSTRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn("vstrb.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] +;; +(define_insn "mve_vstrbq_scatter_offset_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VSTRBSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrb.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] +;; +(define_insn "mve_vstrwq_scatter_base_v4si" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSTRWSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..7c34f7f3b8e22bdc6e64f52fa306833d339c42e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int16x8_t value) +{ + vstrbq_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * addr, int16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..a0925529e7c2066d034b20519cea660e159fc4d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int32x4_t value) +{ + vstrbq_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * addr, int32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..d56e6c208c07eec84353c080f2cd209a17451736 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value) +{ + vstrbq_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..aacf7fc87de328013a3597bd554a821738d404a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset_s16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..ef8a9b1aa97311a9e9ef3d61f8aa130652e1f354 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..ee5ec04693a7166e5d498fcbca22db88d093485e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset_s8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..f73cf9ec0590e86da71981c5febff14d13fab6ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset_u16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..b305b1c42244c844b15972695ad81da4c992d90d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..cf0c267d8f9939d8f12122ece12166e102898dc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset_u8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..4cdf967aa68e035ec428bb2d1b4857d3599a3d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint16x8_t value) +{ + vstrbq_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * addr, uint16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..c64ed808289f6a17968014b284909e2e72ece8fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint32x4_t value) +{ + vstrbq_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * addr, uint32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..94d14a4fb71cec8fdb07438be1a1d1fc29e55198 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value) +{ + vstrbq_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..d107819f7dfcec71471d67eabbcf32b425f426dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base_s32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..148516f57fb115ea5bd0dbb5c5bee4fe3b8d02e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base_u32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 6dffb36fe179357c62cb4f35d486513971e3487d..ec88199bb5e7e9c15a346061c70841f3086004ef 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -555,6 +555,39 @@ arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ (arm_quadop_unone_unone_unone_none_unone_qualifiers) +static enum arm_type_qualifiers +arm_strs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_none }; +#define STRS_QUALIFIERS (arm_strs_qualifiers) + +static enum arm_type_qualifiers +arm_stru_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned }; +#define STRU_QUALIFIERS (arm_stru_qualifiers) + +static enum arm_type_qualifiers +arm_strss_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_none}; +#define STRSS_QUALIFIERS (arm_strss_qualifiers) + +static enum arm_type_qualifiers +arm_strsu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer, qualifier_unsigned, + qualifier_unsigned}; +#define STRSU_QUALIFIERS (arm_strsu_qualifiers) + +static enum arm_type_qualifiers +arm_strsbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, qualifier_none}; +#define STRSBS_QUALIFIERS (arm_strsbs_qualifiers) + +static enum arm_type_qualifiers +arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned}; +#define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 896410a843716376b576016a07bc9ece41f63e7d..3d64033dd23636b041cbd6ecb3eb18c3b9db3aed 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1702,6 +1702,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vsubq_m_f16(__inactive, __a, __b, __p) __arm_vsubq_m_f16(__inactive, __a, __b, __p) #define vsubq_m_n_f32(__inactive, __a, __b, __p) __arm_vsubq_m_n_f32(__inactive, __a, __b, __p) #define vsubq_m_n_f16(__inactive, __a, __b, __p) __arm_vsubq_m_n_f16(__inactive, __a, __b, __p) +#define vstrbq_s8( __addr, __value) __arm_vstrbq_s8( __addr, __value) +#define vstrbq_u8( __addr, __value) __arm_vstrbq_u8( __addr, __value) +#define vstrbq_u16( __addr, __value) __arm_vstrbq_u16( __addr, __value) +#define vstrbq_scatter_offset_s8( __base, __offset, __value) __arm_vstrbq_scatter_offset_s8( __base, __offset, __value) +#define vstrbq_scatter_offset_u8( __base, __offset, __value) __arm_vstrbq_scatter_offset_u8( __base, __offset, __value) +#define vstrbq_scatter_offset_u16( __base, __offset, __value) __arm_vstrbq_scatter_offset_u16( __base, __offset, __value) +#define vstrbq_s16( __addr, __value) __arm_vstrbq_s16( __addr, __value) +#define vstrbq_u32( __addr, __value) __arm_vstrbq_u32( __addr, __value) +#define vstrbq_scatter_offset_s16( __base, __offset, __value) __arm_vstrbq_scatter_offset_s16( __base, __offset, __value) +#define vstrbq_scatter_offset_u32( __base, __offset, __value) __arm_vstrbq_scatter_offset_u32( __base, __offset, __value) +#define vstrbq_s32( __addr, __value) __arm_vstrbq_s32( __addr, __value) +#define vstrbq_scatter_offset_s32( __base, __offset, __value) __arm_vstrbq_scatter_offset_s32( __base, __offset, __value) +#define vstrwq_scatter_base_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_s32(__addr, __offset, __value) +#define vstrwq_scatter_base_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_u32(__addr, __offset, __value) #endif __extension__ extern __inline void @@ -10995,6 +11009,103 @@ __arm_vshrntq_m_n_u16 (uint8x16_t __a, uint16x8_t __b, const int __imm, mve_pred return __builtin_mve_vshrntq_m_n_uv8hi (__a, __b, __imm, __p); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s8 (int8_t * __base, uint8x16_t __offset, int8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s32 (int8_t * __base, uint32x4_t __offset, int32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_s16 (int8_t * __base, uint16x8_t __offset, int16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_sv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u8 (uint8_t * __base, uint8x16_t __offset, uint8x16_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv16qi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u32 (uint8_t * __base, uint32x4_t __offset, uint32x4_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv4si ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_scatter_offset_u16 (uint8_t * __base, uint16x8_t __offset, uint16x8_t __value) +{ + __builtin_mve_vstrbq_scatter_offset_uv8hi ((__builtin_neon_qi *) __base, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s8 (int8_t * __addr, int8x16_t __value) +{ + __builtin_mve_vstrbq_sv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s32 (int8_t * __addr, int32x4_t __value) +{ + __builtin_mve_vstrbq_sv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_s16 (int8_t * __addr, int16x8_t __value) +{ + __builtin_mve_vstrbq_sv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u8 (uint8_t * __addr, uint8x16_t __value) +{ + __builtin_mve_vstrbq_uv16qi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u32 (uint8_t * __addr, uint32x4_t __value) +{ + __builtin_mve_vstrbq_uv4si ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrbq_u16 (uint8_t * __addr, uint16x8_t __value) +{ + __builtin_mve_vstrbq_uv8hi ((__builtin_neon_qi *) __addr, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_s32 (uint32x4_t __addr, const int __offset, int32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_sv4si (__addr, __offset, __value); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vstrwq_scatter_base_u32 (uint32x4_t __addr, const int __offset, uint32x4_t __value) +{ + __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); +} #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -17542,6 +17653,35 @@ extern void *__ARM_undef; #define vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) #define __arm_vrmlsldavhaxq_p(p0,p1,p2,p3) __arm_vrmlsldavhaxq_p_s32(p0,p1,p2,p3) +#define vstrbq(p0,p1) __arm_vstrbq(p0,p1) +#define __arm_vstrbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vstrbq_scatter_offset(p0,p1,p2) __arm_vstrbq_scatter_offset(p0,p1,p2) +#define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));}) + +#define vstrwq_scatter_base(p0,p1,p2) __arm_vstrwq_scatter_base(p0,p1,p2) +#define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0, p1, __ARM_mve_coerce(__p2, uint32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index a18b9b3f433ead3c5d9e73afa3c2d94ae87765f7..149c4115b6167e3f2f0eb43fbdeaa8708ba5d723 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -685,3 +685,9 @@ VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vandq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_n_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vaddq_m_f, v8hf, v4sf) VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vabdq_m_f, v8hf, v4sf) +VAR3 (STRS, vstrbq_s, v16qi, v8hi, v4si) +VAR3 (STRU, vstrbq_u, v16qi, v8hi, v4si) +VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) +VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si) +VAR1 (STRSBS, vstrwq_scatter_base_s, v4si) +VAR1 (STRSBU, vstrwq_scatter_base_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 741c1e84e7d2379d22cf6239649019453b037bc2..eb365166e934f32f7695e5354258151202f378c0 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -191,7 +191,8 @@ VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F - VMINNMQ_M_F VSUBQ_M_F]) + VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -342,7 +343,9 @@ (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u") (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") - (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")]) + (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") + (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -359,6 +362,7 @@ (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) +(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -562,6 +566,9 @@ (define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S]) (define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U]) (define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U]) +(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) +(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) +(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w") @@ -7933,3 +7940,65 @@ "vpst\;vsubt.f%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) + +;; +;; [vstrbq_s vstrbq_u] +;; +(define_insn "mve_vstrbq_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w")] + VSTRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno = REGNO (operands[1]); + ops[1] = gen_rtx_REG (TImode, regno); + ops[0] = operands[0]; + output_asm_insn("vstrb.\t%q1, %E0",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] +;; +(define_insn "mve_vstrbq_scatter_offset_" + [(set (match_operand: 0 "memory_operand" "=Us") + (unspec: + [(match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VSTRBSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrb.\t%q2, [%m0, %q1]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] +;; +(define_insn "mve_vstrwq_scatter_base_v4si" + [(set (mem:BLK (scratch)) + (unspec:BLK + [(match_operand:V4SI 0 "s_register_operand" "w") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:V4SI 2 "s_register_operand" "w")] + VSTRWSBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] = operands[0]; + ops[1] = operands[1]; + ops[2] = operands[2]; + output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..7c34f7f3b8e22bdc6e64f52fa306833d339c42e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int16x8_t value) +{ + vstrbq_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * addr, int16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..a0925529e7c2066d034b20519cea660e159fc4d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int32x4_t value) +{ + vstrbq_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * addr, int32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..d56e6c208c07eec84353c080f2cd209a17451736 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16_t value) +{ + vstrbq_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * addr, int8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..aacf7fc87de328013a3597bd554a821738d404a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset_s16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (int8_t * base, uint16x8_t offset, int16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..ef8a9b1aa97311a9e9ef3d61f8aa130652e1f354 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset_s32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (int8_t * base, uint32x4_t offset, int32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..ee5ec04693a7166e5d498fcbca22db88d093485e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset_s8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (int8_t * base, uint8x16_t offset, int8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..f73cf9ec0590e86da71981c5febff14d13fab6ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset_u16 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..b305b1c42244c844b15972695ad81da4c992d90d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset_u32 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..cf0c267d8f9939d8f12122ece12166e102898dc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset_u8 (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value) +{ + vstrbq_scatter_offset (base, offset, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..4cdf967aa68e035ec428bb2d1b4857d3599a3d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint16x8_t value) +{ + vstrbq_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ + +void +foo1 (uint8_t * addr, uint16x8_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..c64ed808289f6a17968014b284909e2e72ece8fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint32x4_t value) +{ + vstrbq_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ + +void +foo1 (uint8_t * addr, uint32x4_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..94d14a4fb71cec8fdb07438be1a1d1fc29e55198 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16_t value) +{ + vstrbq_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16_t value) +{ + vstrbq (addr, value); +} + +/* { dg-final { scan-assembler "vstrb.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..d107819f7dfcec71471d67eabbcf32b425f426dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base_s32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, int32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..148516f57fb115ea5bd0dbb5c5bee4fe3b8d02e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +void +foo (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base_u32 (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */ + +void +foo1 (uint32x4_t addr, uint32x4_t value) +{ + vstrwq_scatter_base (addr, 8, value); +} + +/* { dg-final { scan-assembler "vstrw.u32" } } */