From patchwork Thu Nov 14 15:30:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513419-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="rNwf4rHn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47DQRb4H3Bz9sP4 for ; Fri, 15 Nov 2019 02:30:51 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=HBVechx0HRw1eZtigzaWtpWUQ7aoNGaocMwcsGcZAXpvM9Pbs+q0x KZ3e3884SNbh9GFmV6hCk/jzvetX5F/ZT/eU7EuzVY3H0rxLcV/rLkwh+g5DZrlg A7m++Pe5rcMKBk46hUgnod6YLzqdIVTpRPFnSOtJjlMg0+AMpxcYpc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; s=default; bh=kmohlZ6SpK1vvLYN5eA6kEAJCtk=; b=rNwf4rHnrIaJseja+APY+TbdUmb4 wISxVP48c9Yp0VIJP1hk1j8HKa+fPquSDuuy5cn8MoLFQj+fFXmiX687W/lw8mNR HmEYf3qhE7ujWCwB0DSDyKsBfa16+Dx0e11mO44ob2KnlEin7RBuK4ZCSWoiIHJT ZlEEKr5WosK1fNM= Received: (qmail 106683 invoked by alias); 14 Nov 2019 15:30:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 106528 invoked by uid 89); 14 Nov 2019 15:30:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=employ, H*f:sk:0b37b07, H*i:sk:0b37b07, H*MI:sk:0b37b07 X-HELO: esa1.mentor.iphmx.com Received: from esa1.mentor.iphmx.com (HELO esa1.mentor.iphmx.com) (68.232.129.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 15:30:24 +0000 IronPort-SDR: JGfxySgdNI1ewSAr1mMmvj7bxnY5fFL8j/uH/qFz31Hm0ZaG10QbnJ0YxwtDZEmzSrDyING1XN 9PnD81EZLqENkBVC/0upN8M0Ik8xdqgrRSFksqzcVyoRn8ZrJg2xNekfcpZyS+XO1p0jbjYKuM vthDwjV5pAo3IdCgUcuNS4rbDsxNkSrufYEc9lxd+ZKYOoJXjcll2kxG0rPqVBXQL8JsGyzKly /ELmlpMhNI+DsDq25A+NeKJIFF1w7XxbrLmFBZx7k/9L3rtTnk4A01x2Dghp18nJSUD76sFxDm ud8= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:30:22 -0800 IronPort-SDR: 3K727QKIiiNON6Hx9TarxHkShRAOGQWELESDbiq9dixg3pIQ+iJAm5JaHCVSh1k/C8I5Kwud4r Qoue5an45ieQ338VgF1CzWfJZDl2i79/dd/Ksex9DdnoyhDvFd6M1V81UrNiIE0hDrJsTBFcBP DvLeYHx48xFCYAO41JcOeSSjuO25W4sMqEqlmzYd+VXF9Z51joi6eGLCAx/zgWhKwPqsLIYyY1 qPsIOHFBJgt8TYgt3mZZiL/tZmzHIOLTrEi/lVivCdaFb5Dl5mkoZ6GgVsQHq73WXKAO1mqy1e u3Q= Subject: [PATCH 1/5] [amdgcn] Use first lane of v1 for zero constant From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: Date: Thu, 14 Nov 2019 15:30:03 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> GCN 5 has commonly-used global memory instructions that specify the address as [SGPR address] + [VGPR offset] + [constant offset], and we often want the VGPR offset to be zero, so v0 is currently reserved for that purpose. However, v1 contains [0, 1, 2..., 63], and as we only use the first lane of the VGPR for the offset (the instructions actually work on vectors of addresses, but we only employ them in single-lane mode for all memory accesses except for explicit scatter-gather instructions), v1 can be used in place of v0, freeing v0 for other purposes. Okay for trunk? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.c (gcn_expand_prologue): Remove initialization and prologue use of v0. (print_operand_address): Use v1 for zero vector offset. --- gcc/config/gcn/gcn.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) { @@ -5324,9 +5313,9 @@ print_operand_address (FILE *file, rtx mem) /* The assembler requires a 64-bit VGPR pair here, even though the offset should be only 32-bit. */ if (vgpr_offset == NULL_RTX) - /* In this case, the vector offset is zero, so we use v0, - which is initialized by the kernel prologue to zero. */ - fprintf (file, "v[0:1]"); + /* In this case, the vector offset is zero, so we use the first + lane of v1, which is initialized to zero. */ + fprintf (file, "v[1:2]"); else if (REG_P (vgpr_offset) && VGPR_REGNO_P (REGNO (vgpr_offset))) { diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 1a69737..2c08771 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2799,15 +2799,6 @@ gcn_expand_prologue () cfun->machine->args. reg[PRIVATE_SEGMENT_WAVE_OFFSET_ARG]); - if (TARGET_GCN5_PLUS) - { - /* v0 is reserved for constant zero so that "global" - memory instructions can have a nul-offset without - causing reloads. */ - emit_insn (gen_vec_duplicatev64si - (gen_rtx_REG (V64SImode, VGPR_REGNO (0)), const0_rtx)); - } - if (cfun->machine->args.requested & (1 << FLAT_SCRATCH_INIT_ARG)) { rtx fs_init_lo = @@ -2866,8 +2857,6 @@ gcn_expand_prologue () gen_int_mode (LDS_SIZE, SImode)); emit_insn (gen_prologue_use (gen_rtx_REG (SImode, M0_REG))); - if (TARGET_GCN5_PLUS) - emit_insn (gen_prologue_use (gen_rtx_REG (SImode, VGPR_REGNO (0)))); if (cfun && cfun->machine && !cfun->machine->normal_function && flag_openmp) From patchwork Thu Nov 14 15:30:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194928 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513421-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RgRN3DYa"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47DQS92sL2z9sP4 for ; Fri, 15 Nov 2019 02:31:21 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=cy9dxHh2V64K0QRkgJDOcuc+mRNrWdB09WekVVFLcJACpReOtI2Vm EFEiAvktBnZUgIM3t0CjGH7Ncx4cWesKHnAvXsik+IS+9oDGm0fm5hWyTdmDREgZ XsmpHmwiGX00wh/UjvYZLduYpzVgQG5caNoyBPJeKuvttMKJtnzi/U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; 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Thu, 14 Nov 2019 15:31:08 +0000 IronPort-SDR: 7wYyrZSNA6j7MetQ1SlBQ4RsB3ejdM+rElW5sOUOnZcczCEfUecFcfo3KHmJie2HUR+fsvStMu lp5GZL7xuS2MubrGT4IYMHrXKMChI9h3GUxOeqpUkZLpNb45pfqwGkdNoAQTDRpozQ8HYRxFlN L7ersjGhsmgXyyHw0YLaYve1vIcCBSJZD29ujmTT25b+WWhyJTE/k6Vu5YsLrX6UDJetK9AOnT YQ1BaufxC4qSRDG/ETLfdg/s8Dh+dVBtLn2yqwvKDIK+IPwvGFC4tDPu9Fzrj+MIqYaQifHjQg /6Y= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa2.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:31:07 -0800 IronPort-SDR: WDaSN72jaeoENinZJImHlfF/T3h3m+TMPI4q3JQq5BEYg9bDZnMe9vuTHngNaXgY3EwnvaqnDR IO1ymkN+jV044uPOnPlUBtJlDOUzfJurkUce0cBWzfuWZRB4MAXTxpSK2lWNwXqTgwAF+r7quu WlEBbuXqcdGmOEI/5orwpb1djGvuHPRVWarWFFOGORvO5d542aKK6MylvZ6k3wVnHNOu3+Str/ NPU0oPkWeYK+bwbNR5UWfHypuiOeX0mnoSB4HC6w4kRi08Ub4MLAzPLL9qjEl5XK+04aPbOtsE fx8= Subject: [PATCH 2/5] [amdgcn] Reinitialize registers for every function From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: <1029c8c6-41fe-4fca-bd49-f3a089f8b5d7@codesourcery.com> Date: Thu, 14 Nov 2019 15:30:48 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> The set of fixed registers is adjusted by the TARGET_CONDITIONAL_REGISTER_USAGE hook, but this needs to be done on a per-function basis, whereas the hook is normally called once during GCC initialization before any functions have been processed (which means the majority of the current implementation is actually dead code!). I have added a call to reinit_regs in gcn_init_cumulative_args to setup the available registers for each function. Okay for trunk? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.c (gcn_init_cumulative_args): Call reinit_regs. --- gcc/config/gcn/gcn.c | 2 ++ 1 file changed, 2 insertions(+) static bool diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 2c08771..09dfabb 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2434,6 +2434,8 @@ gcn_init_cumulative_args (CUMULATIVE_ARGS *cum /* Argument info to init */ , cfun->machine->args = cum->args; if (!caller && cfun->machine->normal_function) gcn_detect_incoming_pointer_arg (fndecl); + + reinit_regs (); } From patchwork Thu Nov 14 15:32:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194929 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513422-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="V3jiRhAI"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47DQTp2sSdz9sNT for ; Fri, 15 Nov 2019 02:32:46 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=vTOxjAoCKElZiQqhPCIXpGkCJKVqwG5qGtZ3gZcztJIZ0cHH/5sQx Guyxo3QU/NUkjhwLetWEHfDAQVw3mUQghiRj2eFPebGeIrAe/MdzoiF5tC1vbAI6 dDnpe083jkkty1jgGhyPLRizY/7VwmZ248w3M3NEBhcYsSev6eSGu4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; s=default; bh=DfcoAeWHv95ENb3wxNoXKhii7UY=; b=V3jiRhAIoV4B8Dg79ZHD7PhnRSBJ HW0BMxbTD6TpWMclhJIsJOUYM3hxAWuARa6vELLltyV2zCZD9QYKRdST4r7Gk5b6 eSWBgRayLasM335FAI8lhLGLcB8JeoGBbiFuBKupoAQx3YKfEA1SwQL43dskcV3Q llBf70OJJ9d06G8= Received: (qmail 112305 invoked by alias); 14 Nov 2019 15:32:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 112295 invoked by uid 89); 14 Nov 2019 15:32:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=Restrict X-HELO: esa2.mentor.iphmx.com Received: from esa2.mentor.iphmx.com (HELO esa2.mentor.iphmx.com) (68.232.141.98) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 15:32:36 +0000 IronPort-SDR: 3HP/dzk7PNwiq1NalKligDedj1o7wEdYsFgNqMKDL2/FClxGwU/hctJ41EL9xlIIZ+SqBhQn4S LcLosv8DceO4hpDZDaX37AGjnoJEAeHwkRNlXJUViuUHlMWZyPJJYonG89EGHH5wpDNfWUf/kI R0+oWLtDz6ELKcj5QuLMo2fO3LCocqm6FQmU78wxRDmuRCcUq0fTQJYsucJxnMoDru4iIwvbQ8 edSQtpABG54kh9KDouQyuFfFlnOwPLspspY4+MNj/hgkIwml3xLP50bcz5g2CU7SbGisIVv5dj bb4= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa2.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:32:35 -0800 IronPort-SDR: Kc6rRCpRoJPiyRO7zlV+eArazn6cyYeBxUnWZxcxrhMJgqAfUR8SBqxnooDk+Wxl1knCKStF5K Xj9zYUUnxpnkL4sMPX661CkUgyMEE+oCih2zZQygBGVG2Zedsn8ghR9MVi0Gx0Tf0pKrlpoLUM GicaeNbFmqsmp+al2H9HMUWTbHW7UJBqR0avlpGTVjraQslw2PZxEpuCkDg29MAOTqFRfI0oeF E6FMTK4G2/7qg8uBMJOUBKQv96Odt3KC6u6dXK+Zusp9gmMUTqAbBvVza2QDPft78Y9FFoQT8A rFI= Subject: [PATCH 3/5] [amdgcn] Restrict register usage in non-kernel functions From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: Date: Thu, 14 Nov 2019 15:32:16 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> This patch restricts non-kernel functions to using a maximum of 64 SGPRs and 24 VGPRs. Kernels can request various pieces of information from the HSA runtime, and these will be loaded into the registers consecutively before the kernel executes. These registers are normally fixed. Since non-kernel functions cannot make these requests, they have to assume that the default set of information has been requested. If a non-leaf kernel requests information not in the defaults, a warning is now emitted as pieces of info needed by callees may have shifted locations. A leaf kernel can do whatever it wants. I have setup FIXED_REGISTERS for the default case now - if a different set of startup info is requested (which should be rare), then the set of fixed registers will be adjusted accordingly by gcn_conditional_register_usage. Compared to before, v0, s2 and s3 are now unfixed (due to the newlib patch 'Stash reent marker in upper bits of s1 on AMD GCN' and the first patch in this series). Okay to commit? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.c (default_requested_args): New. (gcn_parse_amdgpu_hsa_kernel_attribute): Initialize requested args set with default_requested_args. (gcn_conditional_register_usage): Limit register usage of non-kernel functions. Reassign fixed registers if a non-standard set of args is requested. * config/gcn/gcn.h (FIXED_REGISTERS): Fix registers according to ABI. --- gcc/config/gcn/gcn.c | 63 ++++++++++++++++++++++++++++++---------------------- gcc/config/gcn/gcn.h | 6 ++--- 2 files changed, 39 insertions(+), 30 deletions(-) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 09dfabb..8a2f7d7 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -191,6 +191,17 @@ static const struct gcn_kernel_arg_type {"work_item_id_Z", NULL, V64SImode, FIRST_VGPR_REG + 2} }; +static const long default_requested_args + = (1 << PRIVATE_SEGMENT_BUFFER_ARG) + | (1 << DISPATCH_PTR_ARG) + | (1 << QUEUE_PTR_ARG) + | (1 << KERNARG_SEGMENT_PTR_ARG) + | (1 << PRIVATE_SEGMENT_WAVE_OFFSET_ARG) + | (1 << WORKGROUP_ID_X_ARG) + | (1 << WORK_ITEM_ID_X_ARG) + | (1 << WORK_ITEM_ID_Y_ARG) + | (1 << WORK_ITEM_ID_Z_ARG); + /* Extract parameter settings from __attribute__((amdgpu_hsa_kernel ())). This function also sets the default values for some arguments. @@ -201,10 +212,7 @@ gcn_parse_amdgpu_hsa_kernel_attribute (struct gcn_kernel_args *args, tree list) { bool err = false; - args->requested = ((1 << PRIVATE_SEGMENT_BUFFER_ARG) - | (1 << QUEUE_PTR_ARG) - | (1 << KERNARG_SEGMENT_PTR_ARG) - | (1 << PRIVATE_SEGMENT_WAVE_OFFSET_ARG)); + args->requested = default_requested_args; args->nargs = 0; for (int a = 0; a < GCN_KERNEL_ARG_TYPES; a++) @@ -242,8 +250,6 @@ gcn_parse_amdgpu_hsa_kernel_attribute (struct gcn_kernel_args *args, args->requested |= (1 << a); args->order[args->nargs++] = a; } - args->requested |= (1 << WORKGROUP_ID_X_ARG); - args->requested |= (1 << WORK_ITEM_ID_Z_ARG); /* Requesting WORK_ITEM_ID_Z_ARG implies requesting WORK_ITEM_ID_X_ARG and WORK_ITEM_ID_Y_ARG. Similarly, requesting WORK_ITEM_ID_Y_ARG implies @@ -253,10 +259,6 @@ gcn_parse_amdgpu_hsa_kernel_attribute (struct gcn_kernel_args *args, if (args->requested & (1 << WORK_ITEM_ID_Y_ARG)) args->requested |= (1 << WORK_ITEM_ID_X_ARG); - /* Always enable this so that kernargs is in a predictable place for - gomp_print, etc. */ - args->requested |= (1 << DISPATCH_PTR_ARG); - int sgpr_regno = FIRST_SGPR_REG; args->nsgprs = 0; for (int a = 0; a < GCN_KERNEL_ARG_TYPES; a++) @@ -2041,27 +2043,34 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass, static void gcn_conditional_register_usage (void) { - int i; + if (!cfun || !cfun->machine) + return; - /* FIXME: Do we need to reset fixed_regs? */ + if (cfun->machine->normal_function) + { + /* Restrict the set of SGPRs and VGPRs used by non-kernel functions. */ + for (int i = SGPR_REGNO (62); i <= LAST_SGPR_REG; i++) + fixed_regs[i] = 1, call_used_regs[i] = 1; -/* Limit ourselves to 1/16 the register file for maximimum sized workgroups. - There are enough SGPRs not to limit those. - TODO: Adjust this more dynamically. */ - for (i = FIRST_VGPR_REG + 64; i <= LAST_VGPR_REG; i++) - fixed_regs[i] = 1, call_used_regs[i] = 1; + for (int i = VGPR_REGNO (24); i <= LAST_VGPR_REG; i++) + fixed_regs[i] = 1, call_used_regs[i] = 1; - if (!cfun || !cfun->machine || cfun->machine->normal_function) - { - /* Normal functions can't know what kernel argument registers are - live, so just fix the bottom 16 SGPRs, and bottom 3 VGPRs. */ - for (i = 0; i < 16; i++) - fixed_regs[FIRST_SGPR_REG + i] = 1; - for (i = 0; i < 3; i++) - fixed_regs[FIRST_VGPR_REG + i] = 1; return; } + /* If the set of requested args is the default set, nothing more needs to + be done. */ + if (cfun->machine->args.requested == default_requested_args) + return; + + /* Requesting a set of args different from the default violates the ABI. */ + if (!leaf_function_p ()) + warning (0, "A non-default set of initial values has been requested, " + "which violates the ABI!"); + + for (int i = SGPR_REGNO (0); i < SGPR_REGNO (14); i++) + fixed_regs[i] = 0; + /* Fix the runtime argument register containing values that may be needed later. DISPATCH_PTR_ARG and FLAT_SCRATCH_* should not be needed after the prologue so there's no need to fix them. */ @@ -2069,10 +2078,10 @@ gcn_conditional_register_usage (void) fixed_regs[cfun->machine->args.reg[PRIVATE_SEGMENT_WAVE_OFFSET_ARG]] = 1; if (cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG] >= 0) { + /* The upper 32-bits of the 64-bit descriptor are not used, so allow + the containing registers to be used for other purposes. */ fixed_regs[cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG]] = 1; fixed_regs[cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG] + 1] = 1; - fixed_regs[cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG] + 2] = 1; - fixed_regs[cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG] + 3] = 1; } if (cfun->machine->args.reg[KERNARG_SEGMENT_PTR_ARG] >= 0) { diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index b3b2d1a..dd3789b 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -160,9 +160,9 @@ #define FIXED_REGISTERS { \ /* Scalars. */ \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, \ /* fp sp lr. */ \ - 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ + 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, \ /* exec_save, cc_save */ \ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -180,7 +180,7 @@ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ /* VGRPs */ \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ From patchwork Thu Nov 14 15:33:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194930 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513423-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="JMVVQOCB"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47DQVn2b0Jz9sNT for ; Fri, 15 Nov 2019 02:33:37 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; 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14 Nov 2019 15:33:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:2331 X-HELO: esa2.mentor.iphmx.com Received: from esa2.mentor.iphmx.com (HELO esa2.mentor.iphmx.com) (68.232.141.98) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 15:33:26 +0000 IronPort-SDR: sDJ3LVWW7cqyP4MZ2eWnHTimTu15TcEoqgK3MJgHDVF041nuT8m0kAtdMRSOZYxyZU/CX8/9Ko OIxqMKrCy1HvcGa32uqCmxbWKRdpVFZPY0LjJ/7qBLtAzH06oT++oa82tjA9BmGlh7BGOIWSSn VXDZTXtEx+KAJ/nuEbf8llKNiaH85YXmQ8UPzyrNBYboyvrE1UUXWYvBzi85Lph4z0p9lLV3o7 BpynGhHjc5deTJkuyhEih3SqTb9XyERN4twSfi253wyEWVhQz7JOUDjXT6oxXPigktbTMJ0LjN Usk= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa2.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:33:25 -0800 IronPort-SDR: UTqE6V8on0m+ki1LQJhzF01dt45PcrMX3iCAKa9x69jqaarYXQ5zdTd/vZQC/IUoxYdUdgQ4VF g6bHW8XYPROKYC/ZOiozAAajOVrPunogIxha/ZR6JOxG0uwarpiuGFY89NJ29qeJPmR8DHP9nk 8YWD8esBD7jtdhszcJNNHEquZrrs/mE13p4HSqVpXCbbkwtzTukI9PanoTAN7VBBIc2Llyy9sP emVymakQC47s7aOAwK4F2icOaxmlhmBZa1ztAA1ljej7ZmMh4vzI9dUTYOt5W+p6ja9cmvpj7h FpM= Subject: [PATCH 4/5] [amdgcn] Update lower limits requested by non-leaf kernels From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: Date: Thu, 14 Nov 2019 15:33:06 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> The kernel attributes are changed to request at least 64 SGPRs and 24 VGPRs (i.e. the non-kernel maximum, otherwise the callees may not have enough registers to run in) for non-leaf kernels to take advantage of the reduced number of registers used in non-kernel functions. Okay for trunk? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.c (MAX_NORMAL_SGPR_COUNT, MAX_NORMAL_VGPR_COUNT): New. (gcn_conditional_register_usage): Use constants in place of hard-coded values. (gcn_hsa_declare_function_name): Set lower bound for number of SGPRs/VGPRs in non-leaf kernels to MAX_NORMAL_SGPR_COUNT and MAX_NORMAL_VGPR_COUNT. --- gcc/config/gcn/gcn.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) return; @@ -4905,10 +4913,10 @@ gcn_hsa_declare_function_name (FILE *file, const char *name, tree) if (!leaf_function_p ()) { /* We can't know how many registers function calls might use. */ - if (vgpr < 64) - vgpr = 64; - if (sgpr + extra_regs < 102) - sgpr = 102 - extra_regs; + if (vgpr < MAX_NORMAL_VGPR_COUNT) + vgpr = MAX_NORMAL_VGPR_COUNT; + if (sgpr + extra_regs < MAX_NORMAL_SGPR_COUNT) + sgpr = MAX_NORMAL_SGPR_COUNT - extra_regs; } fputs ("\t.align\t256\n", file); diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 8a2f7d7..976843b 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -75,6 +75,12 @@ int gcn_isa = 3; /* Default to GCN3. */ #define LDS_SIZE 65536 +/* The number of registers usable by normal non-kernel functions. + The SGPR count includes any special extra registers such as VCC. */ + +#define MAX_NORMAL_SGPR_COUNT 64 +#define MAX_NORMAL_VGPR_COUNT 24 + /* }}} */ /* {{{ Initialization and options. */ @@ -2049,10 +2055,12 @@ gcn_conditional_register_usage (void) if (cfun->machine->normal_function) { /* Restrict the set of SGPRs and VGPRs used by non-kernel functions. */ - for (int i = SGPR_REGNO (62); i <= LAST_SGPR_REG; i++) + for (int i = SGPR_REGNO (MAX_NORMAL_SGPR_COUNT - 2); + i <= LAST_SGPR_REG; i++) fixed_regs[i] = 1, call_used_regs[i] = 1; - for (int i = VGPR_REGNO (24); i <= LAST_VGPR_REG; i++) + for (int i = VGPR_REGNO (MAX_NORMAL_VGPR_COUNT); + i <= LAST_VGPR_REG; i++) fixed_regs[i] = 1, call_used_regs[i] = 1; From patchwork Thu Nov 14 15:34:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194931 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513424-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; 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s=default; bh=cdar1/UiY1gMxr9JE9RBukOIN2E=; b=p4idkhh2bXfE731eTNCHtLptft0n 4I8lImF1jFCLPisqH6QCY/yD3p+f4AXSmCrs3koNcbkCq/e4DjtVIYLo4t/dh0BR AKZIhg+qdn9PAXhX4qCa8FFozGF7jrE1UBkqIjI3o0sB/x73qLpV2rTt9D0u9agA kMgw5Xys92ugWac= Received: (qmail 117155 invoked by alias); 14 Nov 2019 15:34:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 117147 invoked by uid 89); 14 Nov 2019 15:34:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1252 X-HELO: esa1.mentor.iphmx.com Received: from esa1.mentor.iphmx.com (HELO esa1.mentor.iphmx.com) (68.232.129.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 15:34:26 +0000 IronPort-SDR: /dh7d0FnSkl/kwDIrP9nbfWe21r+NhBhaz/481CZvbZDOPnRbDGjiiMqHHnN6+ANx/EM3Mvhbm /K51ks2+E1e5JEau42vAXkGiXR+vFYtEvykJsZQ1D7oLl2LJpN47Z6okd/BtuUsbIFIb9XUhcZ jDeGAibvEaCw4k3ZoyLVeectxbQ7y1vVpJGx+rCbtAseZQwkCboCbqeCz8+8UyOsNa2gKrBtlU fZuLc+q49OzMpqHwYgrLMAkwZotxieleU9NbIOkgPnRkeYlGeIZOi63gfehAZV1zr5iT38AgjJ GEM= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:34:25 -0800 IronPort-SDR: GqG+xZU/U4oOhdsWpshznPrXxNr3Goo0lcqyyyz1sdLnUz1ncZD5Q845uZFrzkgCa7c1WMH+dg qViBgfzgBIzizhQHZut4xEeDQ3YnxlkFAxuyvKuXDKMClwQ8P4yx0/EGPQuBf+Qr1Z58zWd7b6 yQSMESAgKuuZ+9QkHq1Ik9dCBzvCFzqd6I2VMDdIpUxYpLlPtYYBk8gVAOffldWp2kbtxzIMzi HGKxDsQjheYzo7jnQllh7Neu/dF4gUnVIZjDtDDe/YcnrKP3zKmpAOHs+Sb88eCJh1cC/3SmNe UwY= Subject: [PATCH 5/5] [amdgcn] Unfix frame pointer From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: Date: Thu, 14 Nov 2019 15:34:08 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> This patch unfixes the registers for the hard frame pointer so that they can be used for other purposes if the frame pointer is not in use. This patch is dependent on the commit 'Support using multiple registers to hold the frame pointer' (r277895) to work properly. Okay for trunk? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.h (FIXED_REGISTERS): Unfix frame pointer. (CALL_USED_REGISTERS): Make frame pointer callee-saved. --- gcc/config/gcn/gcn.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index dd3789b..e60b431 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -162,7 +162,7 @@ /* Scalars. */ \ 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, \ /* fp sp lr. */ \ - 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, \ + 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, \ /* exec_save, cc_save */ \ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -203,7 +203,7 @@ #define CALL_USED_REGISTERS { \ /* Scalars. */ \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \