From patchwork Thu Nov 14 05:52:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194588 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9nL4v82z9s4Y for ; Thu, 14 Nov 2019 17:00:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 77DCCC21D83; Thu, 14 Nov 2019 06:00:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 92802C21C29; Thu, 14 Nov 2019 06:00:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A40B2C21C2F; Thu, 14 Nov 2019 06:00:10 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 671EEC21BE5 for ; Thu, 14 Nov 2019 06:00:09 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE61EfX061893; Thu, 14 Nov 2019 14:01:14 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 13:59:35 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:21 +0800 Message-ID: <20191114055230.20289-2-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE61EfX061893 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 01/10] riscv: ax25: add SPL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen The U-Boot SPL will boot in M mode and load the FIT image which include OpenSBI and U-Boot proper images. After loading progress, it will jump to OpenSBI first and then U-Boot proper which will run in S mode. Also remove V5L2_CACHE due to U-Boot SPL code size consideration. Without this concern, it can be enable manually for performance. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/ax25/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index d411a79..8d8d71d 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,7 +6,9 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. From patchwork Thu Nov 14 05:52:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194590 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9pk1d53z9sPF for ; Thu, 14 Nov 2019 17:01:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7069AC21DEC; Thu, 14 Nov 2019 06:00:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B4125C21D8A; Thu, 14 Nov 2019 06:00:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C2CE2C21C29; Thu, 14 Nov 2019 06:00:10 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id AFE01C21C2C for ; Thu, 14 Nov 2019 06:00:09 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE61Oxj061928; Thu, 14 Nov 2019 14:01:24 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 13:59:45 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:22 +0800 Message-ID: <20191114055230.20289-3-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE61Oxj061928 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 02/10] riscv: ax25-ae350: add SPL configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen This patch provides four configurations which can support U-Boot SPL to boot from RAM or FLASH and then boot FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices. With ae350_rv[32|64]_spl_defconfigs: U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode and then load FIT image from RAM device on AE350. With ae350_rv[32|64]_spl_xip_defconfigs: U-Boot SPL can be burned into SPI flash and run in flash in machine mode and then load FIT image from SPI flash or MMC device on AE350. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- board/AndesTech/ax25-ae350/Kconfig | 9 ++++++++ board/AndesTech/ax25-ae350/MAINTAINERS | 4 ++++ board/AndesTech/ax25-ae350/ax25-ae350.c | 27 ++++++++++++++++++++++ configs/ae350_rv32_spl_defconfig | 37 ++++++++++++++++++++++++++++++ configs/ae350_rv32_spl_xip_defconfig | 39 ++++++++++++++++++++++++++++++++ configs/ae350_rv64_spl_defconfig | 38 +++++++++++++++++++++++++++++++ configs/ae350_rv64_spl_xip_defconfig | 40 +++++++++++++++++++++++++++++++++ include/configs/ax25-ae350.h | 17 ++++++++++++++ 8 files changed, 211 insertions(+) create mode 100644 configs/ae350_rv32_spl_defconfig create mode 100644 configs/ae350_rv32_spl_xip_defconfig create mode 100644 configs/ae350_rv64_spl_defconfig create mode 100644 configs/ae350_rv64_spl_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 5e682b6..321dd0c 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -21,9 +21,18 @@ config ENV_SIZE config ENV_OFFSET default 0x140000 if ENV_IS_IN_SPI_FLASH +config SPL_TEXT_BASE + default 0x800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x01000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select RISCV_NDS + select SUPPORT_SPL imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE endif diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS index feed5d1..eebee16 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ax25-ae350/MAINTAINERS @@ -7,3 +7,7 @@ F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig F: configs/ae350_rv32_xip_defconfig F: configs/ae350_rv64_xip_defconfig +F: configs/ae350_rv32_spl_defconfig +F: configs/ae350_rv64_spl_defconfig +F: configs/ae350_rv32_spl_xip_defconfig +F: configs/ae350_rv64_spl_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index b43eebb..b0164a9 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -110,3 +111,29 @@ int board_early_init_f(void) return 0; } #endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC_SUPPORT + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig new file mode 100644 index 0000000..53055b7 --- /dev/null +++ b/configs/ae350_rv32_spl_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SPL=y +CONFIG_RISCV_SMODE=y +CONFIG_SYS_TEXT_BASE=0x01200000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_PRIOR_STAGE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig new file mode 100644 index 0000000..fdbab43 --- /dev/null +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -0,0 +1,39 @@ +CONFIG_RISCV=y +CONFIG_SPL=y +CONFIG_RISCV_SMODE=y +CONFIG_SPL_TEXT_BASE=0x80000000 +CONFIG_SYS_TEXT_BASE=0x01200000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_AX25_AE350=y +CONFIG_XIP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig new file mode 100644 index 0000000..866b9b4 --- /dev/null +++ b/configs/ae350_rv64_spl_defconfig @@ -0,0 +1,38 @@ +CONFIG_RISCV=y +CONFIG_SPL=y +CONFIG_RISCV_SMODE=y +CONFIG_SYS_TEXT_BASE=0x01200000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_PRIOR_STAGE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig new file mode 100644 index 0000000..271ec21 --- /dev/null +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -0,0 +1,40 @@ +CONFIG_RISCV=y +CONFIG_SPL=y +CONFIG_RISCV_SMODE=y +CONFIG_SPL_TEXT_BASE=0x80000000 +CONFIG_SYS_TEXT_BASE=0x01200000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_XIP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index a4037f3..ef3864a 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -7,6 +7,23 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x04000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 + +#ifndef CONFIG_XIP +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00200000 +#else +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80010000 +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +#endif +#endif + /* * CPU and Board Configuration Options */ From patchwork Thu Nov 14 05:52:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194594 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9rS3rtKz9s4Y for ; Thu, 14 Nov 2019 17:03:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0DEAAC21BE5; Thu, 14 Nov 2019 06:01:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E0BD9C21D8E; Thu, 14 Nov 2019 06:01:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2E1A2C21C4A; Thu, 14 Nov 2019 06:00:22 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 88682C21DFD for ; Thu, 14 Nov 2019 06:00:19 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE61YFv061963; Thu, 14 Nov 2019 14:01:34 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 13:59:55 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:23 +0800 Message-ID: <20191114055230.20289-4-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE61YFv061963 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 03/10] riscv: ax25-ae350: Use generic memory size setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen To get memory size from device tree instead of get_ram_size(). This can avoid memory access fault in U-Boot proper after PMP configurations in OpenSBI. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index b0164a9..47e6929 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -30,29 +30,12 @@ int board_init(void) int dram_init(void) { - unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; - unsigned long actual_size; - - actual_size = get_ram_size((void *)sdram_base, expected_size); - gd->ram_size = actual_size; - - if (expected_size != actual_size) { - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - } - - return 0; + return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_0; - gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; - - return 0; + return fdtdec_setup_memory_banksize(); } #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) From patchwork Thu Nov 14 05:52:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194595 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9rc1L8Nz9sNT for ; Thu, 14 Nov 2019 17:03:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D00B3C21CB1; Thu, 14 Nov 2019 06:01:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72D6BC21DB3; Thu, 14 Nov 2019 06:01:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7D406C21DAF; Thu, 14 Nov 2019 06:00:42 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 04830C21DE8 for ; Thu, 14 Nov 2019 06:00:35 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE61iNg061987; Thu, 14 Nov 2019 14:01:44 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:06 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:24 +0800 Message-ID: <20191114055230.20289-5-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE61iNg061987 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 04/10] riscv: andes_plic: Fix some wrong configurations X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Fix two wrong settings of andes plic driver as below: 1. Fix wrong pending register base definition. 2. Declaring the en variable in enable_ipi() as unsigned int instead of int can help to fix wrong plic enabling setting in RV64. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/lib/andes_plic.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 28568e4..42394b9 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -19,7 +19,7 @@ #include /* pending register */ -#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) /* enable register */ #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) /* claim register */ @@ -46,7 +46,7 @@ static int init_plic(void); static int enable_ipi(int hart) { - int en; + unsigned int en; en = ENABLE_HART_IPI >> hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); @@ -94,10 +94,13 @@ static int init_plic(void) int riscv_send_ipi(int hart) { + unsigned int ipi; + PLIC_BASE_GET(); - writel(SEND_IPI_TO_HART(hart), - (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); + ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, + gd->arch.boot_hart)); return 0; } From patchwork Thu Nov 14 05:52:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194591 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9q959nRz9sP6 for ; Thu, 14 Nov 2019 17:01:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5C865C21D65; Thu, 14 Nov 2019 06:01:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4993CC21C6A; Thu, 14 Nov 2019 06:01:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5FCBBC21DA1; Thu, 14 Nov 2019 06:00:45 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 6C62CC21D83 for ; Thu, 14 Nov 2019 06:00:39 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE61te6062018; Thu, 14 Nov 2019 14:01:55 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:16 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:25 +0800 Message-ID: <20191114055230.20289-6-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE61te6062018 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 05/10] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/ax25/cache.c | 60 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 14 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 41de30c..e0b5fdd 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -11,18 +11,46 @@ #include #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) /* mcctlcommand */ #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc /* D-cache operation */ #define CCTL_L1D_WBINVAL_ALL 6 #endif +#endif + +#ifdef CONFIG_V5L2_CACHE +static void _cache_enable(void) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); +} + +static void _cache_disable(void) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); +} +#endif void flush_dcache_all(void) { +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); #endif +#endif +#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -39,6 +67,7 @@ void icache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x1\n\t" @@ -46,12 +75,14 @@ void icache_enable(void) ); #endif #endif +#endif } void icache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) asm volatile ( "fence.i\n\t" "csrr t1, mcache_ctl\n\t" @@ -60,24 +91,23 @@ void icache_disable(void) ); #endif #endif +#endif } void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE - struct udevice *dev = NULL; - +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" "csrw mcache_ctl, t0\n\t" ); - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_enable(dev); +#endif +#ifdef CONFIG_V5L2_CACHE + _cache_enable(); +#endif #endif #endif } @@ -86,19 +116,17 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE - struct udevice *dev = NULL; - +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" ); - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_disable(dev); +#endif +#ifdef CONFIG_V5L2_CACHE + _cache_disable(); +#endif #endif #endif } @@ -108,6 +136,7 @@ int icache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x01\n\t" @@ -116,6 +145,7 @@ int icache_status(void) : "memory" ); #endif +#endif return ret; } @@ -125,6 +155,7 @@ int dcache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE +#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x02\n\t" @@ -133,6 +164,7 @@ int dcache_status(void) : "memory" ); #endif +#endif return ret; } From patchwork Thu Nov 14 05:52:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194597 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9sy3jbsz9sNT for ; Thu, 14 Nov 2019 17:04:22 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 03D1DC21DAF; Thu, 14 Nov 2019 06:02:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3967AC21D83; Thu, 14 Nov 2019 06:02:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1D0DDC21D8E; Thu, 14 Nov 2019 06:00:49 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 59F8AC21DEC for ; Thu, 14 Nov 2019 06:00:49 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE625F3062068; Thu, 14 Nov 2019 14:02:05 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:26 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:26 +0800 Message-ID: <20191114055230.20289-7-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE625F3062068 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 06/10] spl: cache: Allow cache drivers in SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen When ax25-ae350 try to enable v5l2 cache driver in SPL configuration, it need this option for cache support in SPL. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- common/spl/Kconfig | 7 +++++++ drivers/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 8f0ba8e..9ed7a42 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -439,6 +439,13 @@ config SPL_FIT_IMAGE_TINY ensure this information is available to the next image invoked). +config SPL_CACHE_SUPPORT + bool "Support CACHE drivers" + help + Enable CACHE drivers in SPL. These drivers can keep data so that + future requests for that data can be served faster. Enable this option + to build the drivers in drivers/cache as part of an SPL build. + config SPL_CPU_SUPPORT bool "Support CPU drivers" help diff --git a/drivers/Makefile b/drivers/Makefile index 0befedd..8c29b1e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -31,6 +31,7 @@ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ +obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/ obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ From patchwork Thu Nov 14 05:52:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194600 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9vD2xV6z9s4Y for ; Thu, 14 Nov 2019 17:05:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F0E9BC21DA6; Thu, 14 Nov 2019 06:02:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4283C21D74; Thu, 14 Nov 2019 06:02:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 99F15C21D72; Thu, 14 Nov 2019 06:01:00 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 7F3D6C21DCA for ; Thu, 14 Nov 2019 06:00:59 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE62Fh3062088; Thu, 14 Nov 2019 14:02:15 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:36 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:27 +0800 Message-ID: <20191114055230.20289-8-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE62Fh3062088 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 07/10] riscv: Fix clear bss loop in the start-up code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/start.S | 4 ++-- arch/riscv/cpu/u-boot-spl.lds | 2 +- arch/riscv/cpu/u-boot.lds | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 0a2ce6d..ee6d471 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -174,7 +174,7 @@ spl_clear_bss: spl_clear_bss_loop: SREG zero, 0(t0) addi t0, t0, REGBYTES - bne t0, t1, spl_clear_bss_loop + blt t0, t1, spl_clear_bss_loop spl_stack_gd_setup: jal spl_relocate_stack_gd @@ -324,7 +324,7 @@ clear_bss: clbss_l: SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES - bne t0, t1, clbss_l + blt t0, t1, clbss_l relocate_secondary_harts: #ifdef CONFIG_SMP diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index 32255d5..955dd31 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -76,7 +76,7 @@ SECTIONS .bss : { __bss_start = .; *(.bss*) - . = ALIGN(4); + . = ALIGN(8); __bss_end = .; } > .bss_mem } diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 11bc4a7..838a844 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -82,7 +82,7 @@ SECTIONS .bss : { __bss_start = .; *(.bss*) - . = ALIGN(4); + . = ALIGN(8); __bss_end = .; } } From patchwork Thu Nov 14 05:52:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194599 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9tw4vCrz9s4Y for ; Thu, 14 Nov 2019 17:05:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 526C1C21DAF; Thu, 14 Nov 2019 06:02:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 04A7AC21DAF; Thu, 14 Nov 2019 06:02:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 48088C21DAF; Thu, 14 Nov 2019 06:01:11 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 500FCC21D8E for ; Thu, 14 Nov 2019 06:01:09 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE62PUI062124; Thu, 14 Nov 2019 14:02:25 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:46 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:28 +0800 Message-ID: <20191114055230.20289-9-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE62PUI062124 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 08/10] riscv: dts: Support four cores SMP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/dts/ae350_32.dts | 57 ++++++++++++++++++++++++++++++++++++++++++--- arch/riscv/dts/ae350_64.dts | 57 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 108 insertions(+), 6 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 97b7cee..c6c2040 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -62,6 +62,48 @@ compatible = "riscv,cpu-intc"; }; }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; L2: l2-cache@e0500000 { @@ -94,7 +136,10 @@ interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; }; plic1: interrupt-controller@e6400000 { @@ -104,12 +149,18 @@ interrupt-controller; reg = <0xe6400000 0x400000>; riscv,ndev=<2>; - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; }; plmt0@e6000000 { compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; reg = <0xe6000000 0x100000>; }; }; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index d8f00f8..c57efe3 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,6 +62,48 @@ compatible = "riscv,cpu-intc"; }; }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; L2: l2-cache@e0500000 { @@ -94,7 +136,10 @@ interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; }; plic1: interrupt-controller@e6400000 { @@ -104,12 +149,18 @@ interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; riscv,ndev=<2>; - interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; }; plmt0@e6000000 { compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; reg = <0x0 0xe6000000 0x0 0x100000>; }; }; From patchwork Thu Nov 14 05:52:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194596 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9sW56tjz9sNT for ; Thu, 14 Nov 2019 17:03:59 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5171DC21DF8; Thu, 14 Nov 2019 06:03:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66284C21D72; Thu, 14 Nov 2019 06:03:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C0200C21C8B; Thu, 14 Nov 2019 06:01:22 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 479F5C21D8A for ; Thu, 14 Nov 2019 06:01:19 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE62ZnP062142; Thu, 14 Nov 2019 14:02:35 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:00:56 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:29 +0800 Message-ID: <20191114055230.20289-10-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE62ZnP062142 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 09/10] riscv: dts: Add #address-cells and #size-cells in nor node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/dts/ae350_32.dts | 4 +++- arch/riscv/dts/ae350_64.dts | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index c6c2040..3f8525f 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -296,8 +296,10 @@ }; nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "cfi-flash"; - reg = <0x88000000 0x1000>; + reg = <0x88000000 0x4000000>; bank-width = <2>; device-width = <1>; }; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index c57efe3..482c707 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -296,8 +296,10 @@ }; nor@0,0 { + #address-cells = <2>; + #size-cells = <2>; compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; + reg = <0x0 0x88000000 0x0 0x4000000>; bank-width = <2>; device-width = <1>; }; From patchwork Thu Nov 14 05:52:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1194598 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47D9tY6fjMz9sNT for ; Thu, 14 Nov 2019 17:04:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 87EB0C21DD7; Thu, 14 Nov 2019 06:02:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8B21DC21DAF; Thu, 14 Nov 2019 06:02:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B28DFC21D83; Thu, 14 Nov 2019 06:01:33 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 6596CC21DD4 for ; Thu, 14 Nov 2019 06:01:32 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id xAE62jDw062162; Thu, 14 Nov 2019 14:02:45 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Thu, 14 Nov 2019 14:01:06 +0800 From: Andes To: Date: Thu, 14 Nov 2019 13:52:30 +0800 Message-ID: <20191114055230.20289-11-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191114055230.20289-1-uboot@andestech.com> References: <20191114055230.20289-1-uboot@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com xAE62jDw062162 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v2 10/10] doc: update AX25-AE350 RISC-V documentation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rick Chen Add descriptions about U-Boot SPL feature and how to build and run. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- doc/board/AndesTech/ax25-ae350.rst | 209 ++++++++++++++++++++++++++++++++++++- 1 file changed, 206 insertions(+), 3 deletions(-) diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ax25-ae350.rst index 7a01893..a7bd1a7 100644 --- a/doc/board/AndesTech/ax25-ae350.rst +++ b/doc/board/AndesTech/ax25-ae350.rst @@ -324,6 +324,209 @@ Boot bbl and riscv-linux via U-Boot on QEMU / # -TODO ----- -Boot bbl and riscv-linux via U-Boot on AE350 board +Running U-Boot SPL +------------------ +The U-Boot SPL will boot in M mode and load the FIT image which include +OpenSBI and U-Boot proper images. After loading progress, it will jump +to OpenSBI first and then U-Boot proper which will run in S mode. + + +How to build U-Boot SPL +----------------------- +Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be +cloned and build for AE350 as below: + +git clone https://github.com/riscv/opensbi.git +cd opensbi +make PLATFORM=andes/ae350 + +Copy OpenSBI FW_DYNAMIC image (build\platform\andes\ae350\firmware\fw_dynamic.bin) +into U-Boot root directory + + +How to build U-Boot SPL booting from RAM +---------------------------------------- +With ae350_rv[32|64]_spl_defconfigs: + +U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode +and then load FIT image from RAM device on AE350. + + +How to build U-Boot SPL booting from ROM +---------------------------------------- +With ae350_rv[32|64]_spl_xip_defconfigs: + +U-Boot SPL can be burned into SPI flash and run in flash in machine mode +and then load FIT image from SPI flash or MMC device on AE350. + + +Messages of U-Boot SPL boots Kernel on AE350 board +-------------------------------------------------- + +.. code-block:: none + +U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) +Trying to boot from RAM + +OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39) + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Andes AE350 +Platform HART Features : RV64ACIMSUX +Platform Max HARTs : 4 +Current Hart : 0 +Firmware Base : 0x0 +Firmware Size : 84 KB +Runtime SBI Version : 0.2 + +PMP0: 0x0000000000000000-0x000000000001ffff (A) +PMP1: 0x0000000000000000-0x00000001ffffffff (A,R,W,X) + + +U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800) + +DRAM: 1 GiB +Flash: 64 MiB +MMC: mmc@f0e00000: 0 +Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB +OK +In: serial@f0300000 +Out: serial@f0300000 +Err: serial@f0300000 +Net: no alias for ethernet0 + +Warning: mac@e0100000 (eth0) using random MAC address - a2:ae:93:7b:cc:8f +eth0: mac@e0100000 +Hit any key to stop autoboot: 0 +6455 bytes read in 31 ms (203.1 KiB/s) +20421684 bytes read in 8647 ms (2.3 MiB/s) +## Booting kernel from Legacy Image at 00600000 ... + Image Name: + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size: 20421620 Bytes = 19.5 MiB + Load Address: 00200000 + Entry Point: 00200000 + Verifying Checksum ... OK +## Flattened Device Tree blob at 20000000 + Booting using the fdt blob at 0x20000000 + Loading Kernel Image + Loading Device Tree to 000000001effb000, end 000000001efff936 ... OK + +Starting kernel ... + +OF: fdt: Ignoring memory range 0x0 - 0x200000 +Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 23:41:49 CST 2019 +bootconsole [early0] enabled +Initial ramdisk at: 0x (ptrval) (13665712 bytes) +Zone ranges: + DMA32 [mem 0x0000000000200000-0x000000003fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000000200000-0x000000003fffffff] +Initmem setup node 0 [mem 0x0000000000200000-0x000000003fffffff] +software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [ (ptrval)- (ptrval)] +elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0 +compatible privileged spec version 1.10 +percpu: Embedded 16 pages/cpu @ (ptrval) s28184 r8192 d29160 u65536 +Built 1 zonelists, mobility grouping on. Total pages: 258055 +Kernel command line: console=ttyS0,38400n8 debug loglevel=7 +log_buf_len individual max cpu contribution: 4096 bytes +log_buf_len total cpu_extra contributions: 12288 bytes +log_buf_len min size: 16384 bytes +log_buf_len: 32768 bytes +early log buf free: 14608(89%) +Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) +Inode-cache hash table entries: 65536 (order: 7, 524288 bytes) +Sorting __ex_table... +Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +Preemptible hierarchical RCU implementation. + Tasks RCU enabled. +NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0 +riscv,cpu_intc,0: 64 local interrupts mapped +riscv,cpu_intc,1: 64 local interrupts mapped +riscv,cpu_intc,2: 64 local interrupts mapped +riscv,cpu_intc,3: 64 local interrupts mapped +riscv,plic0,e4000000: mapped 71 interrupts to 8/8 handlers +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1bacf917bf, max_idle_ns: 881590412290 ns +sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns +Console: colour dummy device 40x30 +Calibrating delay loop (skipped), value calculated using timer frequency.. 120.00 BogoMIPS (lpj=600000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 2048 (order: 2, 16384 bytes) +Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes) +Hierarchical SRCU implementation. +smp: Bringing up secondary CPUs ... +CPU0: online +CPU2: online +CPU3: online +smp: Brought up 1 node, 4 CPUs +devtmpfs: initialized +random: get_random_u32 called from bucket_table_alloc+0x198/0x1d8 with crng_init=0 +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns +futex hash table entries: 1024 (order: 4, 65536 bytes) +NET: Registered protocol family 16 +Advanced Linux Sound Architecture Driver Initialized. +clocksource: Switched to clocksource riscv_clocksource +NET: Registered protocol family 2 +tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes) +TCP established hash table entries: 8192 (order: 4, 65536 bytes) +TCP bind hash table entries: 8192 (order: 5, 131072 bytes) +TCP: Hash tables configured (established 8192 bind 8192) +UDP hash table entries: 512 (order: 2, 16384 bytes) +UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) +NET: Registered protocol family 1 +RPC: Registered named UNIX socket transport module. +RPC: Registered udp transport module. +RPC: Registered tcp transport module. +RPC: Registered tcp NFSv4.1 backchannel transport module. +Unpacking initramfs... +workingset: timestamp_bits=62 max_order=18 bucket_order=0 +NFS: Registering the id_resolver key type +Key type id_resolver registered +Key type id_legacy registered +nfs4filelayout_init: NFSv4 File Layout Driver Registering... +io scheduler noop registered +io scheduler cfq registered (default) +io scheduler mq-deadline registered +io scheduler kyber registered +Console: switching to colour frame buffer device 40x30 +Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled +console [ttyS0] disabled +f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 20, base_baud = 1228800) is a 16550A +console [ttyS0] enabled +console [ttyS0] enabled +bootconsole [early0] disabled +bootconsole [early0] disabled +loop: module loaded +tun: Universal TUN/TAP device driver, 1.6 +ftmac100: Loading version 0.2 ... +ftmac100 e0100000.mac eth0: irq 21, mapped at (ptrval) +ftmac100 e0100000.mac eth0: generated random MAC address 4e:fd:bd:f3:04:fc +ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ +mmc0: new SDHC card at address d555 +ftssp010 card registered! +mmcblk0: mmc0:d555 SD04G 3.79 GiB +NET: Registered protocol family 10 + mmcblk0: p1 +Segment Routing with IPv6 +sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +NET: Registered protocol family 17 +NET: Registered protocol family 15 +ALSA device list: + #0: ftssp_ac97 controller +Freeing unused kernel memory: 13520K +This architecture does not have kernel memory protection. +Sysinit starting +Sat Apr 6 23:33:53 CST 2019 +nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... + +~ #