From patchwork Mon Nov 11 14:21:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1192953 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rkKzMxgW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47BY7N27ftz9sR4 for ; Tue, 12 Nov 2019 01:25:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1284FC21E57; Mon, 11 Nov 2019 14:24:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9A267C21DFB; Mon, 11 Nov 2019 14:24:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4AA24C21E0D; Mon, 11 Nov 2019 14:21:41 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id B5B95C21DD3 for ; Mon, 11 Nov 2019 14:21:39 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id j18so14621wmk.1 for ; Mon, 11 Nov 2019 06:21:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=i2nQMRM8qXRFo9+u9qm+tkE3BPOOIqw83SANIvT4GOg=; b=rkKzMxgWkG7PToiixbjwzdiHcheiyCostdHreyv0Rmao8Un7kxpdihefzVfbEyaOez K386SvditFgIwK+27nrAmZ0/dFA9xhJ/tBxCtHcdUcyBAZQAazrYL7jtzTSegdfvv9L9 D0LpbRVP+VjOuwm/Hnkq3wg13nby9s6+TPRpin0xy9EBrQkwoTy0wW82MxTALst8Oh7N TVMP1aFdg64DOS/C23mj/6demI3jUPCGjia2bX+2F7rvFU+iROKnMB6JC6GGS5R2NXnV qQTtmU62Go/LxuaO/waKqiyN+ls232YO4UmBjfZQpzKRj4SmD4u7Dgy04FcHPfNbPLjg 1fVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=i2nQMRM8qXRFo9+u9qm+tkE3BPOOIqw83SANIvT4GOg=; b=qIiqS6IvG/I9+OwjK+1wDhiB4ar+miqq6j4kUtBSI/4PkIHEsa3b8h3RnnvyotHztY kQlAg3xj1tgAJHiSuxyYSOsGq0cfTNHyUNsiCODPXyOtA/HTbnhYjt4laCxlMtrA0fD+ h+/gU+Om/0RngYv08W8ks+jo5KPGYOAUH3tgMrDfXPBAxDLFA/ou/PyqF/vXkIgZ+TvW oj3yxQ8T/gqOgfdFWCOhQPg2OFL9fWYgl/7bAl7gKuYB+uLejuDrxiWc0TQ98nBWD+6l QCvGmcHvRriLyLrpQOOsxgvBfpLF1KOlf5GkxaPzQnvWbh+982HJuq9TbiAJULT6fQWX HoEA== X-Gm-Message-State: APjAAAVlqKBgd9MDq95KLElkFPduKA05UMi0CJ8ynVR48OngWU6zsk9c C0n2SDJ8fto2oChNO2WpN0sC2pwn X-Google-Smtp-Source: APXvYqy6DWsCuixSshvM7uOEmon09ukRehpnhYnYBmBmGRL5m80xm1DoBAJACw892SoYpGoFUuWesw== X-Received: by 2002:a7b:cd86:: with SMTP id y6mr20349180wmj.163.1573482098708; Mon, 11 Nov 2019 06:21:38 -0800 (PST) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id y15sm14453663wrh.94.2019.11.11.06.21.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Nov 2019 06:21:38 -0800 (PST) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Mon, 11 Nov 2019 16:21:34 +0200 Message-Id: <20191111142135.21923-1-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 Cc: "NXP i.MX U-Boot Team" , Stefan Agner , Marcel Ziswiler , Igor Opaniuk , Otavio Salvador , Max Krummenacher Subject: [U-Boot] [PATCH v1] imx: bootaux: elf firmware support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c Signed-off-by: Igor Opaniuk Signed-off-by: Stefan Agner --- arch/arm/include/asm/mach-imx/sys_proto.h | 7 ++ arch/arm/mach-imx/imx_bootaux.c | 87 +++++++++++++++++++++-- arch/arm/mach-imx/mx7/soc.c | 28 ++++++++ 3 files changed, 118 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 52c83ba9e4..4428a7fa0b 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -139,6 +139,13 @@ enum boot_dev_type_e { extern struct rom_api *g_rom_api; #endif +/* address translation table */ +struct rproc_att { + u32 da; /* device address (From Cortex M4 view) */ + u32 sa; /* system bus address */ + u32 size; /* size of reg range */ +}; + u32 get_nr_cpus(void); u32 get_cpu_rev(void); u32 get_cpu_speed_grade_hz(void); diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 3d9422d5a2..7f4bbfe885 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -7,18 +7,94 @@ #include #include #include +#include #include #include -int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader, assumes the image is valid, returns the + * entry point address. + */ +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} + +int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; - if (!boot_private_data) + if (!addr) return -EINVAL; - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); + if (valid_elf_image(addr)) { + stack = 0x0; + pc = load_elf_image_phdr(addr); + if (!pc) + return CMD_RET_FAILURE; + + } else { + /* + * Assume binary file with vector table at the beginning. + * Cortex-M4 vector tables start with the stack pointer (SP) + * and reset vector (initial PC). + */ + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + } /* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); @@ -80,6 +156,9 @@ static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); + if (!addr) + return CMD_RET_FAILURE; + printf("## Starting auxiliary core at 0x%08lX ...\n", addr); ret = arch_auxiliary_core_up(0, addr); diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 35160f4b37..4aafeed188 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -193,6 +193,34 @@ static void init_cpu_basic(void) #endif } +#ifdef CONFIG_IMX_BOOTAUX +/* + * Table of mappings of physical mem regions in both + * Cortex-A7 and Cortex-M4 address spaces. + * + * For additional details check sections 2.1.2 and 2.1.3 in + * i.MX7Dual Applications Processor Reference Manual + * + */ +const struct rproc_att hostmap[] = { + /* aux core , host core, size */ + { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */ + { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */ + { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ + { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { /* sentinel */ } +}; +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* enable all periherial can be accessed in nosec mode */ static void init_csu(void)