From patchwork Sat Nov 9 11:36:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1192401 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="lzRQEQYv"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 479FV74ZWSz9sP4 for ; Sat, 9 Nov 2019 22:37:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B8E89C21E07; Sat, 9 Nov 2019 11:36:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 99F4CC21C38; Sat, 9 Nov 2019 11:36:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C6645C21C38; Sat, 9 Nov 2019 11:36:52 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id 0DB5CC21BE5 for ; Sat, 9 Nov 2019 11:36:52 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id q17so5861471pgt.9 for ; Sat, 09 Nov 2019 03:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8FybDBiGOLsgye4su3BTgGZL5EKxj2Wjh+LRSIcgTZg=; b=lzRQEQYvhU0ZrhxaFLp6pkI2XrsDksW/VXlWUWzuZs3ueWc7rm263EVn9o8veNUeBr ctsk0Xny6EiJdLkQ/8mIgGONsdVfbiM8kheGDwvERLXiRJuNdabYgLlbv404R/wXC5KT d52n6GMOXvRg+vVSw6Jl9lpj0dky/wqLHltiY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8FybDBiGOLsgye4su3BTgGZL5EKxj2Wjh+LRSIcgTZg=; b=R+lXAQ4Hb+mVHwy/KQuViODnpACriWVoqe/ptdBJlBcnXwqxn9l5QVN2Pn6Fqb4+g5 /Ex2n4kZwNmfdhfzbXFUv+YNYqh/muIUVXBYc0zPxvyfrmi6HKpcVIwTI/F2/nZOESrC oUQZkyu2FwenSOWgVLyuW8+PyJanMgvKlRyP9IL8XDflSXvDf/7fXMEC6QHMh47bRLGE BDq8w+LagyYB5hCqkmHuTWfSqGbl4bIrrMMdb5U8t4ho2nFZirSp3fXdHbnXcHkkRHWZ h/Dyyr6oM0Ck42vBnaEeD/a/X7oNd7js8/kb/pL94+5TpT0EecVgSQrDHWKKCkKH3Ya2 mXsQ== X-Gm-Message-State: APjAAAXS6rMNXbDeCEKXsXJ54FSV/ueXSLufhYHDkANV9C9sVvY1s1Vt bg0rOWkTZv/mDNuQOcw4k6TcUg== X-Google-Smtp-Source: APXvYqz3q4r+X8w+7DGswvM9AoTjx+ei2nnB0mpoypazouPkJ3XxhsSZU/JqTCaUohAyiIjAl3Cx2Q== X-Received: by 2002:a65:63cf:: with SMTP id n15mr18389451pgv.314.1573299409979; Sat, 09 Nov 2019 03:36:49 -0800 (PST) Received: from jagan-XPS-13-9350.lan ([103.30.141.124]) by smtp.gmail.com with ESMTPSA id 76sm10348403pfw.75.2019.11.09.03.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Nov 2019 03:36:49 -0800 (PST) From: Jagan Teki To: Rick Chen Date: Sat, 9 Nov 2019 17:06:34 +0530 Message-Id: <20191109113635.2157-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 1/2] riscv: dts: Add hifive-unleashed-a00 dts from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki --- Changes for v3: - none arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f9cd606a9a..4f30e6936f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 0000000000..afa43c7ea3 --- /dev/null +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = ð0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42 43 44 45>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46 47 48 49>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..88cfcb96bf --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = ; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; From patchwork Sat Nov 9 11:36:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1192402 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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bh=zAEzRTymC0epNHqwgl1dyc7dnLQbDdjT/ZgGK/ZpPyE=; b=L/gzldL7mSzDvCggfjV648EI0bLsIqjJrytwhri5+8191F65k54dch7vUgTHkPmEa/ HDCXSHNdAyVm87XBSjewbX+3gcKHwEukTK1ixr//uKk4p7hsMSLYw8JDvZu/Jfhs4m37 p7zu5GD5OvFQlKem6UXzba2BCzksG8NhU581uGxV6ca8SQVAgO6jUQOfYdwkoJ4UQeG8 qlCl9NBogMkWed9Lv44S9gQFVgsZM673JihpVp3rtze6NiFJu9iUZZXhRS1QI9/aJEuA bz+kEmDvI1/5kLGvAnAg7aF8MU9QuIxza9a5yAeE043Gv6SG9fTTX8ZuMZL+RvUTjLkV Q6qw== X-Gm-Message-State: APjAAAVX4oz3bZpVzrcY0sega5uaFFVJkuA1aPoMf2YL54ojS8zZ40Dh nfWpq7eWOMTlJ5fxeHQMD5XPsA== X-Google-Smtp-Source: APXvYqw8DYOH7DeaHqI92l6Dzdp/iG/emhXO0YGwInlMa0dildvE8iz9kYbm031q4Cuvoh0n9Jocrg== X-Received: by 2002:a17:902:b082:: with SMTP id p2mr16360229plr.123.1573299413028; Sat, 09 Nov 2019 03:36:53 -0800 (PST) Received: from jagan-XPS-13-9350.lan ([103.30.141.124]) by smtp.gmail.com with ESMTPSA id 76sm10348403pfw.75.2019.11.09.03.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Nov 2019 03:36:52 -0800 (PST) From: Jagan Teki To: Rick Chen Date: Sat, 9 Nov 2019 17:06:35 +0530 Message-Id: <20191109113635.2157-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191109113635.2157-1-jagan@amarulasolutions.com> References: <20191109113635.2157-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 2/2] sifive: fu540: Enable OF_SEPARATE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi. This would help to make the necessary changes in drivers and device trees in U-Boot tree itself. This feature would also be helpful to not pass dtb during opensbi builds. Signed-off-by: Jagan Teki --- Changes for v3: - fixed typo changes. configs/sifive_fu540_defconfig | 3 ++- doc/board/sifive/fu540.rst | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 48865e5f11..979d0a0418 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -6,6 +6,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_MISC_INIT_R=y +CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_SEPARATE=y diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 7807f5b2c1..91b94ee06f 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -58,7 +58,7 @@ firmware. We need to compile OpenSBI with below command: .. code-block:: none - make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= FW_PAYLOAD_FDT_PATH= + make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= (Note: Prefer hifive-unleashed-a00.dtb from Linux-5.3 or higher) (Note: Linux-5.2 is also fine but it does not have ethernet DT node)