From patchwork Fri Nov 8 08:45:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WdY6nR0/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478YlD5Mdmz9sR1 for ; Fri, 8 Nov 2019 19:46:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730632AbfKHIpb (ORCPT ); Fri, 8 Nov 2019 03:45:31 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46177 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726072AbfKHIpa (ORCPT ); Fri, 8 Nov 2019 03:45:30 -0500 Received: by mail-wr1-f66.google.com with SMTP id b3so5994238wrs.13; Fri, 08 Nov 2019 00:45:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lXctZT9szOude0/tzOobu9MVmKEaCphOc5TWHI1R/+o=; b=WdY6nR0/Jp+x7ZOowmnVHfztGLVygNvroENA6yBkFeG6Y8J6MdNWkU5wlp+hZFdGLE JGz2/0cgugAvqCRFUlxMF40CNgPH0eOMT4XkfrObYacIn3gXmDD4p/aMz1PTm7fpW3ha r80j+ukVgX1HPOMbZ1Ss+smvyms6gB94q3id8WN/f4wdRgpnJoQRomnSGLtmbE9RtQna h9bklZ9VcEXBTCv1lGEkNbk34tPD8tpDwvUJAgm5QImq5gklZenXpk2ss5cmVyJFsnCy PXYbFfziTLWXsrOfjpeSz2QMyZ2wumiEo/KTYw5054vX82a/EEuMWkeu8Nrb1Kn3/mOh qC+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lXctZT9szOude0/tzOobu9MVmKEaCphOc5TWHI1R/+o=; b=PyvcUaeZNVkVom08Rik6MHqMwP7hlUSWlAI7kLLRuEt412jl8p1jtXCanmkrMPvUyt Rh/wCbxSBZK3CxCqTQJdIvy6AahAZcV1wHsaYGgvF5UpuoS+ydXHblmKHNLjGTE3V7Zp Zr6TSe+f7kNne2kkt1oR1C2SPdbpiH19s+u7caKB/YIyy/hcTTtG6wvCe8HILuTUljx7 1UtPMD2ChnWghLpCm7LAUpk+BraIfujodLatuFzLR2EA27Kh3AZ2eS2S3RPiIKyTZTol E5qc/tqhJpPonzoKXa/iu7P6NQHS4Da4OL24OlXArZmqtY43QliLtvlWN8x3nB3B6ymA a8AA== X-Gm-Message-State: APjAAAXn4CipsfUEr0SBWYsaFruZ+vd3029gXe6wu7mIYQX+OusbcNh6 frBsqi7cp/sVVMAK8JS/KMU= X-Google-Smtp-Source: APXvYqwP1PQg+Qz0CsAYeKQRWcWxaJuimaCkAjha6SKIoYhOxnoyF8fMyOe15V7v2E8HDLzWw/GVZg== X-Received: by 2002:adf:f685:: with SMTP id v5mr7586956wrp.246.1573202727559; Fri, 08 Nov 2019 00:45:27 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:27 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Fri, 8 Nov 2019 09:45:11 +0100 Message-Id: <20191108084517.21617-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Reviewed-by: Rob Herring --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..1bae446febbb 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,51 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + items: + - description: Module Clock + - description: Bus Clock + + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clock-names: true + + resets: maxItems: 1 + if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + + else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +92,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Fri Nov 8 08:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XAIZ3SDF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478YlF3xDkz9sNx for ; Fri, 8 Nov 2019 19:46:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730596AbfKHIpb (ORCPT ); Fri, 8 Nov 2019 03:45:31 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46179 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbfKHIpa (ORCPT ); Fri, 8 Nov 2019 03:45:30 -0500 Received: by mail-wr1-f68.google.com with SMTP id b3so5994270wrs.13; Fri, 08 Nov 2019 00:45:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4QB9cDt6fQFRk5SFMea9eu/ALXFa2Va/mC6ymi+w/Cs=; b=XAIZ3SDFz73VRt8TZCqiOw69FrFZzRA1dTXc1hz0ORCz+jktoeMrothomPqIFQnMX/ zXyXRHN5y/AOcEwPSMzCu1ucukhVGog6MOeheYacZR9kWZc4zYpImP1NmndcN/7OPHOo xpsr6JYrl4Lt7gC1iuvuA+cojKhG0Zhk+SndYQCpyrKrISaaubKr+9LL7/bIV9keknYJ pk3O4dJCG7kgfcX2HK8D2cJesxBVmihhqFZVUGJNkN5PQSJmtk4hl9zh6utMONSE1e0H VvZEIPGHrezzqSrg6HYEJF7ayIb4arDg3BA3A7hbfceyczL1rswg/VN08wgDRfX7MXsL vhVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4QB9cDt6fQFRk5SFMea9eu/ALXFa2Va/mC6ymi+w/Cs=; b=g/sJs1oPKQrSOaPZ26UmsqDxjWfhmTBhnwG0BHLydtNsQ8ddyM4PLFXubIVHciiSGO u+hF6zWAnCH+pNWTMg0F2gD+JkaxDHaJQr5nPalxm4h5pEICIut2GQ/UXvpGGPZ+KHI/ 19Z3czVCKCa7jNzu4Zco4LSdarpwPzucNXT7o48kAG2m0Oe4BAMo5L8uxWbAe5NI1338 dICBr5AbnZ78dFhzeuqpDrrBjUFLrL7A/p88g9vrfuJsDhE4Lr8PB7qd6eMapbir6UwK S9GVtC5CKKUK9UhyHPAkYHM1/bsv9sqIxm8Vyd91cuYbVGvw/EKRujsETIL9CvwWmrzx tCnA== X-Gm-Message-State: APjAAAWCTBIGu++CPWotlkTX/YXUTthT6IuRrueVwwvxmrpxnMgOplJc S8YcIc6t6gdDcYW9ryNKbnYl+qT4+gw= X-Google-Smtp-Source: APXvYqxd907rYnKrigSrYCn3h6dEANybH8eRG+Xwv2u3fyvd4zj6zcYXc+0Y4jkia+vCViGcSMYgog== X-Received: by 2002:a5d:6947:: with SMTP id r7mr7396315wrw.129.1573202728267; Fri, 08 Nov 2019 00:45:28 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:27 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 2/7] pwm: sun4i: Add an optional probe for reset line Date: Fri, 8 Nov 2019 09:45:12 +0100 Message-Id: <20191108084517.21617-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6f5840a1a82d..2b9a2a78591f 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get reset failed %pe\n", + pwm->rst); + return PTR_ERR(pwm->rst); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -377,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Fri Nov 8 08:45:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191731 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aNtq9XYb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478YlC3dKtz9sNx for ; Fri, 8 Nov 2019 19:45:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731064AbfKHIpy (ORCPT ); Fri, 8 Nov 2019 03:45:54 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:42699 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726672AbfKHIpb (ORCPT ); Fri, 8 Nov 2019 03:45:31 -0500 Received: by mail-wr1-f68.google.com with SMTP id a15so6014444wrf.9; Fri, 08 Nov 2019 00:45:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q1SErrR/PV8Tu23yQ+QPofy4bJ7Dz3186/De70+A1IY=; b=aNtq9XYb7Gu//QxS2dCLqucgCUuU8TBnf5eyiZhT71GJbpm0UqL9w82WhhkQHRVCUq NzeDeGxap26Im/l8wl6SakWrh5xds93z+g9ASE1k2qSh8genXmeldFSsKfndoe6J0GLa 9YX4X1xMRj/oaVMEfFAuDLzD8bzOwtoNnTsSVHN0jLWX761Q9LV/ALME+UskSZQsJR2p av7GDVFzwQscc4CFe0oK/T1l1/hG5YUkxmYj+yv/EDylNkzBUM6fn8sIOmcFrFMyMb94 sP0eRWAcpjkTAhD9xcFBL5MFAolAt0OojTyKlABS9QK5PNQJOd2kUK74iRb3bNNw+ZiW TGoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q1SErrR/PV8Tu23yQ+QPofy4bJ7Dz3186/De70+A1IY=; b=SWqSBm4oXlgK4mwxBzlLeXNjucgeezMds58eOmZQq2xrXdnxgrSiPJvi/jaQFE10C4 tKwBpoBGs4xTNCgvgQeu5Kj/5ux/cZpxXHkBvWKCorlSSYu7J0C8ZqhXgVdpBnxlUQwg fB4JTSauvCL/Fq2VBmMC4sedFBGM64bfY43amsvxjikvEB3VlU62Vw+bRJ4YOW76QRgb Ryo78kgI3W9hbf3fLbQJSCYVcERiUbBMnF/7K1vzVXKnb8JwmQ3oFelWcbkC818E2v6t VmEM+Ku84R047o40QO1uIo/kj8FKQb9/Mn4cO1HsC48KUv774l3Y0962L6IIc13BY7Nt OYBw== X-Gm-Message-State: APjAAAWI+6haNUTWrZVEaHuSRPyP947rF+G8b29mR9F2bCB5nbZmAQI+ NyQyHPl8Z7K4DlAwMnyptmBooDWPcis= X-Google-Smtp-Source: APXvYqxd0/kwcmVD9KXQBezV2WMCtP44Hqqg6T96a3Zyb0CObgdqvf/lotqgnPAwLqFub2sJvDK8aw== X-Received: by 2002:adf:9506:: with SMTP id 6mr7599277wrs.274.1573202728901; Fri, 08 Nov 2019 00:45:28 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:28 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 3/7] pwm: sun4i: Add an optional probe for bus clock Date: Fri, 8 Nov 2019 09:45:13 +0100 Message-Id: <20191108084517.21617-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it and a fallback for previous bindings without name on module clock. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 2b9a2a78591f..a10022d6c0fd 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -363,9 +364,38 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->base)) return PTR_ERR(pwm->base); - pwm->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) + /* Get all clocks and reset line */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get clock failed %pe\n", + pwm->clk); return PTR_ERR(pwm->clk); + } + + /* + * Fallback for old dtbs with a single clock and no name. + * If a parent has a clock-name called "mod" whereas the + * current node is unnamed the clock reference will be + * incorrectly obtained and will not go into this fallback. + */ + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get clock failed %pe\n", + pwm->clk); + return PTR_ERR(pwm->clk); + } + } + + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get bus_clock failed %pe\n", + pwm->bus_clk); + return PTR_ERR(pwm->bus_clk); + } pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { @@ -382,6 +412,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* + * We're keeping the bus clock on for the sake of simplicity. + * Actually it only needs to be on for hardware register + * accesses. + */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -402,6 +443,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -416,6 +459,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Fri Nov 8 08:45:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C1dyS/W0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478Ykk45BZz9sNx for ; Fri, 8 Nov 2019 19:45:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730758AbfKHIpc (ORCPT ); Fri, 8 Nov 2019 03:45:32 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53306 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725975AbfKHIpc (ORCPT ); Fri, 8 Nov 2019 03:45:32 -0500 Received: by mail-wm1-f65.google.com with SMTP id x4so5260697wmi.3; Fri, 08 Nov 2019 00:45:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o1BbTTGdSFKY2gKlnZB56hqOxy66kjY0LgiclhRJDv0=; b=C1dyS/W0NAlPRWhXtx8M04st3Ji81RU6NVq5t+9WHq97OdhgLePwxDGl3Cruq/vZPd DhMB3BDpQ9jyil8oXeLUcnBbpOhWwv0qM4eJ9r1DWxSVAXweAgSmuhTKrKoIW/UjqRB8 3iIe5/qXLUa7pNPl83YENVRzssGRhi4YaVcGmiVRgz7IBMqSAZAhijS+2p7GRQfbwuFk cl38aPIvbDXot2aNqlghO7DJoyJx3cor3VtsLCISWwWyl1arlRUPR4VUcxBxW+kfmzmf EV+V1LpkKB8obh/ddgEvSJ9UeBITSOTJAlg23+Lw9qzcOjOi6UY2ZlMHWRXoO0xS1W5/ t7Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o1BbTTGdSFKY2gKlnZB56hqOxy66kjY0LgiclhRJDv0=; b=HCj9SDME4t+LmbfunJ+8jstJeJ4CttmhLoQSSMNAe/mUPo15hDgWP/NFiIZL74Afof 5wEm9rZyTWwUvmTxWliRNhywn4kpJZRz0erPs8jyVmjFIHojeZzskITW3cPqIJAT36SC 2u5ZNtYZUBC39umTcwuzKsgZWOiaz4Q9abK4ayrEfyhxZn4JeaoysC/DhFDdWIxDSrSq GsP7cnels99It1bG+zz/2u7D9a7YArfAGfU9KrkZ3/o2ClN3pZqXp1RP+lkip199AhzH wS9BYWxLk/IXF+xINLx3c/XHzs/0lQ6Gh4DqOmz3QsJtYlCZu2iYCZ9y1O9ugKouRR23 hb0A== X-Gm-Message-State: APjAAAVCWb+89vaEGpk51cZXa6qYH6YlPGk69OSucfBX1A+VOsABrwZq JvBTyezuDKGcrvnlMiOcml0= X-Google-Smtp-Source: APXvYqxwBaxdGVAxdGG5OfhwPgDnJ/JZT/ybNdD4d2t31vpqkvY3E2BRG4vS88zywqSF6FNS60xWrQ== X-Received: by 2002:a1c:740a:: with SMTP id p10mr7053319wmc.121.1573202729584; Fri, 08 Nov 2019 00:45:29 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:29 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 4/7] pwm: sun4i: Add support to output source clock directly Date: Fri, 8 Nov 2019 09:45:14 +0100 Message-Id: <20191108084517.21617-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index a10022d6c0fd..9cc928ab47bc 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; u32 ctrl; + bool bypass = false; int ret; unsigned int delay_us; unsigned long now; @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, } } + /* + * Although it would make much more sense to check for bypass in + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". + */ + if (state->enabled) { + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + } + spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* We can skip calculation and apply parameters */ + if (bypass && sun4i_pwm->data->has_direct_mod_clk_output) + goto bypass_mode; + if ((cstate.period != state->period) || (cstate.duty_cycle != state->duty_cycle)) { u32 period, duty, val; @@ -258,6 +293,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -265,6 +301,14 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + else + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); + } + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Fri Nov 8 08:45:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191729 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l7g2WJEp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478Yl23VMmz9sR4 for ; Fri, 8 Nov 2019 19:45:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730811AbfKHIpd (ORCPT ); Fri, 8 Nov 2019 03:45:33 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:53309 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730668AbfKHIpc (ORCPT ); Fri, 8 Nov 2019 03:45:32 -0500 Received: by mail-wm1-f67.google.com with SMTP id x4so5260729wmi.3; Fri, 08 Nov 2019 00:45:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R2H2SvNfp2D1pWuVIAXfuUZmaanE3ag429BW1Qs5Xbw=; b=l7g2WJEpz9iGWpW4GTr4NP4iWFjfeqIW/bvPcR3EzXT2ZRovXiQKEnOhFWbdCJXCxk Iz2ZpqyTGYXS9YGss2IsRNMUjehpu59CVhlJ5oLvIHrCnAWn+z+hav9dakiqTp43ILcn /8HOFk22TZhhXrZ0AY5tdwQvrF3pNUeVis/lWQzmJxGS9gbhAtpmq/RJIFEfNjeC+K3L 3PUpygxp1f49wq+iE/Ygu2Hv8TR5hQVWalsNamPIhh2ikiGMmYEOJ4g4JePT8KBF7n7q 8poH1me3sjiJpA62sJOTO/xoo4FuCUtcPWlQCHb2xPf65p3lVNY9C/egXNNNerIfJwWw S3+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R2H2SvNfp2D1pWuVIAXfuUZmaanE3ag429BW1Qs5Xbw=; b=NEGDUu47Jn7FrTyb+NWu5MG6Goe8mTaWQpFQwHNxVNXKZq8OU47Kjvxu04qeylSGCq ZbHznuCuoIMaWxN/hJo2uE8c0vT4VlZ/Yr5ihqU6foZzp08PKVsUPSQuNkok9N5vf9Dd 9ObnWkaF350RIB179t6YnkqzF2hPPlbtGOFnKBkPLMrtdRuquAcmArWXd8BAmjs187MM Lbfmosb5ydySz7HPRRuA45SbibgK3t83NZfYMnBdgvnhDPKZp++1BZlm8+RA5eRyGbFt kFJs7YzOkUX3jIL8x+4fJfLC7ekkfJ//08UiCGK1RhwJjU/Yggh8yxLPP9GC6UottJAm DH0A== X-Gm-Message-State: APjAAAWrbmxzWW/kS9rPOqLlPLg5MdIXoVnsefpAK2tXOHr4LH6PtgET 9shXXXXMIGz3NoDpWEg/CkU= X-Google-Smtp-Source: APXvYqyXzyJC3Dq6/PPn4+ahFI8wCQAvazATqLEj08DnRqbjTFB1hb1Zf/mNsFjSrGyw/2NztoTOgA== X-Received: by 2002:a05:600c:210c:: with SMTP id u12mr4568420wml.49.1573202730371; Fri, 08 Nov 2019 00:45:30 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:29 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 5/7] pwm: sun4i: Add support for H6 PWM Date: Fri, 8 Nov 2019 09:45:15 +0100 Message-Id: <20191108084517.21617-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 9cc928ab47bc..a57637de41c9 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -367,6 +367,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -383,6 +389,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Fri Nov 8 08:45:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191730 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="D1qm1SPD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478Yl34C4yz9sP6 for ; Fri, 8 Nov 2019 19:45:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731020AbfKHIpt (ORCPT ); Fri, 8 Nov 2019 03:45:49 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:39056 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730692AbfKHIpd (ORCPT ); Fri, 8 Nov 2019 03:45:33 -0500 Received: by mail-wm1-f68.google.com with SMTP id t26so5299727wmi.4; Fri, 08 Nov 2019 00:45:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=D1qm1SPDt8A+Vradbdz+NjuzHC3n4lBb5MQIo2TILRUGKh3ZesXy/5dY+ojmZZlJMA HEC7oYdHVO5tzy9/xg3R/T8rNfSdAE0gsnMXQ0RRXbVfyCv2ndh5STSSlPaQnPVpB8RD L6RCBuhRtjIC8SY8CrI7BoeSjlUS8EY9z0wDzYBNe0fTVqQpOPNZkmHsNuGIUTrdvPED IlHnB++2WeruWNFQHdwtEI90y55KjFmKidqYkPeBMtFdDgbm2WInoaioHeK8KAPPXVYz eCHENLiXN1Bj9ASqFoUtAZ7OjxSgbUd9QE756mC6/LRhS2FdfuqqlP7sfUjgF3Gi484j H7hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=r5bWf09c3SdJhoZTd4vatE/j4ACWyL+FV/dVjRfG4KJ6/QY2WMWWFntFpCkmMAGcat 4qZhbMlbd5JQ28SbE0NNA/nWzO8d0xJG/7Nj1xSAf/hMGC87IBLk78jjLuVbuOxjB2Hz jSn/XjW9+OMt8BUpd8oPbNjAzHOKOERUHuH8v4+MzXoMF4m0A4QTos1NxCpOCeI7kAS3 SIjf9hXkEE1KIfyvM9kbi5JbKK1UvsfVwvg0gQ7eh46uvextC+7X80L5bP73X/w+xLSX +cUdY/GzWOwRycAQXYGJDjxNAJv3flUk18tu0yh+XexJM3hW4TdhCl2uU1cezmH7TgPv I9OQ== X-Gm-Message-State: APjAAAUKAg8K7xMUww6NMC40ztX36wUD6unZ8XzbMiWnu5C7BMyymC2o B2uN3REg/NfK8xFFb0jhUsU= X-Google-Smtp-Source: APXvYqw6E/M1y7UeZTduVCL8358877o3jME7J6MDaZJII3rFx5yNJyEOeWFuDlIotS5YQXzjenELiw== X-Received: by 2002:a1c:ab0a:: with SMTP id u10mr7503819wme.0.1573202731003; Fri, 08 Nov 2019 00:45:31 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:30 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 6/7] arm64: dts: allwinner: h6: Add PWM node Date: Fri, 8 Nov 2019 09:45:16 +0100 Message-Id: <20191108084517.21617-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 0d5ea19336a1..b0d9ee1ead13 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -222,6 +222,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Fri Nov 8 08:45:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1191728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fewmUdz8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 478Yl10Z2Dz9sR1 for ; Fri, 8 Nov 2019 19:45:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730858AbfKHIpf (ORCPT ); Fri, 8 Nov 2019 03:45:35 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33192 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730743AbfKHIpe (ORCPT ); Fri, 8 Nov 2019 03:45:34 -0500 Received: by mail-wm1-f65.google.com with SMTP id a17so6017714wmb.0; Fri, 08 Nov 2019 00:45:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aSxRdpuFtWHR4fiaYF0NucipXPgTqmHceHSDmByEc8=; b=fewmUdz8Bc1voBvS9gkVz79gCkt7venyCUove7xWvuUQ7Y4j/5GuWd2AXvvgJu1Kfj N0dQ5nNqgLQudUbMeirlTSoTROX+NXDVjv7tmF7iOf3rJrWmkKmh2vS/eJjIzlX3uqx4 STJgeC8x6DSUy9PENPKGwtPtmXM483oVZq4Tm20Sg9l4PF42SkfQzBy8FNi7A54AoFCP k5F6YhLTTRPhmtsmFWLs8KjOql5qNPJDr74p2c7q4oNgfFgToC/aHzfjzHqwBIH5YJcz u/9zV1l8RwIgs5Kml7dx0uYElJGbgKN5fExDkFmeNqi4iAmfvBOItS7w5LRN0zL+qcHs ssbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9aSxRdpuFtWHR4fiaYF0NucipXPgTqmHceHSDmByEc8=; b=rJg1cIZnjA1j/18+0GfLSqJG7FV3ZyFOozrzAgJX1OKGg5PBwbwldvO+Ft/6fg7swT UqwfIOQ+8ccayn/7xEmLiwFyIWLUPxyvyQlWoiMBB7/5tOhm64KEt498nz/VtuOi/C1A Xgn26Bf5h70ZwvEnjU20VOPktKNVCtN7+z0S0AYaw4egVa9dJeQIJY8udfeeHWsP6V/C BCxbAOhUwcZUQE8aM4QqOCcUn4sQAdJBzpU/ONK/5qf7g6mh7uyrJcK/kQTpZfMYUZMW 6zdHTDfgP52FfiFYW2eEy6y2T1GWVQt3UPgXuO8zBLb0PAeCLs1sohxCsRcErqvM6K+i cgoA== X-Gm-Message-State: APjAAAVmE3+dSPATC3w3YnyKwhpm4//U2H+IuChlE4Ad0gfzNKbxu313 WOcvSBJxwQXtA+m6lenBG/4= X-Google-Smtp-Source: APXvYqzDrSyXBmSgmOwIGNCEnIg0mdtNJewcjpzu3/9Z4+a5/R+2nI67UgxKiYB47MIydRckpkp04g== X-Received: by 2002:a1c:558a:: with SMTP id j132mr6983373wmb.21.1573202731677; Fri, 08 Nov 2019 00:45:31 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id q25sm6662665wra.3.2019.11.08.00.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 00:45:31 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v4 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Fri, 8 Nov 2019 09:45:17 +0100 Message-Id: <20191108084517.21617-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108084517.21617-1-peron.clem@gmail.com> References: <20191108084517.21617-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 1d05d570142f..38aba7e5bbd9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -131,6 +131,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";